[MooreToCore] Unsupported $fatal to sim.terminate conversion

[Scheremo]

New circt user here, trying to run circt-verilog on my design.
I run into an issue when trying to parse the $fatal system verilog system task.

The System Verilog code in question is:

 $fatal(1, "Timeout exceeded!");

The moore IR emitted is:

%12 = moore.fmt.literal "Timeout exceeded!"
moore.builtin.severity fatal %12
moore.builtin.finish_message false
moore.builtin.finish 1
moore.unreachable

I suppose this should be converted into a sim.terminate op, but I am unsure how to match/combine moore.builtin.finish. Any advice?

[fabianschuiki]

Hey Moritz! Thanks for giving circt-verilog a spin 😁. The problem is that we don't have a lowering for moore.builtin.severity yet. The $fatal(1, "...") is syntactic sugar for a $error("...") and a $finish(1):

// $error("...")
%0 = moore.fmt.literal "Timeout exceeded!"
moore.builtin.severity error %0
// $finish(1)
moore.builtin.finish_message false
moore.builtin.finish 0

The $finish gets lowered to the sim.terminate op as you pointed out, but the $error fails with error: failed to legalize operation 'moore.builtin.severity'.

We already have a lowering from $display to sim.proc.print. As a first implementation, we could just lower $error and all the other things that produce a moore.builtin.severity to a sim.proc.print as well, maybe with a "error: " prefix for errors, and similar for warnings. This could be something like the following:

// ----- $display -----
// %0 = moore.fmt.literal "Timeout exceeded!\0A"
// moore.builtin.display %0
%0 = sim.fmt.lit "Timeout exceeded!\0A"
sim.proc.print %0

// ----- $error -----
// %0 = moore.fmt.literal "Timeout exceeded!\0A"
// moore.builtin.severity error %0
%0 = sim.fmt.lit "Timeout exceeded!\0A"
%1 = sim.fmt.lit "error: "  // or "fatal: ", "warning: "
%2 = sim.fmt.concat %1, %0
sim.proc.print %2

WDYT?

[Scheremo]

Hi Fabian! Long time no see, hope you're doing well :)
I think what you describe makes sense, at least for an initial version. If you don't mind I would give this a go with an OpConversionPattern matching the moore::SeverityBIOp and replace fatals with an error print. Would that be a reasonable way to implement what you describe?

[fabianschuiki]

I'm doing great! Working on CIRCT and getting some Verilog support going has been a pretty fun challenge 😅. Hope you're doing well, too!

I think what you describe makes sense, at least for an initial version. If you don't mind I would give this a go with an OpConversionPattern matching the moore::SeverityBIOp and replace fatals with an error print.

Yeah that sounds great! 🥳 Looking forward to your PR 🙂