mv88e6xxx: Fast ageing is broken on multichip systems

[wkz]

Problem

When a port transitions from forwarding to blocking, the DSA layer will flush ("fast age") all learned entries on that port. This works well on single-chip systems, but consider a multichip setup like this:

A and B are communicating along the golden path. Some topology change then causes sw2p1 to transition to the blocking state, at which point the DSA layer will flush all dynamic entries from the ATU which belongs to that port, so that the purple path can be used instead. However, sw2 still has the old record of B being located behind sw1p6 - so packets can not flow from A to B until B sends a packet in to sw1p5, thereby triggering an ATU update on sw1.

Discovered during regression testing

Suggested solution

Much like management of static FDB entries, flushing must be made multichip-aware, such that all DSA ports which are upstream from the affected port are also flushed. This will cause unrelated flows to be flooded for some period of time - but it is the best we can do given the hardware limitations.

[wkz]

This was merely worked around by the referenced change in Infix.