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cmd/compile, cmd/asm: incorrect use of T0 (X5) register in riscv64 assembly causes RAS mismatch and performance issue #76654

@BoyaoWang430

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@BoyaoWang430

Based on The RISC-V Instruction Set Manual, not only X0 register but also X5 register can be used to be a link register. As described in Chapter 2.5.1, when two different link registers (x1 and x5) are given as rs1 and rd, the Return-address prediction stacks(RAS) will pop then push.

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The Go runtime’s handwritten assembly and the code generated by the Go compiler incorrectly emit JALR X1, X5 instruction. When a function call uses x5 as the source register for JALR, it causes unintended RAS behavior. Although functionally correct, these instructions make the RAS perform a pop-then-push instead of a normal push, breaking call/return pairing and significantly degrading front-end branch prediction performance.

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BugReportIssues describing a possible bug in the Go implementation.FixPendingIssues that have a fix which has not yet been reviewed or submitted.arch-riscvIssues solely affecting the riscv64 architecture.compiler/runtimeIssues related to the Go compiler and/or runtime.

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