vec: optimize AVX2/FMA sum-of-squares with loop unrolling and FMA#17642
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vec: optimize AVX2/FMA sum-of-squares with loop unrolling and FMA#17642GermanAizek wants to merge 1 commit into
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…l FMA
- **Loop Unrolling:** The loop step is increased from 8 to 32 elements, reducing loop overhead and exposing more instruction-level parallelism.
- **Parallel Accumulators:** Instead of accumulating into a single scalar sum, four `__m256` vector registers are used to accumulate partial sums in parallel. This breaks the dependency chain on a single accumulator, allowing for better pipeline utilization.
- **Fused Multiply-Add (FMA):** The `_mm256_fmadd_ps` intrinsic is explicitly used for `val * val + sum_vec`, combining the multiplication and addition into a single instruction, which can improve both throughput and numerical precision.
- **Broadcast `mean` once:** The `mean` value is broadcast to a `__m256` vector once outside the loop (`mean_vec`), avoiding repeated broadcasts within the loop.
- **Post-loop Reduction:** The final horizontal sum of the four parallel accumulators is performed efficiently after the main loop.
References:
1. **Intel - Fast Parallel Reductions with SIMD Instructions:**
* Explains the concept of using multiple accumulators for parallel reduction, directly relevant to this optimization.
* Link: [https://software.intel.com/content/www/us/en/develop/articles/fast-parallel-reductions-with-simd-instructions.html](https://software.intel.com/content/www/us/en/develop/articles/fast-parallel-reductions-with-simd-instructions.html)
2. **Intel - Fused Multiply-Add (FMA) Instructions:**
* Details the benefits and usage of FMA instructions for improved performance and precision.
* Link: [https://software.intel.com/content/www/us/en/develop/articles/fused-multiply-add-fma-instructions.html](https://software.intel.com/content/www/us/en/develop/articles/fused-multiply-add-fma-instructions.html)
3. **Wikipedia - Loop Unrolling:**
* A general explanation of loop unrolling, a fundamental optimization technique used here.
* Link: [https://en.wikipedia.org/wiki/Loop_unrolling](https://en.wikipedia.org/wiki/Loop_unrolling)
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This simply change has greatly affected
vec_dot_q, and in my tests it floats strongly, sometimes 2-3-4 times almost higher, and sometimes a 2-3 times worse.Full Benchmark
Description
__m256vector registers are used to accumulate partial sums in parallel. This breaks the dependency chain on a single accumulator, allowing for better pipeline utilization._mm256_fmadd_psintrinsic is explicitly used forval * val + sum_vec, combining the multiplication and addition into a single instruction, which can improve both throughput and numerical precision.meanonce: Themeanvalue is broadcast to a__m256vector once outside the loop (mean_vec), avoiding repeated broadcasts within the loop.References:
Intel - Fast Parallel Reductions with SIMD Instructions:
Intel - Fused Multiply-Add (FMA) Instructions:
Wikipedia - Loop Unrolling:
Co-Authored-By: Gemini 2.5 Pro (References and description commit changes)