ggml-cpu : add basic RVV support for vector f32 ops #15057
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This PR introduces RVV support for several f32 vector kernels.
The implementation required refactoring the vectorization logic. Due to RVV's flexible vector length, its intrinsic types are sizeless, which prevents the compiler from creating arrays of vector registers (a similar limitation also can be found in Arm's SVE). This makes traditional loop unrolling techniques incompatible, necessitating a rewrite of the code to support RVV's architecture.