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[RISC-V] Replace addi, addiw with mov, sext.w when immediate is zero #117932
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Pull Request Overview
This PR optimizes RISC-V assembly code generation by replacing addi
/addiw
instructions with more appropriate mov
/sext.w
instructions when the immediate value is zero. This change improves code clarity and potentially performance by using semantically correct instructions for register moves and sign extension operations.
Key changes:
- Replace
addi rd, rs, 0
withmov rd, rs
for 64-bit register moves - Replace
addiw rd, rs, 0
withsext.w rd, rs
for 32-bit sign extension operations - Update conditional logic to use appropriate instruction based on attribute size
Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch |
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@risc-vv /run |
RISC-V Release-CLR-QEMU: 9092 / 9122 (99.67%)
report.xml, report.md, failures.xml, testclr_details.tar.zst RISC-V Release-FX-QEMU: 284268 / 285403 (99.60%)
report.xml, report.md, failures.xml, testclr_details.tar.zst RISC-V Release-CLR-VF2: 9093 / 9123 (99.67%)
report.xml, report.md, failures.xml, testclr_details.tar.zst RISC-V Release-FX-VF2: 307796 / 309263 (99.53%)
report.xml, report.md, failures.xml, testclr_details.tar.zst Build information and commandsGIT: |
@jakobbotsch Could you review this PR and #117967 as well? Thank you. |
@jakobbotsch Could you review this PR too? Thank you. |
/ba-g Unknown failure was #117961 |
1 similar comment
/ba-g Unknown failure was #117961 |
Replace addi, addiw with mov, sext.w when immediate is zero
@clamp03 @tomeksowi @SkyShield, @namu-lee
part of #84834, cc @dotnet/samsung