Skip to content

x64: refactor the representation of *Mem and *MemImm #10775

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
wants to merge 1 commit into
base: main
Choose a base branch
from
Open

x64: refactor the representation of *Mem and *MemImm #10775

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
33 changes: 27 additions & 6 deletions cranelift/codegen/src/isa/x64/inst.isle
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1553,17 +1553,38 @@
(type Gpr (primitive Gpr))
(type WritableGpr (primitive WritableGpr))
(type OptionWritableGpr (primitive OptionWritableGpr))
(type GprMem extern (enum))
(type GprMemImm extern (enum))
(type GprMem extern
(enum
(Reg (reg Reg))
Copy link
Member Author

@abrown abrown May 14, 2025 •
edited
Loading

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Is it now theoretically possible to create a GprMem.Reg in ISLE using the wrong kind of register? If so, we could alter this type to Gpr?

Copy link
Member

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Would it be possible to type this as (Gpr (reg Gpr))? That more closely matches the semantics of the GprMem constructor in Rust

Copy link
Member

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Following up from today's Cranelift meeting, where we briefly discussed this PR: I want to +1 Alex's comment here.

We want to maintain the invariant that all Gpr* newtypes can only ever contain GPR registers when they aren't a memory or immediate or whatever. If we expose raw Regs in these enum variants, then users can accidentally (say transitively through a series of abstractions) do something like

if let GprMem::Reg { reg } = &mut gpr_mem {
   std::mem::swap(reg, my_xmm_reg);
}

which would break that invariant.

In order to both allow matching on GprMem et al and preserve that invariant, we need to define new enums (to allow matching) but keep the register variants as Gprs (to preserve encapsulation and the GPR invariant). This would look like the ISLE equivalent of something like this:

enum GprMem {
    Gpr { reg: Gpr },
    Mem { addr: SyntheticAmode },
}

Which is, I believe, what Alex is suggesting just above this comment.

(Mem (addr SyntheticAmode))))
(type GprMemImm extern
(enum
(Reg (reg Reg))
(Mem (addr SyntheticAmode))
(Imm (simm32 u32))))
(type Imm8Gpr extern (enum))

(type Xmm (primitive Xmm))
(type WritableXmm (primitive WritableXmm))
(type OptionWritableXmm (primitive OptionWritableXmm))
(type XmmMem extern (enum))
(type XmmMemAligned extern (enum))
(type XmmMemImm extern (enum))
(type XmmMemAlignedImm extern (enum))
(type XmmMem extern
(enum
(Reg (reg Reg))
(Mem (addr SyntheticAmode))))
(type XmmMemAligned extern
(enum
(Reg (reg Reg))
(Mem (addr SyntheticAmode))))
(type XmmMemImm extern
(enum
(Reg (reg Reg))
(Mem (addr SyntheticAmode))
(Imm (simm32 u32))))
(type XmmMemAlignedImm extern
(enum
(Reg (reg Reg))
(Mem (addr SyntheticAmode))
(Imm (simm32 u32))))

;; Convert an `Imm8Reg` into an `Imm8Gpr`.
(decl imm8_reg_to_imm8_gpr (Imm8Reg) Imm8Gpr)
Expand Down
97 changes: 55 additions & 42 deletions cranelift/codegen/src/isa/x64/inst/args.rs
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -128,31 +128,34 @@ macro_rules! newtype_of_reg {
}

$(
/// A newtype wrapper around `RegMem` for general-purpose registers.
/// A newtype wrapper around `RegMem`; these variants should match
/// the `RegMem` variants exactly.
#[derive(Clone, Debug)]
pub struct $newtype_reg_mem(RegMem);
#[expect(missing_docs, reason = "see `RegMem`")]
pub enum $newtype_reg_mem {
Reg { reg: Reg },
Mem { addr: SyntheticAmode },
}

impl From<$newtype_reg_mem> for RegMem {
fn from(rm: $newtype_reg_mem) -> Self {
rm.0
}
}
impl<'a> From<&'a $newtype_reg_mem> for &'a RegMem {
fn from(rm: &'a $newtype_reg_mem) -> &'a RegMem {
&rm.0
match rm {
$newtype_reg_mem::Reg { reg } => RegMem::Reg { reg },
$newtype_reg_mem::Mem { addr } => RegMem::Mem { addr },
}
}
}

impl From<$newtype_reg> for $newtype_reg_mem {
fn from(r: $newtype_reg) -> Self {
$newtype_reg_mem(RegMem::reg(r.into()))
$newtype_reg_mem::Reg { reg: r.into() }
}
}

impl $newtype_reg_mem {
/// Construct a `RegMem` newtype from the given `RegMem`, or return
/// `None` if the `RegMem` is not a valid instance of this `RegMem`
/// newtype.
/// Construct a `RegMem` newtype from the given `RegMem`, or
/// return `None` if the `RegMem` is not a valid instance of
/// this `RegMem` newtype.
pub fn new(rm: RegMem) -> Option<Self> {
match rm {
RegMem::Mem { addr } => {
Expand All @@ -163,7 +166,7 @@ macro_rules! newtype_of_reg {
}
)?
if _allow {
Some(Self(RegMem::Mem { addr }))
Some(Self::Mem { addr })
} else {
None
}
Expand All @@ -185,48 +188,59 @@ macro_rules! newtype_of_reg {
);
}
)?
Self(RegMem::Mem { addr })
Self::Mem { addr }
}
RegMem::Reg { reg } => $newtype_reg::unwrap_new(reg).into(),
}
}

/// Convert this newtype into its underlying `RegMem`.
pub fn to_reg_mem(self) -> RegMem {
self.0
self.into()
}

#[allow(dead_code)] // Used by some newtypes and not others.
pub(crate) fn get_operands(&mut self, collector: &mut impl OperandVisitor) {
self.0.get_operands(collector);
match self {
Self::Reg { reg } => collector.reg_use(reg),
Self::Mem { addr } => addr.get_operands(collector),
}
}
}
impl PrettyPrint for $newtype_reg_mem {
fn pretty_print(&self, size: u8) -> String {
self.0.pretty_print(size)
match self {
Self::Reg { reg } => pretty_print_reg(*reg, size),
Self::Mem { addr } => addr.pretty_print(size),
}
}
}
)*

$(
/// A newtype wrapper around `RegMemImm`.
/// A newtype wrapper imitating `RegMemImm`; these variants should
/// match the `RegMemImm` variants exactly.
#[derive(Clone, Debug)]
pub struct $newtype_reg_mem_imm(RegMemImm);
#[expect(missing_docs, reason = "see `RegMemImm`")]
pub enum $newtype_reg_mem_imm {
Reg { reg: Reg },
Mem { addr: SyntheticAmode },
Imm { simm32: u32 },
}

impl From<$newtype_reg_mem_imm> for RegMemImm {
fn from(rmi: $newtype_reg_mem_imm) -> RegMemImm {
rmi.0
}
}
impl<'a> From<&'a $newtype_reg_mem_imm> for &'a RegMemImm {
fn from(rmi: &'a $newtype_reg_mem_imm) -> &'a RegMemImm {
&rmi.0
match rmi {
$newtype_reg_mem_imm::Reg { reg } => RegMemImm::Reg { reg },
$newtype_reg_mem_imm::Mem { addr } => RegMemImm::Mem { addr },
$newtype_reg_mem_imm::Imm { simm32 } => RegMemImm::Imm { simm32 },
}
}
}

impl From<$newtype_reg> for $newtype_reg_mem_imm {
fn from(r: $newtype_reg) -> Self {
$newtype_reg_mem_imm(RegMemImm::reg(r.into()))
$newtype_reg_mem_imm::Reg { reg: r.into() }
}
}

Expand All @@ -236,7 +250,7 @@ macro_rules! newtype_of_reg {
/// newtype.
pub fn new(rmi: RegMemImm) -> Option<Self> {
match rmi {
RegMemImm::Imm { .. } => Some(Self(rmi)),
RegMemImm::Imm { simm32 } => Some(Self::Imm { simm32 }),
RegMemImm::Mem { addr } => {
let mut _allow = true;
$(
Expand All @@ -245,7 +259,7 @@ macro_rules! newtype_of_reg {
}
)?
if _allow {
Some(Self(RegMemImm::Mem { addr }))
Some(Self::Mem { addr })
} else {
None
}
Expand All @@ -258,7 +272,7 @@ macro_rules! newtype_of_reg {
/// messages in case of failure.
pub fn unwrap_new(rmi: RegMemImm) -> Self {
match rmi {
RegMemImm::Imm { .. } => Self(rmi),
RegMemImm::Imm { simm32 } => Self::Imm { simm32 },
RegMemImm::Mem { addr } => {
$(
if $aligned_imm && !addr.aligned() {
Expand All @@ -269,7 +283,7 @@ macro_rules! newtype_of_reg {
);
}
)?
Self(RegMemImm::Mem { addr })
Self::Mem { addr }

}
RegMemImm::Reg { reg } => $newtype_reg::unwrap_new(reg).into(),
Expand All @@ -279,18 +293,26 @@ macro_rules! newtype_of_reg {
/// Convert this newtype into its underlying `RegMemImm`.
#[allow(dead_code)] // Used by some newtypes and not others.
pub fn to_reg_mem_imm(self) -> RegMemImm {
self.0
self.into()
}

#[allow(dead_code)] // Used by some newtypes and not others.
pub(crate) fn get_operands(&mut self, collector: &mut impl OperandVisitor) {
self.0.get_operands(collector);
match self {
Self::Reg { reg } => collector.reg_use(reg),
Self::Mem { addr } => addr.get_operands(collector),
Self::Imm { .. } => {}
}
}
}

impl PrettyPrint for $newtype_reg_mem_imm {
fn pretty_print(&self, size: u8) -> String {
self.0.pretty_print(size)
match self {
Self::Reg { reg } => pretty_print_reg(*reg, size),
Self::Mem { addr } => addr.pretty_print(size),
Self::Imm { simm32 } => format!("${}", *simm32 as i32),
}
}
}
)*
Expand Down Expand Up @@ -679,15 +701,6 @@ impl RegMemImm {
debug_assert_eq!(reg.class(), expected_reg_class);
}
}

/// Add the regs mentioned by `self` to `collector`.
pub(crate) fn get_operands(&mut self, collector: &mut impl OperandVisitor) {
match self {
Self::Reg { reg } => collector.reg_use(reg),
Self::Mem { addr } => addr.get_operands(collector),
Self::Imm { .. } => {}
}
}
}

impl From<RegMem> for RegMemImm {
Expand Down
Loading
Loading