Fix ad485x fmcz cmos #1890
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Fix ad485x fmcz cmos #1890
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The ad485x_fmcz design is advertised at 100MHz interface clock. But it
was only running at 50 MHz interface clock. This commit gets the
interface clock at 100 MHz. With this change it is also changed:
- the core clock from 100 MHz to 200 MHz
- restructure the interface to work at 100 MHz
- run the whole capture logic on the scko echoed clock
- add pipes between stages
- create a more robust CDC for data between scko and core clock
- optimize the CRC to run at a faster clock
- change the constraints file accordingly to the new structure
Signed-off-by: AndreiGrozav <[email protected]>
When enabling a number of channels which is not a power of two, the channels order swaps randomly between the pack and DMA without a sync signal. Signed-off-by: AndreiGrozav <[email protected]>
IuliaCMoldovan
requested changes
Sep 2, 2025
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Update the documentation as well (the block diagrams and in text maybe) |
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