PowerPC VLE NOP Istruction not patchable

[gmgunderground]

In PowerPC VLE for generating a NOP you must use 18 00 D0 00, and Ghidra decompile it correctly

but if I want to generate " e_ori r0,r0,0x0" patch, Ghidra gives an error

[GhidorahRex]

I think it's worth adding e_nop and se_nop definitions for the NOPs, but the issue of patching VLE instructions still remains. I can't patch any of them.

[GhidorahRex]

I was able to fix some of the issues and successfully assemble e_ori r0,r0,0x0 by fixing the SCALE sub-constructor. Note: I haven't tested much beyond this, just a quick and dirty fix to see if it would work. The previous version disassembled fine, but because of the way the bitwise logic was handled the assembler wasn't able to reverse to determine the value of the immediate operand.

ppc_vle.sinc:36:

@if REGISTER_SIZE == "4"
SCALE: val						is BIT_10=1 & SCL_VLE & IMM8 [ val = (0xFFFFFFFF) & ~((0xFF-IMM8) << (SCL_VLE*8)); ] { export *[const]:4 val;}
SCALE: val						is BIT_10=0 & SCL_VLE & IMM8 [ val = (IMM8 << (SCL_VLE*8));   ] { export *[const]:4 val;}
@else
SCALE: val						is BIT_10=1 & SCL_VLE & IMM8 [ val = (0xFFFFFFFFFFFFFFFF) & ~((0xFF-IMM8) << (SCL_VLE*8)); ] { export *[const]:8 val;}
SCALE: val						is BIT_10=0 & SCL_VLE & IMM8 [ val = IMM8 << (SCL_VLE*8); ] { export *[const]:8 val;}
@endif

edit 2: This version of the SCALE sub-constructor can handle negative operands as well.

[gmgunderground]

Perfect, as soon as available the update,i will make some tests