Skip to content

Conversation

SEmmmer
Copy link

@SEmmmer SEmmmer commented May 13, 2022

This is experimental and not guaranteed to work (it just compiles under QEMU)

My uname -a

Linux fedora-riscv 5.5.0-0.rc5.git0.1.1.riscv64.fc32.riscv64 #1 SMP Mon Jan 6 17:31:22 UTC 2020 riscv64 riscv64 riscv64 GNU/Linux

@CLAassistant
Copy link

CLAassistant commented May 13, 2022

CLA assistant check
Thank you for your submission! We really appreciate it. Like many open source projects, we ask that you sign our Contributor License Agreement before we can accept your contribution.


SEmmmer seems not to be a GitHub user. You need a GitHub account to be able to sign the CLA. If you have already a GitHub account, please add the email address used for this commit to your account.
You have signed the CLA already but the status is still pending? Let us recheck it.

@mtijanic
Copy link
Collaborator

Thank you for the interest and this PR! It is shaping up really well.

We do need to figure out internally how to handle additional architectures first, so expect some back and forth here and please have patience. But that shouldn't preclude the work to get the driver functional and we'll gladly help with that.

@@ -65,7 +65,7 @@ extern "C" {
#define NV_PRINTF_LEVEL_ENABLED(level) ((level) >= NV_PRINTF_LEVEL)
#endif

#if defined(GSP_PLUGIN_BUILD) || (defined(NVRM) && NVCPU_IS_RISCV64)
#if defined(GSP_PLUGIN_BUILD) || (defined(NVRM) && NVCPU_IS_RISCV64 && !NVOS_IS_LINUX)
Copy link
Collaborator

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Bit of background here, since we don't officially support riscv hosts, NVCPU_IS_RISCV64 is often used as a shorthand for "this code is running on one of our risc-v microcontrollers (a.k.a. Falcons)", so any place you see this or similar check used, there's a good chance the code was never meant to run on the host system - like here.

I am sure there will be many such instances in the codebase. We should really define a better macro to check if we're on a falcon and not tie it to the specific CPU arch.

Copy link

@imkiva imkiva May 13, 2022

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I noticed another macro NVCPU_NVRISCV64 here. Perhaps that's the macro for Falcon-like microcontrollers.

I am sure there will be many such instances in the codebase. We should really define a better macro to check if we're on a falcon and not tie it to the specific CPU arch.

Yes, the current codebase almost treats them the same way, which is different: NVCPU_NVRISCV64 runs on libos while NVCPU_RISCV64 can run on Linux.

Thanks for your explanation!

SEmmmer and others added 3 commits May 15, 2022 22:48
Co-authored-by: imkiva <[email protected]>
Co-authored-by: SEmmmer <[email protected]>
Co-authored-by: imkiva <[email protected]>
Co-authored-by: SEmmmer <[email protected]>
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

Successfully merging this pull request may close these issues.

4 participants