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stm32: Improve the CRC function to support fully accumulate #9347
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Hi I didn't review the updated code yet, but tests results are quite good:
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PR can be approved if you quickly want the update for the current targets supporting CRC
i.e. F0/F3/F7/L0/L4
But if you enable CRC at STM32_FAMILY, tests-mbed_hal-crc is still failing for the other families (F1/F2/F4/L1)
CI started |
Test run: FAILEDSummary: 6 of 7 test jobs failed Failed test jobs:
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CI job was aborted, 5.11.2 RC candidate is in the CI. We will restart it as soon as 5.11.2 RC is ready |
CI started |
Test run: FAILEDSummary: 6 of 7 test jobs failed Failed test jobs:
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@kevinong0108 Please take a look at the build failures. |
@cmonr OK, got it. I can't open detail link of "jenkins-ci/build-GCC_ARM — Error", and I try to compile on my own environment is OK. @jeromecoutant has tested before too. |
@kevinong0108 The The logs are updloaded to AWS, and provided in the |
@cmonr oh~~ thanks!!! I will fix it asap. |
Travis failure is related to the master bug - the fix is in the CI now, should be resolved soon (rebase will be needed ,we can do it for you) |
Tested on DISCO_L476VG and NUCLEO_L476RG
Those series have not CRC_POLYLENGTH_32B definition
Currently, mbed supported input data format fix on bytes, so those devices are not supported at default.
NOTE: This PR has now been rebased. If this was made in error, feel free to force-push your local branch to restore the PR. |
CI started |
Test run: FAILEDSummary: 1 of 11 test jobs failed Failed test jobs:
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restarted ci: greentea-test |
Description
Some STM32 series can support 32, 16, 8 and 7 bit hardware CRC but API only apply 32-bit.
Tested on DISCO_L476VG and NUCLEO_L476RG
Reopen: #7951
Pull request type
Reviewers
@jeromecoutant, @bcostm