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Unify RTC, lp ticker, and us ticker for NRF51 and NRF52 series #7172

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Merged
merged 10 commits into from
Jun 20, 2018

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mprse
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@mprse mprse commented Jun 8, 2018

Description

Add the following ticker modifications for NRF5x boards:

  • Increase NRF52 timer width to 32 bits,
  • Remove duplicate lp ticker initialization from I2C and flash,
  • common_rtc_set_interrupt(): Wrap <ticks_count> before comparisons,
  • NRF51, NRF52: Implement us_ticker_free() function,
  • NRF5x: Add bug fix for the first timer read,
  • NRF5x: Increase lp us ticker interrupt priority,
  • Use same ticker implementation for both NRF51 and NRF52.

Most of these changes have been proposed by @marcuschangarm. Can you review this PR?

Pull request type

[ ] Fix
[ ] Refactor
[ ] New target
[X] Feature
[ ] Breaking change

mprse added 3 commits June 7, 2018 16:00
RTC counter is 24-bit. Upper layer handles counter size and wraps ticks count when interrupt is to be fired before passing it to common_rtc_set_interrupt(), but for consistency and safety reasons we can wrap it again in the NRF driver.
@0xc0170 0xc0170 requested review from marcuschangarm and a team June 8, 2018 11:11
fkjagodzinski
fkjagodzinski previously approved these changes Jun 18, 2018
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LGTM

@@ -100,6 +100,9 @@ void us_ticker_init(void)

nrf_timer_task_trigger(NRF_TIMER1, NRF_TIMER_TASK_START);

/* Bug fix. First value can't be trusted. */
nrf_timer_task_trigger(NRF_TIMER1, NRF_TIMER_TASK_CAPTURE1);
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If this is somehow related to one of the known anomalies, it may be worth adding a reference.

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I don't think it is. I just noticed some very odd behavior on my boards.

#define LP_TICKER_COUNTER_BITS 32u
#define LP_TICKER_FREQ 31250

#endif // LP_TICKER_H
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I can't see where this file is being used?

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This file is added by mistake. I have removed it.

@@ -110,7 +110,9 @@ void us_ticker_set_interrupt(timestamp_t timestamp)
{
core_util_critical_section_enter();

nrf_timer_cc_write(NRF_TIMER1, NRF_TIMER_CC_CHANNEL0, timestamp & 0xFFFF);
const uint32_t counter_mask = ((1 << US_TICKER_COUNTER_BITS) - 1);
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Will this bit-shift always work? I was expecting this:

((1ULL << US_TICKER_COUNTER_BITS) - 1)

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Fixed as suggested.

@@ -110,7 +110,9 @@ void us_ticker_set_interrupt(timestamp_t timestamp)
{
core_util_critical_section_enter();

nrf_timer_cc_write(NRF_TIMER1, NRF_TIMER_CC_CHANNEL0, timestamp & 0xFFFF);
const uint32_t counter_mask = ((1 << US_TICKER_COUNTER_BITS) - 1);
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Same comment as above.

@marcuschangarm
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@mprse I just got back in the office, thank you for pushing this! I've added a couple of minor comments.

mprse added 7 commits June 19, 2018 08:46
It has been noticed that first read value can not be trusted.
Set the second highest user level, leaving the highest for UART (we are having constant overflows) and two levels below for everything else.
This should increase the timer accuracy.
@mprse mprse dismissed stale reviews from fkjagodzinski and maciejbocianski via 02d7d25 June 19, 2018 07:53
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mprse commented Jun 19, 2018

Provided some fixes after review.

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Looks good! Thank you!

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0xc0170 commented Jun 20, 2018

/morph build

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mbed-ci commented Jun 20, 2018

Build : SUCCESS

Build number : 2402
Build artifacts/logs : http://mbed-os.s3-website-eu-west-1.amazonaws.com/?prefix=builds/7172/

Triggering tests

/morph test
/morph uvisor-test
/morph export-build
/morph mbed2-build

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mbed-ci commented Jun 20, 2018

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mbed-ci commented Jun 20, 2018

@cmonr cmonr merged commit 84d6b79 into ARMmbed:master Jun 20, 2018
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7 participants