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Update cmsis/rtx for Cortex-A #7032

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Merged
merged 4 commits into from
Jun 3, 2018
Merged

Update cmsis/rtx for Cortex-A #7032

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0226b11
RTX5: disabled OS Tick interrupt during post processing in IRQ handle…
VladimirUmek Mar 28, 2018
b6c4139
RTX5: ignoring CPUID field in GIC implementation
VladimirUmek Apr 9, 2018
165c663
RTX5: fixed nesting interrupt handling (Cortex-A)
VladimirUmek Apr 10, 2018
4251af0
RTX5 (Cortex-A): exception handling restructured, post processing mov…
VladimirUmek May 24, 2018
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14 changes: 10 additions & 4 deletions cmsis/TARGET_CORTEX_A/irq_ctrl_gic.c
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Original file line number Diff line number Diff line change
@@ -1,8 +1,8 @@
/**************************************************************************//**
* @file irq_ctrl_gic.c
* @brief Interrupt controller handling implementation for GIC
* @version V1.0.0
* @date 30. June 2017
* @version V1.0.1
* @date 9. April 2018
******************************************************************************/
/*
* Copyright (c) 2017 ARM Limited. All rights reserved.
Expand Down Expand Up @@ -37,7 +37,7 @@
#endif

static IRQHandler_t IRQTable[IRQ_GIC_LINE_COUNT] = { 0U };
static uint32_t IRQ_ID0;
static uint32_t IRQ_ID0;

/// Initialize interrupt controller.
__WEAK int32_t IRQ_Initialize (void) {
Expand Down Expand Up @@ -70,6 +70,9 @@ __WEAK int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler) {
__WEAK IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn) {
IRQHandler_t h;

// Ignore CPUID field (software generated interrupts)
irqn &= 0x3FFU;

if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
h = IRQTable[irqn];
} else {
Expand Down Expand Up @@ -271,9 +274,12 @@ __WEAK IRQn_ID_t IRQ_GetActiveFIQ (void) {
/// Signal end of interrupt processing.
__WEAK int32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn) {
int32_t status;
IRQn_Type irq = (IRQn_Type)irqn;

irqn &= 0x3FFU;

if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
GIC_EndInterrupt ((IRQn_Type)irqn);
GIC_EndInterrupt (irq);

if (irqn == 0) {
IRQ_ID0 = 0U;
Expand Down
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