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Merged
merged 3 commits into from
Apr 23, 2018
Merged

STM32L0: Update with CubeL0 V1.10.0 #6666

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8191487
L0 ST CUBE V1.10.0
bcostm Mar 29, 2018
61576f8
L0 ST CUBE V1.10.0: spi and i2c corrections
bcostm Apr 9, 2018
893b759
L0 ST CUBE V1.10.0: change adc sampling time
bcostm Apr 9, 2018
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5 changes: 2 additions & 3 deletions ..._STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/device/TOOLCHAIN_ARM_MICRO/startup_stm32l011xx.S
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@@ -1,8 +1,8 @@
;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
;* File Name : startup_stm32l011xx.s
;* Author : MCD Application Team
;* Version : V1.5.0
;* Date : 8-January-2016
;* Version : V1.7.1
;* Date : 25-November-2016
;* Description : STM32l011xx Devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
Expand All @@ -12,7 +12,6 @@
;* calls main()).
;* After Reset the Cortex-M0+ processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;*
;* Redistribution and use in source and binary forms, with or without modification,
Expand Down
8 changes: 3 additions & 5 deletions targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/device/stm32l011xx.h
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Expand Up @@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l011xx.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for stm32l011xx devices.
Expand All @@ -16,7 +14,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
Expand Down Expand Up @@ -752,7 +750,7 @@ typedef struct

/******************* Bits definition for ADC_CFGR2 register *****************/
#define ADC_CFGR2_TOVS_Pos (9U)
#define ADC_CFGR2_TOVS_Msk (0x400001U << ADC_CFGR2_TOVS_Pos) /*!< 0x80000200 */
#define ADC_CFGR2_TOVS_Msk (0x1U << ADC_CFGR2_TOVS_Pos) /*!< 0x80000200 */
#define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< Triggered Oversampling */
#define ADC_CFGR2_OVSS_Pos (5U)
#define ADC_CFGR2_OVSS_Msk (0xFU << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
Expand Down Expand Up @@ -5736,7 +5734,7 @@ typedef struct
#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
((INSTANCE) == COMP2))

#define IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON)
#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)

/******************************* CRC Instances ********************************/
#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
Expand Down
14 changes: 6 additions & 8 deletions targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/device/stm32l0xx.h
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Expand Up @@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l0xx.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for STM32L0xx devices.
Expand All @@ -20,7 +18,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
Expand Down Expand Up @@ -114,16 +112,16 @@
#endif /* USE_HAL_DRIVER */

/**
* @brief CMSIS Device version number V1.7.0
* @brief CMSIS Device version number V1.7.1
*/
#define __STM32L0xx_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32L0xx_CMSIS_VERSION_SUB1 (0x07) /*!< [23:16] sub1 version */
#define __STM32L0xx_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32L0xx_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
#define __STM32L0xx_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32L0xx_CMSIS_VERSION ((__STM32L0xx_CMSIS_VERSION_MAIN << 24)\
|(__STM32L0xx_CMSIS_VERSION_SUB1 << 16)\
|(__STM32L0xx_CMSIS_VERSION_SUB2 << 8 )\
|(__STM32L0xx_CMSIS_VERSION_RC))
|(__STM32L0xx_CMSIS_VERSION_SUB1 << 16)\
|(__STM32L0xx_CMSIS_VERSION_SUB2 << 8 )\
|(__STM32L0xx_CMSIS_VERSION_RC))

/**
* @}
Expand Down
4 changes: 1 addition & 3 deletions targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/device/system_stm32l0xx.h
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Expand Up @@ -2,13 +2,11 @@
******************************************************************************
* @file system_stm32l0xx.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
Expand Down
5 changes: 2 additions & 3 deletions ..._STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/device/TOOLCHAIN_ARM_MICRO/startup_stm32l031xx.S
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@@ -1,8 +1,8 @@
;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
;* File Name : startup_stm32l053xx.s
;* Author : MCD Application Team
;* Version : V1.5.0
;* Date : 8-January-2016
;* Version : V1.7.1
;* Date : 25-November-2016
;* Description : STM32l053xx Devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
Expand All @@ -12,7 +12,6 @@
;* calls main()).
;* After Reset the Cortex-M0+ processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;*
;* Redistribution and use in source and binary forms, with or without modification,
Expand Down
5 changes: 2 additions & 3 deletions ...ET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/device/TOOLCHAIN_ARM_STD/startup_stm32l031xx.S
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@@ -1,8 +1,8 @@
;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
;* File Name : startup_stm32l053xx.s
;* Author : MCD Application Team
;* Version : V1.5.0
;* Date : 8-January-2016
;* Version : V1.7.1
;* Date : 25-November-2016
;* Description : STM32l053xx Devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
Expand All @@ -12,7 +12,6 @@
;* calls main()).
;* After Reset the Cortex-M0+ processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;*
;* Redistribution and use in source and binary forms, with or without modification,
Expand Down
2 changes: 0 additions & 2 deletions ...ET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/device/TOOLCHAIN_GCC_ARM/startup_stm32l031xx.S
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Expand Up @@ -2,8 +2,6 @@
******************************************************************************
* @file startup_stm32l031xx.s
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @brief STM32L031xx Devices vector table for Atollic TrueSTUDIO toolchain.
* This module performs:
* - Set the initial SP
Expand Down
4 changes: 2 additions & 2 deletions ...TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/device/TOOLCHAIN_IAR/startup_stm32l031xx.S
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@@ -1,8 +1,8 @@
;/******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
;* File Name : startup_stm32l031xx.s
;* Author : MCD Application Team
;* Version : V1.5.0
;* Date : 8-January-2016
;* Version : V1.7.1
;* Date : 25-November-2016
;* Description : STM32L031xx Ultra Low Power Devices vector
;* This module performs:
;* - Set the initial SP
Expand Down
8 changes: 3 additions & 5 deletions targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/device/stm32l031xx.h
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Expand Up @@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l031xx.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for stm32l031xx devices.
Expand All @@ -16,7 +14,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
Expand Down Expand Up @@ -761,7 +759,7 @@ typedef struct

/******************* Bits definition for ADC_CFGR2 register *****************/
#define ADC_CFGR2_TOVS_Pos (9U)
#define ADC_CFGR2_TOVS_Msk (0x400001U << ADC_CFGR2_TOVS_Pos) /*!< 0x80000200 */
#define ADC_CFGR2_TOVS_Msk (0x1U << ADC_CFGR2_TOVS_Pos) /*!< 0x80000200 */
#define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< Triggered Oversampling */
#define ADC_CFGR2_OVSS_Pos (5U)
#define ADC_CFGR2_OVSS_Msk (0xFU << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
Expand Down Expand Up @@ -5857,7 +5855,7 @@ typedef struct
#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
((INSTANCE) == COMP2))

#define IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON)
#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)

/******************************* CRC Instances ********************************/
#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
Expand Down
14 changes: 6 additions & 8 deletions targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/device/stm32l0xx.h
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Expand Up @@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l0xx.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for STM32L0xx devices.
Expand All @@ -20,7 +18,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
Expand Down Expand Up @@ -114,16 +112,16 @@
#endif /* USE_HAL_DRIVER */

/**
* @brief CMSIS Device version number V1.7.0
* @brief CMSIS Device version number V1.7.1
*/
#define __STM32L0xx_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32L0xx_CMSIS_VERSION_SUB1 (0x07) /*!< [23:16] sub1 version */
#define __STM32L0xx_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32L0xx_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
#define __STM32L0xx_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32L0xx_CMSIS_VERSION ((__STM32L0xx_CMSIS_VERSION_MAIN << 24)\
|(__STM32L0xx_CMSIS_VERSION_SUB1 << 16)\
|(__STM32L0xx_CMSIS_VERSION_SUB2 << 8 )\
|(__STM32L0xx_CMSIS_VERSION_RC))
|(__STM32L0xx_CMSIS_VERSION_SUB1 << 16)\
|(__STM32L0xx_CMSIS_VERSION_SUB2 << 8 )\
|(__STM32L0xx_CMSIS_VERSION_RC))

/**
* @}
Expand Down
4 changes: 1 addition & 3 deletions targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/device/system_stm32l0xx.h
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Expand Up @@ -2,13 +2,11 @@
******************************************************************************
* @file system_stm32l0xx.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
Expand Down
5 changes: 2 additions & 3 deletions ..._STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/device/TOOLCHAIN_ARM_MICRO/startup_stm32l073xx.S
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Original file line number Diff line number Diff line change
@@ -1,8 +1,8 @@
;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
;* File Name : startup_stm32l073xx.s
;* Author : MCD Application Team
;* Version : V1.5.0
;* Date : 8-January-2016
;* Version : V1.7.1
;* Date : 25-November-2016
;* Description : STM32l073xx Devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
Expand All @@ -12,7 +12,6 @@
;* calls main()).
;* After Reset the Cortex-M0+ processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;*
;* Redistribution and use in source and binary forms, with or without modification,
Expand Down
5 changes: 2 additions & 3 deletions ...ET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/device/TOOLCHAIN_ARM_STD/startup_stm32l073xx.S
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Original file line number Diff line number Diff line change
@@ -1,8 +1,8 @@
;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
;* File Name : startup_stm32l073xx.s
;* Author : MCD Application Team
;* Version : V1.5.0
;* Date : 8-January-2016
;* Version : V1.7.1
;* Date : 25-November-2016
;* Description : STM32l073xx Devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
Expand All @@ -12,7 +12,6 @@
;* calls main()).
;* After Reset the Cortex-M0+ processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;*
;* Redistribution and use in source and binary forms, with or without modification,
Expand Down
2 changes: 0 additions & 2 deletions ...ET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/device/TOOLCHAIN_GCC_ARM/startup_stm32l073xx.S
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Expand Up @@ -2,8 +2,6 @@
******************************************************************************
* @file startup_stm32l073xx.s
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @brief STM32L073xx Devices vector table for Atollic TrueSTUDIO toolchain.
* This module performs:
* - Set the initial SP
Expand Down
4 changes: 2 additions & 2 deletions ...TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/device/TOOLCHAIN_IAR/startup_stm32l073xx.S
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Original file line number Diff line number Diff line change
@@ -1,8 +1,8 @@
;/******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
;* File Name : startup_stm32l073xx.s
;* Author : MCD Application Team
;* Version : V1.5.0
;* Date : 8-January-2016
;* Version : V1.7.1
;* Date : 25-November-2016
;* Description : STM32L073xx Ultra Low Power Devices vector
;* This module performs:
;* - Set the initial SP
Expand Down
8 changes: 3 additions & 5 deletions targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/device/stm32l073xx.h
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Expand Up @@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l073xx.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for stm32l073xx devices.
Expand All @@ -16,7 +14,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
Expand Down Expand Up @@ -950,7 +948,7 @@ typedef struct

/******************* Bits definition for ADC_CFGR2 register *****************/
#define ADC_CFGR2_TOVS_Pos (9U)
#define ADC_CFGR2_TOVS_Msk (0x400001U << ADC_CFGR2_TOVS_Pos) /*!< 0x80000200 */
#define ADC_CFGR2_TOVS_Msk (0x1U << ADC_CFGR2_TOVS_Pos) /*!< 0x80000200 */
#define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< Triggered Oversampling */
#define ADC_CFGR2_OVSS_Pos (5U)
#define ADC_CFGR2_OVSS_Msk (0xFU << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
Expand Down Expand Up @@ -7532,7 +7530,7 @@ typedef struct
#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
((INSTANCE) == COMP2))

#define IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON)
#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)

/******************************* CRC Instances ********************************/
#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
Expand Down
14 changes: 6 additions & 8 deletions targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/device/stm32l0xx.h
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Original file line number Diff line number Diff line change
Expand Up @@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l0xx.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for STM32L0xx devices.
Expand All @@ -20,7 +18,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
Expand Down Expand Up @@ -114,16 +112,16 @@
#endif /* USE_HAL_DRIVER */

/**
* @brief CMSIS Device version number V1.7.0
* @brief CMSIS Device version number V1.7.1
*/
#define __STM32L0xx_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32L0xx_CMSIS_VERSION_SUB1 (0x07) /*!< [23:16] sub1 version */
#define __STM32L0xx_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32L0xx_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
#define __STM32L0xx_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32L0xx_CMSIS_VERSION ((__STM32L0xx_CMSIS_VERSION_MAIN << 24)\
|(__STM32L0xx_CMSIS_VERSION_SUB1 << 16)\
|(__STM32L0xx_CMSIS_VERSION_SUB2 << 8 )\
|(__STM32L0xx_CMSIS_VERSION_RC))
|(__STM32L0xx_CMSIS_VERSION_SUB1 << 16)\
|(__STM32L0xx_CMSIS_VERSION_SUB2 << 8 )\
|(__STM32L0xx_CMSIS_VERSION_RC))

/**
* @}
Expand Down
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