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STM32WB update drivers version to CUBE V1.7.0 #13304

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Jul 22, 2020
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Original file line number Diff line number Diff line change
Expand Up @@ -86,6 +86,7 @@ static bool get_bd_address(uint8_t *bd_addr);
static bool sysevt_wait(void);
static bool sysevt_check(void);

extern int BLE_inited;
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Shouldn't it be BLE_initialized?

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@jeromecoutant shall this be updated ?


namespace ble {
namespace vendor {
Expand Down Expand Up @@ -675,6 +676,9 @@ class TransportDriver : public cordio::CordioHCITransportDriver {
* Starts the BLE Stack on CPU2
*/
SHCI_C2_BLE_Init(&ble_init_cmd_packet);

/* Used in flash_api.c */
BLE_inited = 1;
}

TL_CmdPacket_t *bleCmdBuf;
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -100,11 +100,17 @@ extern "C" {
uint8_t *m0cmd_buffer;
} MB_LldTestsTable_t;

typedef struct
{
uint8_t *cmdrsp_buffer;
uint8_t *m0cmd_buffer;
} MB_LldBleTable_t;

typedef struct
{
uint8_t *notifM0toM4_buffer;
uint8_t *appliCmdM4toM0_buffer;
uint8_t *loggingM0toM4_buffer;
uint8_t *requestM0toM4_buffer;
} MB_ZigbeeTable_t;
/**
* msg
Expand Down Expand Up @@ -151,6 +157,7 @@ extern "C" {
MB_Mac_802_15_4_t *p_mac_802_15_4_table;
MB_ZigbeeTable_t *p_zigbee_table;
MB_LldTestsTable_t *p_lld_tests_table;
MB_LldBleTable_t *p_lld_ble_table;
} MB_RefTable_t;

#ifdef __cplusplus
Expand Down Expand Up @@ -194,6 +201,13 @@ extern "C" {
* | |
* |<---HW_IPCC_BLE_EVENT_CHANNEL--------------------|
* | |
* | (LLD BLE) |
* |----HW_IPCC_LLD_BLE_CMD_CHANNEL----------------->|
* | |
* |<---HW_IPCC_LLD_BLE_RSP_CHANNEL------------------|
* | |
* |<---HW_IPCC_LLD_BLE_M0_CMD_CHANNEL---------------|
* | |
* | (MAC) |
* |----HW_IPCC_MAC_802_15_4_CMD_RSP_CHANNEL-------->|
* | |
Expand Down Expand Up @@ -221,6 +235,8 @@ extern "C" {
#define HW_IPCC_MM_RELEASE_BUFFER_CHANNEL LL_IPCC_CHANNEL_4
#define HW_IPCC_THREAD_CLI_CMD_CHANNEL LL_IPCC_CHANNEL_5
#define HW_IPCC_LLDTESTS_CLI_CMD_CHANNEL LL_IPCC_CHANNEL_5
#define HW_IPCC_LLD_BLE_CLI_CMD_CHANNEL LL_IPCC_CHANNEL_5
#define HW_IPCC_LLD_BLE_CMD_CHANNEL LL_IPCC_CHANNEL_5
#define HW_IPCC_HCI_ACL_DATA_CHANNEL LL_IPCC_CHANNEL_6

/** CPU2 */
Expand All @@ -230,10 +246,13 @@ extern "C" {
#define HW_IPCC_ZIGBEE_APPLI_NOTIF_ACK_CHANNEL LL_IPCC_CHANNEL_3
#define HW_IPCC_MAC_802_15_4_NOTIFICATION_ACK_CHANNEL LL_IPCC_CHANNEL_3
#define HW_IPCC_LLDTESTS_M0_CMD_CHANNEL LL_IPCC_CHANNEL_3
#define HW_IPCC_LLD_BLE_M0_CMD_CHANNEL LL_IPCC_CHANNEL_3
#define HW_IPCC_TRACES_CHANNEL LL_IPCC_CHANNEL_4
#define HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL LL_IPCC_CHANNEL_5
#define HW_IPCC_LLDTESTS_CLI_RSP_CHANNEL LL_IPCC_CHANNEL_5
#define HW_IPCC_ZIGBEE_APPLI_LOGGING_CHANNEL LL_IPCC_CHANNEL_5
#define HW_IPCC_LLD_BLE_CLI_RSP_CHANNEL LL_IPCC_CHANNEL_5
#define HW_IPCC_LLD_BLE_RSP_CHANNEL LL_IPCC_CHANNEL_5
#define HW_IPCC_ZIGBEE_M0_REQUEST_CHANNEL LL_IPCC_CHANNEL_5
#endif /*__MBOX_H */

/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Original file line number Diff line number Diff line change
Expand Up @@ -298,6 +298,24 @@ SHCI_CmdStatus_t SHCI_C2_LLDTESTS_Init( uint8_t param_size, uint8_t * p_param )
return (SHCI_CmdStatus_t)(((TL_CcEvt_t*)(p_rsp->evtserial.evt.payload))->payload[0]);
}

SHCI_CmdStatus_t SHCI_C2_LLD_BLE_Init( uint8_t param_size, uint8_t * p_param )
{
/**
* Buffer is large enough to hold command complete without payload
*/
uint8_t local_buffer[TL_BLEEVT_CS_BUFFER_SIZE];
TL_EvtPacket_t * p_rsp;

p_rsp = (TL_EvtPacket_t *)local_buffer;

shci_send( SHCI_OPCODE_C2_LLD_TESTS_INIT,
param_size,
p_param,
p_rsp );

return (SHCI_CmdStatus_t)(((TL_CcEvt_t*)(p_rsp->evtserial.evt.payload))->payload[0]);
}

SHCI_CmdStatus_t SHCI_C2_ZIGBEE_Init( void )
{
/**
Expand All @@ -315,6 +333,7 @@ SHCI_CmdStatus_t SHCI_C2_ZIGBEE_Init( void )

return (SHCI_CmdStatus_t)(((TL_CcEvt_t*)(p_rsp->evtserial.evt.payload))->payload[0]);
}

SHCI_CmdStatus_t SHCI_C2_DEBUG_Init( SHCI_C2_DEBUG_Init_Cmd_Packet_t *pCmdPacket )
{
/**
Expand Down Expand Up @@ -494,6 +513,27 @@ SHCI_CmdStatus_t SHCI_C2_ExtpaConfig(uint32_t gpio_port, uint16_t gpio_pin_numbe
return (SHCI_CmdStatus_t)(((TL_CcEvt_t*)(p_rsp->evtserial.evt.payload))->payload[0]);
}

SHCI_CmdStatus_t SHCI_C2_SetFlashActivityControl(SHCI_C2_SET_FLASH_ACTIVITY_CONTROL_Source_t Source)
{
/**
* TL_BLEEVT_CS_BUFFER_SIZE is 15 bytes so it is large enough to hold the 1 byte of command parameter
* Buffer is large enough to hold command complete without payload
*/
uint8_t local_buffer[TL_BLEEVT_CS_BUFFER_SIZE];
TL_EvtPacket_t * p_rsp;

p_rsp = (TL_EvtPacket_t *)local_buffer;

local_buffer[0] = (uint8_t)Source;

shci_send( SHCI_OPCODE_C2_SET_FLASH_ACTIVITY_CONTROL,
1,
local_buffer,
p_rsp );

return (SHCI_CmdStatus_t)(((TL_CcEvt_t*)(p_rsp->evtserial.evt.payload))->payload[0]);
}

/**
* Local System COMMAND
* These commands are NOT sent to the CPU2
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -137,7 +137,9 @@ extern "C" {
SHCI_OCF_C2_REINIT,
SHCI_OCF_C2_ZIGBEE_INIT,
SHCI_OCF_C2_LLD_TESTS_INIT,
SHCI_OCF_C2_EXTPA_CONFIG
SHCI_OCF_C2_EXTPA_CONFIG,
SHCI_OCF_C2_SET_FLASH_ACTIVITY_CONTROL,
SHCI_OCF_C2_LLD_BLE_INIT
} SHCI_OCF_t;

#define SHCI_OPCODE_C2_FUS_GET_STATE (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_GET_STATE)
Expand Down Expand Up @@ -296,6 +298,20 @@ extern "C" {

#define SHCI_OPCODE_C2_DEBUG_INIT (( SHCI_OGF << 10) + SHCI_OCF_C2_DEBUG_INIT)
/** Command parameters */
typedef PACKED_STRUCT
{
uint8_t thread_config;
uint8_t ble_config;
uint8_t mac_802_15_4_config;
uint8_t zigbee_config;
} SHCI_C2_DEBUG_TracesConfig_t;

typedef PACKED_STRUCT
{
uint8_t ble_dtb_cfg;
uint8_t reserved[3];
} SHCI_C2_DEBUG_GeneralConfig_t;

typedef PACKED_STRUCT{
uint8_t *pGpioConfig;
uint8_t *pTracesConfig;
Expand Down Expand Up @@ -352,6 +368,8 @@ extern "C" {

#define SHCI_OPCODE_C2_LLD_TESTS_INIT (( SHCI_OGF << 10) + SHCI_OCF_C2_LLD_TESTS_INIT)

#define SHCI_OPCODE_C2_LLD_BLE_INIT (( SHCI_OGF << 10) + SHCI_OCF_C2_LLD_BLE_INIT)

#define SHCI_OPCODE_C2_EXTPA_CONFIG (( SHCI_OGF << 10) + SHCI_OCF_C2_EXTPA_CONFIG)
/** Command parameters */
enum
Expand All @@ -375,6 +393,16 @@ extern "C" {

/** No response parameters*/

#define SHCI_OPCODE_C2_SET_FLASH_ACTIVITY_CONTROL (( SHCI_OGF << 10) + SHCI_OCF_C2_SET_FLASH_ACTIVITY_CONTROL)
/** Command parameters */
typedef enum
{
FLASH_ACTIVITY_CONTROL_PES,
FLASH_ACTIVITY_CONTROL_SEM7,
}SHCI_C2_SET_FLASH_ACTIVITY_CONTROL_Source_t;

/** No response parameters*/

/* Exported type --------------------------------------------------------*/

typedef MB_WirelessFwInfoTable_t SHCI_WirelessFwInfoTable_t;
Expand Down Expand Up @@ -427,16 +455,21 @@ typedef MB_WirelessFwInfoTable_t SHCI_WirelessFwInfoTable_t;
#define INFO_STACK_TYPE_MASK 0x000000ff
#define INFO_STACK_TYPE_NONE 0

#define INFO_STACK_TYPE_BLE_STANDARD 0x1
#define INFO_STACK_TYPE_BLE_HCI 0x2
#define INFO_STACK_TYPE_BLE_STANDARD 0x01
#define INFO_STACK_TYPE_BLE_HCI 0x02
#define INFO_STACK_TYPE_BLE_LIGHT 0x03
#define INFO_STACK_TYPE_THREAD_FTD 0x10
#define INFO_STACK_TYPE_THREAD_MTD 0x11
#define INFO_STACK_TYPE_ZIGBEE 0x30
#define INFO_STACK_TYPE_ZIGBEE_FFD 0x30
#define INFO_STACK_TYPE_ZIGBEE_RFD 0x31
#define INFO_STACK_TYPE_MAC 0x40
#define INFO_STACK_TYPE_BLE_THREAD_FTD_STATIC 0x50
#define INFO_STACK_TYPE_802154_LLD_TESTS 0x60
#define INFO_STACK_TYPE_802154_PHY_VALID 0x61
#define INFO_STACK_TYPE_BLE_PHY_VALID 0x62
#define INFO_STACK_TYPE_BLE_LLD_TESTS 0x63
#define INFO_STACK_TYPE_BLE_RLV 0x64
#define INFO_STACK_TYPE_802154_RLV 0x65
#define INFO_STACK_TYPE_BLE_ZIGBEE_FFD_STATIC 0x70

typedef struct {
Expand Down Expand Up @@ -587,6 +620,16 @@ typedef struct {
*/
SHCI_CmdStatus_t SHCI_C2_LLDTESTS_Init( uint8_t param_size, uint8_t * p_param );

/**
* SHCI_C2_LLD_BLE_Init
* @brief Starts the LLD tests CLI
*
* @param param_size : Nb of bytes
* @param p_param : pointeur with data to give from M4 to M0
* @retval Status
*/
SHCI_CmdStatus_t SHCI_C2_LLD_BLE_Init( uint8_t param_size, uint8_t * p_param );

/**
* SHCI_C2_ZIGBEE_Init
* @brief Starts the Zigbee Stack
Expand Down Expand Up @@ -706,6 +749,18 @@ typedef struct {
*/
SHCI_CmdStatus_t SHCI_C2_ExtpaConfig(uint32_t gpio_port, uint16_t gpio_pin_number, uint8_t gpio_polarity, uint8_t gpio_status);

/**
* SHCI_C2_SetFlashActivityControl
* @brief Set the mechanism to be used on CPU2 to prevent the CPU1 to either write or erase in flash
*
* @param Source: It can be one of the following list
* - FLASH_ACTIVITY_CONTROL_PES : The CPU2 set the PES bit to prevent the CPU1 to either read or write in flash
* - FLASH_ACTIVITY_CONTROL_SEM7 : The CPU2 gets the semaphore 7 to prevent the CPU1 to either read or write in flash.
* This requires the CPU1 to first get semaphore 7 before erasing or writing the flash.
*
* @retval Status
*/
SHCI_CmdStatus_t SHCI_C2_SetFlashActivityControl(SHCI_C2_SET_FLASH_ACTIVITY_CONTROL_Source_t Source);

#ifdef __cplusplus
}
Expand Down
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