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Merged
merged 26 commits into from
Nov 13, 2019
Merged

Improve QSPIFBlockDevice conformance to SFDP #11531

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e2b1ac0
Update reading/writing of status registers to conform to SFDP standard
Aug 30, 2019
cd78bf9
Reorder some functions
Aug 30, 2019
4785e83
Update flash device reset to conform to SFDP standard
Aug 30, 2019
cf9b6d5
Enable 4-byte addressing when supported in accordance with the SFDP s…
Aug 30, 2019
08a0b3d
Clear block protection on non-SST flash devices
Aug 30, 2019
ba41273
Move configuration of QSPI format to within commands where it is nece…
Aug 30, 2019
8fd1a50
Update SDFP erase detection to properly handle legacy erase instruction
Aug 30, 2019
4f01392
Replace power function with bit shift
Aug 30, 2019
d330dee
Streamline setting of instruction member variables
Aug 30, 2019
91141bb
Add missing debug prints to command functions
Aug 30, 2019
19330da
Correct typos and formatting
Aug 30, 2019
2154948
Update QSPI format after enabling 4-byte addressing
Aug 30, 2019
a1c7403
Enable some of the kvstore tests for PSoC 6 MCUs
Sep 5, 2019
619c5d9
Remove redundant QSPI erase alignment
Sep 11, 2019
92829bd
Generalize KVStore phase 1/2 test BlockDevice sizes
Sep 11, 2019
78569aa
Enable TDBStore whitebox test on PSoC 6
Sep 11, 2019
106fd5b
Update QSPI test to reflect fixes in QSPIFBlockDevice
Sep 13, 2019
60e4d14
Fix Astyle issues
Sep 19, 2019
cc4d428
Remove hard-coded instruction ids from QSPI Tests
Sep 23, 2019
d2ef568
QSPIF: Add back enable_fast_mode
Oct 18, 2019
26314d9
Don't clear quad enable when clearing block protection
Oct 21, 2019
eb5494e
QSPIF: Centralize handling of vendor quirks
Oct 24, 2019
02dbf68
QSPIF: Handle parts with extra config registers
Oct 24, 2019
2526b9f
QSPIF: Handle fast mode enable via vendor quirks
Oct 24, 2019
96cfc73
Disable attempted 4-byte addressing for some boards
Nov 11, 2019
0103e3a
General Block Device Test: Expand Thread Stack
Nov 12, 2019
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1 change: 1 addition & 0 deletions TESTS/mbed_hal/qspi/main.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -84,6 +84,7 @@ static uint32_t gen_flash_address()
{
srand(ticker_read(get_us_ticker_data()));
uint32_t address = (((uint32_t)rand()) % QSPI_SECTOR_COUNT) * QSPI_SECTOR_SIZE;
address &= 0xFFFFFF; // Ensure address is within 24 bits so as to not have to deal with 4-byte addressing
return address;
}

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26 changes: 21 additions & 5 deletions TESTS/mbed_hal/qspi/qspi_test_utils.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -58,7 +58,7 @@ void QspiCommand::set_dummy_cycles(int dummy_cycles)

void QspiCommand::build(int instruction, int address, int alt)
{
_cmd.instruction.disabled = (instruction == QSPI_NONE);
_cmd.instruction.disabled = (instruction == QSPI_NO_INST);
if (!_cmd.instruction.disabled) {
_cmd.instruction.value = instruction;
}
Expand Down Expand Up @@ -127,17 +127,33 @@ void flash_init(Qspi &qspi)
ret = qspi_command_transfer(&qspi.handle, qspi.cmd.get(), NULL, 0, status, QSPI_STATUS_REG_SIZE);
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);

qspi.cmd.build(QSPI_CMD_RSTEN);
ret = qspi_command_transfer(&qspi.handle, qspi.cmd.get(), NULL, 0, NULL, 0);
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
// Only do reset enable if device needs it
if (QSPI_CMD_RSTEN != 0) {
qspi.cmd.build(QSPI_CMD_RSTEN);
ret = qspi_command_transfer(&qspi.handle, qspi.cmd.get(), NULL, 0, NULL, 0);
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);

WAIT_FOR(WRSR_MAX_TIME, qspi);
WAIT_FOR(WRSR_MAX_TIME, qspi);
}

qspi.cmd.build(QSPI_CMD_RST);
ret = qspi_command_transfer(&qspi.handle, qspi.cmd.get(), NULL, 0, NULL, 0);
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);

WAIT_FOR(WAIT_MAX_TIME, qspi);

// Zero out status register to attempt to clear block protection bits
uint8_t blanks[QSPI_STATUS_REG_SIZE] = {0};

qspi.cmd.build(QSPI_CMD_WREN);
ret = qspi_command_transfer(&qspi.handle, qspi.cmd.get(), NULL, 0, NULL, 0);
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);

qspi.cmd.build(QSPI_CMD_WRSR);
ret = qspi_command_transfer(&qspi.handle, qspi.cmd.get(), blanks, 1, NULL, 0);
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);

WAIT_FOR(WRSR_MAX_TIME, qspi);
}


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