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Description
Description
Target: CY8CKIT_062_WIFI tested, most likely all PSoC 6 targets affected
Mbed OS ver: 5.14.0
Toolchain: doesn't matter
Hardware: FPGA Test Shield + CY8CKIT_062_WIFI_BT
Steps to reproduce
- Modify the board to remove resistor R100 and add 0 ohm resistor R104 (I just shorted R104 pads together). This disables the level shifter that connects some gpio/i2c/spi to the debug interface).
- Attach Mbed FPGA Test shield & Arduino form factor adapter. Plug in one usb cable to power the shield and one cable to power the board under test.
- Import the latest Mbed OS 5.14.0
- Add mbed_app.json in the root directory. Add these contents to enable FPGA test shield tests.
{
"target_overrides": {
"*": {
"target.components_add": ["FPGA_CI_TEST_SHIELD"],
}
}
}
- Add this function to the end of \targets\TARGET_Cypress\TARGET_PSOC6\mbed_overrides.c. This avoids testing D2, D14, D15 which have external pull downs or pull ups.
const PinList *pinmap_restricted_pins()
{
/*D2 has a pull down on board, D14, D15 have pullups on the board */
static const PinName pins[] = {
USBRX, USBTX, D2, D14, D15
};
static const PinList pin_list = {
sizeof(pins) / sizeof(pins[0]),
pins
};
return &pin_list;
}
- Run the tests with the following command (after previously setting target and toolchain)
mbed test -n tests-mbed_hal_fpga_ci_test_shield-gpio -v
Issue 1
Testcases in \TESTS\mbed_hal_fpga_ci_test_shield\gpio\main.cpp
The "tester.gpio_write" will drive the pin high or low from the FPGA. The gpio_read will check the state of the pin. When the pullmode is set to PullNone, it fails to read a correct pin value.
The first and third assert will fail.
// Test input, pull-none mode.
gpio_mode(&gpio, PullNone);
tester.gpio_write(MbedTester::LogicalPinGPIO0, 1, true);
TEST_ASSERT_EQUAL_INT(1, gpio_read(&gpio));
tester.gpio_write(MbedTester::LogicalPinGPIO0, 0, true);
TEST_ASSERT_EQUAL_INT(0, gpio_read(&gpio));
tester.gpio_write(MbedTester::LogicalPinGPIO0, 1, true);
TEST_ASSERT_EQUAL_INT(1, gpio_read(&gpio));
Suspected cause:
In cy_gpio_api.c, there doesn't seem to be any handling of PullNone. The expectation is that the pin is in input mode, but the pullup or pulldown is disabled. On a logic analyzer, it appears that the pin is driven low by the psoc 6 when it should be high-z input on the psoc 6 and driven high by the FPGA.
Is there any logic that should be added to explicilty disable the pull resistor?
void apply_config(gpio_t *obj)
{
MBED_ASSERT(obj->pin != CYHAL_NC_PIN_VALUE);
cy_rslt_t rslt;
if (CY_RSLT_SUCCESS != (rslt = cyhal_gpio_configure(obj->pin, obj->direction, obj->drive_mode))) {
MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER_GPIO, CY_RSLT_GET_CODE(rslt)), "cyhal_gpio_configure failed");
}
if (obj->drive_mode == PullUp) {
gpio_write(obj, 1);
} else if (obj->drive_mode == PullDown) {
gpio_write(obj, 0);
}
}
Also, in PinNamesTypes.h, this define sets it to strong drive. Is that correct in the case of an input mode?
// Pin Modes
#define PullNone CYHAL_GPIO_DRIVE_STRONG
Issue 2
gpio_init_inout() fails to enable pull up when requested
Testcases in \TESTS\mbed_hal_fpga_ci_test_shield\gpio\main.cpp
Setting the PullUp, appears to not work in this section of the code. It is supposed to enable the pullup and the pin should float high, but it doesn't.
// Initialize GPIO pin as an input, pull-up mode.
memset(&gpio, 0, sizeof gpio);
gpio_init_inout(&gpio, pin, PIN_INPUT, PullUp, 0);
TEST_ASSERT_NOT_EQUAL(0, gpio_is_connected(&gpio));
tester.gpio_write(MbedTester::LogicalPinGPIO0, 0, false);
wait_us(HI_Z_READ_DELAY_US);
TEST_ASSERT_EQUAL_INT(1, gpio_read(&gpio)); // hi-Z, pulled up
Issue request type
[ ] Question
[ ] Enhancement
[X] Bug