ARM-Processor-32-bit

A 32-bit Arm Processor Using Verilog HDL With Hazard Detection, Forwarding Unit, SRAM Memory & A 2-Way Set-Associative Cache.

Name		Name	Last commit message	Last commit date
Latest commit History 29 Commits
.gitignore		.gitignore
ALU.v		ALU.v
ARM.v		ARM.v
ARM_TB.v		ARM_TB.v
Adder.v		Adder.v
Cache.v		Cache.v
Cache_Controller.v		Cache_Controller.v
Condition_Check.v		Condition_Check.v
Control_Unit.v		Control_Unit.v
EXE_Stage.v		EXE_Stage.v
EXE_Stage_Reg.v		EXE_Stage_Reg.v
ForwardingUnit.v		ForwardingUnit.v
Hazard_Detection_Unit.v		Hazard_Detection_Unit.v
ID_Stage.v		ID_Stage.v
ID_Stage_Reg.v		ID_Stage_Reg.v
IF_Stage.v		IF_Stage.v
IF_Stage_Reg.v		IF_Stage_Reg.v
Instruction_Memory.v		Instruction_Memory.v
MEM_Stage.v		MEM_Stage.v
MEM_Stage_Reg.v		MEM_Stage_Reg.v
MUX_2_to_1.v		MUX_2_to_1.v
MUX_4_to_1.v		MUX_4_to_1.v
Memory.v		Memory.v
PC.v		PC.v
README.md		README.md
Register_File.v		Register_File.v
SRAM.v		SRAM.v
SRAM_Controller.v		SRAM_Controller.v
Status_Register.v		Status_Register.v
Val2_Generate.v		Val2_Generate.v
WB_Stage.v		WB_Stage.v

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