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Move LPC bits from chihiro.c to it's own device
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3 files changed

+140
-92
lines changed

3 files changed

+140
-92
lines changed

‎hw/xbox/chihiro.c

Lines changed: 1 addition & 92 deletions
Original file line numberDiff line numberDiff line change
@@ -83,97 +83,6 @@ typedef struct ChihiroMachineClass {
8383
/*< public >*/
8484
} ChihiroMachineClass;
8585

86-
87-
88-
#define SEGA_CHIP_REVISION 0xF0
89-
# define SEGA_CHIP_REVISION_CHIP_ID 0xFF00
90-
# define SEGA_CHIP_REVISION_FPGA_CHIP_ID 0x0000
91-
# define SEGA_CHIP_REVISION_ASIC_CHIP_ID 0x0100
92-
# define SEGA_CHIP_REVISION_REVISION_ID_MASK 0x00FF
93-
#define SEGA_DIMM_SIZE 0xF4
94-
# define SEGA_DIMM_SIZE_128M 0
95-
# define SEGA_DIMM_SIZE_256M 1
96-
# define SEGA_DIMM_SIZE_512M 2
97-
# define SEGA_DIMM_SIZE_1024M 3
98-
99-
//#define DEBUG_CHIHIRO
100-
101-
typedef struct ChihiroLPCState {
102-
ISADevice dev;
103-
MemoryRegion ioport;
104-
} ChihiroLPCState;
105-
106-
#define CHIHIRO_LPC_DEVICE(obj) \
107-
OBJECT_CHECK(ChihiroLPCState, (obj), "chihiro-lpc")
108-
109-
110-
static uint64_t chhiro_lpc_io_read(void *opaque, hwaddr addr,
111-
unsigned size)
112-
{
113-
uint64_t r = 0;
114-
switch (addr) {
115-
case SEGA_CHIP_REVISION:
116-
r = SEGA_CHIP_REVISION_ASIC_CHIP_ID;
117-
break;
118-
case SEGA_DIMM_SIZE:
119-
r = SEGA_DIMM_SIZE_128M;
120-
break;
121-
}
122-
#ifdef DEBUG_CHIHIRO
123-
printf("chihiro lpc read [0x%llx] -> 0x%llx\n", addr, r);
124-
#endif
125-
return r;
126-
}
127-
128-
static void chhiro_lpc_io_write(void *opaque, hwaddr addr, uint64_t val,
129-
unsigned size)
130-
{
131-
#ifdef DEBUG_CHIHIRO
132-
printf("chihiro lpc write [0x%llx] = 0x%llx\n", addr, val);
133-
#endif
134-
}
135-
136-
static const MemoryRegionOps chihiro_lpc_io_ops = {
137-
.read = chhiro_lpc_io_read,
138-
.write = chhiro_lpc_io_write,
139-
.impl = {
140-
.min_access_size = 2,
141-
.max_access_size = 2,
142-
},
143-
};
144-
145-
static void chihiro_lpc_realize(DeviceState *dev, Error **errp)
146-
{
147-
ChihiroLPCState *s = CHIHIRO_LPC_DEVICE(dev);
148-
ISADevice *isa = ISA_DEVICE(dev);
149-
150-
memory_region_init_io(&s->ioport, OBJECT(dev), &chihiro_lpc_io_ops, s,
151-
"chihiro-lpc-io", 0x100);
152-
isa_register_ioport(isa, &s->ioport, 0x4000);
153-
}
154-
155-
static void chihiro_lpc_class_initfn(ObjectClass *klass, void *data)
156-
{
157-
DeviceClass *dc = DEVICE_CLASS(klass);
158-
dc->realize = chihiro_lpc_realize;
159-
dc->desc = "Chihiro LPC";
160-
}
161-
162-
static const TypeInfo chihiro_lpc_info = {
163-
.name = "chihiro-lpc",
164-
.parent = TYPE_ISA_DEVICE,
165-
.instance_size = sizeof(ChihiroLPCState),
166-
.class_init = chihiro_lpc_class_initfn,
167-
};
168-
169-
static void chihiro_register_types(void)
170-
{
171-
type_register_static(&chihiro_lpc_info);
172-
}
173-
174-
type_init(chihiro_register_types)
175-
176-
17786
/* The chihiro baseboard communicates with the xbox by acting as an IDE
17887
* device. The device maps the boot rom from the mediaboard, a communication
17988
* area for interfacing with the network board, and the ram on the baseboard.
@@ -285,7 +194,7 @@ static void chihiro_init(MachineState *machine)
285194

286195
ISABus *isa_bus;
287196
xbox_init_common(machine, NULL, &isa_bus);
288-
isa_create_simple(isa_bus, "chihiro-lpc");
197+
isa_create_simple(isa_bus, "lpcsega");
289198
}
290199

291200
static void chihiro_machine_options(MachineClass *m)

‎hw/xbox/lpcsega.c

Lines changed: 138 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,138 @@
1+
/*
2+
* QEMU Chihiro emulation
3+
*
4+
* Copyright (c) 2013 espes
5+
* Copyright (c) 2018-2021 Matt Borgerson
6+
*
7+
* This library is free software; you can redistribute it and/or
8+
* modify it under the terms of the GNU Lesser General Public
9+
* License as published by the Free Software Foundation; either
10+
* version 2 of the License, or (at your option) any later version.
11+
*
12+
* This library is distributed in the hope that it will be useful,
13+
* but WITHOUT ANY WARRANTY; without even the implied warranty of
14+
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15+
* Lesser General Public License for more details.
16+
*
17+
* You should have received a copy of the GNU Lesser General Public
18+
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
19+
*/
20+
21+
#include "qemu/osdep.h"
22+
#include "hw/qdev-properties.h"
23+
#include "hw/qdev-properties-system.h"
24+
#include "migration/vmstate.h"
25+
#include "sysemu/sysemu.h"
26+
#include "hw/char/serial.h"
27+
#include "hw/isa/isa.h"
28+
#include "qapi/error.h"
29+
30+
#define SEGA_CHIP_REVISION 0xF0
31+
# define SEGA_CHIP_REVISION_CHIP_ID 0xFF00
32+
# define SEGA_CHIP_REVISION_FPGA_CHIP_ID 0x0000
33+
# define SEGA_CHIP_REVISION_ASIC_CHIP_ID 0x0100
34+
# define SEGA_CHIP_REVISION_REVISION_ID_MASK 0x00FF
35+
#define SEGA_DIMM_SIZE 0xF4
36+
# define SEGA_DIMM_SIZE_128M 0
37+
# define SEGA_DIMM_SIZE_256M 1
38+
# define SEGA_DIMM_SIZE_512M 2
39+
# define SEGA_DIMM_SIZE_1024M 3
40+
41+
#define TYPE_ISA_LPCSEGA_DEVICE "lpcsega"
42+
#define ISA_LPCSEGA_DEVICE(obj) \
43+
OBJECT_CHECK(ISALPCSEGAState, (obj), TYPE_ISA_LPCSEGA_DEVICE)
44+
45+
// #define DEBUG
46+
#ifdef DEBUG
47+
# define DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
48+
#else
49+
# define DPRINTF(format, ...) do { } while (0)
50+
#endif
51+
52+
typedef struct LPCSEGAState {
53+
MemoryRegion io;
54+
} LPCSEGAState;
55+
56+
typedef struct ISALPCSEGAState {
57+
ISADevice parent_obj;
58+
59+
bool sysopt;
60+
uint16_t iobase;
61+
LPCSEGAState state;
62+
} ISALPCSEGAState;
63+
64+
static void lpcsega_io_write(void *opaque, hwaddr addr, uint64_t val,
65+
unsigned int size)
66+
{
67+
DPRINTF("lpcsega io write 0x%02" HWADDR_PRIx " = 0x%02" PRIx64 "\n", addr, val);
68+
}
69+
70+
static uint64_t lpcsega_io_read(void *opaque, hwaddr addr, unsigned int size)
71+
{
72+
uint32_t val = 0;
73+
74+
switch (addr) {
75+
case SEGA_CHIP_REVISION:
76+
val = SEGA_CHIP_REVISION_ASIC_CHIP_ID;
77+
break;
78+
case SEGA_DIMM_SIZE:
79+
val = SEGA_DIMM_SIZE_128M;
80+
break;
81+
}
82+
83+
DPRINTF("lpcsega io read 0x%02" HWADDR_PRIx " -> 0x%02x\n", addr, val);
84+
85+
return val;
86+
}
87+
88+
static const MemoryRegionOps lpcsega_io_ops = {
89+
.read = lpcsega_io_read,
90+
.write = lpcsega_io_write,
91+
.valid = {
92+
.min_access_size = 2,
93+
.max_access_size = 2,
94+
},
95+
};
96+
97+
static void lpcsega_realize(DeviceState *dev, Error **errp)
98+
{
99+
ISADevice *isadev = ISA_DEVICE(dev);
100+
ISALPCSEGAState *isa = ISA_LPCSEGA_DEVICE(isadev);
101+
LPCSEGAState *s = &isa->state;
102+
103+
memory_region_init_io(&s->io, OBJECT(dev), &lpcsega_io_ops, s,
104+
"lpcsega-io", 0x100);
105+
isa_register_ioport(isadev, &s->io, 0x4000);
106+
}
107+
108+
static Property lpcsega_properties[] = {
109+
DEFINE_PROP_BOOL("sysopt", ISALPCSEGAState, sysopt, false),
110+
DEFINE_PROP_END_OF_LIST(),
111+
};
112+
113+
static void lpcsega_class_init(ObjectClass *klass, void *data)
114+
{
115+
DeviceClass *dc = DEVICE_CLASS(klass);
116+
117+
dc->realize = lpcsega_realize;
118+
device_class_set_props(dc, lpcsega_properties);
119+
}
120+
121+
static void lpcsega_initfn(Object *o)
122+
{
123+
}
124+
125+
static const TypeInfo lpcsega_type_info = {
126+
.name = TYPE_ISA_LPCSEGA_DEVICE,
127+
.parent = TYPE_ISA_DEVICE,
128+
.instance_init = lpcsega_initfn,
129+
.instance_size = sizeof(ISALPCSEGAState),
130+
.class_init = lpcsega_class_init,
131+
};
132+
133+
static void lpcsega_register_types(void)
134+
{
135+
type_register_static(&lpcsega_type_info);
136+
}
137+
138+
type_init(lpcsega_register_types)

‎hw/xbox/meson.build

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5,6 +5,7 @@ specific_ss.add(files(
55
# 'chihiro.c',
66
'eeprom_generation.c',
77
'lpc47m157.c',
8+
'lpcsega.c',
89
'nvnet.c',
910
'smbus_adm1032.c',
1011
'smbus_cx25871.c',

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