Skip to content

Commit a21bd7f

Browse files
author
Eric Botcazou
committed
Fix PR target/109140
This is a regression present on the mainline and 12 branch at -O2, but the issue is related to vectorization so was present at -O3 in earlier versions. The vcondu expander that was added for VIS 3 more than a decade ago does not fully work, because it does not filter out the unsigned condition codes (the instruction is an UNSPEC that accepts only signed condition codes). While I was at it, I also added the missing vcond and vcondu expanders for the new comparison instructions that were added in VIS 4. gcc/ PR target/109140 * config/sparc/sparc.cc (sparc_expand_vcond): Call signed_condition on operand gcc-mirror#3 to get the final condition code. Use std::swap. * config/sparc/sparc.md (vcondv8qiv8qi): New VIS 4 expander. (fucmp<gcond:code>8<P:mode>_vis): Move around. (fpcmpu<gcond:code><GCM:gcm_name><P:mode>_vis): Likewise. (vcondu<GCM:mode><GCM:mode>): New VIS 4 expander. gcc/testsuite/ * gcc.target/sparc/20230328-1.c: New test. * gcc.target/sparc/20230328-2.c: Likewise. * gcc.target/sparc/20230328-3.c: Likewise. * gcc.target/sparc/20230328-4.c: Likewise.
1 parent 5cea00d commit a21bd7f

File tree

6 files changed

+122
-22
lines changed

6 files changed

+122
-22
lines changed

‎gcc/config/sparc/sparc.cc

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -13662,18 +13662,16 @@ sparc_expand_conditional_move (machine_mode mode, rtx *operands)
1366213662
void
1366313663
sparc_expand_vcond (machine_mode mode, rtx *operands, int ccode, int fcode)
1366413664
{
13665+
enum rtx_code code = signed_condition (GET_CODE (operands[3]));
1366513666
rtx mask, cop0, cop1, fcmp, cmask, bshuf, gsr;
13666-
enum rtx_code code = GET_CODE (operands[3]);
1366713667

1366813668
mask = gen_reg_rtx (Pmode);
1366913669
cop0 = operands[4];
1367013670
cop1 = operands[5];
1367113671
if (code == LT || code == GE)
1367213672
{
13673-
rtx t;
13674-
1367513673
code = swap_condition (code);
13676-
t = cop0; cop0 = cop1; cop1 = t;
13674+
std::swap (cop0, cop1);
1367713675
}
1367813676

1367913677
gsr = gen_rtx_REG (DImode, SPARC_GSR_REG);

‎gcc/config/sparc/sparc.md

Lines changed: 44 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -9033,6 +9033,50 @@ visl")
90339033
DONE;
90349034
})
90359035

9036+
(define_expand "vcondv8qiv8qi"
9037+
[(match_operand:V8QI 0 "register_operand" "")
9038+
(match_operand:V8QI 1 "register_operand" "")
9039+
(match_operand:V8QI 2 "register_operand" "")
9040+
(match_operator 3 ""
9041+
[(match_operand:V8QI 4 "register_operand" "")
9042+
(match_operand:V8QI 5 "register_operand" "")])]
9043+
"TARGET_VIS4"
9044+
{
9045+
sparc_expand_vcond (V8QImode, operands, UNSPEC_CMASK8, UNSPEC_FCMP);
9046+
DONE;
9047+
})
9048+
9049+
(define_insn "fucmp<gcond:code>8<P:mode>_vis"
9050+
[(set (match_operand:P 0 "register_operand" "=r")
9051+
(unspec:P [(gcond:V8QI (match_operand:V8QI 1 "register_operand" "e")
9052+
(match_operand:V8QI 2 "register_operand" "e"))]
9053+
UNSPEC_FUCMP))]
9054+
"TARGET_VIS3"
9055+
"fucmp<gcond:code>8\t%1, %2, %0"
9056+
[(set_attr "type" "viscmp")])
9057+
9058+
(define_insn "fpcmpu<gcond:code><GCM:gcm_name><P:mode>_vis"
9059+
[(set (match_operand:P 0 "register_operand" "=r")
9060+
(unspec:P [(gcond:GCM (match_operand:GCM 1 "register_operand" "e")
9061+
(match_operand:GCM 2 "register_operand" "e"))]
9062+
UNSPEC_FUCMP))]
9063+
"TARGET_VIS4"
9064+
"fpcmpu<gcond:code><GCM:gcm_name>\t%1, %2, %0"
9065+
[(set_attr "type" "viscmp")])
9066+
9067+
(define_expand "vcondu<GCM:mode><GCM:mode>"
9068+
[(match_operand:GCM 0 "register_operand" "")
9069+
(match_operand:GCM 1 "register_operand" "")
9070+
(match_operand:GCM 2 "register_operand" "")
9071+
(match_operator 3 ""
9072+
[(match_operand:GCM 4 "register_operand" "")
9073+
(match_operand:GCM 5 "register_operand" "")])]
9074+
"TARGET_VIS4"
9075+
{
9076+
sparc_expand_vcond (<MODE>mode, operands, UNSPEC_CMASK<gcm_name>, UNSPEC_FUCMP);
9077+
DONE;
9078+
})
9079+
90369080
(define_expand "vconduv8qiv8qi"
90379081
[(match_operand:V8QI 0 "register_operand" "")
90389082
(match_operand:V8QI 1 "register_operand" "")
@@ -9351,24 +9395,6 @@ visl")
93519395
[(set_attr "type" "fga")
93529396
(set_attr "subtype" "other")])
93539397

9354-
(define_insn "fucmp<gcond:code>8<P:mode>_vis"
9355-
[(set (match_operand:P 0 "register_operand" "=r")
9356-
(unspec:P [(gcond:V8QI (match_operand:V8QI 1 "register_operand" "e")
9357-
(match_operand:V8QI 2 "register_operand" "e"))]
9358-
UNSPEC_FUCMP))]
9359-
"TARGET_VIS3"
9360-
"fucmp<gcond:code>8\t%1, %2, %0"
9361-
[(set_attr "type" "viscmp")])
9362-
9363-
(define_insn "fpcmpu<gcond:code><GCM:gcm_name><P:mode>_vis"
9364-
[(set (match_operand:P 0 "register_operand" "=r")
9365-
(unspec:P [(gcond:GCM (match_operand:GCM 1 "register_operand" "e")
9366-
(match_operand:GCM 2 "register_operand" "e"))]
9367-
UNSPEC_FUCMP))]
9368-
"TARGET_VIS4"
9369-
"fpcmpu<gcond:code><GCM:gcm_name>\t%1, %2, %0"
9370-
[(set_attr "type" "viscmp")])
9371-
93729398
(define_insn "*naddsf3"
93739399
[(set (match_operand:SF 0 "register_operand" "=f")
93749400
(neg:SF (plus:SF (match_operand:SF 1 "register_operand" "f")

‎gcc/testsuite/gcc.target/sparc/20230328-1.c

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,19 @@
1+
/* PR target/109140 */
2+
/* { dg-do compile } */
3+
/* { dg-options "-O3 -mvis3 -std=c99" } */
4+
5+
#define TYPE unsigned char
6+
7+
struct S { TYPE ub[8]; };
8+
9+
struct S s;
10+
11+
TYPE v;
12+
13+
void foo (void)
14+
{
15+
for (int i = 0; i < 8; i++)
16+
s.ub[i] = s.ub[i] > v;
17+
}
18+
19+
/* { dg-final { scan-assembler "fucmpgt8\t%" } } */

‎gcc/testsuite/gcc.target/sparc/20230328-2.c

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,19 @@
1+
/* PR target/109140 */
2+
/* { dg-do compile } */
3+
/* { dg-options "-O3 -mvis4 -std=c99" } */
4+
5+
#define TYPE char
6+
7+
struct S { TYPE ub[8]; };
8+
9+
struct S s;
10+
11+
TYPE v;
12+
13+
void foo (void)
14+
{
15+
for (int i = 0; i < 8; i++)
16+
s.ub[i] = s.ub[i] > v;
17+
}
18+
19+
/* { dg-final { scan-assembler "fpcmpgt8\t%" } } */

‎gcc/testsuite/gcc.target/sparc/20230328-3.c

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,19 @@
1+
/* PR target/109140 */
2+
/* { dg-do compile } */
3+
/* { dg-options "-O3 -mvis4 -std=c99" } */
4+
5+
#define TYPE unsigned short
6+
7+
struct S { TYPE ub[4]; };
8+
9+
struct S s;
10+
11+
TYPE v;
12+
13+
void foo (void)
14+
{
15+
for (int i = 0; i < 4; i++)
16+
s.ub[i] = s.ub[i] > v;
17+
}
18+
19+
/* { dg-final { scan-assembler "fpcmpugt16\t%" } } */

‎gcc/testsuite/gcc.target/sparc/20230328-4.c

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,19 @@
1+
/* PR target/109140 */
2+
/* { dg-do compile } */
3+
/* { dg-options "-O3 -mvis3 -std=c99" } */
4+
5+
#define TYPE short
6+
7+
struct S { TYPE ub[4]; };
8+
9+
struct S s;
10+
11+
TYPE v;
12+
13+
void foo (void)
14+
{
15+
for (int i = 0; i < 4; i++)
16+
s.ub[i] = s.ub[i] > v;
17+
}
18+
19+
/* { dg-final { scan-assembler "fcmpgt16\t%" } } */

0 commit comments

Comments
 (0)