From 5788579b1b32068b2418001d3402e4ad6d3c81bc Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 22 Jan 2024 14:30:48 -0800 Subject: [PATCH] Fix broken GCD example --- docs/Customization/Keys-Traits-Configs.rst | 4 +- docs/Customization/MMIO-Peripherals.rst | 8 +--- .../chipyard/src/main/scala/DigitalTop.scala | 1 - .../chipyard/src/main/scala/example/GCD.scala | 39 ++++++++----------- 4 files changed, 20 insertions(+), 32 deletions(-) diff --git a/docs/Customization/Keys-Traits-Configs.rst b/docs/Customization/Keys-Traits-Configs.rst index 7b6d565b8e..b91e47480a 100644 --- a/docs/Customization/Keys-Traits-Configs.rst +++ b/docs/Customization/Keys-Traits-Configs.rst @@ -40,12 +40,12 @@ Top-level traits specify that the ``DigitalTop`` has been parameterized to read Top-level traits should be defined and documented in subprojects, alongside their corresponding keys. The traits should then be added to the ``DigitalTop`` being used by Chipyard. -Below we see the traits for the GCD example. The Lazy trait connects the GCD module to the Diplomacy graph, while the Implementation trait causes the ``DigitalTop`` to instantiate an additional port and concretely connect it to the GCD module. +Below we see the traits for the GCD example. The Lazy trait connects the GCD module to the Diplomacy graph. .. literalinclude:: ../../generators/chipyard/src/main/scala/example/GCD.scala :language: scala :start-after: DOC include start: GCD lazy trait - :end-before: DOC include end: GCD imp trait + :end-before: DOC include end: GCD lazy trait These traits are added to the default ``DigitalTop`` in Chipyard. diff --git a/docs/Customization/MMIO-Peripherals.rst b/docs/Customization/MMIO-Peripherals.rst index 4d0ba16a21..f3f2bc8ddc 100644 --- a/docs/Customization/MMIO-Peripherals.rst +++ b/docs/Customization/MMIO-Peripherals.rst @@ -79,13 +79,7 @@ Register routers have a TileLink node simply named "node", which we can hook up This will automatically add address map and device tree entries for the peripheral. Also observe how we have to place additional AXI4 buffers and converters for the AXI4 version of this peripheral. -For peripherals which instantiate a concrete module, or which need to be connected to concrete IOs or wires, a matching concrete trait is necessary. We will make our GCD example output a ``gcd_busy`` signal as a top-level port to demonstrate. In the concrete module implementation trait, we instantiate the top level IO (a concrete object) and wire it to the IO of our lazy module. - - -.. literalinclude:: ../../generators/chipyard/src/main/scala/example/GCD.scala - :language: scala - :start-after: DOC include start: GCD imp trait - :end-before: DOC include end: GCD imp trait +Peripherals which expose I/O can use `InModuleBody` to punch their I/O to the `DigitalTop` module. Constructing the DigitalTop and Config -------------------------------------- diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala index 3a0e2fa901..ec8ffd9980 100644 --- a/generators/chipyard/src/main/scala/DigitalTop.scala +++ b/generators/chipyard/src/main/scala/DigitalTop.scala @@ -48,6 +48,5 @@ class DigitalTopModule[+L <: DigitalTop](l: L) extends ChipyardSystemModule(l) with sifive.blocks.devices.gpio.HasPeripheryGPIOModuleImp with sifive.blocks.devices.spi.HasPeripherySPIFlashModuleImp with sifive.blocks.devices.spi.HasPeripherySPIModuleImp - with chipyard.example.CanHavePeripheryGCDModuleImp with freechips.rocketchip.util.DontTouch // DOC include end: DigitalTop diff --git a/generators/chipyard/src/main/scala/example/GCD.scala b/generators/chipyard/src/main/scala/example/GCD.scala index 1c1d2e2fe8..24c9918758 100644 --- a/generators/chipyard/src/main/scala/example/GCD.scala +++ b/generators/chipyard/src/main/scala/example/GCD.scala @@ -161,10 +161,10 @@ trait CanHavePeripheryGCD { this: BaseSubsystem => private val portName = "gcd" // Only build if we are using the TL (nonAXI4) version - val gcd = p(GCDKey) match { + val gcd_busy = p(GCDKey) match { case Some(params) => { - if (params.useAXI4) { - val gcd = LazyModule(new GCDAXI4(params, pbus.beatBytes)(p)) + val gcd = if (params.useAXI4) { + val gcd = pbus { LazyModule(new GCDAXI4(params, pbus.beatBytes)(p)) } pbus.coupleTo(portName) { gcd.node := AXI4Buffer () := @@ -172,34 +172,29 @@ trait CanHavePeripheryGCD { this: BaseSubsystem => // toVariableWidthSlave doesn't use holdFirstDeny, which TLToAXI4() needsx TLFragmenter(pbus.beatBytes, pbus.blockBytes, holdFirstDeny = true) := _ } - Some(gcd) + gcd } else { - val gcd = LazyModule(new GCDTL(params, pbus.beatBytes)(p)) + val gcd = pbus { LazyModule(new GCDTL(params, pbus.beatBytes)(p)) } pbus.coupleTo(portName) { gcd.node := TLFragmenter(pbus.beatBytes, pbus.blockBytes) := _ } - Some(gcd) + gcd } + val pbus_io = pbus { InModuleBody { + val busy = IO(Output(Bool())) + busy := gcd.module.io.gcd_busy + busy + }} + val gcd_busy = InModuleBody { + val busy = IO(Output(Bool())).suggestName("gcd_busy") + busy := pbus_io + busy + } + Some(gcd_busy) } case None => None } } // DOC include end: GCD lazy trait -// DOC include start: GCD imp trait -trait CanHavePeripheryGCDModuleImp extends LazyRawModuleImp { - val outer: CanHavePeripheryGCD - val gcd_busy = outer.gcd match { - case Some(gcd) => { - val busy = IO(Output(Bool())) - busy := gcd.module.io.gcd_busy - Some(busy) - } - case None => None - } -} - -// DOC include end: GCD imp trait - - // DOC include start: GCD config fragment class WithGCD(useAXI4: Boolean = false, useBlackBox: Boolean = false) extends Config((site, here, up) => { case GCDKey => Some(GCDParams(useAXI4 = useAXI4, useBlackBox = useBlackBox))