From dfb991770a9c022425e90dad31ec4354dfae94e7 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 19 Jul 2023 18:41:49 -0700 Subject: [PATCH 1/2] Fix FIFO-fixing Fragmenter infront of FIFO-fixer needs to track way too many source-Ids --- .../chipyard/src/main/scala/clocking/ClockBinders.scala | 6 +++--- .../chipyard/src/main/scala/clocking/HasChipyardPRCI.scala | 5 ++--- 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/generators/chipyard/src/main/scala/clocking/ClockBinders.scala b/generators/chipyard/src/main/scala/clocking/ClockBinders.scala index 3c2bab0424..d031b0db46 100644 --- a/generators/chipyard/src/main/scala/clocking/ClockBinders.scala +++ b/generators/chipyard/src/main/scala/clocking/ClockBinders.scala @@ -38,9 +38,9 @@ class WithPLLSelectorDividerClockGenerator extends OverrideLazyIOBinder({ val clockSelector = system.prci_ctrl_domain { LazyModule(new TLClockSelector(baseAddress + 0x30000, tlbus.beatBytes)) } val pllCtrl = system.prci_ctrl_domain { LazyModule(new FakePLLCtrl (baseAddress + 0x40000, tlbus.beatBytes)) } - clockDivider.tlNode := system.prci_ctrl_bus.get - clockSelector.tlNode := system.prci_ctrl_bus.get - pllCtrl.tlNode := system.prci_ctrl_bus.get + clockDivider.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := system.prci_ctrl_bus.get + clockSelector.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := system.prci_ctrl_bus.get + pllCtrl.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := system.prci_ctrl_bus.get system.allClockGroupsNode := clockDivider.clockNode := clockSelector.clockNode diff --git a/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala b/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala index 906a631dcd..356a04329d 100644 --- a/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala +++ b/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala @@ -42,7 +42,6 @@ trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesTiles => val prci_ctrl_bus = Option.when(prciParams.generatePRCIXBar) { prci_ctrl_domain { TLXbar() } } prci_ctrl_bus.foreach(xbar => tlbus.coupleTo("prci_ctrl") { (xbar := TLFIFOFixer(TLFIFOFixer.all) - := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := TLBuffer() := _) }) @@ -87,13 +86,13 @@ trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesTiles => } val tileClockGater = Option.when(prciParams.enableTileClockGating) { prci_ctrl_domain { val clock_gater = LazyModule(new TileClockGater(prciParams.baseAddress + 0x00000, tlbus.beatBytes)) - clock_gater.tlNode := prci_ctrl_bus.get + clock_gater.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := prci_ctrl_bus.get clock_gater } } val tileResetSetter = Option.when(prciParams.enableTileResetSetting) { prci_ctrl_domain { val reset_setter = LazyModule(new TileResetSetter(prciParams.baseAddress + 0x10000, tlbus.beatBytes, tile_prci_domains.map(_.tile_reset_domain.clockNode.portParams(0).name.get), Nil)) - reset_setter.tlNode := prci_ctrl_bus.get + reset_setter.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := prci_ctrl_bus.get reset_setter } } From 387b51ef95537a46f68bcc35e4b5b03948e34cee Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 20 Jul 2023 10:12:40 -0700 Subject: [PATCH 2/2] Put ClockBinder Fragmenters in the correct clock domain --- .../chipyard/src/main/scala/clocking/ClockBinders.scala | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/generators/chipyard/src/main/scala/clocking/ClockBinders.scala b/generators/chipyard/src/main/scala/clocking/ClockBinders.scala index d031b0db46..412dd43df0 100644 --- a/generators/chipyard/src/main/scala/clocking/ClockBinders.scala +++ b/generators/chipyard/src/main/scala/clocking/ClockBinders.scala @@ -38,9 +38,9 @@ class WithPLLSelectorDividerClockGenerator extends OverrideLazyIOBinder({ val clockSelector = system.prci_ctrl_domain { LazyModule(new TLClockSelector(baseAddress + 0x30000, tlbus.beatBytes)) } val pllCtrl = system.prci_ctrl_domain { LazyModule(new FakePLLCtrl (baseAddress + 0x40000, tlbus.beatBytes)) } - clockDivider.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := system.prci_ctrl_bus.get - clockSelector.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := system.prci_ctrl_bus.get - pllCtrl.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := system.prci_ctrl_bus.get + clockDivider.tlNode := system.prci_ctrl_domain { TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := system.prci_ctrl_bus.get } + clockSelector.tlNode := system.prci_ctrl_domain { TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := system.prci_ctrl_bus.get } + pllCtrl.tlNode := system.prci_ctrl_domain { TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := system.prci_ctrl_bus.get } system.allClockGroupsNode := clockDivider.clockNode := clockSelector.clockNode