From f1c24383b94918ae1cd8a078bd10237e286ac019 Mon Sep 17 00:00:00 2001 From: Ella Schwarz Date: Wed, 8 Mar 2023 10:14:57 -0800 Subject: [PATCH 1/2] Add graphml visualization section --- docs/Simulation/Software-RTL-Simulation.rst | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/docs/Simulation/Software-RTL-Simulation.rst b/docs/Simulation/Software-RTL-Simulation.rst index 5fd3ee7527..dbd5d92c53 100644 --- a/docs/Simulation/Software-RTL-Simulation.rst +++ b/docs/Simulation/Software-RTL-Simulation.rst @@ -188,6 +188,16 @@ An open-source vcd-capable waveform viewer is `GTKWave `__. + +The ``*.graphml`` file will be located in ``generated-src/<...>--/``. Open the file in the graph viewer. +To get a clearer view of the SoC, switch to "hierarchical" view. For yEd, this would be done by selecting ``layout`` -> ``hierarchical``, and then choosing "Ok" without changing any settings. + .. _sw-sim-verilator-opts: Additional Verilator Options From c7ea3b6a47cbcb2a6eff55e04cb1005aa82b6770 Mon Sep 17 00:00:00 2001 From: Ella Schwarz Date: Wed, 8 Mar 2023 13:01:42 -0800 Subject: [PATCH 2/2] Minor clarification in visualization section --- docs/Simulation/Software-RTL-Simulation.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/Simulation/Software-RTL-Simulation.rst b/docs/Simulation/Software-RTL-Simulation.rst index dbd5d92c53..d62f6f1cd5 100644 --- a/docs/Simulation/Software-RTL-Simulation.rst +++ b/docs/Simulation/Software-RTL-Simulation.rst @@ -191,11 +191,11 @@ If you have Synopsys licenses, we recommend using the DVE waveform viewer. Visualizing Chipyard SoCs -------------------------- -During the creation of the simulation executable, a graphml file is emitted that will allow you to visualize your Chipyard SoC in a graph format. +During verilog creation, a graphml file is emitted that will allow you to visualize your Chipyard SoC as a diplomacy graph. To view the graph, first download a viewer such as `yEd `__. -The ``*.graphml`` file will be located in ``generated-src/<...>--/``. Open the file in the graph viewer. +The ``*.graphml`` file will be located in ``generated-src/<...>/``. Open the file in the graph viewer. To get a clearer view of the SoC, switch to "hierarchical" view. For yEd, this would be done by selecting ``layout`` -> ``hierarchical``, and then choosing "Ok" without changing any settings. .. _sw-sim-verilator-opts: