From 5509771558e79b12b7183d742dd4a8e0dca0ffdf Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Wed, 24 Jun 2015 14:32:21 +0300 Subject: [PATCH 01/26] mmc: block: don't use parameter prefix if built as module It's excessive to use prefix for the parameters when you do modprobe mmc-block mmcblk.perdev_minors=16 Make this available only for built-in case. Change-Id: I85b3ab146cca341795315fb5578fec8ceda3d30c Signed-off-by: Andy Shevchenko Signed-off-by: Ulf Hansson --- drivers/mmc/card/block.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/mmc/card/block.c b/drivers/mmc/card/block.c index 2206d4477dbbdb..347821a4e51e67 100644 --- a/drivers/mmc/card/block.c +++ b/drivers/mmc/card/block.c @@ -48,10 +48,13 @@ #include "queue.h" MODULE_ALIAS("mmc:block"); + +#ifdef KERNEL #ifdef MODULE_PARAM_PREFIX #undef MODULE_PARAM_PREFIX #endif #define MODULE_PARAM_PREFIX "mmcblk." +#endif #define INAND_CMD38_ARG_EXT_CSD 113 #define INAND_CMD38_ARG_ERASE 0x00 From 127199a6bfe0364a28f80d5571950bb5ec0b3e53 Mon Sep 17 00:00:00 2001 From: Anand Moon Date: Sun, 12 Jul 2015 18:41:20 +0530 Subject: [PATCH 02/26] regulator: s2mps11: Added shutdown function to poweroff Added .shutdown function to s2mps11 to help poweroff the board successfully. The device driver clears the register to turn off the PMIC. s2mps11-pmic: S2MPS11_REG_CTRL1 reg value 16:00000000000000000000000000010000 Console log. * Unmounting temporary filesystems... [ OK ] * Deactivating swap... [ OK ] * Unmounting local filesystems... [ OK ] * Will now halt [ 209.020280] reboot: Power down [ 209.122039] Power down failed, please power off system manually. Change-Id: If6ea0dec154b00ceeaaddbac393c67dc35c26279 Signed-off-by: Anand Moon --- drivers/regulator/s2mps11.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/regulator/s2mps11.c b/drivers/regulator/s2mps11.c index d838e77dd94785..5244844c17b4f9 100644 --- a/drivers/regulator/s2mps11.c +++ b/drivers/regulator/s2mps11.c @@ -1220,6 +1220,31 @@ static int s2mps11_pmic_probe(struct platform_device *pdev) return ret; } +static void s2mps11_pmic_shutdown(struct platform_device *pdev) +{ + struct sec_pmic_dev *iodev = dev_get_drvdata(pdev->dev.parent); + unsigned int reg_val, ret; + + ret = regmap_read(iodev->regmap_pmic, S2MPS11_REG_CTRL1, ®_val); + if (ret < 0) { + dev_crit(&pdev->dev, "could not read S2MPS11_REG_CTRL1 value\n"); + } else { + /* + * s2mps11-pmic: S2MPS11_REG_CTRL1 reg value + * is 00000000000000000000000000010000 + * clear the S2MPS11_REG_CTRL1 0x10 value to shutdown. + */ + if (reg_val & BIT(4)) { + ret = regmap_update_bits(iodev->regmap_pmic, + S2MPS11_REG_CTRL1, + BIT(4), BIT(0)); + if (ret) + dev_crit(&pdev->dev, + "could not write S2MPS11_REG_CTRL1 value\n"); + } + } +} + static const struct platform_device_id s2mps11_pmic_id[] = { { "s2mps11-regulator", S2MPS11X}, { "s2mps13-regulator", S2MPS13X}, @@ -1235,6 +1260,7 @@ static struct platform_driver s2mps11_pmic_driver = { .name = "s2mps11-pmic", }, .probe = s2mps11_pmic_probe, + .shutdown = s2mps11_pmic_shutdown, .id_table = s2mps11_pmic_id, }; From 78a3e71506f553417f9489457a9be8b33ab21486 Mon Sep 17 00:00:00 2001 From: Vivek Gautam Date: Fri, 31 Oct 2014 18:56:29 +0530 Subject: [PATCH 03/26] phy: exynos5-usbdrd: Calibrate LOS levels for exynos5420/5800 Adding phy calibration sequence for USB 3.0 DRD PHY present on Exynos5420/5800 systems. This calibration facilitates setting certain PHY parameters viz. the Loss-of-Signal (LOS) Detector Threshold Level, as well as Tx-Vboost-Level for Super-Speed operations. Additionally we also set proper time to wait for RxDetect measurement, for desired PHY reference clock, so as to solve issue with enumeration of few USB 3.0 devices, like Samsung SUM-TSB16S 3.0 USB drive on the controller. We are using CR_port for this purpose to send required data to override the LOS values. On testing with USB 3.0 devices on USB 3.0 port present on SMDK5420, and peach-pit boards should see following message: usb 2-1: new SuperSpeed USB device number 2 using xhci-hcd and without this patch, should see below shown message: usb 1-1: new high-speed USB device number 2 using xhci-hcd [Also removed unnecessary extra lines in the register macro definitions] Change-Id: I81dcd0dfa057b6b63e18578f2bc9dc276cc5b74a Signed-off-by: Vivek Gautam --- drivers/phy/phy-exynos5-usbdrd.c | 219 ++++++++++++++++++++++++++++--- 1 file changed, 203 insertions(+), 16 deletions(-) diff --git a/drivers/phy/phy-exynos5-usbdrd.c b/drivers/phy/phy-exynos5-usbdrd.c index 20696f53303f07..70ef7e37e02133 100644 --- a/drivers/phy/phy-exynos5-usbdrd.c +++ b/drivers/phy/phy-exynos5-usbdrd.c @@ -37,13 +37,11 @@ /* EXYNOS5: USB 3.0 DRD PHY registers */ #define EXYNOS5_DRD_LINKSYSTEM 0x04 - #define LINKSYSTEM_FLADJ_MASK (0x3f << 1) #define LINKSYSTEM_FLADJ(_x) ((_x) << 1) #define LINKSYSTEM_XHCI_VERSION_CONTROL BIT(27) #define EXYNOS5_DRD_PHYUTMI 0x08 - #define PHYUTMI_OTGDISABLE BIT(6) #define PHYUTMI_FORCESUSPEND BIT(1) #define PHYUTMI_FORCESLEEP BIT(0) @@ -51,26 +49,20 @@ #define EXYNOS5_DRD_PHYPIPE 0x0c #define EXYNOS5_DRD_PHYCLKRST 0x10 - #define PHYCLKRST_EN_UTMISUSPEND BIT(31) - #define PHYCLKRST_SSC_REFCLKSEL_MASK (0xff << 23) #define PHYCLKRST_SSC_REFCLKSEL(_x) ((_x) << 23) - #define PHYCLKRST_SSC_RANGE_MASK (0x03 << 21) #define PHYCLKRST_SSC_RANGE(_x) ((_x) << 21) - #define PHYCLKRST_SSC_EN BIT(20) #define PHYCLKRST_REF_SSP_EN BIT(19) #define PHYCLKRST_REF_CLKDIV2 BIT(18) - #define PHYCLKRST_MPLL_MULTIPLIER_MASK (0x7f << 11) #define PHYCLKRST_MPLL_MULTIPLIER_100MHZ_REF (0x19 << 11) #define PHYCLKRST_MPLL_MULTIPLIER_50M_REF (0x32 << 11) #define PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF (0x68 << 11) #define PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF (0x7d << 11) #define PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF (0x02 << 11) - #define PHYCLKRST_FSEL_UTMI_MASK (0x7 << 5) #define PHYCLKRST_FSEL_PIPE_MASK (0x7 << 8) #define PHYCLKRST_FSEL(_x) ((_x) << 5) @@ -78,46 +70,68 @@ #define PHYCLKRST_FSEL_PAD_24MHZ (0x2a << 5) #define PHYCLKRST_FSEL_PAD_20MHZ (0x31 << 5) #define PHYCLKRST_FSEL_PAD_19_2MHZ (0x38 << 5) - #define PHYCLKRST_RETENABLEN BIT(4) - #define PHYCLKRST_REFCLKSEL_MASK (0x03 << 2) #define PHYCLKRST_REFCLKSEL_PAD_REFCLK (0x2 << 2) #define PHYCLKRST_REFCLKSEL_EXT_REFCLK (0x3 << 2) - #define PHYCLKRST_PORTRESET BIT(1) #define PHYCLKRST_COMMONONN BIT(0) #define EXYNOS5_DRD_PHYREG0 0x14 +#define PHYREG0_SSC_REF_CLK_SEL BIT(21) +#define PHYREG0_SSC_RANGE BIT(20) +#define PHYREG0_CR_WRITE BIT(19) +#define PHYREG0_CR_READ BIT(18) +#define PHYREG0_CR_DATA_IN(_x) ((_x) << 2) +#define PHYREG0_CR_CAP_DATA BIT(1) +#define PHYREG0_CR_CAP_ADDR BIT(0) + #define EXYNOS5_DRD_PHYREG1 0x18 +#define PHYREG1_CR_DATA_OUT(_x) ((_x) << 1) +#define PHYREG1_CR_ACK BIT(0) #define EXYNOS5_DRD_PHYPARAM0 0x1c - #define PHYPARAM0_REF_USE_PAD BIT(31) #define PHYPARAM0_REF_LOSLEVEL_MASK (0x1f << 26) #define PHYPARAM0_REF_LOSLEVEL (0x9 << 26) #define EXYNOS5_DRD_PHYPARAM1 0x20 - #define PHYPARAM1_PCS_TXDEEMPH_MASK (0x1f << 0) #define PHYPARAM1_PCS_TXDEEMPH (0x1c) #define EXYNOS5_DRD_PHYTERM 0x24 #define EXYNOS5_DRD_PHYTEST 0x28 - #define PHYTEST_POWERDOWN_SSP BIT(3) #define PHYTEST_POWERDOWN_HSP BIT(2) #define EXYNOS5_DRD_PHYADP 0x2c #define EXYNOS5_DRD_PHYUTMICLKSEL 0x30 - #define PHYUTMICLKSEL_UTMI_CLKSEL BIT(2) #define EXYNOS5_DRD_PHYRESUME 0x34 #define EXYNOS5_DRD_LINKPORT 0x44 +/* USB 3.0 DRD PHY SS Function Control Reg; accessed by CR_PORT */ +#define EXYNOS5_DRD_PHYSS_LOSLEVEL_OVRD_IN (0x15) +#define LOSLEVEL_OVRD_IN_LOS_BIAS_5420 (0x5 << 13) +#define LOSLEVEL_OVRD_IN_LOS_BIAS_DEFAULT (0x0 << 13) +#define LOSLEVEL_OVRD_IN_EN (0x1 << 10) +#define LOSLEVEL_OVRD_IN_LOS_LEVEL_DEFAULT (0x9 << 0) + +#define EXYNOS5_DRD_PHYSS_TX_VBOOSTLEVEL_OVRD_IN (0x12) +#define TX_VBOOSTLEVEL_OVRD_IN_VBOOST_5420 (0x5 << 13) +#define TX_VBOOSTLEVEL_OVRD_IN_VBOOST_DEFAULT (0x4 << 13) + +#define EXYNOS5_DRD_PHYSS_LANE0_TX_DEBUG (0x1010) +#define LANE0_TX_DEBUG_RXDET_MEAS_TIME_19M2_20M (0x4 << 4) +#define LANE0_TX_DEBUG_RXDET_MEAS_TIME_24M (0x8 << 4) +#define LANE0_TX_DEBUG_RXDET_MEAS_TIME_25M_26M (0x8 << 4) +#define LANE0_TX_DEBUG_RXDET_MEAS_TIME_48M_50M_52M (0x20 << 4) +#define LANE0_TX_DEBUG_RXDET_MEAS_TIME_62M5 (0x20 << 4) +#define LANE0_TX_DEBUG_RXDET_MEAS_TIME_96M_100M (0x40 << 4) + #define KHZ 1000 #define MHZ (KHZ * KHZ) @@ -135,6 +149,7 @@ struct exynos5_usbdrd_phy_config { void (*phy_isol)(struct phy_usb_instance *inst, u32 on); void (*phy_init)(struct exynos5_usbdrd_phy *phy_drd); unsigned int (*set_refclk)(struct phy_usb_instance *inst); + int (*phy_calibrate)(struct phy_usb_instance *inst); }; struct exynos5_usbdrd_phy_drvdata { @@ -142,6 +157,7 @@ struct exynos5_usbdrd_phy_drvdata { u32 pmu_offset_usbdrd0_phy; u32 pmu_offset_usbdrd1_phy; bool has_common_clk_gate; + int (*phy_exynos_calibrate)(struct exynos5_usbdrd_phy *phy_drd); }; /** @@ -408,9 +424,21 @@ static int exynos5_usbdrd_phy_init(struct phy *phy) reg &= ~PHYCLKRST_PORTRESET; writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST); + /* + * Calibrate some of the PHY parameters, using cr_port control + * register, which are internal to PHY and are not exposed + * directly to the outside world for configuring. + */ + if (inst->phy_cfg->phy_calibrate) { + ret = inst->phy_cfg->phy_calibrate(inst); + if (ret) + dev_err(phy_drd->dev, + "Exiting init: Failed to calibrate PHY\n"); + } + clk_disable_unprepare(phy_drd->clk); - return 0; + return ret; } static int exynos5_usbdrd_phy_exit(struct phy *phy) @@ -526,6 +554,163 @@ static int exynos5_usbdrd_phy_power_off(struct phy *phy) return 0; } +static int crport_handshake(struct exynos5_usbdrd_phy *phy_drd, + u32 val, u32 cmd) +{ + u32 usec = 100; + unsigned int result; + + writel(val | cmd, phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0); + + do { + result = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYREG1); + if (result & PHYREG1_CR_ACK) + break; + + udelay(1); + } while (usec-- > 0); + + if (!usec) { + dev_err(phy_drd->dev, + "CRPORT handshake timeout1 (0x%08x)\n", val); + return -ETIME; + } + + usec = 100; + + writel(val, phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0); + + do { + result = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYREG1); + if (!(result & PHYREG1_CR_ACK)) + break; + + udelay(1); + } while (usec-- > 0); + + if (!usec) { + dev_err(phy_drd->dev, + "CRPORT handshake timeout2 (0x%08x)\n", val); + return -ETIME; + } + + return 0; +} + +static int crport_ctrl_write(struct exynos5_usbdrd_phy *phy_drd, + u32 addr, u32 data) +{ + int ret; + + /* Write Address */ + writel(PHYREG0_CR_DATA_IN(addr), + phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0); + ret = crport_handshake(phy_drd, PHYREG0_CR_DATA_IN(addr), + PHYREG0_CR_CAP_ADDR); + if (ret) + return ret; + + /* Write Data */ + writel(PHYREG0_CR_DATA_IN(data), + phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0); + ret = crport_handshake(phy_drd, PHYREG0_CR_DATA_IN(data), + PHYREG0_CR_CAP_DATA); + if (ret) + return ret; + + ret = crport_handshake(phy_drd, PHYREG0_CR_DATA_IN(data), + PHYREG0_CR_WRITE); + + return ret; +} + +/* + * Calibrate few PHY parameters using CR_PORT register to meet + * SuperSpeed requirements on Exynos5420 and Exynos5800 systems, + * which have 28nm USB 3.0 DRD PHY. + */ +static void exynos5420_usbdrd_phy_calibrate(struct exynos5_usbdrd_phy *phy_drd) +{ + unsigned int temp; + int ret = 0; + + /* + * Change los_bias to (0x5) for 28nm PHY from a + * default value (0x0); los_level is set as default + * (0x9) as also reflected in los_level[30:26] bits + * of PHYPARAM0 register. + */ + temp = LOSLEVEL_OVRD_IN_LOS_BIAS_5420 | + LOSLEVEL_OVRD_IN_EN | + LOSLEVEL_OVRD_IN_LOS_LEVEL_DEFAULT; + ret = crport_ctrl_write(phy_drd, + EXYNOS5_DRD_PHYSS_LOSLEVEL_OVRD_IN, + temp); + if (ret) { + dev_err(phy_drd->dev, + "Failed setting Loss-of-Signal level for SuperSpeed\n"); + return ret; + } + + /* + * Set tx_vboost_lvl to (0x5) for 28nm PHY Tuning, + * to raise Tx signal level from its default value of (0x4) + */ + temp = TX_VBOOSTLEVEL_OVRD_IN_VBOOST_5420; + ret = crport_ctrl_write(phy_drd, + EXYNOS5_DRD_PHYSS_TX_VBOOSTLEVEL_OVRD_IN, + temp); + if (ret) { + dev_err(phy_drd->dev, + "Failed setting Tx-Vboost-Level for SuperSpeed\n"); + return ret; + } + + /* + * Set proper time to wait for RxDetect measurement, for + * desired reference clock of PHY, by tuning the CR_PORT + * register LANE0.TX_DEBUG which is internal to PHY. + * This fixes issue with few USB 3.0 devices, which are + * not detected (not even generate interrupts on the bus + * on insertion) without this change. + * e.g. Samsung SUM-TSB16S 3.0 USB drive. + */ + switch (phy_drd->extrefclk) { + case EXYNOS5_FSEL_50MHZ: + temp = LANE0_TX_DEBUG_RXDET_MEAS_TIME_48M_50M_52M; + break; + case EXYNOS5_FSEL_20MHZ: + case EXYNOS5_FSEL_19MHZ2: + temp = LANE0_TX_DEBUG_RXDET_MEAS_TIME_19M2_20M; + break; + case EXYNOS5_FSEL_24MHZ: + default: + temp = LANE0_TX_DEBUG_RXDET_MEAS_TIME_24M; + break; + } + + ret = crport_ctrl_write(phy_drd, + EXYNOS5_DRD_PHYSS_LANE0_TX_DEBUG, + temp); + if (ret) + dev_err(phy_drd->dev, + "Failed setting RxDetect measurement time for SuperSpeed\n"); + + return ret; +} + +/* Calibrate PIPE3 PHY settings, if any */ +static int exynos5_usbdrd_pipe3_calibrate(struct phy_usb_instance *inst) +{ + struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst); + + /* Call respective phy_calibrate given by certain platform */ + if (phy_drd->drv_data->phy_exynos_calibrate) + return phy_drd->drv_data->phy_exynos_calibrate(phy_drd); + + return -ENODEV; +} + static struct phy *exynos5_usbdrd_phy_xlate(struct device *dev, struct of_phandle_args *args) { @@ -608,6 +793,7 @@ static const struct exynos5_usbdrd_phy_config phy_cfg_exynos5[] = { .phy_isol = exynos5_usbdrd_phy_isol, .phy_init = exynos5_usbdrd_pipe3_init, .set_refclk = exynos5_usbdrd_pipe3_set_refclk, + .phy_calibrate = exynos5_usbdrd_pipe3_calibrate, }, }; @@ -615,6 +801,7 @@ static const struct exynos5_usbdrd_phy_drvdata exynos5420_usbdrd_phy = { .phy_cfg = phy_cfg_exynos5, .pmu_offset_usbdrd0_phy = EXYNOS5_USBDRD_PHY_CONTROL, .pmu_offset_usbdrd1_phy = EXYNOS5420_USBDRD1_PHY_CONTROL, + .phy_exynos_calibrate = exynos5420_usbdrd_phy_calibrate, .has_common_clk_gate = true, }; From 1e6c2c7fd26b33bf8afa61ddf20db2c1a0dd63c5 Mon Sep 17 00:00:00 2001 From: Dongjin Kim Date: Sat, 1 Aug 2015 03:02:19 +0000 Subject: [PATCH 04/26] media/rc: Add new receiver to specify gpio number for IR sensor This driver helps to register the device of GPIO based IR receiver, "gpio-ir-recv", with the gpio number and pulse trigger when driver is loading. For example, # modprobe gpio-ir-recv # modprobe gpioplug-ir-recv gpio_nr=24 active_low=1 Signed-off-by: Dongjin Kim --- drivers/media/rc/Kconfig | 10 ++ drivers/media/rc/Makefile | 1 + drivers/media/rc/gpio-ir-recv.c | 3 - drivers/media/rc/gpioplug-ir-recv.c | 93 +++++++++++++++++++ .../linux/platform_data/media/gpio-ir-recv.h | 3 + 5 files changed, 107 insertions(+), 3 deletions(-) create mode 100644 drivers/media/rc/gpioplug-ir-recv.c diff --git a/drivers/media/rc/Kconfig b/drivers/media/rc/Kconfig index 370e16e07867a8..edd06623ce6dd9 100644 --- a/drivers/media/rc/Kconfig +++ b/drivers/media/rc/Kconfig @@ -368,6 +368,16 @@ config IR_GPIO_CIR To compile this driver as a module, choose M here: the module will be called gpio-ir-recv. +config IR_GPIOPLUG_CIR + tristate "GPIOPLUG IR remote control" + depends on RC_CORE + select IR_GPIO_CIR + ---help--- + Say Y if you want to use GPIOPLUG based IR Receiver. + + To compile this driver as a module, choose M here: the module will + be called gpio-ir-recv. + config RC_ST tristate "ST remote control receiver" depends on RC_CORE diff --git a/drivers/media/rc/Makefile b/drivers/media/rc/Makefile index 379a5c0f137920..61939e44ad9912 100644 --- a/drivers/media/rc/Makefile +++ b/drivers/media/rc/Makefile @@ -31,6 +31,7 @@ obj-$(CONFIG_IR_STREAMZAP) += streamzap.o obj-$(CONFIG_IR_WINBOND_CIR) += winbond-cir.o obj-$(CONFIG_RC_LOOPBACK) += rc-loopback.o obj-$(CONFIG_IR_GPIO_CIR) += gpio-ir-recv.o +obj-$(CONFIG_IR_GPIOPLUG_CIR) += gpioplug-ir-recv.o obj-$(CONFIG_IR_IGORPLUGUSB) += igorplugusb.o obj-$(CONFIG_IR_IGUANA) += iguanair.o obj-$(CONFIG_IR_TTUSBIR) += ttusbir.o diff --git a/drivers/media/rc/gpio-ir-recv.c b/drivers/media/rc/gpio-ir-recv.c index 5b63b1f15cb18b..240e9bc1e493a5 100644 --- a/drivers/media/rc/gpio-ir-recv.c +++ b/drivers/media/rc/gpio-ir-recv.c @@ -23,9 +23,6 @@ #include #include -#define GPIO_IR_DRIVER_NAME "gpio-rc-recv" -#define GPIO_IR_DEVICE_NAME "gpio_ir_recv" - struct gpio_rc_dev { struct rc_dev *rcdev; int gpio_nr; diff --git a/drivers/media/rc/gpioplug-ir-recv.c b/drivers/media/rc/gpioplug-ir-recv.c new file mode 100644 index 00000000000000..624ed426389361 --- /dev/null +++ b/drivers/media/rc/gpioplug-ir-recv.c @@ -0,0 +1,93 @@ +/* + * Pluggable GPIO IR receiver + * + * Copyright (c) 2015 Dongjin Kim (tobetter@gmail.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include + +static unsigned gpio_nr = -1; +module_param(gpio_nr, uint, 0); +MODULE_PARM_DESC(gpio_nr, "GPIO number to receive IR pulse"); + +static bool active_low = 0; +module_param(active_low, bool, 0); +MODULE_PARM_DESC(active_low, + "IR pulse trigger level, (1=low active, 0=high active"); + +static struct platform_device *pdev; +static struct gpio_ir_recv_platform_data *pdata; + +static int __init gpio_init(void) +{ + int rc = -ENOMEM; + + if (gpio_nr == -1) { + pr_err("gpioplug-ir-recv: missing module parameter: 'gpio_nr'\n"); + return -EINVAL; + } + + pdev = platform_device_alloc(GPIO_IR_DRIVER_NAME, -1); + if (!pdev) + return rc; + + pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); + if (!pdata) + goto err_free_platform_data; + + pdev->dev.platform_data = pdata; + + pdata->gpio_nr = gpio_nr; + pdata->active_low = active_low; + pdata->allowed_protos = 0; + pdata->map_name = NULL; + + rc = platform_device_add(pdev); + if (rc < 0) + goto err_free_device; + + dev_info (&pdev->dev, "IR driver is initialized (gpio=%d, pulse level=%s)\n", + pdata->gpio_nr, pdata->active_low ? "low" : "high"); + + return 0; + +err_free_platform_data: + kfree(pdata); + +err_free_device: + platform_device_put(pdev); + + return rc; +} + +static void __exit gpio_exit(void) +{ + dev_info(&pdev->dev, "gpioplug-ir-recv: IR driver is removed\n"); + platform_device_unregister(pdev); +} + +MODULE_DESCRIPTION("GPIO IR Receiver driver"); +MODULE_LICENSE("GPL v2"); + +module_init(gpio_init); +module_exit(gpio_exit); diff --git a/include/linux/platform_data/media/gpio-ir-recv.h b/include/linux/platform_data/media/gpio-ir-recv.h index 0c298f569d5abd..5d212e0a274e22 100644 --- a/include/linux/platform_data/media/gpio-ir-recv.h +++ b/include/linux/platform_data/media/gpio-ir-recv.h @@ -13,6 +13,9 @@ #ifndef __GPIO_IR_RECV_H__ #define __GPIO_IR_RECV_H__ +#define GPIO_IR_DRIVER_NAME "gpio-rc-recv" +#define GPIO_IR_DEVICE_NAME "gpio_ir_recv" + struct gpio_ir_recv_platform_data { int gpio_nr; bool active_low; From c2e483c83b066c2a96a58e5069570e3ce46854db Mon Sep 17 00:00:00 2001 From: Anand Moon Date: Mon, 15 Jun 2015 12:23:21 +0930 Subject: [PATCH 05/26] ARM: dts: exynos5422-odroidxu3: Enable TMU at Exynos5422 base This changes enables TMU IP block on the Exynos5422 Odroid-XU3 device. Signed-off-by: Anand Moon Acked-by: Lukasz Majewski Signed-off-by: Krzysztof Kozlowski --- .../boot/dts/exynos5422-odroidxu3-common.dtsi | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi index d56253049ccbca..fb493218b97958 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi @@ -590,6 +590,31 @@ vtmu-supply = <&ldo7_reg>; }; +&tmu_cpu0 { + vtmu-supply = <&ldo7_reg>; + status = "okay"; +}; + +&tmu_cpu1 { + vtmu-supply = <&ldo7_reg>; + status = "okay"; +}; + +&tmu_cpu2 { + vtmu-supply = <&ldo7_reg>; + status = "okay"; +}; + +&tmu_cpu3 { + vtmu-supply = <&ldo7_reg>; + status = "okay"; +}; + +&tmu_gpu { + vtmu-supply = <&ldo7_reg>; + status = "okay"; +}; + &rtc { status = "okay"; clocks = <&clock CLK_RTC>, <&s2mps11_osc S2MPS11_CLK_AP>; From 07409ca71dd13cefd1159f0114fe4bbff7ec8d45 Mon Sep 17 00:00:00 2001 From: Dongjin Kim Date: Tue, 21 Jul 2015 14:37:21 +0900 Subject: [PATCH 06/26] ARM: dts: Add to enable SPI1 on ODROID-XU4 Change-Id: I65e9f38395dddfbe14daf7300a34a955453b5cb4 Signed-off-by: Dongjin Kim --- arch/arm/boot/dts/exynos5422-odroidxu4.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/exynos5422-odroidxu4.dts b/arch/arm/boot/dts/exynos5422-odroidxu4.dts index 2faf88627a4895..6f1c93562eff8d 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu4.dts +++ b/arch/arm/boot/dts/exynos5422-odroidxu4.dts @@ -46,3 +46,7 @@ &usbdrd_dwc3_1 { dr_mode = "host"; }; + +&spi_1 { + status = "okay"; +}; From c8d9ff4006407d6c005d0f4207be760a1076a5f0 Mon Sep 17 00:00:00 2001 From: Dongjin Kim Date: Tue, 21 Jul 2015 14:35:52 +0900 Subject: [PATCH 07/26] staging: fbtft: Add new fbtft lcd for ODROID board Signed-off-by: Dongjin Kim --- drivers/staging/fbtft/fbtft_device.c | 27 ++++++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/drivers/staging/fbtft/fbtft_device.c b/drivers/staging/fbtft/fbtft_device.c index e4a355aefb25bb..11032cccdaa78e 100644 --- a/drivers/staging/fbtft/fbtft_device.c +++ b/drivers/staging/fbtft/fbtft_device.c @@ -20,6 +20,7 @@ #include #include #include