From 25e917c9723388b5341e131fe6a7bf8fbe8bcd3c Mon Sep 17 00:00:00 2001 From: Jim Huang Date: Wed, 13 Nov 2019 06:46:37 +0800 Subject: [PATCH 01/19] Perform consistent indention --- emu-rv32i.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/emu-rv32i.c b/emu-rv32i.c index 47b6da4..b449dd5 100644 --- a/emu-rv32i.c +++ b/emu-rv32i.c @@ -1092,12 +1092,6 @@ void execute_instruction() } else { debug_out(">>> BGE\n"); stats[7]++; - } -#endif - cond = ((int32_t) reg[rs1] < (int32_t) reg[rs2]); - break; - case 3: /* bltu/bgeu */ -#ifdef DEBUG_EXTRA if (!(funct3 & 1)) { debug_out(">>> BLTU\n"); stats[8]++; From 275aa51db51479f55e5d37fdd56be56b1bdc71cc Mon Sep 17 00:00:00 2001 From: "f74064054@mail.ncku.edu.tw" Date: Fri, 13 Dec 2019 03:07:44 +0800 Subject: [PATCH 02/19] Create the CSRs.h for CSR --- CSRs.h | 91 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 91 insertions(+) create mode 100644 CSRs.h diff --git a/CSRs.h b/CSRs.h new file mode 100644 index 0000000..32daaee --- /dev/null +++ b/CSRs.h @@ -0,0 +1,91 @@ +/* Modified by Nober + 13-DEC-2019 - Define all CSR macro +*/ + +/* +RISCV emulator for the RV32I architecture +based on TinyEMU by Fabrice Bellard, see https://bellard.org/tinyemu/ +stripped down for RV32I only, all "gotos" removed, and fixed some bugs for the compliance test +by Frank Buss, 2018 + +Requires libelf-dev: + +sudo apt-get install libelf-dev + + +Compile it like this: + +gcc -O3 -Wall -lelf emu-rv32i.c -o emu-rv32i + + +It is compatible to Spike for the command line arguments, which means you can run +the compliance test from https://github.com/riscv/riscv-compliance like this: + +make RISCV_TARGET=spike RISCV_DEVICE=rv32i TARGET_SIM=/full/path/emulator variant + +It is also compatible with qemu32, as it is used for Zephyr. You can compile the +Zephyr examples for qemu like this: + +cd zephyr +source zephyr-env.sh +cd samples/synchronization +mkdir build && cd build +cmake -GNinja -DBOARD=qemu_riscv32 .. +ninja + +After this you can run it with the emulator like this: + +emu-rv32i zephyr/zephyr.elf + + +original copyright: +*/ + + + +/* + * RISCV emulator + * + * Copyright (c) 2016 Fabrice Bellard + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include + + +// ====================================================== // +// =================== User Trap Setup ================== // +// ====================================================== // +uint32_t ustatus; /* User status register */ +uint32_t uie; /* User interrupt-enable register */ +uint32_t utvec; /* User trap handler base address */ +// ====================================================== // +// ================= User Trap Handling ================= // +// ====================================================== // +uint32_t uscratch; /* Scratch register for user trap handlers*/ +uint32_t uepc; /* User exception program counter */ +uint32_t ucause; /* User trap cause*/ +uint32_t ubadaddr; /* User bad address */ +uint32_t uip; /* User interrupt pending */ +// ====================================================== // +// ============== User Floating-Point CSRs ============== // +// ====================================================== // +uint32_t fflags; /* Floating-Point Accrued Exceptions*/ +uint32_t frm; /* Floating-Point Dynamic Rounding Mode*/ From 5b853e53847088ba39de47f7af16913a452f27d2 Mon Sep 17 00:00:00 2001 From: "f74064054@mail.ncku.edu.tw" Date: Sun, 29 Dec 2019 19:55:09 +0800 Subject: [PATCH 03/19] Add the compressed C.NOP and C.ADDI --- emu-rv32i.c | 94 ++++++++++++++++++++++++++++++++++++++++++++++------- 1 file changed, 83 insertions(+), 11 deletions(-) diff --git a/emu-rv32i.c b/emu-rv32i.c index b449dd5..3e9e057 100644 --- a/emu-rv32i.c +++ b/emu-rv32i.c @@ -160,12 +160,18 @@ int machine_running = TRUE; #define PRV_H 2 #define PRV_M 3 +/* Instruction state*/ +#define CINSN 1 +#define INSN 0 +unsigned char insn_type; + /* CPU state */ uint32_t pc; uint32_t next_pc; uint32_t insn; uint32_t reg[32]; + uint8_t priv = PRV_M; /* see PRV_x */ uint8_t fs; /* MSTATUS_FS value */ uint8_t mxl; /* MXL field in MISA register */ @@ -703,7 +709,7 @@ int raise_interrupt() /* read 32-bit instruction from memory by PC */ -uint32_t get_insn32(uint32_t pc) +uint32_t get_insn32(uint32_t pc, uint32_t *insn) { #ifdef DEBUG_EXTRA if (pc && pc < minmemr) @@ -712,10 +718,16 @@ uint32_t get_insn32(uint32_t pc) maxmemr = pc + 3; #endif uint32_t ptr = pc - ram_start; - if (ptr > RAM_SIZE) - return 1; - uint8_t *p = ram + ptr; - return p[0] | (p[1] << 8) | (p[2] << 16) | (p[3] << 24); + if (ptr > RAM_SIZE) return 1; + uint8_t* p = ram + ptr; +#ifdef RV32C + if((p[0] & 0x03) < 3){ + *insn = (p[0] | (p[1] << 8)) & 0x0000ffff; + return CINSN; + } +#endif + *insn = p[0] | (p[1] << 8) | (p[2] << 16) | (p[3] << 24); + return INSN; } /* read 8-bit data from memory */ @@ -1005,10 +1017,22 @@ void execute_instruction() int32_t imm, cond, err; uint32_t addr, val = 0, val2; - opcode = insn & 0x7f; - rd = (insn >> 7) & 0x1f; - rs1 = (insn >> 15) & 0x1f; - rs2 = (insn >> 20) & 0x1f; + uint16_t midpart; + + if(insn_type == INSN){ + opcode = insn & 0x7f; + rd = (insn >> 7) & 0x1f; + rs1 = (insn >> 15) & 0x1f; + rs2 = (insn >> 20) & 0x1f; + } + +#ifdef RV32C + if(insn_type == CINSN){ + opcode = insn & 0x3; + } +#endif + + switch (opcode) { case 0x37: /* lui */ @@ -1836,6 +1860,47 @@ void execute_instruction() break; #endif +#ifdef RV32C + /* Compressed insn */ + case 0: + break; + case 1: + funct3 = (insn >> 13) & 0x7; + midpart = (insn >> 2) & 0x07ff; + switch(funct3){ + case 0: /* C.NOP, C.ADDI */ + if( ((midpart >> 5) & 0x1f) == 0){ /* C.NOP*/ + return; + } else { + rs1 = rd = (midpart >> 5) & 0x1f; + imm = (midpart & 0x1f) | ((midpart >> 5) & 0x20); + val = reg[rs1] + imm; + } + break; + case 1: /* C.JAL, C.ADDIW */ + break; + case 2: /* C.LI */ + break; + case 3: /* C.ADDI16SP, C.LUI */ + break; + case 4: /* C.SRLI, C.SRLI64, C.SRAI, C.SRAI64, C.ANDI, C.SUB, C.XOR, C.OR, C.AND, C.SUBW, C.ADDW*/ + break; + case 5: /* C.J */ + break; + case 6: /* C.BEQZ */ + break; + case 7: /* C.BNEZ */ + break; + default: + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + return; + } + if(rd != 0){ + reg[rd] = val; + } + break; + case 2: + break; default: raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); @@ -1878,8 +1943,15 @@ void riscv_cpu_interp_x32() if ((mip & mie) != 0 && (mstatus & MSTATUS_MIE)) { raise_interrupt(); } else { - /* normal instruction execution */ - insn = get_insn32(pc); + /* Compressed or normal */ + insn_type = get_insn32(pc, &insn); +#ifdef RV32C + if(insn_type) + next_pc = pc + 2; +#endif +#ifdef DEBUG_EXTRA + printf("insn : %#x\n", insn); +#endif insn_counter++; debug_out("[%08x]=%08x, mtime: %lx, mtimecmp: %lx\n", pc, insn, From 7a9c40682bdeeb0c29fd6a81295c73cb7773ef51 Mon Sep 17 00:00:00 2001 From: "f74064054@mail.ncku.edu.tw" Date: Sun, 29 Dec 2019 20:17:10 +0800 Subject: [PATCH 04/19] Add the C.JAL and C.ADDIW insn --- emu-rv32i.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/emu-rv32i.c b/emu-rv32i.c index 3e9e057..eedb342 100644 --- a/emu-rv32i.c +++ b/emu-rv32i.c @@ -1878,6 +1878,32 @@ void execute_instruction() } break; case 1: /* C.JAL, C.ADDIW */ + switch(XLEN){ + case 32: + imm = (midpart & 0x400) | + ((midpart << 3) & 0x200) | + (midpart & 0x170) | + ((midpart << 2) & 0x40) | + (midpart & 0x20) | + ((midpart << 4) & 0x10) | + ((midpart >> 6) & 0x8) | + ((midpart >> 1) & 0x7); + imm = imm & 0xfffe; + if (rd != 0) + reg[1] = pc + 2; /* Store the link to x1 register */ + next_pc = (int32_t)(pc + imm); + if(next_pc > pc) forward_counter++; + else backward_counter++; + jump_counter++; + break; + case 64: + case 128: + rs1 = rd = (midpart >> 5) & 0x1f; + imm = (midpart >> (11 - 5)) | + midpart & 0x1f; + val = reg[rs1] + imm; + break; + } break; case 2: /* C.LI */ break; From dc68602baaa554a54048f776fc0b6cd0cb3b5b84 Mon Sep 17 00:00:00 2001 From: "f74064054@mail.ncku.edu.tw" Date: Thu, 2 Jan 2020 02:58:17 +0800 Subject: [PATCH 05/19] Modified some implementataion detail to support compressed instruction --- debug.txt | 12249 ++++++++++++++++++++++++++++++++++++++++++++++++++ emu-rv32i.c | 267 +- 2 files changed, 12507 insertions(+), 9 deletions(-) create mode 100644 debug.txt diff --git a/debug.txt b/debug.txt new file mode 100644 index 0000000..ac5df94 --- /dev/null +++ b/debug.txt @@ -0,0 +1,12249 @@ +./emu-rv32i work/rv32imc/C-NOP.elf +sym '/tmp/ccoevK6z.o' 0 +sym 'reset_vector' 80000040 +sym 'trap_vector' 80000004 +sym 'write_tohost' 80000036 +sym 'handle_exception' 80000032 +sym 'other_exception' 80000032 +sym 'begin_testcode' 800000f0 +sym 'test_1_res' 80002000 +sym 'end_testcode' 80000122 +sym 'end_signature' 80002020 +sym 'begin_regstate' 80002100 +sym 'begin_signature' 80002000 +sym '_start' 80000000 +sym 'end_regstate' 80002200 +sym '_end' 80002204 +sym 'fromhost' 80001100 +sym 'tohost' 80001000 +begin_signature: 0x80002000 +end_signature: 0x80002020 +start: 0x80000000 +codesize: 0x00002204 (8708) +codesize with offset: 8708 +address 0001a081 +insn_type : CINSN +[80000000]=0000a081, mtime: 1db9bc30e4d, mtimecmp: 0 +>>> C.J +address f1402573 +insn_type : INSN +[80000040]=f1402573, mtime: 1db9bc30f47, mtimecmp: 0 +csr_read: csr=0xf14 0 +csr_read: csr=0xf14 --> 0x00000000 +>>> CSRRS +address 0297e101 +insn_type : CINSN +[80000044]=0000e101, mtime: 1db9bc3103b, mtimecmp: 0 +>>> C.BNEZ +rd : 0, rs1: 10, imm: 0, reg[rs1] : 0, pc: 407b4e99, next_pc: 407b4e9a +address 00000297 +insn_type : INSN +[80000046]=00000297, mtime: 1db9bc3110a, mtimecmp: 0 +>>> AUIPC +address 01228293 +insn_type : INSN +[8000004a]=01228293, mtime: 1db9bc311ae, mtimecmp: 0 +>>> ADDI +address 30529073 +insn_type : INSN +[8000004e]=30529073, mtime: 1db9bc3124f, mtimecmp: 0 +>>> CSRRW +csr_read: csr=0x305 -1 +csr_read: csr=0x305 --> 0x00000000 +csr_write: csr=0x305 val=0x80000058 +address 18005073 +insn_type : INSN +[80000052]=18005073, mtime: 1db9bc31368, mtimecmp: 0 +>>> CSRRWI +csr_read: csr=0x180 -1 +csr_read: csr=0x180 --> 0x00000000 +csr_write: csr=0x180 val=0x00000000 +address 02970001 +insn_type : CINSN +[80000056]=00000001, mtime: 1db9bc3146e, mtimecmp: 0 +>>> C.NOP +address 00000297 +insn_type : INSN +[80000058]=00000297, mtime: 1db9bc3150f, mtimecmp: 0 +>>> AUIPC +address 01828293 +insn_type : INSN +[8000005c]=01828293, mtime: 1db9bc315ae, mtimecmp: 0 +>>> ADDI +address 30529073 +insn_type : INSN +[80000060]=30529073, mtime: 1db9bc3164a, mtimecmp: 0 +>>> CSRRW +csr_read: csr=0x305 -1 +csr_read: csr=0x305 --> 0x80000058 +csr_write: csr=0x305 val=0x80000070 +address 907352fd +insn_type : CINSN +[80000064]=000052fd, mtime: 1db9bc31751, mtimecmp: 0 +>>> C.LI +0000003f, rd: 5 +address 3b029073 +insn_type : INSN +[80000066]=3b029073, mtime: 1db9bc31814, mtimecmp: 0 +>>> CSRRW +csr_read: csr=0x3b0 -1 +csr_read: invalid CSR=0x3b0 +csr_write: csr=0x3b0 val=0x0000003f +address 907342fd +insn_type : CINSN +[8000006a]=000042fd, mtime: 1db9bc31997, mtimecmp: 0 +>>> C.LI +0000001f, rd: 5 +address 3a029073 +insn_type : INSN +[8000006c]=3a029073, mtime: 1db9bc31aaf, mtimecmp: 0 +>>> CSRRW +csr_read: csr=0x3a0 -1 +csr_read: invalid CSR=0x3a0 +csr_write: csr=0x3a0 val=0x0000001f +address 00000297 +insn_type : INSN +[80000070]=00000297, mtime: 1db9bc31bb5, mtimecmp: 0 +>>> AUIPC +address 01828293 +insn_type : INSN +[80000074]=01828293, mtime: 1db9bc31dd9, mtimecmp: 0 +>>> ADDI +address 30529073 +insn_type : INSN +[80000078]=30529073, mtime: 1db9bc31e7c, mtimecmp: 0 +>>> CSRRW +csr_read: csr=0x305 -1 +csr_read: csr=0x305 --> 0x80000070 +csr_write: csr=0x305 val=0x80000088 +address 30205073 +insn_type : INSN +[8000007c]=30205073, mtime: 1db9bc31f7c, mtimecmp: 0 +>>> CSRRWI +csr_read: csr=0x302 -1 +csr_read: csr=0x302 --> 0x00000000 +csr_write: csr=0x302 val=0x00000000 +address 30305073 +insn_type : INSN +[80000080]=30305073, mtime: 1db9bc3207e, mtimecmp: 0 +>>> CSRRWI +csr_read: csr=0x303 -1 +csr_read: csr=0x303 --> 0x00000000 +csr_write: csr=0x303 val=0x00000000 +address 30405073 +insn_type : INSN +[80000084]=30405073, mtime: 1db9bc321a1, mtimecmp: 0 +>>> CSRRWI +csr_read: csr=0x304 -1 +csr_read: csr=0x304 --> 0x00000000 +csr_write: csr=0x304 val=0x00000000 +address 02974181 +insn_type : CINSN +[80000088]=00004181, mtime: 1db9bc3229f, mtimecmp: 0 +>>> C.LI +00000000, rd: 3 +address 00000297 +insn_type : INSN +[8000008a]=00000297, mtime: 1db9bc3235e, mtimecmp: 0 +>>> AUIPC +address f7a28293 +insn_type : INSN +[8000008e]=f7a28293, mtime: 1db9bc323fc, mtimecmp: 0 +>>> ADDI +address 30529073 +insn_type : INSN +[80000092]=30529073, mtime: 1db9bc3249f, mtimecmp: 0 +>>> CSRRW +csr_read: csr=0x305 -1 +csr_read: csr=0x305 --> 0x80000088 +csr_write: csr=0x305 val=0x80000004 +address 057e4505 +insn_type : CINSN +[80000096]=00004505, mtime: 1db9bc325e5, mtimecmp: 0 +>>> C.LI +00000001, rd: 10 +address 4763057e +insn_type : CINSN +[80000098]=0000057e, mtime: 1db9bc326a8, mtimecmp: 0 +address 00054763 +insn_type : INSN +[8000009a]=00054763, mtime: 1db9bc3270d, mtimecmp: 0 +>>> BLT +address 0ff0000f +insn_type : INSN +[8000009e]=0ff0000f, mtime: 1db9bc327ae, mtimecmp: 0 +>>> FENCE +address 00734185 +insn_type : CINSN +[800000a2]=00004185, mtime: 1db9bc32853, mtimecmp: 0 +>>> C.LI +00000001, rd: 3 +address 00000073 +insn_type : INSN +[800000a4]=00000073, mtime: 1db9bc32914, mtimecmp: 0 +>>> ECALL +syscall: 0001 +Unimplement Machine ecall! +address 80000297 +insn_type : INSN +[800000a8]=80000297, mtime: 1db9bc32a14, mtimecmp: 0 +>>> AUIPC +address f5828293 +insn_type : INSN +[800000ac]=f5828293, mtime: 1db9bc32ab2, mtimecmp: 0 +>>> ADDI +address 00028e63 +insn_type : INSN +[800000b0]=00028e63, mtime: 1db9bc32b50, mtimecmp: 0 +>>> BEQ +address 30005073 +insn_type : INSN +[800000cc]=30005073, mtime: 1db9bc32bf7, mtimecmp: 0 +>>> CSRRWI +csr_read: csr=0x300 -1 +csr_read: csr=0x300 --> 0x00000000 +csr_write: csr=0x300 val=0x00000000 +address 00002537 +insn_type : INSN +[800000d0]=00002537, mtime: 1db9bc32cfb, mtimecmp: 0 +>>> LUI +address 80050513 +insn_type : INSN +[800000d4]=80050513, mtime: 1db9bc32d9c, mtimecmp: 0 +>>> ADDI +address 30052073 +insn_type : INSN +[800000d8]=30052073, mtime: 1db9bc32e3a, mtimecmp: 0 +csr_read: csr=0x300 1 +csr_read: csr=0x300 --> 0x00000000 +>>> CSRRS +csr_write: csr=0x300 val=0x00001800 +address 00000297 +insn_type : INSN +[800000dc]=00000297, mtime: 1db9bc32f45, mtimecmp: 0 +>>> AUIPC +address 01428293 +insn_type : INSN +[800000e0]=01428293, mtime: 1db9bc32fe3, mtimecmp: 0 +>>> ADDI +address 34129073 +insn_type : INSN +[800000e4]=34129073, mtime: 1db9bc33081, mtimecmp: 0 +>>> CSRRW +csr_read: csr=0x341 -1 +csr_read: csr=0x341 --> 0x00000000 +csr_write: csr=0x341 val=0x800000f0 +address f1402573 +insn_type : INSN +[800000e8]=f1402573, mtime: 1db9bc33186, mtimecmp: 0 +csr_read: csr=0xf14 0 +csr_read: csr=0xf14 --> 0x00000000 +>>> CSRRS +address 30200073 +insn_type : INSN +[800000ec]=30200073, mtime: 1db9bc33266, mtimecmp: 0 +>>> MRET +address 00002117 +insn_type : INSN +[800000f0]=00002117, mtime: 1db9bc33304, mtimecmp: 0 +>>> AUIPC +address f1010113 +insn_type : INSN +[800000f4]=f1010113, mtime: 1db9bc333a2, mtimecmp: 0 +>>> ADDI +address 00000013 +insn_type : INSN +[800000f8]=00000013, mtime: 1db9bc3343f, mtimecmp: 0 +>>> ADDI +address c0020001 +insn_type : CINSN +[800000fc]=00000001, mtime: 1db9bc334dd, mtimecmp: 0 +>>> C.NOP +address 4201c002 +insn_type : CINSN +[800000fe]=0000c002, mtime: 1db9bc33584, mtimecmp: 0 +address 02014201 +insn_type : CINSN +[80000100]=00004201, mtime: 1db9bc335e6, mtimecmp: 0 +>>> C.LI +00000000, rd: 4 +address c2120201 +insn_type : CINSN +[80000102]=00000201, mtime: 1db9bc336a7, mtimecmp: 0 +>>> C.ADDI +address 4401c212 +insn_type : CINSN +[80000104]=0000c212, mtime: 1db9bc33746, mtimecmp: 0 +address 04014401 +insn_type : CINSN +[80000106]=00004401, mtime: 1db9bc337b1, mtimecmp: 0 +>>> C.LI +00000000, rd: 8 +address c4220401 +insn_type : CINSN +[80000108]=00000401, mtime: 1db9bc3386f, mtimecmp: 0 +>>> C.ADDI +address 4481c422 +insn_type : CINSN +[8000010a]=0000c422, mtime: 1db9bc3390e, mtimecmp: 0 +address 04814481 +insn_type : CINSN +[8000010c]=00004481, mtime: 1db9bc33970, mtimecmp: 0 +>>> C.LI +00000000, rd: 9 +address c6260481 +insn_type : CINSN +[8000010e]=00000481, mtime: 1db9bc33a2e, mtimecmp: 0 +>>> C.ADDI +address 4581c626 +insn_type : CINSN +[80000110]=0000c626, mtime: 1db9bc33acc, mtimecmp: 0 +address 05814581 +insn_type : CINSN +[80000112]=00004581, mtime: 1db9bc33b2e, mtimecmp: 0 +>>> C.LI +00000000, rd: 11 +address c82e0581 +insn_type : CINSN +[80000114]=00000581, mtime: 1db9bc33bf4, mtimecmp: 0 +>>> C.ADDI +address 000fc82e +insn_type : CINSN +[80000116]=0000c82e, mtime: 1db9bc33c92, mtimecmp: 0 +address 0ff0000f +insn_type : INSN +[80000118]=0ff0000f, mtime: 1db9bc33cf5, mtimecmp: 0 +>>> FENCE +address 00734185 +insn_type : CINSN +[8000011c]=00004185, mtime: 1db9bc33d94, mtimecmp: 0 +>>> C.LI +00000001, rd: 3 +address 00000073 +insn_type : INSN +[8000011e]=00000073, mtime: 1db9bc33e54, mtimecmp: 0 +>>> ECALL +syscall: 0001 +Unimplement Machine ecall! +address 00000000 +insn_type : CINSN +[80000122]=00000000, mtime: 1db9bc33f7a, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000124]=00000000, mtime: 1db9bc33fe0, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000126]=00000000, mtime: 1db9bc34044, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000128]=00000000, mtime: 1db9bc340a7, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000012a]=00000000, mtime: 1db9bc3410b, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000012c]=00000000, mtime: 1db9bc3416e, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000012e]=00000000, mtime: 1db9bc341d1, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000130]=00000000, mtime: 1db9bc34234, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000132]=00000000, mtime: 1db9bc34297, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000134]=00000000, mtime: 1db9bc342f9, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000136]=00000000, mtime: 1db9bc34362, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000138]=00000000, mtime: 1db9bc343c4, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000013a]=00000000, mtime: 1db9bc34426, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000013c]=00000000, mtime: 1db9bc34488, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000013e]=00000000, mtime: 1db9bc344e9, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000140]=00000000, mtime: 1db9bc3454b, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000142]=00000000, mtime: 1db9bc345b0, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000144]=00000000, mtime: 1db9bc34614, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000146]=00000000, mtime: 1db9bc34676, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000148]=00000000, mtime: 1db9bc346d7, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000014a]=00000000, mtime: 1db9bc34739, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000014c]=00000000, mtime: 1db9bc3479b, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000014e]=00000000, mtime: 1db9bc347ff, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000150]=00000000, mtime: 1db9bc34861, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000152]=00000000, mtime: 1db9bc348c5, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000154]=00000000, mtime: 1db9bc34927, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000156]=00000000, mtime: 1db9bc34990, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000158]=00000000, mtime: 1db9bc349f2, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000015a]=00000000, mtime: 1db9bc34a54, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000015c]=00000000, mtime: 1db9bc34ab5, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000015e]=00000000, mtime: 1db9bc34b17, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000160]=00000000, mtime: 1db9bc34b79, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000162]=00000000, mtime: 1db9bc34bdd, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000164]=00000000, mtime: 1db9bc34c69, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000166]=00000000, mtime: 1db9bc34cf8, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000168]=00000000, mtime: 1db9bc34d7d, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000016a]=00000000, mtime: 1db9bc34dfb, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000016c]=00000000, mtime: 1db9bc34e5c, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000016e]=00000000, mtime: 1db9bc34ebe, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000170]=00000000, mtime: 1db9bc34f20, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000172]=00000000, mtime: 1db9bc34f81, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000174]=00000000, mtime: 1db9bc34fe3, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000176]=00000000, mtime: 1db9bc35045, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000178]=00000000, mtime: 1db9bc350a7, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000017a]=00000000, mtime: 1db9bc35108, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000017c]=00000000, mtime: 1db9bc3516a, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000017e]=00000000, mtime: 1db9bc351fe, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000180]=00000000, mtime: 1db9bc35261, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000182]=00000000, mtime: 1db9bc352c3, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000184]=00000000, mtime: 1db9bc35328, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000186]=00000000, mtime: 1db9bc3538a, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000188]=00000000, mtime: 1db9bc353f0, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000018a]=00000000, mtime: 1db9bc35452, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000018c]=00000000, mtime: 1db9bc354b3, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000018e]=00000000, mtime: 1db9bc355a2, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000190]=00000000, mtime: 1db9bc355f5, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000192]=00000000, mtime: 1db9bc35645, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000194]=00000000, mtime: 1db9bc35694, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000196]=00000000, mtime: 1db9bc356e4, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000198]=00000000, mtime: 1db9bc35732, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000019a]=00000000, mtime: 1db9bc35781, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000019c]=00000000, mtime: 1db9bc357d1, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000019e]=00000000, mtime: 1db9bc35820, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001a0]=00000000, mtime: 1db9bc35876, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001a2]=00000000, mtime: 1db9bc358c5, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001a4]=00000000, mtime: 1db9bc35915, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001a6]=00000000, mtime: 1db9bc35964, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001a8]=00000000, mtime: 1db9bc359b3, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001aa]=00000000, mtime: 1db9bc35a02, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001ac]=00000000, mtime: 1db9bc35a51, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001ae]=00000000, mtime: 1db9bc35aa3, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001b0]=00000000, mtime: 1db9bc35af2, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001b2]=00000000, mtime: 1db9bc35b41, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001b4]=00000000, mtime: 1db9bc35b95, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001b6]=00000000, mtime: 1db9bc35be6, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001b8]=00000000, mtime: 1db9bc35c37, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001ba]=00000000, mtime: 1db9bc35c86, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001bc]=00000000, mtime: 1db9bc35cd5, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001be]=00000000, mtime: 1db9bc35d25, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001c0]=00000000, mtime: 1db9bc35d74, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001c2]=00000000, mtime: 1db9bc35dc3, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001c4]=00000000, mtime: 1db9bc35e13, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001c6]=00000000, mtime: 1db9bc35e68, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001c8]=00000000, mtime: 1db9bc35eb8, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001ca]=00000000, mtime: 1db9bc35f07, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001cc]=00000000, mtime: 1db9bc35f57, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001ce]=00000000, mtime: 1db9bc35fa6, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001d0]=00000000, mtime: 1db9bc35ff5, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001d2]=00000000, mtime: 1db9bc36044, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001d4]=00000000, mtime: 1db9bc36093, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001d6]=00000000, mtime: 1db9bc360e6, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001d8]=00000000, mtime: 1db9bc36137, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001da]=00000000, mtime: 1db9bc361a0, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001dc]=00000000, mtime: 1db9bc361f1, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001de]=00000000, mtime: 1db9bc36240, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001e0]=00000000, mtime: 1db9bc3628f, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001e2]=00000000, mtime: 1db9bc362e2, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001e4]=00000000, mtime: 1db9bc36331, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001e6]=00000000, mtime: 1db9bc36381, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001e8]=00000000, mtime: 1db9bc363d0, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001ea]=00000000, mtime: 1db9bc36425, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001ec]=00000000, mtime: 1db9bc36479, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001ee]=00000000, mtime: 1db9bc364c8, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001f0]=00000000, mtime: 1db9bc36517, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001f2]=00000000, mtime: 1db9bc36565, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001f4]=00000000, mtime: 1db9bc365b5, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001f6]=00000000, mtime: 1db9bc36604, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001f8]=00000000, mtime: 1db9bc36654, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001fa]=00000000, mtime: 1db9bc366a8, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001fc]=00000000, mtime: 1db9bc366fa, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001fe]=00000000, mtime: 1db9bc3674b, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000200]=00000000, mtime: 1db9bc3679a, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000202]=00000000, mtime: 1db9bc367ea, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000204]=00000000, mtime: 1db9bc3683a, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000206]=00000000, mtime: 1db9bc3688a, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000208]=00000000, mtime: 1db9bc368df, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000020a]=00000000, mtime: 1db9bc3692e, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000020c]=00000000, mtime: 1db9bc3697e, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000020e]=00000000, mtime: 1db9bc369cc, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000210]=00000000, mtime: 1db9bc36a1b, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000212]=00000000, mtime: 1db9bc36a6a, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000214]=00000000, mtime: 1db9bc36ab9, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000216]=00000000, mtime: 1db9bc36b0b, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000218]=00000000, mtime: 1db9bc36b5d, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000021a]=00000000, mtime: 1db9bc36baf, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000021c]=00000000, mtime: 1db9bc36bff, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000021e]=00000000, mtime: 1db9bc36c50, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000220]=00000000, mtime: 1db9bc36ca1, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000222]=00000000, mtime: 1db9bc36cf3, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000224]=00000000, mtime: 1db9bc36d43, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000226]=00000000, mtime: 1db9bc36d94, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000228]=00000000, mtime: 1db9bc36de4, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000022a]=00000000, mtime: 1db9bc36e35, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000022c]=00000000, mtime: 1db9bc36e85, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000022e]=00000000, mtime: 1db9bc36ed4, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000230]=00000000, mtime: 1db9bc36f23, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000232]=00000000, mtime: 1db9bc36f76, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000234]=00000000, mtime: 1db9bc36fc7, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000236]=00000000, mtime: 1db9bc3701e, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000238]=00000000, mtime: 1db9bc3708c, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000023a]=00000000, mtime: 1db9bc370db, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000023c]=00000000, mtime: 1db9bc3712f, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000023e]=00000000, mtime: 1db9bc37181, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000240]=00000000, mtime: 1db9bc371dc, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000242]=00000000, mtime: 1db9bc37231, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000244]=00000000, mtime: 1db9bc37283, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000246]=00000000, mtime: 1db9bc372d2, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000248]=00000000, mtime: 1db9bc37328, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000024a]=00000000, mtime: 1db9bc3737b, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000024c]=00000000, mtime: 1db9bc373cb, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000024e]=00000000, mtime: 1db9bc3741d, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000250]=00000000, mtime: 1db9bc3746f, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000252]=00000000, mtime: 1db9bc374d5, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000254]=00000000, mtime: 1db9bc37546, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000256]=00000000, mtime: 1db9bc375be, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000258]=00000000, mtime: 1db9bc37626, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000025a]=00000000, mtime: 1db9bc3769b, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000025c]=00000000, mtime: 1db9bc37705, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000025e]=00000000, mtime: 1db9bc37775, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000260]=00000000, mtime: 1db9bc377f4, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000262]=00000000, mtime: 1db9bc3786f, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000264]=00000000, mtime: 1db9bc378e8, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000266]=00000000, mtime: 1db9bc37959, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000268]=00000000, mtime: 1db9bc379c7, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000026a]=00000000, mtime: 1db9bc37a3a, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000026c]=00000000, mtime: 1db9bc37ab7, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000026e]=00000000, mtime: 1db9bc37b2c, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000270]=00000000, mtime: 1db9bc37b9d, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000272]=00000000, mtime: 1db9bc37c11, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000274]=00000000, mtime: 1db9bc37c71, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000276]=00000000, mtime: 1db9bc37cc4, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000278]=00000000, mtime: 1db9bc37d13, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000027a]=00000000, mtime: 1db9bc37d63, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000027c]=00000000, mtime: 1db9bc37db2, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000027e]=00000000, mtime: 1db9bc37e08, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000280]=00000000, mtime: 1db9bc37e58, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000282]=00000000, mtime: 1db9bc37ea8, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000284]=00000000, mtime: 1db9bc37efa, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000286]=00000000, mtime: 1db9bc37f4a, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000288]=00000000, mtime: 1db9bc37f9a, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000028a]=00000000, mtime: 1db9bc37fe9, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000028c]=00000000, mtime: 1db9bc38038, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000028e]=00000000, mtime: 1db9bc3808d, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000290]=00000000, mtime: 1db9bc380dc, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000292]=00000000, mtime: 1db9bc38130, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000294]=00000000, mtime: 1db9bc381ba, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000296]=00000000, mtime: 1db9bc38210, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000298]=00000000, mtime: 1db9bc38260, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000029a]=00000000, mtime: 1db9bc382b2, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000029c]=00000000, mtime: 1db9bc38302, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000029e]=00000000, mtime: 1db9bc38350, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800002a0]=00000000, mtime: 1db9bc383a6, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800002a2]=00000000, mtime: 1db9bc3841a, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800002a4]=00000000, mtime: 1db9bc38495, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800002a6]=00000000, mtime: 1db9bc38506, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800002a8]=00000000, mtime: 1db9bc38575, mtimecmp: 0 +address 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00000000 +insn_type : CINSN +[80001f32]=00000000, mtime: 1db9bc6f756, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f34]=00000000, mtime: 1db9bc6f783, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f36]=00000000, mtime: 1db9bc6f7b0, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f38]=00000000, mtime: 1db9bc6f7dd, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f3a]=00000000, mtime: 1db9bc6f80a, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f3c]=00000000, mtime: 1db9bc6f836, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f3e]=00000000, mtime: 1db9bc6f863, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f40]=00000000, mtime: 1db9bc6f890, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f42]=00000000, mtime: 1db9bc6f8bc, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f44]=00000000, mtime: 1db9bc6f8e9, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f46]=00000000, mtime: 1db9bc6f915, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f48]=00000000, mtime: 1db9bc6f942, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f4a]=00000000, mtime: 1db9bc6f96e, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f4c]=00000000, mtime: 1db9bc6f99b, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f4e]=00000000, mtime: 1db9bc6f9d8, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f50]=00000000, mtime: 1db9bc6fa07, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f52]=00000000, mtime: 1db9bc6fa34, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f54]=00000000, mtime: 1db9bc6fa60, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f56]=00000000, mtime: 1db9bc6fa8c, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f58]=00000000, mtime: 1db9bc6fab9, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f5a]=00000000, mtime: 1db9bc6fae6, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f5c]=00000000, mtime: 1db9bc6fb13, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f5e]=00000000, mtime: 1db9bc6fb40, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f60]=00000000, mtime: 1db9bc6fb6c, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f62]=00000000, mtime: 1db9bc6fb99, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f64]=00000000, mtime: 1db9bc6fbc5, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f66]=00000000, mtime: 1db9bc6fbf2, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f68]=00000000, mtime: 1db9bc6fc1e, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f6a]=00000000, mtime: 1db9bc6fc4b, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f6c]=00000000, mtime: 1db9bc6fc78, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f6e]=00000000, mtime: 1db9bc6fca4, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f70]=00000000, mtime: 1db9bc6fcd1, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f72]=00000000, mtime: 1db9bc6fcfd, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f74]=00000000, mtime: 1db9bc6fd2a, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f76]=00000000, mtime: 1db9bc6fd56, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f78]=00000000, mtime: 1db9bc6fd83, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f7a]=00000000, mtime: 1db9bc6fdaf, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f7c]=00000000, mtime: 1db9bc6fddc, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f7e]=00000000, mtime: 1db9bc6fe08, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f80]=00000000, mtime: 1db9bc6fe35, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f82]=00000000, mtime: 1db9bc6fe61, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f84]=00000000, mtime: 1db9bc6fe8f, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f86]=00000000, mtime: 1db9bc6febb, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f88]=00000000, mtime: 1db9bc6fee8, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f8a]=00000000, mtime: 1db9bc6ff14, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f8c]=00000000, mtime: 1db9bc6ff41, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f8e]=00000000, mtime: 1db9bc6ff6d, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f90]=00000000, mtime: 1db9bc6ff99, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f92]=00000000, mtime: 1db9bc6ffc6, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f94]=00000000, mtime: 1db9bc6fff2, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f96]=00000000, mtime: 1db9bc7001e, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f98]=00000000, mtime: 1db9bc7004c, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f9a]=00000000, mtime: 1db9bc70078, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f9c]=00000000, mtime: 1db9bc700a6, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f9e]=00000000, mtime: 1db9bc700d2, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fa0]=00000000, mtime: 1db9bc700ff, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fa2]=00000000, mtime: 1db9bc7012b, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fa4]=00000000, mtime: 1db9bc70158, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fa6]=00000000, mtime: 1db9bc70184, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fa8]=00000000, mtime: 1db9bc701b1, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001faa]=00000000, mtime: 1db9bc701dd, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fac]=00000000, mtime: 1db9bc7021a, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fae]=00000000, mtime: 1db9bc70246, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fb0]=00000000, mtime: 1db9bc70273, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fb2]=00000000, mtime: 1db9bc702a0, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fb4]=00000000, mtime: 1db9bc702cc, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fb6]=00000000, mtime: 1db9bc702f8, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fb8]=00000000, mtime: 1db9bc70325, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fba]=00000000, mtime: 1db9bc70352, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fbc]=00000000, mtime: 1db9bc7037e, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fbe]=00000000, mtime: 1db9bc703ab, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fc0]=00000000, mtime: 1db9bc703d8, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fc2]=00000000, mtime: 1db9bc70408, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fc4]=00000000, mtime: 1db9bc7043b, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fc6]=00000000, mtime: 1db9bc70477, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fc8]=00000000, mtime: 1db9bc704bb, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fca]=00000000, mtime: 1db9bc704fc, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fcc]=00000000, mtime: 1db9bc7053e, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fce]=00000000, mtime: 1db9bc70573, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fd0]=00000000, mtime: 1db9bc705a2, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fd2]=00000000, mtime: 1db9bc705d2, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fd4]=00000000, mtime: 1db9bc70605, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fd6]=00000000, mtime: 1db9bc70635, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fd8]=00000000, mtime: 1db9bc70665, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fda]=00000000, mtime: 1db9bc70694, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fdc]=00000000, mtime: 1db9bc706c6, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fde]=00000000, mtime: 1db9bc706f6, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fe0]=00000000, mtime: 1db9bc70725, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fe2]=00000000, mtime: 1db9bc70755, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fe4]=00000000, mtime: 1db9bc70784, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fe6]=00000000, mtime: 1db9bc707b4, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fe8]=00000000, mtime: 1db9bc707e3, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fea]=00000000, mtime: 1db9bc70813, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fec]=00000000, mtime: 1db9bc70842, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fee]=00000000, mtime: 1db9bc70872, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001ff0]=00000000, mtime: 1db9bc708a6, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001ff2]=00000000, mtime: 1db9bc708d6, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001ff4]=00000000, mtime: 1db9bc70905, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001ff6]=00000000, mtime: 1db9bc70935, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001ff8]=00000000, mtime: 1db9bc70968, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001ffa]=00000000, mtime: 1db9bc70998, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001ffc]=00000000, mtime: 1db9bc709c7, mtimecmp: 0 +address ffff0000 +insn_type : CINSN +[80001ffe]=00000000, mtime: 1db9bc709f5, mtimecmp: 0 +address ffffffff +insn_type : INSN +[80002000]=ffffffff, mtime: 1db9bc70a22, mtimecmp: 0 +raise_exception: illegal instruction 0x2 0xffffffff +done interp faf int=0 mstatus=80 prv=3 + +Registers: +x0 zero: 00000000 +x1 ra: 00000000 +x2 sp: 80002000 +x3 gp: 00000001 +x4 tp: 00000000 +x5 t0: 800000f0 +x6 t1: 00000000 +x7 t2: 00000000 +x8 s0: 00000000 +x9 s1: 00000000 +x10 a0: 00000000 +x11 a1: 00000000 +x12 a2: 00000000 +x13 a3: 00000000 +x14 a4: 00000000 +x15 a5: 00000000 +x16 a6: 00000000 +x17 a7: 00000000 +x18 s2: 00000000 +x19 s3: 00000000 +x20 s4: 00000000 +x21 s5: 00000000 +x22 s6: 00000000 +x23 s7: 00000000 +x24 s8: 00000000 +x25 s9: 00000000 +x26 s10: 00000000 +x27 s11: 00000000 +x28 t3: 00000000 +x29 t4: 00000000 +x30 t5: 00000000 +x31 t6: 00000000 + +Instructions Stat: +LUI = 1 +AUIPC = 7 +BEQ = 1 +BLT = 1 +ADDI = 9 +FENCE = 2 +ECALL = 2 +CSRRW = 7 +CSRRS = 3 +CSRRWI = 5 +LI* = 1 +MRET = 1 + +Five Most Frequent: +1) ADDI = 9 (0.22%) +2) AUIPC = 7 (0.17%) +3) CSRRW = 7 (0.17%) +4) CSRRWI = 5 (0.12%) +5) CSRRS = 3 (0.07%) + +Memory Reading Area 80000000...80002003 +Memory Writing Area NONE + +>>> Execution time: 26116764 ns +>>> Instruction count: 4015 (IPS=153732) +>>> Jumps: 2 (0.05%) - 2 forwards, 0 backwards +>>> Branching T=1 (50.00%) F=1 (50.00%) + diff --git a/emu-rv32i.c b/emu-rv32i.c index eedb342..55d989e 100644 --- a/emu-rv32i.c +++ b/emu-rv32i.c @@ -634,6 +634,21 @@ void raise_exception(uint32_t cause, uint32_t tval) return; } + switch(cause){ + case CAUSE_MACHINE_ECALL: + printf("Unimplement Machine ecall!\n"); + return; + case CAUSE_USER_ECALL: + printf("Unimplement User ecall!\n"); + return; + case CAUSE_SUPERVISOR_ECALL: + printf("Unimplement Supervisor ecall!\n"); + return; + case CAUSE_HYPERVISOR_ECALL: + printf("Unimplement Hypervisor ecall!\n"); + return; + } + if (priv <= PRV_S) { /* delegate the exception to the supervisor priviledge */ if (cause & CAUSE_INTERRUPT) @@ -709,7 +724,7 @@ int raise_interrupt() /* read 32-bit instruction from memory by PC */ -uint32_t get_insn32(uint32_t pc, uint32_t *insn) +unsigned char get_insn32(uint32_t pc, uint32_t *insn) { #ifdef DEBUG_EXTRA if (pc && pc < minmemr) @@ -720,9 +735,12 @@ uint32_t get_insn32(uint32_t pc, uint32_t *insn) uint32_t ptr = pc - ram_start; if (ptr > RAM_SIZE) return 1; uint8_t* p = ram + ptr; +#ifdef DEBUG_OUTPUT + printf("address %08x\n", p[0] | (p[1] << 8) | (p[2] << 16) | (p[3] << 24)); +#endif #ifdef RV32C if((p[0] & 0x03) < 3){ - *insn = (p[0] | (p[1] << 8)) & 0x0000ffff; + *insn = (p[0] | ((p[1] << 8) & 0x0000ffff)); return CINSN; } #endif @@ -1870,15 +1888,35 @@ void execute_instruction() switch(funct3){ case 0: /* C.NOP, C.ADDI */ if( ((midpart >> 5) & 0x1f) == 0){ /* C.NOP*/ +#ifdef DEBUG_EXTRA + dprintf(">>> C.NOP\n"); +#endif return; } else { - rs1 = rd = (midpart >> 5) & 0x1f; +#ifdef DEBUG_EXTRA + dprintf(">>> C.ADDI\n"); +#endif + rs1 = rd = ((midpart >> 5) & 0x1f) + 8; imm = (midpart & 0x1f) | ((midpart >> 5) & 0x20); val = reg[rs1] + imm; } break; case 1: /* C.JAL, C.ADDIW */ +#ifdef DEBUG_EXTRA switch(XLEN){ + case 32: + dprintf(">>> C.JAL\n"); + break; + case 64: + case 128: + dprintf(">>> C.ADDIW\n"); + break; + default: + dprintf(">>> Unknow XLEN\n"); + break; + } +#endif + switch(XLEN) { case 32: imm = (midpart & 0x400) | ((midpart << 3) & 0x200) | @@ -1898,24 +1936,235 @@ void execute_instruction() break; case 64: case 128: - rs1 = rd = (midpart >> 5) & 0x1f; + rs1 = rd = ((midpart >> 5) & 0x1f); imm = (midpart >> (11 - 5)) | - midpart & 0x1f; + (midpart & 0x1f); val = reg[rs1] + imm; break; } break; case 2: /* C.LI */ +#ifdef DEBUG_EXTRA + dprintf(">>> C.LI\n"); +#endif + rs1 = rd = ((midpart >> 5) & 0x1f); + imm = ((midpart >> 5) & 0x20) | (midpart & 0x1f); + val = imm; + printf("%08x, rd: %d\n", val, rd); break; case 3: /* C.ADDI16SP, C.LUI */ +#ifdef DEBUG_EXTRA + switch(rd){ + case 2: + dprintf(">>> C.ADDI16SP\n"); + break; + default: + dprintf(">>> C.LUI\n"); + } +#endif + rs1 = rd = ((midpart >> 5) & 0x1f); + switch(rd){ + case 2: + imm = ((midpart >> 4) & 0x1) | + ((midpart << 1) & 0x2) | + ((midpart) & 0x8) | + ((midpart << 2) & 0xc) | + ((midpart >> 5) & 0x10); + imm = imm << 4; + val = reg[rd] + imm; + break; + default: + imm = (midpart & 0x1f) | ((midpart >> 5) & 0x20); + imm = ((imm << 12) & 0xfffff000); + imm = imm << 14 >> 14; + if(rd != 0) + val = reg[rd] | imm; + break; + } break; case 4: /* C.SRLI, C.SRLI64, C.SRAI, C.SRAI64, C.ANDI, C.SUB, C.XOR, C.OR, C.AND, C.SUBW, C.ADDW*/ + switch(((midpart >> 8) & 0x3)){ + case 0: /* C.SRLI C.SRLI64 */ +#ifdef DEBUG_EXTRA + switch(XLEN){ + case 32: + case 64: + dprintf(">>> C.SRLI\n"); + break; + case 128: + dprintf(">>> C.SRLI64\n"); + break; + } +#endif + switch(XLEN){ + case 32: + case 64: + rs1 = rd = ((midpart >> 5) & 0x1f) + 8; + imm = (midpart & 0xf) | (midpart >> 5 & 0x10); + val = reg[rs1]; + break; + case 128: + rs1 = rd = ((midpart >> 5) & 0x1f) + 8; + imm = 64; + val = reg[rs1]; + break; + } + val = val >> imm; + break; + case 1: /* C.SRAI C.SRAI64 */ +#ifdef DEBUG_EXTRA + switch(XLEN){ + case 32: + case 64: + dprintf(">>> C.SRAI\n"); + case 128: + dprintf(">>> C.SRAI64\n"); + } +#endif + switch(XLEN){ + case 32: case 64: + rs1 = rd = ((midpart >> 5) & 0x1f) + 8; + imm = (midpart & 0xf) | ((midpart >> 5) & 0x10); + val = reg[rs1]; + break; + case 128: + rs1 = rd = ((midpart >> 5) & 0x1f) + 8; + imm = 64; + val = reg[rs1]; + break; + } + val = val << imm; + break; + case 2: /* C.ANDI */ +#ifdef DEBUG_EXTRA + dprintf(">>> C.ANDI\n"); +#endif + rs1 = rd = ((midpart >> 5) & 0x7) + 8; + imm = (midpart & 0x1f) | ((midpart >> 5) & 0x10); + val = reg[rs1]; + val = val & imm; + break; + case 3: /* C.SUB, C.XOR, C.OR, C.AND, C.SUBW, C.ADDW */ + rs2 = (midpart & 0x7) + 8; + rs1 = rd = ((midpart >> 5) & 0x7) + 8; + switch(((midpart >> 3) & 0x3) | ((midpart >> 8) & 0x4) ){ + case 0: /* C.SUB */ +#ifdef DEBUG_EXTRA + dprintf(">>> C.SUB\n"); +#endif + val = reg[rd] - reg[rs2]; + break; + case 1: /* C.XOR */ +#ifdef DEBUG_EXTRA + dprintf(">>> C.XOR\n"); +#endif + val = reg[rd] ^ reg[rs2]; + break; + case 2: /* C.OR */ +#ifdef DEBUG_EXTRA + dprintf(">>> C.OR\n"); +#endif + val = reg[rd] | reg[rs2]; + break; + case 3: /* C.AND */ +#ifdef DEBUG_EXTRA + dprintf(">>> C.AND\n"); +#endif + val = reg[rd] & reg[rs2]; + break; + case 4: /* C.SUBW */ +#ifdef DEBUG_EXTRA + dprintf(">>> C.SUBW\n"); +#endif + val = reg[rd] - reg[rs2]; + if(XLEN == 128){ + val = (int32_t) (val << 96) >> 96; + }else if(XLEN == 64){ + val = (int32_t) (val << 32) >> 32; + }else{ + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + } + break; + case 5: /* C.ADDW */ +#ifdef DEBUG_EXTRA + dprintf(">>> C.ADDW\n"); +#endif + val = reg[rd] + reg[rs2]; + if(XLEN == 128){ + val = (int32_t) (val << 96) >> 96; + }else if(XLEN == 64){ + val = (int32_t) (val << 32) >> 32; + }else{ + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + } + break; + case 6: + case 7: + /* NOP */ + break; + } + } break; case 5: /* C.J */ +#ifdef DEBUG_EXTRA + dprintf(">>> C.J\n"); +#endif + rd = 0; + imm = ((midpart >> 1) & 0x7) | + ((midpart >> 6) & 0x8) | + ((midpart << 5) & 0x10) | + ((midpart) & 0x20) | + ((midpart << 2) & 0x40) | + ((midpart) & 0x180)| + ((midpart << 3) & 0x200)| + ((midpart) & 0x400); + imm = (imm << 1) << 20 >> 20; + next_pc = (int32_t)(pc + imm); + if(next_pc > pc) forward_counter++; + else backward_counter++; + jump_counter++; break; case 6: /* C.BEQZ */ +#ifdef DEBUG_EXTRA + dprintf(">>> C.BEQZ\n"); +#endif + rs1 = ((midpart >> 5) & 0x7) + 8; + rd = 0; + if(reg[rs1] == 0){ + imm = ((midpart >> 1) & 0x3) | + ((midpart >> 3) & 0xc) | + ((midpart << 4) & 0x10) | + ((midpart << 2) & 0x60) | + ((midpart) & 0x80); + imm = (imm << 1) << 23 >> 23; + next_pc = (int32_t)(pc + imm); + if(next_pc > pc) forward_counter++; + else backward_counter++; + jump_counter++; + } break; case 7: /* C.BNEZ */ +#ifdef DEBUG_EXTRA + dprintf(">>> C.BNEZ\n"); +#endif + rs1 = ((midpart >> 5) & 0x7) + 8; + rd = 0; + imm = 0; + if(reg[rs1] != 0){ + imm = ((midpart >> 1) & 0x3) | + ((midpart >> 6) & 0xc) | + ((midpart << 4) & 0x10) | + ((midpart << 2) & 0x60) | + ((midpart) & 0x80); + imm = (imm << 1) << 23 >> 23; + next_pc = (int32_t)(pc + imm); + if(next_pc > pc) forward_counter++; + else backward_counter++; + jump_counter++; + } +#ifdef DEBUG_EXTRA + printf("rd : %d, rs1: %d, imm: %d, reg[rs1] : %d, pc: %08x, next_pc: %08x\n", rd, rs1, imm, reg[rs1]); +#endif break; default: raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); @@ -1972,11 +2221,11 @@ void riscv_cpu_interp_x32() /* Compressed or normal */ insn_type = get_insn32(pc, &insn); #ifdef RV32C - if(insn_type) + if(insn_type == CINSN) next_pc = pc + 2; #endif #ifdef DEBUG_EXTRA - printf("insn : %#x\n", insn); + printf("insn_type : %s\n", insn_type == CINSN ? "CINSN" : "INSN"); #endif insn_counter++; @@ -1985,8 +2234,8 @@ void riscv_cpu_interp_x32() execute_instruction(); } - /* test for misaligned fetches */ - if (next_pc & 3) { + /* test for misaligned fetches , in order to match the compressed instruction. */ + if (next_pc & 0x1) { raise_exception(CAUSE_MISALIGNED_FETCH, next_pc); } From 6331c1535ae1fef98b95c35b7d128957b7c74474 Mon Sep 17 00:00:00 2001 From: "f74064054@mail.ncku.edu.tw" Date: Thu, 2 Jan 2020 17:45:49 +0800 Subject: [PATCH 06/19] Add the new function for signature validation --- Makefile | 1 - debug.txt | 12249 -------------------------------------------------- emu-rv32i.c | 129 +- 3 files changed, 98 insertions(+), 12281 deletions(-) delete mode 100644 debug.txt diff --git a/Makefile b/Makefile index 74f1012..543669f 100644 --- a/Makefile +++ b/Makefile @@ -7,7 +7,6 @@ CFLAGS = -O3 -Wall LDFLAGS = -lelf all: $(BINS) - emu-rv32i: emu-rv32i.c $(CC) $(CFLAGS) -o $@ $< $(LDFLAGS) diff --git a/debug.txt b/debug.txt deleted file mode 100644 index ac5df94..0000000 --- a/debug.txt +++ /dev/null @@ -1,12249 +0,0 @@ -./emu-rv32i work/rv32imc/C-NOP.elf -sym '/tmp/ccoevK6z.o' 0 -sym 'reset_vector' 80000040 -sym 'trap_vector' 80000004 -sym 'write_tohost' 80000036 -sym 'handle_exception' 80000032 -sym 'other_exception' 80000032 -sym 'begin_testcode' 800000f0 -sym 'test_1_res' 80002000 -sym 'end_testcode' 80000122 -sym 'end_signature' 80002020 -sym 'begin_regstate' 80002100 -sym 'begin_signature' 80002000 -sym '_start' 80000000 -sym 'end_regstate' 80002200 -sym '_end' 80002204 -sym 'fromhost' 80001100 -sym 'tohost' 80001000 -begin_signature: 0x80002000 -end_signature: 0x80002020 -start: 0x80000000 -codesize: 0x00002204 (8708) -codesize with offset: 8708 -address 0001a081 -insn_type : CINSN -[80000000]=0000a081, mtime: 1db9bc30e4d, mtimecmp: 0 ->>> C.J -address f1402573 -insn_type : INSN -[80000040]=f1402573, mtime: 1db9bc30f47, mtimecmp: 0 -csr_read: csr=0xf14 0 -csr_read: csr=0xf14 --> 0x00000000 ->>> CSRRS -address 0297e101 -insn_type : CINSN -[80000044]=0000e101, mtime: 1db9bc3103b, mtimecmp: 0 ->>> C.BNEZ -rd : 0, rs1: 10, imm: 0, reg[rs1] : 0, pc: 407b4e99, next_pc: 407b4e9a -address 00000297 -insn_type : INSN -[80000046]=00000297, mtime: 1db9bc3110a, mtimecmp: 0 ->>> AUIPC -address 01228293 -insn_type : INSN -[8000004a]=01228293, mtime: 1db9bc311ae, mtimecmp: 0 ->>> ADDI -address 30529073 -insn_type : INSN -[8000004e]=30529073, mtime: 1db9bc3124f, mtimecmp: 0 ->>> CSRRW -csr_read: csr=0x305 -1 -csr_read: csr=0x305 --> 0x00000000 -csr_write: csr=0x305 val=0x80000058 -address 18005073 -insn_type : INSN -[80000052]=18005073, mtime: 1db9bc31368, mtimecmp: 0 ->>> CSRRWI -csr_read: csr=0x180 -1 -csr_read: csr=0x180 --> 0x00000000 -csr_write: csr=0x180 val=0x00000000 -address 02970001 -insn_type : CINSN -[80000056]=00000001, mtime: 1db9bc3146e, mtimecmp: 0 ->>> C.NOP -address 00000297 -insn_type : INSN -[80000058]=00000297, mtime: 1db9bc3150f, mtimecmp: 0 ->>> AUIPC -address 01828293 -insn_type : INSN -[8000005c]=01828293, mtime: 1db9bc315ae, mtimecmp: 0 ->>> ADDI -address 30529073 -insn_type : INSN -[80000060]=30529073, mtime: 1db9bc3164a, mtimecmp: 0 ->>> CSRRW -csr_read: csr=0x305 -1 -csr_read: csr=0x305 --> 0x80000058 -csr_write: csr=0x305 val=0x80000070 -address 907352fd -insn_type : CINSN -[80000064]=000052fd, mtime: 1db9bc31751, mtimecmp: 0 ->>> C.LI -0000003f, rd: 5 -address 3b029073 -insn_type : INSN -[80000066]=3b029073, mtime: 1db9bc31814, mtimecmp: 0 ->>> CSRRW -csr_read: csr=0x3b0 -1 -csr_read: invalid CSR=0x3b0 -csr_write: csr=0x3b0 val=0x0000003f -address 907342fd -insn_type : CINSN -[8000006a]=000042fd, mtime: 1db9bc31997, mtimecmp: 0 ->>> C.LI -0000001f, rd: 5 -address 3a029073 -insn_type : INSN -[8000006c]=3a029073, mtime: 1db9bc31aaf, mtimecmp: 0 ->>> CSRRW -csr_read: csr=0x3a0 -1 -csr_read: invalid CSR=0x3a0 -csr_write: csr=0x3a0 val=0x0000001f -address 00000297 -insn_type : INSN -[80000070]=00000297, mtime: 1db9bc31bb5, mtimecmp: 0 ->>> AUIPC -address 01828293 -insn_type : INSN -[80000074]=01828293, mtime: 1db9bc31dd9, mtimecmp: 0 ->>> ADDI -address 30529073 -insn_type : INSN -[80000078]=30529073, mtime: 1db9bc31e7c, mtimecmp: 0 ->>> CSRRW -csr_read: csr=0x305 -1 -csr_read: csr=0x305 --> 0x80000070 -csr_write: csr=0x305 val=0x80000088 -address 30205073 -insn_type : INSN -[8000007c]=30205073, mtime: 1db9bc31f7c, mtimecmp: 0 ->>> CSRRWI -csr_read: csr=0x302 -1 -csr_read: csr=0x302 --> 0x00000000 -csr_write: csr=0x302 val=0x00000000 -address 30305073 -insn_type : INSN -[80000080]=30305073, mtime: 1db9bc3207e, mtimecmp: 0 ->>> CSRRWI -csr_read: csr=0x303 -1 -csr_read: csr=0x303 --> 0x00000000 -csr_write: csr=0x303 val=0x00000000 -address 30405073 -insn_type : INSN -[80000084]=30405073, mtime: 1db9bc321a1, mtimecmp: 0 ->>> CSRRWI -csr_read: csr=0x304 -1 -csr_read: csr=0x304 --> 0x00000000 -csr_write: csr=0x304 val=0x00000000 -address 02974181 -insn_type : CINSN -[80000088]=00004181, mtime: 1db9bc3229f, mtimecmp: 0 ->>> C.LI -00000000, rd: 3 -address 00000297 -insn_type : INSN -[8000008a]=00000297, mtime: 1db9bc3235e, mtimecmp: 0 ->>> AUIPC -address f7a28293 -insn_type : INSN -[8000008e]=f7a28293, mtime: 1db9bc323fc, mtimecmp: 0 ->>> ADDI -address 30529073 -insn_type : INSN -[80000092]=30529073, mtime: 1db9bc3249f, mtimecmp: 0 ->>> CSRRW -csr_read: csr=0x305 -1 -csr_read: csr=0x305 --> 0x80000088 -csr_write: csr=0x305 val=0x80000004 -address 057e4505 -insn_type : CINSN -[80000096]=00004505, mtime: 1db9bc325e5, mtimecmp: 0 ->>> C.LI -00000001, rd: 10 -address 4763057e -insn_type : CINSN -[80000098]=0000057e, mtime: 1db9bc326a8, mtimecmp: 0 -address 00054763 -insn_type : INSN -[8000009a]=00054763, mtime: 1db9bc3270d, mtimecmp: 0 ->>> BLT -address 0ff0000f -insn_type : INSN -[8000009e]=0ff0000f, mtime: 1db9bc327ae, mtimecmp: 0 ->>> FENCE -address 00734185 -insn_type : CINSN -[800000a2]=00004185, mtime: 1db9bc32853, mtimecmp: 0 ->>> C.LI -00000001, rd: 3 -address 00000073 -insn_type : INSN -[800000a4]=00000073, mtime: 1db9bc32914, mtimecmp: 0 ->>> ECALL -syscall: 0001 -Unimplement Machine ecall! -address 80000297 -insn_type : INSN -[800000a8]=80000297, mtime: 1db9bc32a14, mtimecmp: 0 ->>> AUIPC -address f5828293 -insn_type : INSN -[800000ac]=f5828293, mtime: 1db9bc32ab2, mtimecmp: 0 ->>> ADDI -address 00028e63 -insn_type : INSN -[800000b0]=00028e63, mtime: 1db9bc32b50, mtimecmp: 0 ->>> BEQ -address 30005073 -insn_type : INSN -[800000cc]=30005073, mtime: 1db9bc32bf7, mtimecmp: 0 ->>> CSRRWI -csr_read: csr=0x300 -1 -csr_read: csr=0x300 --> 0x00000000 -csr_write: csr=0x300 val=0x00000000 -address 00002537 -insn_type : INSN -[800000d0]=00002537, mtime: 1db9bc32cfb, mtimecmp: 0 ->>> LUI -address 80050513 -insn_type : INSN -[800000d4]=80050513, mtime: 1db9bc32d9c, mtimecmp: 0 ->>> ADDI -address 30052073 -insn_type : INSN -[800000d8]=30052073, mtime: 1db9bc32e3a, mtimecmp: 0 -csr_read: csr=0x300 1 -csr_read: csr=0x300 --> 0x00000000 ->>> CSRRS -csr_write: csr=0x300 val=0x00001800 -address 00000297 -insn_type : INSN -[800000dc]=00000297, mtime: 1db9bc32f45, mtimecmp: 0 ->>> AUIPC -address 01428293 -insn_type : INSN -[800000e0]=01428293, mtime: 1db9bc32fe3, mtimecmp: 0 ->>> ADDI -address 34129073 -insn_type : INSN -[800000e4]=34129073, mtime: 1db9bc33081, mtimecmp: 0 ->>> CSRRW -csr_read: csr=0x341 -1 -csr_read: csr=0x341 --> 0x00000000 -csr_write: csr=0x341 val=0x800000f0 -address f1402573 -insn_type : INSN -[800000e8]=f1402573, mtime: 1db9bc33186, mtimecmp: 0 -csr_read: csr=0xf14 0 -csr_read: csr=0xf14 --> 0x00000000 ->>> CSRRS -address 30200073 -insn_type : INSN -[800000ec]=30200073, mtime: 1db9bc33266, mtimecmp: 0 ->>> MRET -address 00002117 -insn_type : INSN -[800000f0]=00002117, mtime: 1db9bc33304, mtimecmp: 0 ->>> AUIPC -address f1010113 -insn_type : INSN -[800000f4]=f1010113, mtime: 1db9bc333a2, mtimecmp: 0 ->>> ADDI -address 00000013 -insn_type : INSN -[800000f8]=00000013, mtime: 1db9bc3343f, mtimecmp: 0 ->>> ADDI -address c0020001 -insn_type : CINSN -[800000fc]=00000001, mtime: 1db9bc334dd, mtimecmp: 0 ->>> C.NOP -address 4201c002 -insn_type : CINSN -[800000fe]=0000c002, mtime: 1db9bc33584, mtimecmp: 0 -address 02014201 -insn_type : CINSN -[80000100]=00004201, mtime: 1db9bc335e6, mtimecmp: 0 ->>> C.LI -00000000, rd: 4 -address c2120201 -insn_type : CINSN -[80000102]=00000201, mtime: 1db9bc336a7, mtimecmp: 0 ->>> C.ADDI -address 4401c212 -insn_type : CINSN -[80000104]=0000c212, mtime: 1db9bc33746, mtimecmp: 0 -address 04014401 -insn_type : CINSN -[80000106]=00004401, mtime: 1db9bc337b1, mtimecmp: 0 ->>> C.LI -00000000, rd: 8 -address c4220401 -insn_type : CINSN -[80000108]=00000401, mtime: 1db9bc3386f, mtimecmp: 0 ->>> C.ADDI -address 4481c422 -insn_type : CINSN -[8000010a]=0000c422, mtime: 1db9bc3390e, mtimecmp: 0 -address 04814481 -insn_type : CINSN -[8000010c]=00004481, mtime: 1db9bc33970, mtimecmp: 0 ->>> C.LI -00000000, rd: 9 -address c6260481 -insn_type : CINSN -[8000010e]=00000481, mtime: 1db9bc33a2e, mtimecmp: 0 ->>> C.ADDI -address 4581c626 -insn_type : CINSN -[80000110]=0000c626, mtime: 1db9bc33acc, mtimecmp: 0 -address 05814581 -insn_type : CINSN -[80000112]=00004581, mtime: 1db9bc33b2e, mtimecmp: 0 ->>> C.LI -00000000, rd: 11 -address c82e0581 -insn_type : CINSN -[80000114]=00000581, mtime: 1db9bc33bf4, mtimecmp: 0 ->>> C.ADDI -address 000fc82e -insn_type : CINSN -[80000116]=0000c82e, mtime: 1db9bc33c92, mtimecmp: 0 -address 0ff0000f -insn_type : INSN -[80000118]=0ff0000f, mtime: 1db9bc33cf5, mtimecmp: 0 ->>> FENCE -address 00734185 -insn_type : CINSN -[8000011c]=00004185, mtime: 1db9bc33d94, mtimecmp: 0 ->>> C.LI -00000001, rd: 3 -address 00000073 -insn_type : INSN -[8000011e]=00000073, mtime: 1db9bc33e54, mtimecmp: 0 ->>> ECALL -syscall: 0001 -Unimplement Machine ecall! -address 00000000 -insn_type : CINSN -[80000122]=00000000, mtime: 1db9bc33f7a, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000124]=00000000, mtime: 1db9bc33fe0, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000126]=00000000, mtime: 1db9bc34044, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000128]=00000000, mtime: 1db9bc340a7, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[8000012a]=00000000, mtime: 1db9bc3410b, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[8000012c]=00000000, mtime: 1db9bc3416e, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[8000012e]=00000000, mtime: 1db9bc341d1, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000130]=00000000, mtime: 1db9bc34234, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000132]=00000000, mtime: 1db9bc34297, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000134]=00000000, mtime: 1db9bc342f9, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000136]=00000000, mtime: 1db9bc34362, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000138]=00000000, mtime: 1db9bc343c4, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[8000013a]=00000000, mtime: 1db9bc34426, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[8000013c]=00000000, mtime: 1db9bc34488, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[8000013e]=00000000, mtime: 1db9bc344e9, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000140]=00000000, mtime: 1db9bc3454b, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000142]=00000000, mtime: 1db9bc345b0, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000144]=00000000, mtime: 1db9bc34614, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000146]=00000000, mtime: 1db9bc34676, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000148]=00000000, mtime: 1db9bc346d7, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[8000014a]=00000000, mtime: 1db9bc34739, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[8000014c]=00000000, mtime: 1db9bc3479b, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[8000014e]=00000000, mtime: 1db9bc347ff, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000150]=00000000, mtime: 1db9bc34861, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000152]=00000000, mtime: 1db9bc348c5, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000154]=00000000, mtime: 1db9bc34927, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000156]=00000000, mtime: 1db9bc34990, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000158]=00000000, mtime: 1db9bc349f2, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[8000015a]=00000000, mtime: 1db9bc34a54, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[8000015c]=00000000, mtime: 1db9bc34ab5, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[8000015e]=00000000, mtime: 1db9bc34b17, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000160]=00000000, mtime: 1db9bc34b79, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000162]=00000000, mtime: 1db9bc34bdd, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000164]=00000000, mtime: 1db9bc34c69, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000166]=00000000, mtime: 1db9bc34cf8, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000168]=00000000, mtime: 1db9bc34d7d, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[8000016a]=00000000, mtime: 1db9bc34dfb, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[8000016c]=00000000, mtime: 1db9bc34e5c, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[8000016e]=00000000, mtime: 1db9bc34ebe, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000170]=00000000, mtime: 1db9bc34f20, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000172]=00000000, mtime: 1db9bc34f81, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000174]=00000000, mtime: 1db9bc34fe3, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000176]=00000000, mtime: 1db9bc35045, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000178]=00000000, mtime: 1db9bc350a7, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[8000017a]=00000000, mtime: 1db9bc35108, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[8000017c]=00000000, mtime: 1db9bc3516a, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[8000017e]=00000000, mtime: 1db9bc351fe, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000180]=00000000, mtime: 1db9bc35261, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000182]=00000000, mtime: 1db9bc352c3, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000184]=00000000, mtime: 1db9bc35328, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000186]=00000000, mtime: 1db9bc3538a, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000188]=00000000, mtime: 1db9bc353f0, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[8000018a]=00000000, mtime: 1db9bc35452, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[8000018c]=00000000, mtime: 1db9bc354b3, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[8000018e]=00000000, mtime: 1db9bc355a2, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000190]=00000000, mtime: 1db9bc355f5, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000192]=00000000, mtime: 1db9bc35645, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000194]=00000000, mtime: 1db9bc35694, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000196]=00000000, mtime: 1db9bc356e4, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000198]=00000000, mtime: 1db9bc35732, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[8000019a]=00000000, mtime: 1db9bc35781, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[8000019c]=00000000, mtime: 1db9bc357d1, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[8000019e]=00000000, mtime: 1db9bc35820, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001a0]=00000000, mtime: 1db9bc35876, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001a2]=00000000, mtime: 1db9bc358c5, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001a4]=00000000, mtime: 1db9bc35915, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001a6]=00000000, mtime: 1db9bc35964, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001a8]=00000000, mtime: 1db9bc359b3, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001aa]=00000000, mtime: 1db9bc35a02, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001ac]=00000000, mtime: 1db9bc35a51, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001ae]=00000000, mtime: 1db9bc35aa3, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001b0]=00000000, mtime: 1db9bc35af2, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001b2]=00000000, mtime: 1db9bc35b41, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001b4]=00000000, mtime: 1db9bc35b95, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001b6]=00000000, mtime: 1db9bc35be6, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001b8]=00000000, mtime: 1db9bc35c37, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001ba]=00000000, mtime: 1db9bc35c86, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001bc]=00000000, mtime: 1db9bc35cd5, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001be]=00000000, mtime: 1db9bc35d25, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001c0]=00000000, mtime: 1db9bc35d74, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001c2]=00000000, mtime: 1db9bc35dc3, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001c4]=00000000, mtime: 1db9bc35e13, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001c6]=00000000, mtime: 1db9bc35e68, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001c8]=00000000, mtime: 1db9bc35eb8, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001ca]=00000000, mtime: 1db9bc35f07, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001cc]=00000000, mtime: 1db9bc35f57, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001ce]=00000000, mtime: 1db9bc35fa6, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001d0]=00000000, mtime: 1db9bc35ff5, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001d2]=00000000, mtime: 1db9bc36044, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001d4]=00000000, mtime: 1db9bc36093, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001d6]=00000000, mtime: 1db9bc360e6, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001d8]=00000000, mtime: 1db9bc36137, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001da]=00000000, mtime: 1db9bc361a0, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001dc]=00000000, mtime: 1db9bc361f1, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001de]=00000000, mtime: 1db9bc36240, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001e0]=00000000, mtime: 1db9bc3628f, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001e2]=00000000, mtime: 1db9bc362e2, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001e4]=00000000, mtime: 1db9bc36331, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001e6]=00000000, mtime: 1db9bc36381, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001e8]=00000000, mtime: 1db9bc363d0, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001ea]=00000000, mtime: 1db9bc36425, mtimecmp: 0 -address 00000000 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-insn_type : CINSN -[80001fd4]=00000000, mtime: 1db9bc70605, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001fd6]=00000000, mtime: 1db9bc70635, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001fd8]=00000000, mtime: 1db9bc70665, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001fda]=00000000, mtime: 1db9bc70694, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001fdc]=00000000, mtime: 1db9bc706c6, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001fde]=00000000, mtime: 1db9bc706f6, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001fe0]=00000000, mtime: 1db9bc70725, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001fe2]=00000000, mtime: 1db9bc70755, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001fe4]=00000000, mtime: 1db9bc70784, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001fe6]=00000000, mtime: 1db9bc707b4, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001fe8]=00000000, mtime: 1db9bc707e3, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001fea]=00000000, mtime: 1db9bc70813, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001fec]=00000000, mtime: 1db9bc70842, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001fee]=00000000, mtime: 1db9bc70872, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001ff0]=00000000, mtime: 1db9bc708a6, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001ff2]=00000000, mtime: 1db9bc708d6, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001ff4]=00000000, mtime: 1db9bc70905, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001ff6]=00000000, mtime: 1db9bc70935, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001ff8]=00000000, mtime: 1db9bc70968, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001ffa]=00000000, mtime: 1db9bc70998, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001ffc]=00000000, mtime: 1db9bc709c7, mtimecmp: 0 -address ffff0000 -insn_type : CINSN -[80001ffe]=00000000, mtime: 1db9bc709f5, mtimecmp: 0 -address ffffffff -insn_type : INSN -[80002000]=ffffffff, mtime: 1db9bc70a22, mtimecmp: 0 -raise_exception: illegal instruction 0x2 0xffffffff -done interp faf int=0 mstatus=80 prv=3 - -Registers: -x0 zero: 00000000 -x1 ra: 00000000 -x2 sp: 80002000 -x3 gp: 00000001 -x4 tp: 00000000 -x5 t0: 800000f0 -x6 t1: 00000000 -x7 t2: 00000000 -x8 s0: 00000000 -x9 s1: 00000000 -x10 a0: 00000000 -x11 a1: 00000000 -x12 a2: 00000000 -x13 a3: 00000000 -x14 a4: 00000000 -x15 a5: 00000000 -x16 a6: 00000000 -x17 a7: 00000000 -x18 s2: 00000000 -x19 s3: 00000000 -x20 s4: 00000000 -x21 s5: 00000000 -x22 s6: 00000000 -x23 s7: 00000000 -x24 s8: 00000000 -x25 s9: 00000000 -x26 s10: 00000000 -x27 s11: 00000000 -x28 t3: 00000000 -x29 t4: 00000000 -x30 t5: 00000000 -x31 t6: 00000000 - -Instructions Stat: -LUI = 1 -AUIPC = 7 -BEQ = 1 -BLT = 1 -ADDI = 9 -FENCE = 2 -ECALL = 2 -CSRRW = 7 -CSRRS = 3 -CSRRWI = 5 -LI* = 1 -MRET = 1 - -Five Most Frequent: -1) ADDI = 9 (0.22%) -2) AUIPC = 7 (0.17%) -3) CSRRW = 7 (0.17%) -4) CSRRWI = 5 (0.12%) -5) CSRRS = 3 (0.07%) - -Memory Reading Area 80000000...80002003 -Memory Writing Area NONE - ->>> Execution time: 26116764 ns ->>> Instruction count: 4015 (IPS=153732) ->>> Jumps: 2 (0.05%) - 2 forwards, 0 backwards ->>> Branching T=1 (50.00%) F=1 (50.00%) - diff --git a/emu-rv32i.c b/emu-rv32i.c index 55d989e..db6724e 100644 --- a/emu-rv32i.c +++ b/emu-rv32i.c @@ -18,7 +18,9 @@ #include #include #include - +#include +#include +#include /* uncomment this for an instruction trace and other debug outputs */ // #define DEBUG_OUTPUT // #define DEBUG_EXTRA @@ -1893,14 +1895,14 @@ void execute_instruction() #endif return; } else { + rs1 = rd = ((midpart >> 5) & 0x1f); + imm = (midpart & 0x1f) | ((midpart >> 5) & 0x20); + val = reg[rs1] + imm; #ifdef DEBUG_EXTRA dprintf(">>> C.ADDI\n"); + printf("rd: %d, rs1: %d, imm: %d, reg[rd]: %d, val: %d\n", rd, rs1, imm, reg[rd], val); #endif - rs1 = rd = ((midpart >> 5) & 0x1f) + 8; - imm = (midpart & 0x1f) | ((midpart >> 5) & 0x20); - val = reg[rs1] + imm; - } - break; + }break; case 1: /* C.JAL, C.ADDIW */ #ifdef DEBUG_EXTRA switch(XLEN){ @@ -1926,9 +1928,8 @@ void execute_instruction() ((midpart << 4) & 0x10) | ((midpart >> 6) & 0x8) | ((midpart >> 1) & 0x7); - imm = imm & 0xfffe; - if (rd != 0) - reg[1] = pc + 2; /* Store the link to x1 register */ + imm = (imm << 1) & 0xfffe; + reg[1] = pc + 2; /* Store the link to x1 register */ next_pc = (int32_t)(pc + imm); if(next_pc > pc) forward_counter++; else backward_counter++; @@ -1950,7 +1951,6 @@ void execute_instruction() rs1 = rd = ((midpart >> 5) & 0x1f); imm = ((midpart >> 5) & 0x20) | (midpart & 0x1f); val = imm; - printf("%08x, rd: %d\n", val, rd); break; case 3: /* C.ADDI16SP, C.LUI */ #ifdef DEBUG_EXTRA @@ -1962,15 +1962,14 @@ void execute_instruction() dprintf(">>> C.LUI\n"); } #endif - rs1 = rd = ((midpart >> 5) & 0x1f); - switch(rd){ + switch(rd){ /* C.ADDI16SP */ case 2: imm = ((midpart >> 4) & 0x1) | ((midpart << 1) & 0x2) | - ((midpart) & 0x8) | - ((midpart << 2) & 0xc) | - ((midpart >> 5) & 0x10); - imm = imm << 4; + ((midpart >> 1) & 0x4) | + ((midpart << 2) & 0x18) | + ((midpart >> 5) & 0x20); + imm = (imm << 4 )<< (31 - 9) >> (31 - 9); val = reg[rd] + imm; break; default: @@ -2175,6 +2174,25 @@ void execute_instruction() } break; case 2: + funct3 = (insn >> 13) & 0x7; + midpart = (insn >> 2) & 0x07ff; + switch(funct3){ + case 6: +#ifdef DEBUG_EXTRA + dprintf(">>> C.SWSP\n"); +#endif + rs2 = midpart & 0x1f; + imm = ((midpart >> 2) & 0x1e0) | + ((midpart << 4) & 0x600); + imm = (imm >> 3) & 0xff; + addr = reg[2] + imm; + val = reg[rs2]; + if (target_write_u32(addr, val)) { + raise_exception(pending_exception, pending_tval); + return; + } + break; + } break; default: @@ -2256,16 +2274,31 @@ int main(int argc, char **argv) /* automatic STDOUT flushing, no fflush needed */ setvbuf(stdout, NULL, _IONBF, 0); - /* parse command line */ - const char *elf_file = NULL; - const char *signature_file = NULL; - for (int i = 1; i < argc; i++) { - char *arg = argv[i]; - if (arg == strstr(arg, "+signature=")) { - signature_file = arg + 11; - } else if (arg[0] != '-') { - elf_file = arg; + const char* elf_file = NULL; + const char* signature_file = NULL; + const char* output_file = NULL; + int cmd_opt = 0; + struct option opts[] = { + {"elf", 1, NULL, 'e'}, + {"signature", 1, NULL, 's'}, + {"output", 1, NULL, 'o'} + }; + const char* optstring = "e:s:o:"; + while((cmd_opt = getopt_long(argc, argv, optstring, opts, NULL)) != -1){ + switch(cmd_opt){ + case 'e': + elf_file = optarg; + break; + case 's': + signature_file = optarg; + break; + case 'o': + output_file = optarg; + break; + default: + printf("Unknow argument: %s\n", optarg); + break; } } if (elf_file == NULL) { @@ -2446,18 +2479,52 @@ int main(int argc, char **argv) uint64_t ns2 = get_clock(); /* write signature */ + /* Check signature */ if (signature_file) { - FILE *sf = fopen(signature_file, "w"); + FILE* sf = fopen(signature_file, "r"); + if(sf == NULL){ + printf("Error opening file\n"); + return -1; + } int size = end_signature - begin_signature; - for (int i = 0; i < size / 16; i++) { - for (int j = 0; j < 16; j++) { - fprintf(sf, "%02x", ram[begin_signature + 15 - j - ram_start]); + char temp[50], ans[50]; + uint32_t tb = begin_signature; + int err = 0; + for(int i=0;i %s\n", temp, ans); + err++; + }else{ + printf("%s\n", temp); + } + memset(temp, '\0', 50); + } + if(err == 0){ + printf("%s TEST PASSED\n", elf_file); + }else{ + printf("%s TEST FAILED\n", elf_file); + printf("Number of failed signature : %d\n", err); } fclose(sf); } + if (output_file) { + FILE* of = fopen(output_file, "w"); + int size = end_signature - begin_signature; + for (int i = 0; i < size / 4; i++) { + for (int j = 0; j < 4; j++) { + fprintf(of, "%02x", ram[begin_signature + 3 - j - ram_start]); + } + begin_signature += 4; + fprintf(of, "\n"); + } + fclose(of); + } #ifdef DEBUG_EXTRA dump_regs(); From 5b143f9b73a621cd7ac580572ad441f266c93a88 Mon Sep 17 00:00:00 2001 From: "f74064054@mail.ncku.edu.tw" Date: Thu, 2 Jan 2020 17:49:01 +0800 Subject: [PATCH 07/19] Modified the gitignore --- .gitignore | 2 ++ 1 file changed, 2 insertions(+) diff --git a/.gitignore b/.gitignore index 4aa3c06..c5adc9d 100644 --- a/.gitignore +++ b/.gitignore @@ -1,2 +1,4 @@ emu-rv32i test1 +sig.txt +rom.v From 25705a36b089e76e2a0a43359fb81afa20763e5f Mon Sep 17 00:00:00 2001 From: kksweet8845 <37268557+kksweet8845@users.noreply.github.com> Date: Thu, 2 Jan 2020 18:02:14 +0800 Subject: [PATCH 08/19] Update README.txt Add the method of how to test file --- README.md | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/README.md b/README.md index 723e246..ad7c8bf 100644 --- a/README.md +++ b/README.md @@ -12,9 +12,13 @@ How to compile it: ```shell $ gcc -O3 -Wall -lelf emu-rv32i.c -o emu-rv32i ``` +or +```shell +$ make emu-rv32i +``` -Run RV32I compliance tests. -Assume `emu-rv32i` in `$PATH` environment variable. +Passed RV32I compliance tests from https://github.com/riscv/riscv-compliance +- Must install the [risc-v toolchain](https://xpack.github.io/riscv-none-embed-gcc/) ```shell $ git clone https://github.com/riscv/riscv-compliance $ cd riscv-compliance @@ -23,12 +27,7 @@ $ make RISCV_PREFIX=riscv-none-embed- RISCV_DEVICE=rv32i TARGET_SIM=emu-rv32i va Compiling and running simple code: ```shell -$ riscv32-unknown-elf-gcc -O3 -nostdlib test1.c -o test1 -``` - -or -```shell -$ riscv64-unknown-elf-gcc -march=rv32i -mabi=ilp32 -O3 -nostdlib test1.c -o test1 +$ make test1 ``` then @@ -37,6 +36,13 @@ $ ./emu-rv32i test1 Hello RISC-V! ``` +Passed RV32C compliance tests from https://github.com/riscv/riscv-compliance +``shell +make C-ADDI.log +``` +If there is no accident, it will output the `TEST PASSED` + + RV32M and RV32A instructions may be enabled by commenting `#define STRICT_RV32I`. ## How to build RISC-V toolchain from scratch From 5036e85845f33bac195a080f7b5dcebfe58179b9 Mon Sep 17 00:00:00 2001 From: kksweet8845 <37268557+kksweet8845@users.noreply.github.com> Date: Thu, 2 Jan 2020 18:05:41 +0800 Subject: [PATCH 09/19] Update README.txt --- README.md | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/README.md b/README.md index ad7c8bf..c0d1243 100644 --- a/README.md +++ b/README.md @@ -36,15 +36,17 @@ $ ./emu-rv32i test1 Hello RISC-V! ``` +- RV32M and RV32A instructions may be enabled by commenting `#define STRICT_RV32I`. + + Passed RV32C compliance tests from https://github.com/riscv/riscv-compliance -``shell +```shell make C-ADDI.log ``` If there is no accident, it will output the `TEST PASSED` -RV32M and RV32A instructions may be enabled by commenting `#define STRICT_RV32I`. - +- RV32C instructions can be enabled by commenting `#define RV32C` ## How to build RISC-V toolchain from scratch https://github.com/riscv/riscv-gnu-toolchain From 965e0d871ea705eb59a1b47a35e4d9686a1d8e73 Mon Sep 17 00:00:00 2001 From: "f74064054@mail.ncku.edu.tw" Date: Thu, 2 Jan 2020 18:15:49 +0800 Subject: [PATCH 10/19] Modified the makefile to enable to check the validation --- Makefile | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/Makefile b/Makefile index 543669f..381d946 100644 --- a/Makefile +++ b/Makefile @@ -1,4 +1,30 @@ BINS = emu-rv32i test1 +TEST_TARGETS = \ + C-ADD.elf \ + C-ADDI.elf \ + C-ADDI4SPN.elf \ + C-AND.elf \ + C-ANDI.elf \ + C-BEQZ.elf \ + C-BNEZ.elf \ + C-J.elf \ + C-JAL.elf \ + C-JALR.elf \ + C-JR.elf \ + C-LI.elf \ + C-LUI.elf \ + C-LW.elf \ + C-LWSP.elf \ + C-MV.elf \ + C-NOP.elf \ + C-OR.elf \ + C-SLLI.elf \ + C-SRAI.elf \ + C-SRLI.elf \ + C-SUB.elf \ + C-SW.elf \ + C-SWSP.elf \ + C-XOR.elf CROSS_COMPILE = riscv-none-embed- RV32I_CFLAGS = -march=rv32i -mabi=ilp32 -O3 -nostdlib From 3ce28805e578cab571e2012bec579be378126570 Mon Sep 17 00:00:00 2001 From: kksweet8845 <37268557+kksweet8845@users.noreply.github.com> Date: Thu, 2 Jan 2020 23:35:35 +0800 Subject: [PATCH 11/19] Update README.md --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index c0d1243..748f7eb 100644 --- a/README.md +++ b/README.md @@ -1,4 +1,4 @@ -# RISC-V RV32I[MA] emulator with ELF support +# RISC-V RV32I[MAC] emulator with ELF support This is a RISC-V emulator for the RV32I architecture, based on [TinyEMU](https://bellard.org/tinyemu/) and stripped down for RV32I only. From 5b770af48e7079235b9066de02183f0409131446 Mon Sep 17 00:00:00 2001 From: "f74064054@mail.ncku.edu.tw" Date: Wed, 22 Jan 2020 22:23:30 +0800 Subject: [PATCH 12/19] Finish the test for rv32i comformance tests I have modified the emu-rv32i for supporting riscv-compliance test-suite. However, it is needed to copy the makefile.include to the specified directory which is explained in README.md. --- .gitignore | 4 + README.md | 15 +- emu-rv32i.c | 86 ++++----- rv32emu/compliance_io.h | 240 ++++++++++++++++++++++++++ rv32emu/compliance_test.h | 34 ++++ rv32emu/device/rv32i/Makefile.include | 32 ++++ 6 files changed, 368 insertions(+), 43 deletions(-) create mode 100644 rv32emu/compliance_io.h create mode 100644 rv32emu/compliance_test.h create mode 100644 rv32emu/device/rv32i/Makefile.include diff --git a/.gitignore b/.gitignore index c5adc9d..2ebc6f7 100644 --- a/.gitignore +++ b/.gitignore @@ -2,3 +2,7 @@ emu-rv32i test1 sig.txt rom.v +debug.txt +# ignore generated files +*.mem +*.signature.output diff --git a/README.md b/README.md index 748f7eb..a77f4ed 100644 --- a/README.md +++ b/README.md @@ -1,4 +1,4 @@ -# RISC-V RV32I[MAC] emulator with ELF support +# RISC-V RV32I[MA] emulator with ELF support This is a RISC-V emulator for the RV32I architecture, based on [TinyEMU](https://bellard.org/tinyemu/) and stripped down for RV32I only. @@ -21,9 +21,20 @@ Passed RV32I compliance tests from https://github.com/riscv/riscv-compliance - Must install the [risc-v toolchain](https://xpack.github.io/riscv-none-embed-gcc/) ```shell $ git clone https://github.com/riscv/riscv-compliance -$ cd riscv-compliance +$ cd rv32emu +$ cp rv32emu ../riscv-compliance/riscv-target +$ cd ../riscv-compliance $ make RISCV_PREFIX=riscv-none-embed- RISCV_DEVICE=rv32i TARGET_SIM=emu-rv32i variant ``` +- Run RV32IMC compliance tests. +Assume `emu-rv32i` in `$PATH` environment variable. +```shell +$ git clone https://github.com/riscv/riscv-compliance +$ cd rv32emu +$ cp rv32emu ../riscv-compliance/riscv-target # If having copied the makefile.include to riscv-compliance, it can be ignored. +$ cd riscv-compliance +$ make RISCV_PREFIX=riscv-none-embed- RISCV_DEVICE=rv32imc TARGET_SIM=/abs/path/to/emu-rv32i variant +``` Compiling and running simple code: ```shell diff --git a/emu-rv32i.c b/emu-rv32i.c index db6724e..eebc99f 100644 --- a/emu-rv32i.c +++ b/emu-rv32i.c @@ -22,8 +22,8 @@ #include #include /* uncomment this for an instruction trace and other debug outputs */ -// #define DEBUG_OUTPUT -// #define DEBUG_EXTRA +#define DEBUG_OUTPUT +#define DEBUG_EXTRA #define STRICT_RV32I #define FALSE (0) @@ -636,21 +636,6 @@ void raise_exception(uint32_t cause, uint32_t tval) return; } - switch(cause){ - case CAUSE_MACHINE_ECALL: - printf("Unimplement Machine ecall!\n"); - return; - case CAUSE_USER_ECALL: - printf("Unimplement User ecall!\n"); - return; - case CAUSE_SUPERVISOR_ECALL: - printf("Unimplement Supervisor ecall!\n"); - return; - case CAUSE_HYPERVISOR_ECALL: - printf("Unimplement Hypervisor ecall!\n"); - return; - } - if (priv <= PRV_S) { /* delegate the exception to the supervisor priviledge */ if (cause & CAUSE_INTERRUPT) @@ -2252,10 +2237,17 @@ void riscv_cpu_interp_x32() execute_instruction(); } - /* test for misaligned fetches , in order to match the compressed instruction. */ + /* test for misaligned fetches , in order to match the compressed + * instruction. */ +#ifdef RV32C if (next_pc & 0x1) { raise_exception(CAUSE_MISALIGNED_FETCH, next_pc); } +#else + if (next_pc & 0x3) { + raise_exception(CAUSE_MISALIGNED_FETCH, next_pc); + } +#endif /* update current PC */ pc = next_pc; @@ -2275,30 +2267,38 @@ int main(int argc, char **argv) /* automatic STDOUT flushing, no fflush needed */ setvbuf(stdout, NULL, _IONBF, 0); /* parse command line */ - const char* elf_file = NULL; + const char *elf_file = NULL; + int output_flag = 0; + const char *output_file = NULL; + const char *elf_name = NULL; const char* signature_file = NULL; - const char* output_file = NULL; int cmd_opt = 0; - struct option opts[] = { - {"elf", 1, NULL, 'e'}, - {"signature", 1, NULL, 's'}, - {"output", 1, NULL, 'o'} - }; - const char* optstring = "e:s:o:"; - while((cmd_opt = getopt_long(argc, argv, optstring, opts, NULL)) != -1){ - switch(cmd_opt){ - case 'e': - elf_file = optarg; - break; - case 's': - signature_file = optarg; - break; - case 'o': - output_file = optarg; - break; - default: - printf("Unknow argument: %s\n", optarg); - break; + struct option opts[] = {{"elf", 1, NULL, 'e'}, + {"verify", 1, NULL, 'v'}, + {"signaturedump", 0, NULL, 's'}}; + const char *optstring = "e:s:o:"; + while ((cmd_opt = getopt_long(argc, argv, optstring, opts, NULL)) != -1) { + switch (cmd_opt) { + case 'e': + elf_file = optarg; + elf_name = strtok(strdup(elf_file), "."); + printf("%s\n", elf_name); + output_file = malloc(strlen(elf_name) + 30); + memset(output_file, '\0', strlen(elf_name) + 30); + strcat(output_file, elf_name); + strcat(output_file, ".signature.output"); + printf("signature.output : %s\n", output_file); + break; + case 'v': + //signature_file = optarg; + break; + case 's': + //output_file = optarg; + output_flag = 1; + break; + default: + printf("Unknow argument: %s\n", optarg); + break; } } if (elf_file == NULL) { @@ -2366,11 +2366,15 @@ int main(int argc, char **argv) while ((scn = elf_nextscn(elf, scn)) != NULL) { gelf_getshdr(scn, &shdr); const char *name = elf_strptr(elf, shstrndx, shdr.sh_name); - + printf("section name: %s\n", name); + printf("Type: %d\n", shdr.sh_type); if (shdr.sh_type == SHT_PROGBITS) { if (strcmp(name, ".text") == 0) { ram_start = shdr.sh_addr; break; + }else if(strcmp(name, ".text.init") == 0){ + ram_start = shdr.sh_addr; + break; } } } diff --git a/rv32emu/compliance_io.h b/rv32emu/compliance_io.h new file mode 100644 index 0000000..c7d3215 --- /dev/null +++ b/rv32emu/compliance_io.h @@ -0,0 +1,240 @@ +// RISC-V Compliance IO Test Header File + +/* + * Copyright (c) 2005-2018 Imperas Software Ltd., www.imperas.com + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, + * either express or implied. + * + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + + +// +// In general the following registers are reserved +// ra, a0, t0, t1 +// x1, x10 x5, x6 +// new reserve x31 +// + +#ifndef _COMPLIANCE_IO_H +#define _COMPLIANCE_IO_H + +#define RVTEST_IO_QUIET + +//----------------------------------------------------------------------- +// RV IO Macros (Character transfer by custom instruction) +//----------------------------------------------------------------------- +#define STRINGIFY(x) #x +#define TOSTRING(x) STRINGIFY(x) + +#define RVTEST_CUSTOM1 0x0005200B + +#ifdef RVTEST_IO_QUIET + +#define RVTEST_IO_INIT +#define RVTEST_IO_WRITE_STR(_SP, _STR) +#define RVTEST_IO_CHECK() +#define RVTEST_IO_ASSERT_GPR_EQ(_SP, _R, _I) +#define RVTEST_IO_ASSERT_SFPR_EQ(_F, _R, _I) +#define RVTEST_IO_ASSERT_DFPR_EQ(_D, _R, _I) + +#else + +#define RSIZE 4 +// _SP = (volatile register) +#define LOCAL_IO_PUSH(_SP) \ + la _SP, begin_regstate; \ + sw x1, (1*RSIZE)(_SP); \ + sw x5, (5*RSIZE)(_SP); \ + sw x6, (6*RSIZE)(_SP); \ + sw x8, (8*RSIZE)(_SP); \ + sw x10, (10*RSIZE)(_SP); + +// _SP = (volatile register) +#define LOCAL_IO_POP(_SP) \ + la _SP, begin_regstate; \ + lw x1, (1*RSIZE)(_SP); \ + lw x5, (5*RSIZE)(_SP); \ + lw x6, (6*RSIZE)(_SP); \ + lw x8, (8*RSIZE)(_SP); \ + lw x10, (10*RSIZE)(_SP); + +#define LOCAL_IO_WRITE_GPR(_R) \ + mv a0, _R; \ + jal FN_WriteA0; + +#define LOCAL_IO_WRITE_FPR(_F) \ + fmv.x.s a0, _F; \ + jal FN_WriteA0; + +#define LOCAL_IO_WRITE_DFPR(_V1, _V2) \ + mv a0, _V1; \ + jal FN_WriteA0; \ + mv a0, _V2; \ + jal FN_WriteA0; \ + +#define LOCAL_IO_PUTC(_R) \ + .word RVTEST_CUSTOM1; \ + +#define RVTEST_IO_INIT + +// Assertion violation: file file.c, line 1234: (expr) +// _SP = (volatile register) +// _R = GPR +// _I = Immediate +#define RVTEST_IO_ASSERT_GPR_EQ(_SP, _R, _I) \ + LOCAL_IO_PUSH(_SP) \ + mv s0, _R; \ + li t0, _I; \ + beq s0, t0, 20002f; \ + LOCAL_IO_WRITE_STR("Assertion violation: file "); \ + LOCAL_IO_WRITE_STR(__FILE__); \ + LOCAL_IO_WRITE_STR(", line "); \ + LOCAL_IO_WRITE_STR(TOSTRING(__LINE__)); \ + LOCAL_IO_WRITE_STR(": "); \ + LOCAL_IO_WRITE_STR(# _R); \ + LOCAL_IO_WRITE_STR("("); \ + LOCAL_IO_WRITE_GPR(s0); \ + LOCAL_IO_WRITE_STR(") != "); \ + LOCAL_IO_WRITE_STR(# _I); \ + LOCAL_IO_WRITE_STR("\n"); \ + li TESTNUM, 100; \ + RVTEST_FAIL; \ +20002: \ + LOCAL_IO_POP(_SP) + +// _F = FPR +// _C = GPR +// _I = Immediate +#define RVTEST_IO_ASSERT_SFPR_EQ(_F, _C, _I) \ + fmv.x.s t0, _F; \ + beq _C, t0, 20003f; \ + LOCAL_IO_WRITE_STR("Assertion violation: file "); \ + LOCAL_IO_WRITE_STR(__FILE__); \ + LOCAL_IO_WRITE_STR(", line "); \ + LOCAL_IO_WRITE_STR(TOSTRING(__LINE__)); \ + LOCAL_IO_WRITE_STR(": "); \ + LOCAL_IO_WRITE_STR(# _F); \ + LOCAL_IO_WRITE_STR("("); \ + LOCAL_IO_WRITE_FPR(_F); \ + LOCAL_IO_WRITE_STR(") != "); \ + LOCAL_IO_WRITE_STR(# _I); \ + LOCAL_IO_WRITE_STR("\n"); \ + li TESTNUM, 100; \ + RVTEST_FAIL; \ +20003: + +// _D = DFPR +// _R = GPR +// _I = Immediate +#define RVTEST_IO_ASSERT_DFPR_EQ(_D, _R, _I) \ + fmv.x.d t0, _D; \ + beq _R, t0, 20005f; \ + LOCAL_IO_WRITE_STR("Assertion violation: file "); \ + LOCAL_IO_WRITE_STR(__FILE__); \ + LOCAL_IO_WRITE_STR(", line "); \ + LOCAL_IO_WRITE_STR(TOSTRING(__LINE__)); \ + LOCAL_IO_WRITE_STR(": "); \ + LOCAL_IO_WRITE_STR(# _D); \ + LOCAL_IO_WRITE_STR("("); \ + LOCAL_IO_WRITE_DFPR(_D); \ + LOCAL_IO_WRITE_STR(") != "); \ + LOCAL_IO_WRITE_STR(# _I); \ + LOCAL_IO_WRITE_STR("\n"); \ + li TESTNUM, 100; \ + RVTEST_FAIL; \ +20005: + +// _SP = (volatile register) +#define LOCAL_IO_WRITE_STR(_STR) RVTEST_IO_WRITE_STR(x31, _STR) +#define RVTEST_IO_WRITE_STR(_SP, _STR) \ + LOCAL_IO_PUSH(_SP) \ + .section .data.string; \ +20001: \ + .string _STR; \ + .section .text.init; \ + la a0, 20001b; \ + jal FN_WriteStr; \ + LOCAL_IO_POP(_SP) + +// generate assertion listing +#define LOCAL_CHECK() RVTEST_IO_CHECK() +#define RVTEST_IO_CHECK() \ + li zero, -1; \ + +// +// FN_WriteStr: Uses a0, t0 +// +FN_WriteStr: + mv t0, a0; +10000: + lbu a0, (t0); + addi t0, t0, 1; + beq a0, zero, 10000f; + LOCAL_IO_PUTC(a0); + j 10000b; +10000: + ret; + +// +// FN_WriteA0: write register a0(x10) (destroys a0(x10), t0-t2(x5-x7)) +// +FN_WriteA0: + mv t0, a0 + // determine architectural register width + li a0, -1 + srli a0, a0, 31 + srli a0, a0, 1 + bnez a0, FN_WriteA0_64 + +FN_WriteA0_32: + // reverse register when xlen is 32 + li t1, 8 +10000: slli t2, t2, 4 + andi a0, t0, 0xf + srli t0, t0, 4 + or t2, t2, a0 + addi t1, t1, -1 + bnez t1, 10000b + li t1, 8 + j FN_WriteA0_common + +FN_WriteA0_64: + // reverse register when xlen is 64 + li t1, 16 +10000: slli t2, t2, 4 + andi a0, t0, 0xf + srli t0, t0, 4 + or t2, t2, a0 + addi t1, t1, -1 + bnez t1, 10000b + li t1, 16 + +FN_WriteA0_common: + // write reversed characters + li t0, 10 +10000: andi a0, t2, 0xf + blt a0, t0, 10001f + addi a0, a0, 'a'-10 + j 10002f +10001: addi a0, a0, '0' +10002: LOCAL_IO_PUTC(a0) + srli t2, t2, 4 + addi t1, t1, -1 + bnez t1, 10000b + ret + +#endif // RVTEST_IO_QUIET + +#endif // _COMPLIANCE_IO_H diff --git a/rv32emu/compliance_test.h b/rv32emu/compliance_test.h new file mode 100644 index 0000000..dcf0a9b --- /dev/null +++ b/rv32emu/compliance_test.h @@ -0,0 +1,34 @@ +// RISC-V Compliance Test Header File +// Copyright (c) 2017, Codasip Ltd. All Rights Reserved. +// See LICENSE for license details. +// +// Description: Common header file for RV32I tests + +#ifndef _COMPLIANCE_TEST_H +#define _COMPLIANCE_TEST_H + +#include "riscv_test.h" + +//----------------------------------------------------------------------- +// RV Compliance Macros +//----------------------------------------------------------------------- + +#define RV_COMPLIANCE_HALT \ + RVTEST_PASS \ + +#define RV_COMPLIANCE_RV32M \ + RVTEST_RV32M \ + +#define RV_COMPLIANCE_CODE_BEGIN \ + RVTEST_CODE_BEGIN \ + +#define RV_COMPLIANCE_CODE_END \ + RVTEST_CODE_END \ + +#define RV_COMPLIANCE_DATA_BEGIN \ + RVTEST_DATA_BEGIN \ + +#define RV_COMPLIANCE_DATA_END \ + RVTEST_DATA_END \ + +#endif diff --git a/rv32emu/device/rv32i/Makefile.include b/rv32emu/device/rv32i/Makefile.include new file mode 100644 index 0000000..136ec00 --- /dev/null +++ b/rv32emu/device/rv32i/Makefile.include @@ -0,0 +1,32 @@ +ifeq ($(OS),Windows_NT) + ARCH := Windows64 +else + ARCH := Linux64 +endif + +TARGET_SIM ?= /home/nober/git/adv_CO/riscv-compliance/riscv-ovpsim/bin/Linux64/riscvOVPsim.exe +TARGET_FLAGS ?= $(RISCV_TARGET_FLAGS) +ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),) + $(error Target simulator executable '$(TARGET_SIM)` not found) +endif + + +RUN_TARGET=\ + $(TARGET_SIM) $(TARGET_FLAGS) \ + --elf $(work_dir_isa)$< \ + --signaturedump + + +RISCV_PREFIX ?= riscv-none-embed- +RISCV_GCC ?= $(RISCV_PREFIX)gcc +RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump +RISCV_GCC_OPTS ?= -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles + +COMPILE_TARGET=\ + $$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) \ + -I$(ROOTDIR)/riscv-test-env/ \ + -I$(ROOTDIR)/riscv-test-env/p/ \ + -I$(TARGETDIR)/$(RISCV_TARGET)/ \ + -T$(ROOTDIR)/riscv-test-env/p/link.ld $$< \ + -o $(work_dir_isa)$$@; \ + $$(RISCV_OBJDUMP) -D $(work_dir_isa)$$@ > $(work_dir_isa)$$@.objdump \ No newline at end of file From a4a2aa2cd5315838b12e12b9459b33d922348ade Mon Sep 17 00:00:00 2001 From: "f74064054@mail.ncku.edu.tw" Date: Wed, 22 Jan 2020 22:44:18 +0800 Subject: [PATCH 13/19] Format all files with postfix c and h --- CSRs.h | 32 +- emu-rv32i.c | 2292 ++++++++++++++++++++++++++------------------------- test1.c | 4 +- 3 files changed, 1168 insertions(+), 1160 deletions(-) diff --git a/CSRs.h b/CSRs.h index 32daaee..72a9d8c 100644 --- a/CSRs.h +++ b/CSRs.h @@ -5,8 +5,8 @@ /* RISCV emulator for the RV32I architecture based on TinyEMU by Fabrice Bellard, see https://bellard.org/tinyemu/ -stripped down for RV32I only, all "gotos" removed, and fixed some bugs for the compliance test -by Frank Buss, 2018 +stripped down for RV32I only, all "gotos" removed, and fixed some bugs for the +compliance test by Frank Buss, 2018 Requires libelf-dev: @@ -18,10 +18,12 @@ Compile it like this: gcc -O3 -Wall -lelf emu-rv32i.c -o emu-rv32i -It is compatible to Spike for the command line arguments, which means you can run -the compliance test from https://github.com/riscv/riscv-compliance like this: +It is compatible to Spike for the command line arguments, which means you can +run the compliance test from https://github.com/riscv/riscv-compliance like +this: -make RISCV_TARGET=spike RISCV_DEVICE=rv32i TARGET_SIM=/full/path/emulator variant +make RISCV_TARGET=spike RISCV_DEVICE=rv32i TARGET_SIM=/full/path/emulator +variant It is also compatible with qemu32, as it is used for Zephyr. You can compile the Zephyr examples for qemu like this: @@ -73,19 +75,19 @@ original copyright: // ====================================================== // // =================== User Trap Setup ================== // // ====================================================== // -uint32_t ustatus; /* User status register */ -uint32_t uie; /* User interrupt-enable register */ -uint32_t utvec; /* User trap handler base address */ +uint32_t ustatus; /* User status register */ +uint32_t uie; /* User interrupt-enable register */ +uint32_t utvec; /* User trap handler base address */ // ====================================================== // // ================= User Trap Handling ================= // // ====================================================== // -uint32_t uscratch; /* Scratch register for user trap handlers*/ -uint32_t uepc; /* User exception program counter */ -uint32_t ucause; /* User trap cause*/ -uint32_t ubadaddr; /* User bad address */ -uint32_t uip; /* User interrupt pending */ +uint32_t uscratch; /* Scratch register for user trap handlers*/ +uint32_t uepc; /* User exception program counter */ +uint32_t ucause; /* User trap cause*/ +uint32_t ubadaddr; /* User bad address */ +uint32_t uip; /* User interrupt pending */ // ====================================================== // // ============== User Floating-Point CSRs ============== // // ====================================================== // -uint32_t fflags; /* Floating-Point Accrued Exceptions*/ -uint32_t frm; /* Floating-Point Dynamic Rounding Mode*/ +uint32_t fflags; /* Floating-Point Accrued Exceptions*/ +uint32_t frm; /* Floating-Point Dynamic Rounding Mode*/ diff --git a/emu-rv32i.c b/emu-rv32i.c index eebc99f..8d2fc26 100644 --- a/emu-rv32i.c +++ b/emu-rv32i.c @@ -9,6 +9,7 @@ #include #include +#include #include #include #include @@ -18,9 +19,6 @@ #include #include #include -#include -#include -#include /* uncomment this for an instruction trace and other debug outputs */ #define DEBUG_OUTPUT #define DEBUG_EXTRA @@ -720,13 +718,14 @@ unsigned char get_insn32(uint32_t pc, uint32_t *insn) maxmemr = pc + 3; #endif uint32_t ptr = pc - ram_start; - if (ptr > RAM_SIZE) return 1; - uint8_t* p = ram + ptr; + if (ptr > RAM_SIZE) + return 1; + uint8_t *p = ram + ptr; #ifdef DEBUG_OUTPUT printf("address %08x\n", p[0] | (p[1] << 8) | (p[2] << 16) | (p[3] << 24)); #endif #ifdef RV32C - if((p[0] & 0x03) < 3){ + if ((p[0] & 0x03) < 3) { *insn = (p[0] | ((p[1] << 8) & 0x0000ffff)); return CINSN; } @@ -1024,7 +1023,7 @@ void execute_instruction() uint16_t midpart; - if(insn_type == INSN){ + if (insn_type == INSN) { opcode = insn & 0x7f; rd = (insn >> 7) & 0x1f; rs1 = (insn >> 15) & 0x1f; @@ -1032,7 +1031,7 @@ void execute_instruction() } #ifdef RV32C - if(insn_type == CINSN){ + if (insn_type == CINSN) { opcode = insn & 0x3; } #endif @@ -1121,776 +1120,780 @@ void execute_instruction() } else { debug_out(">>> BGE\n"); stats[7]++; - if (!(funct3 & 1)) { - debug_out(">>> BLTU\n"); - stats[8]++; - } else { - debug_out(">>> BGEU\n"); - stats[9]++; - } + if (!(funct3 & 1)) { + debug_out(">>> BLTU\n"); + stats[8]++; + } else { + debug_out(">>> BGEU\n"); + stats[9]++; + } #endif - cond = (reg[rs1] < reg[rs2]); - break; - default: - raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); - return; - } - cond ^= (funct3 & 1); - if (cond) { - imm = ((insn >> (31 - 12)) & (1 << 12)) | - ((insn >> (25 - 5)) & 0x7e0) | ((insn >> (8 - 1)) & 0x1e) | - ((insn << (11 - 7)) & (1 << 11)); - imm = (imm << 19) >> 19; - next_pc = (int32_t)(pc + imm); - if (next_pc > pc) - forward_counter++; - else - backward_counter++; - jump_counter++; - true_counter++; + cond = (reg[rs1] < reg[rs2]); + break; + default: + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + return; + } + cond ^= (funct3 & 1); + if (cond) { + imm = ((insn >> (31 - 12)) & (1 << 12)) | + ((insn >> (25 - 5)) & 0x7e0) | + ((insn >> (8 - 1)) & 0x1e) | + ((insn << (11 - 7)) & (1 << 11)); + imm = (imm << 19) >> 19; + next_pc = (int32_t)(pc + imm); + if (next_pc > pc) + forward_counter++; + else + backward_counter++; + jump_counter++; + true_counter++; + break; + } else + false_counter++; break; - } else - false_counter++; - break; - case 0x03: /* LOAD */ + case 0x03: /* LOAD */ - funct3 = (insn >> 12) & 7; - imm = (int32_t) insn >> 20; - addr = reg[rs1] + imm; - switch (funct3) { - case 0: /* lb */ - { + funct3 = (insn >> 12) & 7; + imm = (int32_t) insn >> 20; + addr = reg[rs1] + imm; + switch (funct3) { + case 0: /* lb */ + { #ifdef DEBUG_EXTRA - debug_out(">>> LB\n"); - stats[10]++; + debug_out(">>> LB\n"); + stats[10]++; #endif - uint8_t rval; - if (target_read_u8(&rval, addr)) { - raise_exception(pending_exception, pending_tval); - return; - } - val = (int8_t) rval; - } break; + uint8_t rval; + if (target_read_u8(&rval, addr)) { + raise_exception(pending_exception, pending_tval); + return; + } + val = (int8_t) rval; + } break; - case 1: /* lh */ - { + case 1: /* lh */ + { #ifdef DEBUG_EXTRA - debug_out(">>> LH\n"); - stats[11]++; + debug_out(">>> LH\n"); + stats[11]++; #endif - uint16_t rval; - if (target_read_u16(&rval, addr)) { - raise_exception(pending_exception, pending_tval); - return; - } - val = (int16_t) rval; - } break; + uint16_t rval; + if (target_read_u16(&rval, addr)) { + raise_exception(pending_exception, pending_tval); + return; + } + val = (int16_t) rval; + } break; - case 2: /* lw */ - { + case 2: /* lw */ + { #ifdef DEBUG_EXTRA - debug_out(">>> LW\n"); - stats[12]++; + debug_out(">>> LW\n"); + stats[12]++; #endif - uint32_t rval; - if (target_read_u32(&rval, addr)) { - raise_exception(pending_exception, pending_tval); - return; - } - val = (int32_t) rval; - } break; + uint32_t rval; + if (target_read_u32(&rval, addr)) { + raise_exception(pending_exception, pending_tval); + return; + } + val = (int32_t) rval; + } break; - case 4: /* lbu */ - { + case 4: /* lbu */ + { #ifdef DEBUG_EXTRA - debug_out(">>> LBU\n"); - stats[13]++; + debug_out(">>> LBU\n"); + stats[13]++; #endif - uint8_t rval; - if (target_read_u8(&rval, addr)) { - raise_exception(pending_exception, pending_tval); - return; - } - val = rval; - } break; + uint8_t rval; + if (target_read_u8(&rval, addr)) { + raise_exception(pending_exception, pending_tval); + return; + } + val = rval; + } break; - case 5: /* lhu */ - { + case 5: /* lhu */ + { #ifdef DEBUG_EXTRA - debug_out(">>> LHU\n"); - stats[14]++; + debug_out(">>> LHU\n"); + stats[14]++; #endif - uint16_t rval; - if (target_read_u16(&rval, addr)) { - raise_exception(pending_exception, pending_tval); - return; - } - val = rval; - } break; - - default: - raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); - return; - } - if (rd != 0) - reg[rd] = val; - break; - - case 0x23: /* STORE */ + uint16_t rval; + if (target_read_u16(&rval, addr)) { + raise_exception(pending_exception, pending_tval); + return; + } + val = rval; + } break; - funct3 = (insn >> 12) & 7; - imm = rd | ((insn >> (25 - 5)) & 0xfe0); - imm = (imm << 20) >> 20; - addr = reg[rs1] + imm; - val = reg[rs2]; - switch (funct3) { - case 0: /* sb */ -#ifdef DEBUG_EXTRA - debug_out(">>> SB\n"); - stats[15]++; -#endif - if (target_write_u8(addr, val)) { - raise_exception(pending_exception, pending_tval); + default: + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); return; } + if (rd != 0) + reg[rd] = val; break; - case 1: /* sh */ + case 0x23: /* STORE */ + + funct3 = (insn >> 12) & 7; + imm = rd | ((insn >> (25 - 5)) & 0xfe0); + imm = (imm << 20) >> 20; + addr = reg[rs1] + imm; + val = reg[rs2]; + switch (funct3) { + case 0: /* sb */ #ifdef DEBUG_EXTRA - debug_out(">>> SH\n"); - stats[16]++; + debug_out(">>> SB\n"); + stats[15]++; #endif - if (target_write_u16(addr, val)) { - raise_exception(pending_exception, pending_tval); - return; - } - break; + if (target_write_u8(addr, val)) { + raise_exception(pending_exception, pending_tval); + return; + } + break; + + case 1: /* sh */ +#ifdef DEBUG_EXTRA + debug_out(">>> SH\n"); + stats[16]++; +#endif + if (target_write_u16(addr, val)) { + raise_exception(pending_exception, pending_tval); + return; + } + break; - case 2: /* sw */ + case 2: /* sw */ #ifdef DEBUG_EXTRA - debug_out(">>> SW\n"); - stats[17]++; + debug_out(">>> SW\n"); + stats[17]++; #endif - if (target_write_u32(addr, val)) { - raise_exception(pending_exception, pending_tval); + if (target_write_u32(addr, val)) { + raise_exception(pending_exception, pending_tval); + return; + } + break; + + default: + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); return; } break; - default: - raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); - return; - } - break; - - case 0x13: /* OP-IMM */ + case 0x13: /* OP-IMM */ - funct3 = (insn >> 12) & 7; - imm = (int32_t) insn >> 20; - switch (funct3) { - case 0: /* addi */ + funct3 = (insn >> 12) & 7; + imm = (int32_t) insn >> 20; + switch (funct3) { + case 0: /* addi */ #ifdef DEBUG_EXTRA - debug_out(">>> ADDI\n"); - stats[18]++; - if (rs1 == 0) - stats[47]++; /* li */ + debug_out(">>> ADDI\n"); + stats[18]++; + if (rs1 == 0) + stats[47]++; /* li */ #endif - val = (int32_t)(reg[rs1] + imm); - break; - case 1: /* slli */ + val = (int32_t)(reg[rs1] + imm); + break; + case 1: /* slli */ #ifdef DEBUG_EXTRA - debug_out(">>> SLLI\n"); - stats[24]++; + debug_out(">>> SLLI\n"); + stats[24]++; #endif - if ((imm & ~(XLEN - 1)) != 0) { - raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); - return; - } - val = (int32_t)(reg[rs1] << (imm & (XLEN - 1))); - break; - case 2: /* slti */ + if ((imm & ~(XLEN - 1)) != 0) { + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + return; + } + val = (int32_t)(reg[rs1] << (imm & (XLEN - 1))); + break; + case 2: /* slti */ #ifdef DEBUG_EXTRA - debug_out(">>> SLTI\n"); - stats[19]++; + debug_out(">>> SLTI\n"); + stats[19]++; #endif - val = (int32_t) reg[rs1] < (int32_t) imm; - break; - case 3: /* sltiu */ + val = (int32_t) reg[rs1] < (int32_t) imm; + break; + case 3: /* sltiu */ #ifdef DEBUG_EXTRA - debug_out(">>> SLTIU\n"); - stats[20]++; + debug_out(">>> SLTIU\n"); + stats[20]++; #endif - val = reg[rs1] < (uint32_t) imm; - break; - case 4: /* xori */ + val = reg[rs1] < (uint32_t) imm; + break; + case 4: /* xori */ #ifdef DEBUG_EXTRA - debug_out(">>> XORI\n"); - stats[21]++; + debug_out(">>> XORI\n"); + stats[21]++; #endif - val = reg[rs1] ^ imm; - break; - case 5: /* srli/srai */ - if ((imm & ~((XLEN - 1) | 0x400)) != 0) { - raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); - return; - } - if (imm & 0x400) { + val = reg[rs1] ^ imm; + break; + case 5: /* srli/srai */ + if ((imm & ~((XLEN - 1) | 0x400)) != 0) { + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + return; + } + if (imm & 0x400) { #ifdef DEBUG_EXTRA - debug_out(">>> SRAI\n"); - stats[26]++; + debug_out(">>> SRAI\n"); + stats[26]++; #endif - val = (int32_t) reg[rs1] >> (imm & (XLEN - 1)); - } else { + val = (int32_t) reg[rs1] >> (imm & (XLEN - 1)); + } else { #ifdef DEBUG_EXTRA - debug_out(">>> SRLI\n"); - stats[25]++; + debug_out(">>> SRLI\n"); + stats[25]++; #endif - val = (int32_t)((uint32_t) reg[rs1] >> (imm & (XLEN - 1))); - } - break; - case 6: /* ori */ + val = (int32_t)((uint32_t) reg[rs1] >> (imm & (XLEN - 1))); + } + break; + case 6: /* ori */ #ifdef DEBUG_EXTRA - debug_out(">>> ORI\n"); - stats[22]++; + debug_out(">>> ORI\n"); + stats[22]++; #endif - val = reg[rs1] | imm; - break; - case 7: /* andi */ + val = reg[rs1] | imm; + break; + case 7: /* andi */ #ifdef DEBUG_EXTRA - debug_out(">>> ANDI\n"); - stats[23]++; + debug_out(">>> ANDI\n"); + stats[23]++; #endif - val = reg[rs1] & imm; + val = reg[rs1] & imm; + break; + } + if (rd != 0) + reg[rd] = val; break; - } - if (rd != 0) - reg[rd] = val; - break; - case 0x33: /* OP */ + case 0x33: /* OP */ - imm = insn >> 25; - val = reg[rs1]; - val2 = reg[rs2]; + imm = insn >> 25; + val = reg[rs1]; + val2 = reg[rs2]; #ifndef STRICT_RV32I - if (imm == 1) { - funct3 = (insn >> 12) & 7; - switch (funct3) { - case 0: /* mul */ + if (imm == 1) { + funct3 = (insn >> 12) & 7; + switch (funct3) { + case 0: /* mul */ #ifdef DEBUG_EXTRA - debug_out(">>> MUL\n"); - stats[48]++; + debug_out(">>> MUL\n"); + stats[48]++; #endif - val = (int32_t)((int32_t) val * (int32_t) val2); - break; - case 1: /* mulh */ + val = (int32_t)((int32_t) val * (int32_t) val2); + break; + case 1: /* mulh */ #ifdef DEBUG_EXTRA - debug_out(">>> MULH\n"); - stats[49]++; + debug_out(">>> MULH\n"); + stats[49]++; #endif - val = (int32_t) mulh32(val, val2); - break; - case 2: /* mulhsu */ + val = (int32_t) mulh32(val, val2); + break; + case 2: /* mulhsu */ #ifdef DEBUG_EXTRA - debug_out(">>> MULHSU\n"); - stats[50]++; + debug_out(">>> MULHSU\n"); + stats[50]++; #endif - val = (int32_t) mulhsu32(val, val2); - break; - case 3: /* mulhu */ + val = (int32_t) mulhsu32(val, val2); + break; + case 3: /* mulhu */ #ifdef DEBUG_EXTRA - debug_out(">>> MULHU\n"); - stats[51]++; + debug_out(">>> MULHU\n"); + stats[51]++; #endif - val = (int32_t) mulhu32(val, val2); - break; - case 4: /* div */ + val = (int32_t) mulhu32(val, val2); + break; + case 4: /* div */ #ifdef DEBUG_EXTRA - debug_out(">>> DIV\n"); - stats[52]++; + debug_out(">>> DIV\n"); + stats[52]++; #endif - val = div32(val, val2); - break; - case 5: /* divu */ + val = div32(val, val2); + break; + case 5: /* divu */ #ifdef DEBUG_EXTRA - debug_out(">>> DIVU\n"); - stats[53]++; + debug_out(">>> DIVU\n"); + stats[53]++; #endif - val = (int32_t) divu32(val, val2); - break; - case 6: /* rem */ + val = (int32_t) divu32(val, val2); + break; + case 6: /* rem */ #ifdef DEBUG_EXTRA - debug_out(">>> REM\n"); - stats[54]++; + debug_out(">>> REM\n"); + stats[54]++; #endif - val = rem32(val, val2); - break; - case 7: /* remu */ + val = rem32(val, val2); + break; + case 7: /* remu */ #ifdef DEBUG_EXTRA - debug_out(">>> REMU\n"); - stats[55]++; -#endif - val = (int32_t) remu32(val, val2); - break; - default: - raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); - return; - } - } else + debug_out(">>> REMU\n"); + stats[55]++; #endif - { - if (imm & ~0x20) { - raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); - return; - } - funct3 = ((insn >> 12) & 7) | ((insn >> (30 - 3)) & (1 << 3)); - switch (funct3) { - case 0: /* add */ -#ifdef DEBUG_EXTRA - debug_out(">>> ADD\n"); - stats[27]++; + val = (int32_t) remu32(val, val2); + break; + default: + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + return; + } + } else #endif - val = (int32_t)(val + val2); - break; - case 0 | 8: /* sub */ + { + if (imm & ~0x20) { + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + return; + } + funct3 = ((insn >> 12) & 7) | ((insn >> (30 - 3)) & (1 << 3)); + switch (funct3) { + case 0: /* add */ #ifdef DEBUG_EXTRA - debug_out(">>> SUB\n"); - stats[28]++; + debug_out(">>> ADD\n"); + stats[27]++; #endif - val = (int32_t)(val - val2); - break; - case 1: /* sll */ + val = (int32_t)(val + val2); + break; + case 0 | 8: /* sub */ #ifdef DEBUG_EXTRA - debug_out(">>> SLL\n"); - stats[29]++; + debug_out(">>> SUB\n"); + stats[28]++; #endif - val = (int32_t)(val << (val2 & (XLEN - 1))); - break; - case 2: /* slt */ + val = (int32_t)(val - val2); + break; + case 1: /* sll */ #ifdef DEBUG_EXTRA - debug_out(">>> SLT\n"); - stats[30]++; + debug_out(">>> SLL\n"); + stats[29]++; #endif - val = (int32_t) val < (int32_t) val2; - break; - case 3: /* sltu */ + val = (int32_t)(val << (val2 & (XLEN - 1))); + break; + case 2: /* slt */ #ifdef DEBUG_EXTRA - debug_out(">>> SLTU\n"); - stats[31]++; + debug_out(">>> SLT\n"); + stats[30]++; #endif - val = val < val2; - break; - case 4: /* xor */ + val = (int32_t) val < (int32_t) val2; + break; + case 3: /* sltu */ #ifdef DEBUG_EXTRA - debug_out(">>> XOR\n"); - stats[32]++; + debug_out(">>> SLTU\n"); + stats[31]++; #endif - val = val ^ val2; - break; - case 5: /* srl */ + val = val < val2; + break; + case 4: /* xor */ #ifdef DEBUG_EXTRA - debug_out(">>> SRL\n"); - stats[33]++; + debug_out(">>> XOR\n"); + stats[32]++; #endif - val = (int32_t)((uint32_t) val >> (val2 & (XLEN - 1))); - break; - case 5 | 8: /* sra */ + val = val ^ val2; + break; + case 5: /* srl */ #ifdef DEBUG_EXTRA - debug_out(">>> SRA\n"); - stats[34]++; + debug_out(">>> SRL\n"); + stats[33]++; #endif - val = (int32_t) val >> (val2 & (XLEN - 1)); - break; - case 6: /* or */ + val = (int32_t)((uint32_t) val >> (val2 & (XLEN - 1))); + break; + case 5 | 8: /* sra */ #ifdef DEBUG_EXTRA - debug_out(">>> OR\n"); - stats[35]++; + debug_out(">>> SRA\n"); + stats[34]++; #endif - val = val | val2; - break; - case 7: /* and */ + val = (int32_t) val >> (val2 & (XLEN - 1)); + break; + case 6: /* or */ #ifdef DEBUG_EXTRA - debug_out(">>> AND\n"); - stats[36]++; + debug_out(">>> OR\n"); + stats[35]++; #endif - val = val & val2; - break; - default: - raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); - return; - } - } - if (rd != 0) - reg[rd] = val; - break; - - case 0x73: /* SYSTEM */ - - funct3 = (insn >> 12) & 7; - imm = insn >> 20; - if (funct3 & 4) - val = rs1; - else - val = reg[rs1]; - funct3 &= 3; - switch (funct3) { - case 1: /* csrrw & csrrwi */ + val = val | val2; + break; + case 7: /* and */ #ifdef DEBUG_EXTRA - if ((insn >> 12) & 4) { - debug_out(">>> CSRRWI\n"); - stats[44]++; - } else { - debug_out(">>> CSRRW\n"); - stats[41]++; - } + debug_out(">>> AND\n"); + stats[36]++; #endif - if (csr_read(&val2, imm, TRUE)) { - raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); - return; - } - val2 = (int32_t) val2; - err = csr_write(imm, val); - if (err < 0) { - raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); - return; + val = val & val2; + break; + default: + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + return; + } } if (rd != 0) - reg[rd] = val2; - if (err > 0) { - /* pc = pc + 4; */ - } + reg[rd] = val; break; - case 2: /* csrrs & csrrsi */ - case 3: /* csrrc & csrrci */ - if (csr_read(&val2, imm, (rs1 != 0))) { - raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); - return; - } - val2 = (int32_t) val2; + case 0x73: /* SYSTEM */ + + funct3 = (insn >> 12) & 7; + imm = insn >> 20; + if (funct3 & 4) + val = rs1; + else + val = reg[rs1]; + funct3 &= 3; + switch (funct3) { + case 1: /* csrrw & csrrwi */ #ifdef DEBUG_EXTRA - switch ((insn >> 12) & 7) { - case 2: - debug_out(">>> CSRRS\n"); - stats[42]++; - break; - case 3: - debug_out(">>> CSRRC\n"); - stats[43]++; - break; - case 6: - debug_out(">>> CSRRSI\n"); - stats[45]++; - break; - case 7: - debug_out(">>> CSRRCI\n"); - stats[46]++; - break; - } -#endif - if (rs1 != 0) { - if (funct3 == 2) { - val = val2 | val; + if ((insn >> 12) & 4) { + debug_out(">>> CSRRWI\n"); + stats[44]++; } else { - val = val2 & ~val; + debug_out(">>> CSRRW\n"); + stats[41]++; + } +#endif + if (csr_read(&val2, imm, TRUE)) { + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + return; } + val2 = (int32_t) val2; err = csr_write(imm, val); if (err < 0) { raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); return; } - } else { - err = 0; - } - if (rd != 0) - reg[rd] = val2; - break; + if (rd != 0) + reg[rd] = val2; + if (err > 0) { + /* pc = pc + 4; */ + } + break; - case 0: - switch (imm) { - case 0x000: /* ecall */ -#ifdef DEBUG_EXTRA - debug_out(">>> ECALL\n"); - stats[39]++; -#endif - if (insn & 0x000fff80) { + case 2: /* csrrs & csrrsi */ + case 3: /* csrrc & csrrci */ + if (csr_read(&val2, imm, (rs1 != 0))) { raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); return; } - /* - * compliance test specific: if bit 0 of gp (x3) is 0, it is a - * syscall, otherwise it is the program end, with the exit code - * in the bits 31:1 - */ - if (begin_signature) { - if (reg[3] & 1) { - debug_out("program end, result: %04x\n", reg[3] >> 1); - machine_running = FALSE; - return; - + val2 = (int32_t) val2; +#ifdef DEBUG_EXTRA + switch ((insn >> 12) & 7) { + case 2: + debug_out(">>> CSRRS\n"); + stats[42]++; + break; + case 3: + debug_out(">>> CSRRC\n"); + stats[43]++; + break; + case 6: + debug_out(">>> CSRRSI\n"); + stats[45]++; + break; + case 7: + debug_out(">>> CSRRCI\n"); + stats[46]++; + break; + } +#endif + if (rs1 != 0) { + if (funct3 == 2) { + val = val2 | val; } else { - debug_out("syscall: %04x\n", reg[3]); - raise_exception(CAUSE_USER_ECALL + priv, 0); + val = val2 & ~val; + } + err = csr_write(imm, val); + if (err < 0) { + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + return; } } else { - /* on real hardware, an exception is raised, the I-ECALL-01 - * compliance test tests this as well */ - raise_exception(CAUSE_USER_ECALL + priv, 0); - return; + err = 0; } + if (rd != 0) + reg[rd] = val2; break; - case 0x001: /* ebreak */ + case 0: + switch (imm) { + case 0x000: /* ecall */ #ifdef DEBUG_EXTRA - debug_out(">>> EBREAK\n"); - stats[40]++; + debug_out(">>> ECALL\n"); + stats[39]++; #endif - if (insn & 0x000fff80) { - raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + if (insn & 0x000fff80) { + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + return; + } + /* + * compliance test specific: if bit 0 of gp (x3) is 0, it is + * a syscall, otherwise it is the program end, with the exit + * code in the bits 31:1 + */ + if (begin_signature) { + if (reg[3] & 1) { + debug_out("program end, result: %04x\n", + reg[3] >> 1); + machine_running = FALSE; + return; + + } else { + debug_out("syscall: %04x\n", reg[3]); + raise_exception(CAUSE_USER_ECALL + priv, 0); + } + } else { + /* on real hardware, an exception is raised, the + * I-ECALL-01 compliance test tests this as well */ + raise_exception(CAUSE_USER_ECALL + priv, 0); + return; + } + break; + + case 0x001: /* ebreak */ +#ifdef DEBUG_EXTRA + debug_out(">>> EBREAK\n"); + stats[40]++; +#endif + if (insn & 0x000fff80) { + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + return; + } + raise_exception(CAUSE_BREAKPOINT, 0); return; - } - raise_exception(CAUSE_BREAKPOINT, 0); - return; - case 0x102: /* sret */ - { + case 0x102: /* sret */ + { #ifdef DEBUG_EXTRA - debug_out(">>> SRET\n"); - stats[59]++; + debug_out(">>> SRET\n"); + stats[59]++; #endif - if ((insn & 0x000fff80) || (priv < PRV_S)) { - raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + if ((insn & 0x000fff80) || (priv < PRV_S)) { + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + return; + } + handle_sret(); return; - } - handle_sret(); - return; - } break; + } break; - case 0x105: /* wfi */ + case 0x105: /* wfi */ #ifdef DEBUG_EXTRA - debug_out(">>> WFI\n"); - stats[61]++; + debug_out(">>> WFI\n"); + stats[61]++; #endif - /* wait for interrupt: it is allowed to execute it as nop */ - break; + /* wait for interrupt: it is allowed to execute it as nop */ + break; - case 0x302: /* mret */ - { + case 0x302: /* mret */ + { #ifdef DEBUG_EXTRA - debug_out(">>> MRET\n"); - stats[60]++; + debug_out(">>> MRET\n"); + stats[60]++; #endif - if ((insn & 0x000fff80) || (priv < PRV_M)) { - raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + if ((insn & 0x000fff80) || (priv < PRV_M)) { + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + return; + } + handle_mret(); return; - } - handle_mret(); - return; - } break; + } break; - default: - if ((imm >> 5) == 0x09) { + default: + if ((imm >> 5) == 0x09) { #ifdef DEBUG_EXTRA - debug_out(">>> SFENCE.VMA\n"); - stats[62]++; + debug_out(">>> SFENCE.VMA\n"); + stats[62]++; #endif - /* sfence.vma */ - if ((insn & 0x00007f80) || (priv == PRV_U)) { + /* sfence.vma */ + if ((insn & 0x00007f80) || (priv == PRV_U)) { + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + return; + } + } else { raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); return; } - } else { - raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); - return; + break; } break; + + default: + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + return; } break; - default: - raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); - return; - } - break; - - case 0x0f: /* MISC-MEM */ + case 0x0f: /* MISC-MEM */ - funct3 = (insn >> 12) & 7; - switch (funct3) { - case 0: /* fence */ + funct3 = (insn >> 12) & 7; + switch (funct3) { + case 0: /* fence */ #ifdef DEBUG_EXTRA - debug_out(">>> FENCE\n"); - stats[37]++; + debug_out(">>> FENCE\n"); + stats[37]++; #endif - if (insn & 0xf00fff80) { - raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); - return; - } - break; + if (insn & 0xf00fff80) { + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + return; + } + break; - case 1: /* fence.i */ + case 1: /* fence.i */ #ifdef DEBUG_EXTRA - debug_out(">>> FENCE.I\n"); - stats[38]++; + debug_out(">>> FENCE.I\n"); + stats[38]++; #endif - if (insn != 0x0000100f) { + if (insn != 0x0000100f) { + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + return; + } + break; + + default: raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); return; } break; - default: - raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); - return; - } - break; - #ifndef STRICT_RV32I - case 0x2f: /* AMO */ + case 0x2f: /* AMO */ - funct3 = (insn >> 12) & 7; - switch (funct3) { - case 2: { - uint32_t rval; - - addr = reg[rs1]; - funct3 = insn >> 27; + funct3 = (insn >> 12) & 7; switch (funct3) { - case 2: /* lr.w */ -#ifdef DEBUG_EXTRA - debug_out(">>> LR.W\n"); - stats[56]++; -#endif - if (rs2 != 0) { - raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); - return; - } - if (target_read_u32(&rval, addr)) { - raise_exception(pending_exception, pending_tval); - return; - } - val = (int32_t) rval; - load_res = addr; - break; + case 2: { + uint32_t rval; - case 3: /* sc.w */ + addr = reg[rs1]; + funct3 = insn >> 27; + switch (funct3) { + case 2: /* lr.w */ #ifdef DEBUG_EXTRA - debug_out(">>> SC.W\n"); - stats[57]++; + debug_out(">>> LR.W\n"); + stats[56]++; #endif - if (load_res == addr) { - if (target_write_u32(addr, reg[rs2])) { + if (rs2 != 0) { + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + return; + } + if (target_read_u32(&rval, addr)) { raise_exception(pending_exception, pending_tval); return; } - val = 0; - } else { - val = 1; - } - break; - - case 1: /* amiswap.w */ - case 0: /* amoadd.w */ - case 4: /* amoxor.w */ - case 0xc: /* amoand.w */ - case 0x8: /* amoor.w */ - case 0x10: /* amomin.w */ - case 0x14: /* amomax.w */ - case 0x18: /* amominu.w */ - case 0x1c: /* amomaxu.w */ + val = (int32_t) rval; + load_res = addr; + break; + case 3: /* sc.w */ #ifdef DEBUG_EXTRA - debug_out(">>> AM...\n"); - stats[63]++; + debug_out(">>> SC.W\n"); + stats[57]++; #endif - if (target_read_u32(&rval, addr)) { - raise_exception(pending_exception, pending_tval); - return; - } - val = (int32_t) rval; - val2 = reg[rs2]; - switch (funct3) { - case 1: /* amiswap.w */ - break; - case 0: /* amoadd.w */ - val2 = (int32_t)(val + val2); - break; - case 4: /* amoxor.w */ - val2 = (int32_t)(val ^ val2); - break; - case 0xc: /* amoand.w */ - val2 = (int32_t)(val & val2); - break; - case 0x8: /* amoor.w */ - val2 = (int32_t)(val | val2); + if (load_res == addr) { + if (target_write_u32(addr, reg[rs2])) { + raise_exception(pending_exception, pending_tval); + return; + } + val = 0; + } else { + val = 1; + } break; + + case 1: /* amiswap.w */ + case 0: /* amoadd.w */ + case 4: /* amoxor.w */ + case 0xc: /* amoand.w */ + case 0x8: /* amoor.w */ case 0x10: /* amomin.w */ - if ((int32_t) val < (int32_t) val2) - val2 = (int32_t) val; - break; case 0x14: /* amomax.w */ - if ((int32_t) val > (int32_t) val2) - val2 = (int32_t) val; - break; case 0x18: /* amominu.w */ - if ((uint32_t) val < (uint32_t) val2) - val2 = (int32_t) val; - break; case 0x1c: /* amomaxu.w */ - if ((uint32_t) val > (uint32_t) val2) - val2 = (int32_t) val; + +#ifdef DEBUG_EXTRA + debug_out(">>> AM...\n"); + stats[63]++; +#endif + if (target_read_u32(&rval, addr)) { + raise_exception(pending_exception, pending_tval); + return; + } + val = (int32_t) rval; + val2 = reg[rs2]; + switch (funct3) { + case 1: /* amiswap.w */ + break; + case 0: /* amoadd.w */ + val2 = (int32_t)(val + val2); + break; + case 4: /* amoxor.w */ + val2 = (int32_t)(val ^ val2); + break; + case 0xc: /* amoand.w */ + val2 = (int32_t)(val & val2); + break; + case 0x8: /* amoor.w */ + val2 = (int32_t)(val | val2); + break; + case 0x10: /* amomin.w */ + if ((int32_t) val < (int32_t) val2) + val2 = (int32_t) val; + break; + case 0x14: /* amomax.w */ + if ((int32_t) val > (int32_t) val2) + val2 = (int32_t) val; + break; + case 0x18: /* amominu.w */ + if ((uint32_t) val < (uint32_t) val2) + val2 = (int32_t) val; + break; + case 0x1c: /* amomaxu.w */ + if ((uint32_t) val > (uint32_t) val2) + val2 = (int32_t) val; + break; + default: + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + return; + } + if (target_write_u32(addr, val2)) { + raise_exception(pending_exception, pending_tval); + return; + } break; default: raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); return; } - if (target_write_u32(addr, val2)) { - raise_exception(pending_exception, pending_tval); - return; - } - break; + } break; default: raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); return; } - } break; - default: - raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); - return; - } - if (rd != 0) - reg[rd] = val; - break; + if (rd != 0) + reg[rd] = val; + break; #endif #ifdef RV32C - /* Compressed insn */ - case 0: - break; - case 1: - funct3 = (insn >> 13) & 0x7; - midpart = (insn >> 2) & 0x07ff; - switch(funct3){ - case 0: /* C.NOP, C.ADDI */ - if( ((midpart >> 5) & 0x1f) == 0){ /* C.NOP*/ + /* Compressed insn */ + case 0: + break; + case 1: + funct3 = (insn >> 13) & 0x7; + midpart = (insn >> 2) & 0x07ff; + switch (funct3) { + case 0: /* C.NOP, C.ADDI */ + if (((midpart >> 5) & 0x1f) == 0) { /* C.NOP*/ #ifdef DEBUG_EXTRA - dprintf(">>> C.NOP\n"); + dprintf(">>> C.NOP\n"); #endif - return; - } else { - rs1 = rd = ((midpart >> 5) & 0x1f); - imm = (midpart & 0x1f) | ((midpart >> 5) & 0x20); - val = reg[rs1] + imm; + return; + } else { + rs1 = rd = ((midpart >> 5) & 0x1f); + imm = (midpart & 0x1f) | ((midpart >> 5) & 0x20); + val = reg[rs1] + imm; #ifdef DEBUG_EXTRA - dprintf(">>> C.ADDI\n"); - printf("rd: %d, rs1: %d, imm: %d, reg[rd]: %d, val: %d\n", rd, rs1, imm, reg[rd], val); + dprintf(">>> C.ADDI\n"); + printf("rd: %d, rs1: %d, imm: %d, reg[rd]: %d, val: %d\n", + rd, rs1, imm, reg[rd], val); #endif - }break; - case 1: /* C.JAL, C.ADDIW */ + } + break; + case 1: /* C.JAL, C.ADDIW */ #ifdef DEBUG_EXTRA - switch(XLEN){ + switch (XLEN) { case 32: dprintf(">>> C.JAL\n"); break; @@ -1901,657 +1904,660 @@ void execute_instruction() default: dprintf(">>> Unknow XLEN\n"); break; - } -#endif - switch(XLEN) { - case 32: - imm = (midpart & 0x400) | - ((midpart << 3) & 0x200) | - (midpart & 0x170) | - ((midpart << 2) & 0x40) | - (midpart & 0x20) | - ((midpart << 4) & 0x10) | - ((midpart >> 6) & 0x8) | - ((midpart >> 1) & 0x7); - imm = (imm << 1) & 0xfffe; - reg[1] = pc + 2; /* Store the link to x1 register */ - next_pc = (int32_t)(pc + imm); - if(next_pc > pc) forward_counter++; - else backward_counter++; - jump_counter++; - break; - case 64: - case 128: - rs1 = rd = ((midpart >> 5) & 0x1f); - imm = (midpart >> (11 - 5)) | - (midpart & 0x1f); - val = reg[rs1] + imm; - break; - } - break; - case 2: /* C.LI */ -#ifdef DEBUG_EXTRA - dprintf(">>> C.LI\n"); -#endif - rs1 = rd = ((midpart >> 5) & 0x1f); - imm = ((midpart >> 5) & 0x20) | (midpart & 0x1f); - val = imm; - break; - case 3: /* C.ADDI16SP, C.LUI */ -#ifdef DEBUG_EXTRA - switch(rd){ - case 2: - dprintf(">>> C.ADDI16SP\n"); - break; - default: - dprintf(">>> C.LUI\n"); - } -#endif - switch(rd){ /* C.ADDI16SP */ - case 2: - imm = ((midpart >> 4) & 0x1) | - ((midpart << 1) & 0x2) | - ((midpart >> 1) & 0x4) | - ((midpart << 2) & 0x18) | - ((midpart >> 5) & 0x20); - imm = (imm << 4 )<< (31 - 9) >> (31 - 9); - val = reg[rd] + imm; - break; - default: - imm = (midpart & 0x1f) | ((midpart >> 5) & 0x20); - imm = ((imm << 12) & 0xfffff000); - imm = imm << 14 >> 14; - if(rd != 0) - val = reg[rd] | imm; - break; - } - break; - case 4: /* C.SRLI, C.SRLI64, C.SRAI, C.SRAI64, C.ANDI, C.SUB, C.XOR, C.OR, C.AND, C.SUBW, C.ADDW*/ - switch(((midpart >> 8) & 0x3)){ - case 0: /* C.SRLI C.SRLI64 */ -#ifdef DEBUG_EXTRA - switch(XLEN){ - case 32: - case 64: - dprintf(">>> C.SRLI\n"); - break; - case 128: - dprintf(">>> C.SRLI64\n"); - break; } #endif - switch(XLEN){ + switch (XLEN) { case 32: - case 64: - rs1 = rd = ((midpart >> 5) & 0x1f) + 8; - imm = (midpart & 0xf) | (midpart >> 5 & 0x10); - val = reg[rs1]; - break; - case 128: - rs1 = rd = ((midpart >> 5) & 0x1f) + 8; - imm = 64; - val = reg[rs1]; + imm = (midpart & 0x400) | ((midpart << 3) & 0x200) | + (midpart & 0x170) | ((midpart << 2) & 0x40) | + (midpart & 0x20) | ((midpart << 4) & 0x10) | + ((midpart >> 6) & 0x8) | ((midpart >> 1) & 0x7); + imm = (imm << 1) & 0xfffe; + reg[1] = pc + 2; /* Store the link to x1 register */ + next_pc = (int32_t)(pc + imm); + if (next_pc > pc) + forward_counter++; + else + backward_counter++; + jump_counter++; break; - } - val = val >> imm; - break; - case 1: /* C.SRAI C.SRAI64 */ -#ifdef DEBUG_EXTRA - switch(XLEN){ - case 32: case 64: - dprintf(">>> C.SRAI\n"); - case 128: - dprintf(">>> C.SRAI64\n"); - } -#endif - switch(XLEN){ - case 32: case 64: - rs1 = rd = ((midpart >> 5) & 0x1f) + 8; - imm = (midpart & 0xf) | ((midpart >> 5) & 0x10); - val = reg[rs1]; - break; case 128: - rs1 = rd = ((midpart >> 5) & 0x1f) + 8; - imm = 64; - val = reg[rs1]; + rs1 = rd = ((midpart >> 5) & 0x1f); + imm = (midpart >> (11 - 5)) | (midpart & 0x1f); + val = reg[rs1] + imm; break; } - val = val << imm; break; - case 2: /* C.ANDI */ + case 2: /* C.LI */ #ifdef DEBUG_EXTRA - dprintf(">>> C.ANDI\n"); + dprintf(">>> C.LI\n"); #endif - rs1 = rd = ((midpart >> 5) & 0x7) + 8; - imm = (midpart & 0x1f) | ((midpart >> 5) & 0x10); - val = reg[rs1]; - val = val & imm; + rs1 = rd = ((midpart >> 5) & 0x1f); + imm = ((midpart >> 5) & 0x20) | (midpart & 0x1f); + val = imm; break; - case 3: /* C.SUB, C.XOR, C.OR, C.AND, C.SUBW, C.ADDW */ - rs2 = (midpart & 0x7) + 8; - rs1 = rd = ((midpart >> 5) & 0x7) + 8; - switch(((midpart >> 3) & 0x3) | ((midpart >> 8) & 0x4) ){ - case 0: /* C.SUB */ + case 3: /* C.ADDI16SP, C.LUI */ #ifdef DEBUG_EXTRA - dprintf(">>> C.SUB\n"); -#endif - val = reg[rd] - reg[rs2]; + switch (rd) { + case 2: + dprintf(">>> C.ADDI16SP\n"); break; - case 1: /* C.XOR */ -#ifdef DEBUG_EXTRA - dprintf(">>> C.XOR\n"); + default: + dprintf(">>> C.LUI\n"); + } #endif - val = reg[rd] ^ reg[rs2]; + switch (rd) { /* C.ADDI16SP */ + case 2: + imm = ((midpart >> 4) & 0x1) | ((midpart << 1) & 0x2) | + ((midpart >> 1) & 0x4) | ((midpart << 2) & 0x18) | + ((midpart >> 5) & 0x20); + imm = (imm << 4) << (31 - 9) >> (31 - 9); + val = reg[rd] + imm; break; - case 2: /* C.OR */ -#ifdef DEBUG_EXTRA - dprintf(">>> C.OR\n"); -#endif - val = reg[rd] | reg[rs2]; + default: + imm = (midpart & 0x1f) | ((midpart >> 5) & 0x20); + imm = ((imm << 12) & 0xfffff000); + imm = imm << 14 >> 14; + if (rd != 0) + val = reg[rd] | imm; break; - case 3: /* C.AND */ -#ifdef DEBUG_EXTRA - dprintf(">>> C.AND\n"); + } + break; + case 4: /* C.SRLI, C.SRLI64, C.SRAI, C.SRAI64, C.ANDI, C.SUB, C.XOR, + C.OR, C.AND, C.SUBW, C.ADDW*/ + switch (((midpart >> 8) & 0x3)) { + case 0: /* C.SRLI C.SRLI64 */ +#ifdef DEBUG_EXTRA + switch (XLEN) { + case 32: + case 64: + dprintf(">>> C.SRLI\n"); + break; + case 128: + dprintf(">>> C.SRLI64\n"); + break; + } #endif - val = reg[rd] & reg[rs2]; + switch (XLEN) { + case 32: + case 64: + rs1 = rd = ((midpart >> 5) & 0x1f) + 8; + imm = (midpart & 0xf) | (midpart >> 5 & 0x10); + val = reg[rs1]; + break; + case 128: + rs1 = rd = ((midpart >> 5) & 0x1f) + 8; + imm = 64; + val = reg[rs1]; + break; + } + val = val >> imm; break; - case 4: /* C.SUBW */ -#ifdef DEBUG_EXTRA - dprintf(">>> C.SUBW\n"); + case 1: /* C.SRAI C.SRAI64 */ +#ifdef DEBUG_EXTRA + switch (XLEN) { + case 32: + case 64: + dprintf(">>> C.SRAI\n"); + case 128: + dprintf(">>> C.SRAI64\n"); + } #endif - val = reg[rd] - reg[rs2]; - if(XLEN == 128){ - val = (int32_t) (val << 96) >> 96; - }else if(XLEN == 64){ - val = (int32_t) (val << 32) >> 32; - }else{ - raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + switch (XLEN) { + case 32: + case 64: + rs1 = rd = ((midpart >> 5) & 0x1f) + 8; + imm = (midpart & 0xf) | ((midpart >> 5) & 0x10); + val = reg[rs1]; + break; + case 128: + rs1 = rd = ((midpart >> 5) & 0x1f) + 8; + imm = 64; + val = reg[rs1]; + break; } + val = val << imm; break; - case 5: /* C.ADDW */ + case 2: /* C.ANDI */ #ifdef DEBUG_EXTRA - dprintf(">>> C.ADDW\n"); + dprintf(">>> C.ANDI\n"); #endif - val = reg[rd] + reg[rs2]; - if(XLEN == 128){ - val = (int32_t) (val << 96) >> 96; - }else if(XLEN == 64){ - val = (int32_t) (val << 32) >> 32; - }else{ - raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); - } - break; - case 6: - case 7: - /* NOP */ + rs1 = rd = ((midpart >> 5) & 0x7) + 8; + imm = (midpart & 0x1f) | ((midpart >> 5) & 0x10); + val = reg[rs1]; + val = val & imm; break; + case 3: /* C.SUB, C.XOR, C.OR, C.AND, C.SUBW, C.ADDW */ + rs2 = (midpart & 0x7) + 8; + rs1 = rd = ((midpart >> 5) & 0x7) + 8; + switch (((midpart >> 3) & 0x3) | ((midpart >> 8) & 0x4)) { + case 0: /* C.SUB */ +#ifdef DEBUG_EXTRA + dprintf(">>> C.SUB\n"); +#endif + val = reg[rd] - reg[rs2]; + break; + case 1: /* C.XOR */ +#ifdef DEBUG_EXTRA + dprintf(">>> C.XOR\n"); +#endif + val = reg[rd] ^ reg[rs2]; + break; + case 2: /* C.OR */ +#ifdef DEBUG_EXTRA + dprintf(">>> C.OR\n"); +#endif + val = reg[rd] | reg[rs2]; + break; + case 3: /* C.AND */ +#ifdef DEBUG_EXTRA + dprintf(">>> C.AND\n"); +#endif + val = reg[rd] & reg[rs2]; + break; + case 4: /* C.SUBW */ +#ifdef DEBUG_EXTRA + dprintf(">>> C.SUBW\n"); +#endif + val = reg[rd] - reg[rs2]; + if (XLEN == 128) { + val = (int32_t)(val << 96) >> 96; + } else if (XLEN == 64) { + val = (int32_t)(val << 32) >> 32; + } else { + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + } + break; + case 5: /* C.ADDW */ +#ifdef DEBUG_EXTRA + dprintf(">>> C.ADDW\n"); +#endif + val = reg[rd] + reg[rs2]; + if (XLEN == 128) { + val = (int32_t)(val << 96) >> 96; + } else if (XLEN == 64) { + val = (int32_t)(val << 32) >> 32; + } else { + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + } + break; + case 6: + case 7: + /* NOP */ + break; + } } - } - break; - case 5: /* C.J */ -#ifdef DEBUG_EXTRA - dprintf(">>> C.J\n"); -#endif - rd = 0; - imm = ((midpart >> 1) & 0x7) | - ((midpart >> 6) & 0x8) | - ((midpart << 5) & 0x10) | - ((midpart) & 0x20) | - ((midpart << 2) & 0x40) | - ((midpart) & 0x180)| - ((midpart << 3) & 0x200)| - ((midpart) & 0x400); - imm = (imm << 1) << 20 >> 20; - next_pc = (int32_t)(pc + imm); - if(next_pc > pc) forward_counter++; - else backward_counter++; - jump_counter++; - break; - case 6: /* C.BEQZ */ -#ifdef DEBUG_EXTRA - dprintf(">>> C.BEQZ\n"); -#endif - rs1 = ((midpart >> 5) & 0x7) + 8; - rd = 0; - if(reg[rs1] == 0){ - imm = ((midpart >> 1) & 0x3) | - ((midpart >> 3) & 0xc) | - ((midpart << 4) & 0x10) | - ((midpart << 2) & 0x60) | - ((midpart) & 0x80); - imm = (imm << 1) << 23 >> 23; + break; + case 5: /* C.J */ +#ifdef DEBUG_EXTRA + dprintf(">>> C.J\n"); +#endif + rd = 0; + imm = ((midpart >> 1) & 0x7) | ((midpart >> 6) & 0x8) | + ((midpart << 5) & 0x10) | ((midpart) &0x20) | + ((midpart << 2) & 0x40) | ((midpart) &0x180) | + ((midpart << 3) & 0x200) | ((midpart) &0x400); + imm = (imm << 1) << 20 >> 20; next_pc = (int32_t)(pc + imm); - if(next_pc > pc) forward_counter++; - else backward_counter++; + if (next_pc > pc) + forward_counter++; + else + backward_counter++; jump_counter++; + break; + case 6: /* C.BEQZ */ +#ifdef DEBUG_EXTRA + dprintf(">>> C.BEQZ\n"); +#endif + rs1 = ((midpart >> 5) & 0x7) + 8; + rd = 0; + if (reg[rs1] == 0) { + imm = ((midpart >> 1) & 0x3) | ((midpart >> 3) & 0xc) | + ((midpart << 4) & 0x10) | ((midpart << 2) & 0x60) | + ((midpart) &0x80); + imm = (imm << 1) << 23 >> 23; + next_pc = (int32_t)(pc + imm); + if (next_pc > pc) + forward_counter++; + else + backward_counter++; + jump_counter++; + } + break; + case 7: /* C.BNEZ */ +#ifdef DEBUG_EXTRA + dprintf(">>> C.BNEZ\n"); +#endif + rs1 = ((midpart >> 5) & 0x7) + 8; + rd = 0; + imm = 0; + if (reg[rs1] != 0) { + imm = ((midpart >> 1) & 0x3) | ((midpart >> 6) & 0xc) | + ((midpart << 4) & 0x10) | ((midpart << 2) & 0x60) | + ((midpart) &0x80); + imm = (imm << 1) << 23 >> 23; + next_pc = (int32_t)(pc + imm); + if (next_pc > pc) + forward_counter++; + else + backward_counter++; + jump_counter++; + } +#ifdef DEBUG_EXTRA + printf( + "rd : %d, rs1: %d, imm: %d, reg[rs1] : %d, pc: %08x, " + "next_pc: %08x\n", + rd, rs1, imm, reg[rs1]); +#endif + break; + default: + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + return; } - break; - case 7: /* C.BNEZ */ -#ifdef DEBUG_EXTRA - dprintf(">>> C.BNEZ\n"); -#endif - rs1 = ((midpart >> 5) & 0x7) + 8; - rd = 0; - imm = 0; - if(reg[rs1] != 0){ - imm = ((midpart >> 1) & 0x3) | - ((midpart >> 6) & 0xc) | - ((midpart << 4) & 0x10) | - ((midpart << 2) & 0x60) | - ((midpart) & 0x80); - imm = (imm << 1) << 23 >> 23; - next_pc = (int32_t)(pc + imm); - if(next_pc > pc) forward_counter++; - else backward_counter++; - jump_counter++; + if (rd != 0) { + reg[rd] = val; } + break; + case 2: + funct3 = (insn >> 13) & 0x7; + midpart = (insn >> 2) & 0x07ff; + switch (funct3) { + case 6: #ifdef DEBUG_EXTRA - printf("rd : %d, rs1: %d, imm: %d, reg[rs1] : %d, pc: %08x, next_pc: %08x\n", rd, rs1, imm, reg[rs1]); + dprintf(">>> C.SWSP\n"); #endif + rs2 = midpart & 0x1f; + imm = ((midpart >> 2) & 0x1e0) | ((midpart << 4) & 0x600); + imm = (imm >> 3) & 0xff; + addr = reg[2] + imm; + val = reg[rs2]; + if (target_write_u32(addr, val)) { + raise_exception(pending_exception, pending_tval); + return; + } + break; + } break; + default: raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); return; } - if(rd != 0){ - reg[rd] = val; - } - break; - case 2: - funct3 = (insn >> 13) & 0x7; - midpart = (insn >> 2) & 0x07ff; - switch(funct3){ - case 6: -#ifdef DEBUG_EXTRA - dprintf(">>> C.SWSP\n"); -#endif - rs2 = midpart & 0x1f; - imm = ((midpart >> 2) & 0x1e0) | - ((midpart << 4) & 0x600); - imm = (imm >> 3) & 0xff; - addr = reg[2] + imm; - val = reg[rs2]; - if (target_write_u32(addr, val)) { - raise_exception(pending_exception, pending_tval); - return; - } - break; - } - break; - - default: - raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); - return; } -} -/* returns realtime in nanoseconds */ -int64_t get_clock() -{ - struct timespec ts; - clock_gettime(CLOCK_MONOTONIC, &ts); - return ts.tv_sec * 1000000000LL + ts.tv_nsec; -} + /* returns realtime in nanoseconds */ + int64_t get_clock() + { + struct timespec ts; + clock_gettime(CLOCK_MONOTONIC, &ts); + return ts.tv_sec * 1000000000LL + ts.tv_nsec; + } -void riscv_cpu_interp_x32() -{ - /* we use a single execution loop to keep a simple control flow for - * emscripten */ - while (machine_running) { + void riscv_cpu_interp_x32() + { + /* we use a single execution loop to keep a simple control flow for + * emscripten */ + while (machine_running) { #if 1 - /* update timer, assuming 10 MHz clock (100 ns period) for the mtime - * counter */ - mtime = get_clock() / 100ll; + /* update timer, assuming 10 MHz clock (100 ns period) for the mtime + * counter */ + mtime = get_clock() / 100ll; - /* for reproducible debug runs, you can use a fixed fixed increment per - * instruction */ + /* for reproducible debug runs, you can use a fixed fixed increment + * per instruction */ #else - mtime += 10; + mtime += 10; #endif - /* default value for next PC is next instruction, can be changed by - * branches or exceptions */ - next_pc = pc + 4; + /* default value for next PC is next instruction, can be changed by + * branches or exceptions */ + next_pc = pc + 4; - /* test for timer interrupt */ - if (mtimecmp <= mtime) { - mip |= MIP_MTIP; - } - if ((mip & mie) != 0 && (mstatus & MSTATUS_MIE)) { - raise_interrupt(); - } else { - /* Compressed or normal */ - insn_type = get_insn32(pc, &insn); + /* test for timer interrupt */ + if (mtimecmp <= mtime) { + mip |= MIP_MTIP; + } + if ((mip & mie) != 0 && (mstatus & MSTATUS_MIE)) { + raise_interrupt(); + } else { + /* Compressed or normal */ + insn_type = get_insn32(pc, &insn); #ifdef RV32C - if(insn_type == CINSN) - next_pc = pc + 2; + if (insn_type == CINSN) + next_pc = pc + 2; #endif #ifdef DEBUG_EXTRA - printf("insn_type : %s\n", insn_type == CINSN ? "CINSN" : "INSN"); + printf("insn_type : %s\n", + insn_type == CINSN ? "CINSN" : "INSN"); #endif - insn_counter++; + insn_counter++; - debug_out("[%08x]=%08x, mtime: %lx, mtimecmp: %lx\n", pc, insn, - mtime, mtimecmp); - execute_instruction(); - } + debug_out("[%08x]=%08x, mtime: %lx, mtimecmp: %lx\n", pc, insn, + mtime, mtimecmp); + execute_instruction(); + } - /* test for misaligned fetches , in order to match the compressed - * instruction. */ + /* test for misaligned fetches , in order to match the compressed + * instruction. */ #ifdef RV32C - if (next_pc & 0x1) { - raise_exception(CAUSE_MISALIGNED_FETCH, next_pc); - } + if (next_pc & 0x1) { + raise_exception(CAUSE_MISALIGNED_FETCH, next_pc); + } #else - if (next_pc & 0x3) { - raise_exception(CAUSE_MISALIGNED_FETCH, next_pc); - } + if (next_pc & 0x3) { + raise_exception(CAUSE_MISALIGNED_FETCH, next_pc); + } #endif - /* update current PC */ - pc = next_pc; - } + /* update current PC */ + pc = next_pc; + } - debug_out("done interp %lx int=%x mstatus=%lx prv=%d\n", - (uint64_t) insn_counter, mip & mie, (uint64_t) mstatus, priv); -} + debug_out("done interp %lx int=%x mstatus=%lx prv=%d\n", + (uint64_t) insn_counter, mip & mie, (uint64_t) mstatus, priv); + } -int main(int argc, char **argv) -{ + int main(int argc, char **argv) + { #ifdef DEBUG_OUTPUT - FILE *fo; - char *po, hex_file[100]; -#endif - - /* automatic STDOUT flushing, no fflush needed */ - setvbuf(stdout, NULL, _IONBF, 0); - /* parse command line */ - const char *elf_file = NULL; - int output_flag = 0; - const char *output_file = NULL; - const char *elf_name = NULL; - const char* signature_file = NULL; - int cmd_opt = 0; - struct option opts[] = {{"elf", 1, NULL, 'e'}, - {"verify", 1, NULL, 'v'}, - {"signaturedump", 0, NULL, 's'}}; - const char *optstring = "e:s:o:"; - while ((cmd_opt = getopt_long(argc, argv, optstring, opts, NULL)) != -1) { - switch (cmd_opt) { - case 'e': - elf_file = optarg; - elf_name = strtok(strdup(elf_file), "."); - printf("%s\n", elf_name); - output_file = malloc(strlen(elf_name) + 30); - memset(output_file, '\0', strlen(elf_name) + 30); - strcat(output_file, elf_name); - strcat(output_file, ".signature.output"); - printf("signature.output : %s\n", output_file); - break; - case 'v': - //signature_file = optarg; - break; - case 's': - //output_file = optarg; - output_flag = 1; - break; - default: - printf("Unknow argument: %s\n", optarg); - break; + FILE *fo; + char *po, hex_file[100]; +#endif + + /* automatic STDOUT flushing, no fflush needed */ + setvbuf(stdout, NULL, _IONBF, 0); + /* parse command line */ + const char *elf_file = NULL; + int output_flag = 0; + const char *output_file = NULL; + const char *elf_name = NULL; + const char *signature_file = NULL; + int cmd_opt = 0; + struct option opts[] = {{"elf", 1, NULL, 'e'}, + {"verify", 1, NULL, 'v'}, + {"signaturedump", 0, NULL, 's'}}; + const char *optstring = "e:s:o:"; + while ((cmd_opt = getopt_long(argc, argv, optstring, opts, NULL)) != + -1) { + switch (cmd_opt) { + case 'e': + elf_file = optarg; + elf_name = strtok(strdup(elf_file), "."); + printf("%s\n", elf_name); + output_file = malloc(strlen(elf_name) + 30); + memset(output_file, '\0', strlen(elf_name) + 30); + strcat(output_file, elf_name); + strcat(output_file, ".signature.output"); + printf("signature.output : %s\n", output_file); + break; + case 'v': + // signature_file = optarg; + break; + case 's': + // output_file = optarg; + output_flag = 1; + break; + default: + printf("Unknow argument: %s\n", optarg); + break; + } + } + if (elf_file == NULL) { + printf("missing ELF file\n"); + return 1; } - } - if (elf_file == NULL) { - printf("missing ELF file\n"); - return 1; - } - for (uint32_t u = 0; u < RAM_SIZE; u++) - ram[u] = 0; + for (uint32_t u = 0; u < RAM_SIZE; u++) + ram[u] = 0; #ifdef DEBUG_EXTRA - init_stats(); + init_stats(); #endif - /* open ELF file */ - elf_version(EV_CURRENT); - int fd = open(elf_file, O_RDONLY); - if (fd == -1) { - printf("can't open file %s\n", elf_file); - return 1; - } - Elf *elf = elf_begin(fd, ELF_C_READ, NULL); - - /* scan for symbol table */ - Elf_Scn *scn = NULL; - GElf_Shdr shdr; - while ((scn = elf_nextscn(elf, scn)) != NULL) { - gelf_getshdr(scn, &shdr); - if (shdr.sh_type == SHT_SYMTAB) { - Elf_Data *data = elf_getdata(scn, NULL); - int count = shdr.sh_size / shdr.sh_entsize; - for (int i = 0; i < count; i++) { - GElf_Sym sym; - gelf_getsym(data, i, &sym); - char *name = elf_strptr(elf, shdr.sh_link, sym.st_name); - if (strcmp(name, "begin_signature") == 0) { - begin_signature = sym.st_value; - } - if (strcmp(name, "end_signature") == 0) { - end_signature = sym.st_value; - } + /* open ELF file */ + elf_version(EV_CURRENT); + int fd = open(elf_file, O_RDONLY); + if (fd == -1) { + printf("can't open file %s\n", elf_file); + return 1; + } + Elf *elf = elf_begin(fd, ELF_C_READ, NULL); + + /* scan for symbol table */ + Elf_Scn *scn = NULL; + GElf_Shdr shdr; + while ((scn = elf_nextscn(elf, scn)) != NULL) { + gelf_getshdr(scn, &shdr); + if (shdr.sh_type == SHT_SYMTAB) { + Elf_Data *data = elf_getdata(scn, NULL); + int count = shdr.sh_size / shdr.sh_entsize; + for (int i = 0; i < count; i++) { + GElf_Sym sym; + gelf_getsym(data, i, &sym); + char *name = elf_strptr(elf, shdr.sh_link, sym.st_name); + if (strcmp(name, "begin_signature") == 0) { + begin_signature = sym.st_value; + } + if (strcmp(name, "end_signature") == 0) { + end_signature = sym.st_value; + } - /* for compliance test */ - if (strcmp(name, "_start") == 0) { - start = sym.st_value; - } + /* for compliance test */ + if (strcmp(name, "_start") == 0) { + start = sym.st_value; + } - /* for zephyr */ - if (strcmp(name, "__reset") == 0) { - start = sym.st_value; - } - if (strcmp(name, "__irq_wrapper") == 0) { - mtvec = sym.st_value; + /* for zephyr */ + if (strcmp(name, "__reset") == 0) { + start = sym.st_value; + } + if (strcmp(name, "__irq_wrapper") == 0) { + mtvec = sym.st_value; + } } } } - } - /* set .text section as the base address */ - scn = NULL; - size_t shstrndx; - elf_getshdrstrndx(elf, &shstrndx); - while ((scn = elf_nextscn(elf, scn)) != NULL) { - gelf_getshdr(scn, &shdr); - const char *name = elf_strptr(elf, shstrndx, shdr.sh_name); - printf("section name: %s\n", name); - printf("Type: %d\n", shdr.sh_type); - if (shdr.sh_type == SHT_PROGBITS) { - if (strcmp(name, ".text") == 0) { - ram_start = shdr.sh_addr; - break; - }else if(strcmp(name, ".text.init") == 0){ - ram_start = shdr.sh_addr; - break; + /* set .text section as the base address */ + scn = NULL; + size_t shstrndx; + elf_getshdrstrndx(elf, &shstrndx); + while ((scn = elf_nextscn(elf, scn)) != NULL) { + gelf_getshdr(scn, &shdr); + const char *name = elf_strptr(elf, shstrndx, shdr.sh_name); + printf("section name: %s\n", name); + printf("Type: %d\n", shdr.sh_type); + if (shdr.sh_type == SHT_PROGBITS) { + if (strcmp(name, ".text") == 0) { + ram_start = shdr.sh_addr; + break; + } else if (strcmp(name, ".text.init") == 0) { + ram_start = shdr.sh_addr; + break; + } } } - } - debug_out("begin_signature: 0x%08x\n", begin_signature); - debug_out("end_signature: 0x%08x\n", end_signature); - debug_out("ram_start: 0x%08x\n", ram_start); - debug_out("entry point: 0x%08x\n", start); - - /* scan for program */ - scn = NULL; - while ((scn = elf_nextscn(elf, scn)) != NULL) { - gelf_getshdr(scn, &shdr); - - /* filter NULL address sections and .bss */ - if (shdr.sh_addr && shdr.sh_type != SHT_NOBITS) { - Elf_Data *data = elf_getdata(scn, NULL); - if (shdr.sh_addr >= ram_start) { - for (size_t i = 0; i < shdr.sh_size; i++) { - ram_curr = shdr.sh_addr + i - ram_start; - if (ram_curr >= RAM_SIZE) { - debug_out( - "memory pointer outside of range 0x%08x (section " - "at address 0x%08x)\n", - ram_curr, (uint32_t) shdr.sh_addr); - /* break; */ - } else { - ram[ram_curr] = ((uint8_t *) data->d_buf)[i]; - if (ram_curr > ram_last) - ram_last = ram_curr; + debug_out("begin_signature: 0x%08x\n", begin_signature); + debug_out("end_signature: 0x%08x\n", end_signature); + debug_out("ram_start: 0x%08x\n", ram_start); + debug_out("entry point: 0x%08x\n", start); + + /* scan for program */ + scn = NULL; + while ((scn = elf_nextscn(elf, scn)) != NULL) { + gelf_getshdr(scn, &shdr); + + /* filter NULL address sections and .bss */ + if (shdr.sh_addr && shdr.sh_type != SHT_NOBITS) { + Elf_Data *data = elf_getdata(scn, NULL); + if (shdr.sh_addr >= ram_start) { + for (size_t i = 0; i < shdr.sh_size; i++) { + ram_curr = shdr.sh_addr + i - ram_start; + if (ram_curr >= RAM_SIZE) { + debug_out( + "memory pointer outside of range 0x%08x " + "(section " + "at address 0x%08x)\n", + ram_curr, (uint32_t) shdr.sh_addr); + /* break; */ + } else { + ram[ram_curr] = ((uint8_t *) data->d_buf)[i]; + if (ram_curr > ram_last) + ram_last = ram_curr; + } } + } else { + debug_out("ignoring section at address 0x%08x\n", + (uint32_t) shdr.sh_addr); } - } else { - debug_out("ignoring section at address 0x%08x\n", - (uint32_t) shdr.sh_addr); } } - } - /* close ELF file */ - elf_end(elf); - close(fd); + /* close ELF file */ + elf_end(elf); + close(fd); #ifdef DEBUG_OUTPUT - printf("codesize: 0x%08x (%i)\n", ram_last + 1, ram_last + 1); - strcpy(hex_file, elf_file); - po = strrchr(hex_file, '.'); - if (po != NULL) - *po = 0; - strcat(hex_file, ".mem"); - fo = fopen(hex_file, "wt"); - if (fo != NULL) { - for (uint32_t u = 0; u <= ram_last; u++) { - fprintf(fo, "%02X ", ram[u]); - if ((u & 15) == 15) - fprintf(fo, "\n"); + printf("codesize: 0x%08x (%i)\n", ram_last + 1, ram_last + 1); + strcpy(hex_file, elf_file); + po = strrchr(hex_file, '.'); + if (po != NULL) + *po = 0; + strcat(hex_file, ".mem"); + fo = fopen(hex_file, "wt"); + if (fo != NULL) { + for (uint32_t u = 0; u <= ram_last; u++) { + fprintf(fo, "%02X ", ram[u]); + if ((u & 15) == 15) + fprintf(fo, "\n"); + } + fprintf(fo, "\n"); + fclose(fo); } - fprintf(fo, "\n"); - fclose(fo); - } #if 1 - fo = fopen("rom.v", "wt"); - if (fo != NULL) { - fprintf(fo, "module rom(addr,data);\n"); - uint32_t romsz = (ram_start & 0xFFFF) + ram_last + 1; - printf("codesize with offset: %i\n", romsz); - if (romsz >= 32768) - fprintf(fo, "input [15:0] addr;\n"); - else if (romsz >= 16384) - fprintf(fo, "input [14:0] addr;\n"); - else if (romsz >= 8192) - fprintf(fo, "input [13:0] addr;\n"); - else if (romsz >= 4096) - fprintf(fo, "input [12:0] addr;\n"); - else if (romsz >= 2048) - fprintf(fo, "input [11:0] addr;\n"); - else if (romsz >= 1024) - fprintf(fo, "input [10:0] addr;\n"); - else if (romsz >= 512) - fprintf(fo, "input [9:0] addr;\n"); - else if (romsz >= 256) - fprintf(fo, "input [8:0] addr;\n"); - else - fprintf(fo, "input [7:0] addr;\n"); - fprintf(fo, + fo = fopen("rom.v", "wt"); + if (fo != NULL) { + fprintf(fo, "module rom(addr,data);\n"); + uint32_t romsz = (ram_start & 0xFFFF) + ram_last + 1; + printf("codesize with offset: %i\n", romsz); + if (romsz >= 32768) + fprintf(fo, "input [15:0] addr;\n"); + else if (romsz >= 16384) + fprintf(fo, "input [14:0] addr;\n"); + else if (romsz >= 8192) + fprintf(fo, "input [13:0] addr;\n"); + else if (romsz >= 4096) + fprintf(fo, "input [12:0] addr;\n"); + else if (romsz >= 2048) + fprintf(fo, "input [11:0] addr;\n"); + else if (romsz >= 1024) + fprintf(fo, "input [10:0] addr;\n"); + else if (romsz >= 512) + fprintf(fo, "input [9:0] addr;\n"); + else if (romsz >= 256) + fprintf(fo, "input [8:0] addr;\n"); + else + fprintf(fo, "input [7:0] addr;\n"); + fprintf( + fo, "output reg [7:0] data;\nalways @(addr) begin\n case(addr)\n"); - for (uint32_t u = 0; u <= ram_last; u++) { - fprintf(fo, " %i : data = 8'h%02X;\n", (ram_start & 0xFFFF) + u, - ram[u]); + for (uint32_t u = 0; u <= ram_last; u++) { + fprintf(fo, " %i : data = 8'h%02X;\n", (ram_start & 0xFFFF) + u, + ram[u]); + } + fprintf(fo, + " default: data = 8'h01; // invalid instruction\n " + "endcase\nend\nendmodule\n"); + fclose(fo); } - fprintf(fo, - " default: data = 8'h01; // invalid instruction\n " - "endcase\nend\nendmodule\n"); - fclose(fo); - } #endif #endif - uint64_t ns1 = get_clock(); + uint64_t ns1 = get_clock(); - /* run program in emulator */ - pc = start; - reg[2] = ram_start + RAM_SIZE; - riscv_cpu_interp_x32(); + /* run program in emulator */ + pc = start; + reg[2] = ram_start + RAM_SIZE; + riscv_cpu_interp_x32(); - uint64_t ns2 = get_clock(); + uint64_t ns2 = get_clock(); - /* write signature */ - /* Check signature */ - if (signature_file) { - FILE* sf = fopen(signature_file, "r"); - if(sf == NULL){ - printf("Error opening file\n"); - return -1; - } - int size = end_signature - begin_signature; - char temp[50], ans[50]; - uint32_t tb = begin_signature; - int err = 0; - for(int i=0;i %s\n", temp, ans); + err++; + } else { + printf("%s\n", temp); + } + memset(temp, '\0', 50); } - tb += 4; - if(strncmp(temp, ans, 8) != 0){ - printf("%s -----> %s\n", temp, ans); - err++; - }else{ - printf("%s\n", temp); + if (err == 0) { + printf("%s TEST PASSED\n", elf_file); + } else { + printf("%s TEST FAILED\n", elf_file); + printf("Number of failed signature : %d\n", err); } - memset(temp, '\0', 50); + fclose(sf); } - if(err == 0){ - printf("%s TEST PASSED\n", elf_file); - }else{ - printf("%s TEST FAILED\n", elf_file); - printf("Number of failed signature : %d\n", err); - } - fclose(sf); - } - if (output_file) { - FILE* of = fopen(output_file, "w"); - int size = end_signature - begin_signature; - for (int i = 0; i < size / 4; i++) { - for (int j = 0; j < 4; j++) { - fprintf(of, "%02x", ram[begin_signature + 3 - j - ram_start]); + if (output_file) { + FILE *of = fopen(output_file, "w"); + int size = end_signature - begin_signature; + for (int i = 0; i < size / 4; i++) { + for (int j = 0; j < 4; j++) { + fprintf(of, "%02x", + ram[begin_signature + 3 - j - ram_start]); + } + begin_signature += 4; + fprintf(of, "\n"); } - begin_signature += 4; - fprintf(of, "\n"); + fclose(of); } - fclose(of); - } #ifdef DEBUG_EXTRA - dump_regs(); - print_stats(insn_counter); + dump_regs(); + print_stats(insn_counter); #endif #if 1 - printf("\n"); - printf(">>> Execution time: %llu ns\n", (long long unsigned) ns2 - ns1); - printf(">>> Instruction count: %llu (IPS=%llu)\n", - (long long unsigned) insn_counter, - (long long) insn_counter * 1000000000LL / (ns2 - ns1)); - printf(">>> Jumps: %llu (%2.2lf%%) - %llu forwards, %llu backwards\n", - (long long unsigned) jump_counter, - jump_counter * 100.0 / insn_counter, - (long long unsigned) forward_counter, - (long long unsigned) backward_counter); - printf(">>> Branching T=%llu (%2.2lf%%) F=%llu (%2.2lf%%)\n", - (long long unsigned) true_counter, - true_counter * 100.0 / (true_counter + false_counter), - (long long unsigned) false_counter, - false_counter * 100.0 / (true_counter + false_counter)); - printf("\n"); + printf("\n"); + printf(">>> Execution time: %llu ns\n", (long long unsigned) ns2 - ns1); + printf(">>> Instruction count: %llu (IPS=%llu)\n", + (long long unsigned) insn_counter, + (long long) insn_counter * 1000000000LL / (ns2 - ns1)); + printf(">>> Jumps: %llu (%2.2lf%%) - %llu forwards, %llu backwards\n", + (long long unsigned) jump_counter, + jump_counter * 100.0 / insn_counter, + (long long unsigned) forward_counter, + (long long unsigned) backward_counter); + printf(">>> Branching T=%llu (%2.2lf%%) F=%llu (%2.2lf%%)\n", + (long long unsigned) true_counter, + true_counter * 100.0 / (true_counter + false_counter), + (long long unsigned) false_counter, + false_counter * 100.0 / (true_counter + false_counter)); + printf("\n"); #endif - return 0; -} + return 0; + } diff --git a/test1.c b/test1.c index 99ed3ea..7df402e 100644 --- a/test1.c +++ b/test1.c @@ -3,8 +3,8 @@ */ void _start() { - volatile char* tx = (volatile char*) 0x40002000; - const char* hello = "Hello RISC-V!\n"; + volatile char *tx = (volatile char *) 0x40002000; + const char *hello = "Hello RISC-V!\n"; while (*hello) { *tx = *hello; hello++; From fd0dbd98fcaeee05c91ebfb6c692e3a46b988e7e Mon Sep 17 00:00:00 2001 From: "f74064054@mail.ncku.edu.tw" Date: Sun, 16 Feb 2020 15:31:49 +0800 Subject: [PATCH 14/19] Remove RV32C specific codes --- emu-rv32i.c | 2110 ++++++++++++++++++++++----------------------------- 1 file changed, 891 insertions(+), 1219 deletions(-) diff --git a/emu-rv32i.c b/emu-rv32i.c index 8d2fc26..08ef120 100644 --- a/emu-rv32i.c +++ b/emu-rv32i.c @@ -20,8 +20,8 @@ #include #include /* uncomment this for an instruction trace and other debug outputs */ -#define DEBUG_OUTPUT -#define DEBUG_EXTRA +// #define DEBUG_OUTPUT +// #define DEBUG_EXTRA #define STRICT_RV32I #define FALSE (0) @@ -709,7 +709,7 @@ int raise_interrupt() /* read 32-bit instruction from memory by PC */ -unsigned char get_insn32(uint32_t pc, uint32_t *insn) +uint32_t get_insn32(uint32_t pc) { #ifdef DEBUG_EXTRA if (pc && pc < minmemr) @@ -721,17 +721,7 @@ unsigned char get_insn32(uint32_t pc, uint32_t *insn) if (ptr > RAM_SIZE) return 1; uint8_t *p = ram + ptr; -#ifdef DEBUG_OUTPUT - printf("address %08x\n", p[0] | (p[1] << 8) | (p[2] << 16) | (p[3] << 24)); -#endif -#ifdef RV32C - if ((p[0] & 0x03) < 3) { - *insn = (p[0] | ((p[1] << 8) & 0x0000ffff)); - return CINSN; - } -#endif - *insn = p[0] | (p[1] << 8) | (p[2] << 16) | (p[3] << 24); - return INSN; + return p[0] | (p[1] << 8) | (p[2] << 16) | (p[3] << 24); } /* read 8-bit data from memory */ @@ -1021,22 +1011,10 @@ void execute_instruction() int32_t imm, cond, err; uint32_t addr, val = 0, val2; - uint16_t midpart; - - if (insn_type == INSN) { - opcode = insn & 0x7f; - rd = (insn >> 7) & 0x1f; - rs1 = (insn >> 15) & 0x1f; - rs2 = (insn >> 20) & 0x1f; - } - -#ifdef RV32C - if (insn_type == CINSN) { - opcode = insn & 0x3; - } -#endif - - + opcode = insn & 0x7f; + rd = (insn >> 7) & 0x1f; + rs1 = (insn >> 15) & 0x1f; + rs2 = (insn >> 20) & 0x1f; switch (opcode) { case 0x37: /* lui */ @@ -1120,1444 +1098,1138 @@ void execute_instruction() } else { debug_out(">>> BGE\n"); stats[7]++; - if (!(funct3 & 1)) { - debug_out(">>> BLTU\n"); - stats[8]++; - } else { - debug_out(">>> BGEU\n"); - stats[9]++; - } + } #endif - cond = (reg[rs1] < reg[rs2]); - break; - default: - raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); - return; + cond = ((int32_t) reg[rs1] < (int32_t) reg[rs2]); + break; + case 3: /* bltu/bgeu */ +#ifdef DEBUG_EXTRA + if (!(funct3 & 1)) { + debug_out(">>> BLTU\n"); + stats[8]++; + } else { + debug_out(">>> BGEU\n"); + stats[9]++; } - cond ^= (funct3 & 1); - if (cond) { - imm = ((insn >> (31 - 12)) & (1 << 12)) | - ((insn >> (25 - 5)) & 0x7e0) | - ((insn >> (8 - 1)) & 0x1e) | - ((insn << (11 - 7)) & (1 << 11)); - imm = (imm << 19) >> 19; - next_pc = (int32_t)(pc + imm); - if (next_pc > pc) - forward_counter++; - else - backward_counter++; - jump_counter++; - true_counter++; - break; - } else - false_counter++; +#endif + cond = (reg[rs1] < reg[rs2]); break; + default: + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + return; + } + cond ^= (funct3 & 1); + if (cond) { + imm = ((insn >> (31 - 12)) & (1 << 12)) | + ((insn >> (25 - 5)) & 0x7e0) | ((insn >> (8 - 1)) & 0x1e) | + ((insn << (11 - 7)) & (1 << 11)); + imm = (imm << 19) >> 19; + next_pc = (int32_t)(pc + imm); + if (next_pc > pc) + forward_counter++; + else + backward_counter++; + jump_counter++; + true_counter++; + break; + } else + false_counter++; + break; - case 0x03: /* LOAD */ + case 0x03: /* LOAD */ - funct3 = (insn >> 12) & 7; - imm = (int32_t) insn >> 20; - addr = reg[rs1] + imm; - switch (funct3) { - case 0: /* lb */ - { + funct3 = (insn >> 12) & 7; + imm = (int32_t) insn >> 20; + addr = reg[rs1] + imm; + switch (funct3) { + case 0: /* lb */ + { #ifdef DEBUG_EXTRA - debug_out(">>> LB\n"); - stats[10]++; + debug_out(">>> LB\n"); + stats[10]++; #endif - uint8_t rval; - if (target_read_u8(&rval, addr)) { - raise_exception(pending_exception, pending_tval); - return; - } - val = (int8_t) rval; - } break; + uint8_t rval; + if (target_read_u8(&rval, addr)) { + raise_exception(pending_exception, pending_tval); + return; + } + val = (int8_t) rval; + } break; - case 1: /* lh */ - { + case 1: /* lh */ + { #ifdef DEBUG_EXTRA - debug_out(">>> LH\n"); - stats[11]++; + debug_out(">>> LH\n"); + stats[11]++; #endif - uint16_t rval; - if (target_read_u16(&rval, addr)) { - raise_exception(pending_exception, pending_tval); - return; - } - val = (int16_t) rval; - } break; + uint16_t rval; + if (target_read_u16(&rval, addr)) { + raise_exception(pending_exception, pending_tval); + return; + } + val = (int16_t) rval; + } break; - case 2: /* lw */ - { + case 2: /* lw */ + { #ifdef DEBUG_EXTRA - debug_out(">>> LW\n"); - stats[12]++; + debug_out(">>> LW\n"); + stats[12]++; #endif - uint32_t rval; - if (target_read_u32(&rval, addr)) { - raise_exception(pending_exception, pending_tval); - return; - } - val = (int32_t) rval; - } break; + uint32_t rval; + if (target_read_u32(&rval, addr)) { + raise_exception(pending_exception, pending_tval); + return; + } + val = (int32_t) rval; + } break; - case 4: /* lbu */ - { + case 4: /* lbu */ + { #ifdef DEBUG_EXTRA - debug_out(">>> LBU\n"); - stats[13]++; + debug_out(">>> LBU\n"); + stats[13]++; #endif - uint8_t rval; - if (target_read_u8(&rval, addr)) { - raise_exception(pending_exception, pending_tval); - return; - } - val = rval; - } break; + uint8_t rval; + if (target_read_u8(&rval, addr)) { + raise_exception(pending_exception, pending_tval); + return; + } + val = rval; + } break; - case 5: /* lhu */ - { + case 5: /* lhu */ + { #ifdef DEBUG_EXTRA - debug_out(">>> LHU\n"); - stats[14]++; + debug_out(">>> LHU\n"); + stats[14]++; #endif - uint16_t rval; - if (target_read_u16(&rval, addr)) { - raise_exception(pending_exception, pending_tval); - return; - } - val = rval; - } break; - - default: - raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + uint16_t rval; + if (target_read_u16(&rval, addr)) { + raise_exception(pending_exception, pending_tval); return; } - if (rd != 0) - reg[rd] = val; - break; + val = rval; + } break; + + default: + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + return; + } + if (rd != 0) + reg[rd] = val; + break; - case 0x23: /* STORE */ + case 0x23: /* STORE */ - funct3 = (insn >> 12) & 7; - imm = rd | ((insn >> (25 - 5)) & 0xfe0); - imm = (imm << 20) >> 20; - addr = reg[rs1] + imm; - val = reg[rs2]; - switch (funct3) { - case 0: /* sb */ -#ifdef DEBUG_EXTRA - debug_out(">>> SB\n"); - stats[15]++; -#endif - if (target_write_u8(addr, val)) { - raise_exception(pending_exception, pending_tval); - return; - } - break; + funct3 = (insn >> 12) & 7; + imm = rd | ((insn >> (25 - 5)) & 0xfe0); + imm = (imm << 20) >> 20; + addr = reg[rs1] + imm; + val = reg[rs2]; + switch (funct3) { + case 0: /* sb */ +#ifdef DEBUG_EXTRA + debug_out(">>> SB\n"); + stats[15]++; +#endif + if (target_write_u8(addr, val)) { + raise_exception(pending_exception, pending_tval); + return; + } + break; - case 1: /* sh */ + case 1: /* sh */ #ifdef DEBUG_EXTRA - debug_out(">>> SH\n"); - stats[16]++; + debug_out(">>> SH\n"); + stats[16]++; #endif - if (target_write_u16(addr, val)) { - raise_exception(pending_exception, pending_tval); - return; - } - break; + if (target_write_u16(addr, val)) { + raise_exception(pending_exception, pending_tval); + return; + } + break; - case 2: /* sw */ + case 2: /* sw */ #ifdef DEBUG_EXTRA - debug_out(">>> SW\n"); - stats[17]++; + debug_out(">>> SW\n"); + stats[17]++; #endif - if (target_write_u32(addr, val)) { - raise_exception(pending_exception, pending_tval); - return; - } - break; - - default: - raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + if (target_write_u32(addr, val)) { + raise_exception(pending_exception, pending_tval); return; } break; - case 0x13: /* OP-IMM */ + default: + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + return; + } + break; + + case 0x13: /* OP-IMM */ - funct3 = (insn >> 12) & 7; - imm = (int32_t) insn >> 20; - switch (funct3) { - case 0: /* addi */ + funct3 = (insn >> 12) & 7; + imm = (int32_t) insn >> 20; + switch (funct3) { + case 0: /* addi */ #ifdef DEBUG_EXTRA - debug_out(">>> ADDI\n"); - stats[18]++; - if (rs1 == 0) - stats[47]++; /* li */ + debug_out(">>> ADDI\n"); + stats[18]++; + if (rs1 == 0) + stats[47]++; /* li */ #endif - val = (int32_t)(reg[rs1] + imm); - break; - case 1: /* slli */ + val = (int32_t)(reg[rs1] + imm); + break; + case 1: /* slli */ #ifdef DEBUG_EXTRA - debug_out(">>> SLLI\n"); - stats[24]++; + debug_out(">>> SLLI\n"); + stats[24]++; #endif - if ((imm & ~(XLEN - 1)) != 0) { - raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); - return; - } - val = (int32_t)(reg[rs1] << (imm & (XLEN - 1))); - break; - case 2: /* slti */ + if ((imm & ~(XLEN - 1)) != 0) { + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + return; + } + val = (int32_t)(reg[rs1] << (imm & (XLEN - 1))); + break; + case 2: /* slti */ #ifdef DEBUG_EXTRA - debug_out(">>> SLTI\n"); - stats[19]++; + debug_out(">>> SLTI\n"); + stats[19]++; #endif - val = (int32_t) reg[rs1] < (int32_t) imm; - break; - case 3: /* sltiu */ + val = (int32_t) reg[rs1] < (int32_t) imm; + break; + case 3: /* sltiu */ #ifdef DEBUG_EXTRA - debug_out(">>> SLTIU\n"); - stats[20]++; + debug_out(">>> SLTIU\n"); + stats[20]++; #endif - val = reg[rs1] < (uint32_t) imm; - break; - case 4: /* xori */ + val = reg[rs1] < (uint32_t) imm; + break; + case 4: /* xori */ #ifdef DEBUG_EXTRA - debug_out(">>> XORI\n"); - stats[21]++; + debug_out(">>> XORI\n"); + stats[21]++; #endif - val = reg[rs1] ^ imm; - break; - case 5: /* srli/srai */ - if ((imm & ~((XLEN - 1) | 0x400)) != 0) { - raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); - return; - } - if (imm & 0x400) { + val = reg[rs1] ^ imm; + break; + case 5: /* srli/srai */ + if ((imm & ~((XLEN - 1) | 0x400)) != 0) { + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + return; + } + if (imm & 0x400) { #ifdef DEBUG_EXTRA - debug_out(">>> SRAI\n"); - stats[26]++; + debug_out(">>> SRAI\n"); + stats[26]++; #endif - val = (int32_t) reg[rs1] >> (imm & (XLEN - 1)); - } else { + val = (int32_t) reg[rs1] >> (imm & (XLEN - 1)); + } else { #ifdef DEBUG_EXTRA - debug_out(">>> SRLI\n"); - stats[25]++; + debug_out(">>> SRLI\n"); + stats[25]++; #endif - val = (int32_t)((uint32_t) reg[rs1] >> (imm & (XLEN - 1))); - } - break; - case 6: /* ori */ + val = (int32_t)((uint32_t) reg[rs1] >> (imm & (XLEN - 1))); + } + break; + case 6: /* ori */ #ifdef DEBUG_EXTRA - debug_out(">>> ORI\n"); - stats[22]++; + debug_out(">>> ORI\n"); + stats[22]++; #endif - val = reg[rs1] | imm; - break; - case 7: /* andi */ + val = reg[rs1] | imm; + break; + case 7: /* andi */ #ifdef DEBUG_EXTRA - debug_out(">>> ANDI\n"); - stats[23]++; + debug_out(">>> ANDI\n"); + stats[23]++; #endif - val = reg[rs1] & imm; - break; - } - if (rd != 0) - reg[rd] = val; + val = reg[rs1] & imm; break; + } + if (rd != 0) + reg[rd] = val; + break; - case 0x33: /* OP */ + case 0x33: /* OP */ - imm = insn >> 25; - val = reg[rs1]; - val2 = reg[rs2]; + imm = insn >> 25; + val = reg[rs1]; + val2 = reg[rs2]; #ifndef STRICT_RV32I - if (imm == 1) { - funct3 = (insn >> 12) & 7; - switch (funct3) { - case 0: /* mul */ + if (imm == 1) { + funct3 = (insn >> 12) & 7; + switch (funct3) { + case 0: /* mul */ #ifdef DEBUG_EXTRA - debug_out(">>> MUL\n"); - stats[48]++; + debug_out(">>> MUL\n"); + stats[48]++; #endif - val = (int32_t)((int32_t) val * (int32_t) val2); - break; - case 1: /* mulh */ + val = (int32_t)((int32_t) val * (int32_t) val2); + break; + case 1: /* mulh */ #ifdef DEBUG_EXTRA - debug_out(">>> MULH\n"); - stats[49]++; + debug_out(">>> MULH\n"); + stats[49]++; #endif - val = (int32_t) mulh32(val, val2); - break; - case 2: /* mulhsu */ + val = (int32_t) mulh32(val, val2); + break; + case 2: /* mulhsu */ #ifdef DEBUG_EXTRA - debug_out(">>> MULHSU\n"); - stats[50]++; + debug_out(">>> MULHSU\n"); + stats[50]++; #endif - val = (int32_t) mulhsu32(val, val2); - break; - case 3: /* mulhu */ + val = (int32_t) mulhsu32(val, val2); + break; + case 3: /* mulhu */ #ifdef DEBUG_EXTRA - debug_out(">>> MULHU\n"); - stats[51]++; + debug_out(">>> MULHU\n"); + stats[51]++; #endif - val = (int32_t) mulhu32(val, val2); - break; - case 4: /* div */ + val = (int32_t) mulhu32(val, val2); + break; + case 4: /* div */ #ifdef DEBUG_EXTRA - debug_out(">>> DIV\n"); - stats[52]++; + debug_out(">>> DIV\n"); + stats[52]++; #endif - val = div32(val, val2); - break; - case 5: /* divu */ + val = div32(val, val2); + break; + case 5: /* divu */ #ifdef DEBUG_EXTRA - debug_out(">>> DIVU\n"); - stats[53]++; + debug_out(">>> DIVU\n"); + stats[53]++; #endif - val = (int32_t) divu32(val, val2); - break; - case 6: /* rem */ + val = (int32_t) divu32(val, val2); + break; + case 6: /* rem */ #ifdef DEBUG_EXTRA - debug_out(">>> REM\n"); - stats[54]++; + debug_out(">>> REM\n"); + stats[54]++; #endif - val = rem32(val, val2); - break; - case 7: /* remu */ + val = rem32(val, val2); + break; + case 7: /* remu */ #ifdef DEBUG_EXTRA - debug_out(">>> REMU\n"); - stats[55]++; + debug_out(">>> REMU\n"); + stats[55]++; #endif - val = (int32_t) remu32(val, val2); - break; - default: - raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); - return; - } - } else + val = (int32_t) remu32(val, val2); + break; + default: + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + return; + } + } else #endif - { - if (imm & ~0x20) { - raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); - return; - } - funct3 = ((insn >> 12) & 7) | ((insn >> (30 - 3)) & (1 << 3)); - switch (funct3) { - case 0: /* add */ + { + if (imm & ~0x20) { + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + return; + } + funct3 = ((insn >> 12) & 7) | ((insn >> (30 - 3)) & (1 << 3)); + switch (funct3) { + case 0: /* add */ #ifdef DEBUG_EXTRA - debug_out(">>> ADD\n"); - stats[27]++; + debug_out(">>> ADD\n"); + stats[27]++; #endif - val = (int32_t)(val + val2); - break; - case 0 | 8: /* sub */ + val = (int32_t)(val + val2); + break; + case 0 | 8: /* sub */ #ifdef DEBUG_EXTRA - debug_out(">>> SUB\n"); - stats[28]++; + debug_out(">>> SUB\n"); + stats[28]++; #endif - val = (int32_t)(val - val2); - break; - case 1: /* sll */ + val = (int32_t)(val - val2); + break; + case 1: /* sll */ #ifdef DEBUG_EXTRA - debug_out(">>> SLL\n"); - stats[29]++; + debug_out(">>> SLL\n"); + stats[29]++; #endif - val = (int32_t)(val << (val2 & (XLEN - 1))); - break; - case 2: /* slt */ + val = (int32_t)(val << (val2 & (XLEN - 1))); + break; + case 2: /* slt */ #ifdef DEBUG_EXTRA - debug_out(">>> SLT\n"); - stats[30]++; + debug_out(">>> SLT\n"); + stats[30]++; #endif - val = (int32_t) val < (int32_t) val2; - break; - case 3: /* sltu */ + val = (int32_t) val < (int32_t) val2; + break; + case 3: /* sltu */ #ifdef DEBUG_EXTRA - debug_out(">>> SLTU\n"); - stats[31]++; + debug_out(">>> SLTU\n"); + stats[31]++; #endif - val = val < val2; - break; - case 4: /* xor */ + val = val < val2; + break; + case 4: /* xor */ #ifdef DEBUG_EXTRA - debug_out(">>> XOR\n"); - stats[32]++; + debug_out(">>> XOR\n"); + stats[32]++; #endif - val = val ^ val2; - break; - case 5: /* srl */ + val = val ^ val2; + break; + case 5: /* srl */ #ifdef DEBUG_EXTRA - debug_out(">>> SRL\n"); - stats[33]++; + debug_out(">>> SRL\n"); + stats[33]++; #endif - val = (int32_t)((uint32_t) val >> (val2 & (XLEN - 1))); - break; - case 5 | 8: /* sra */ + val = (int32_t)((uint32_t) val >> (val2 & (XLEN - 1))); + break; + case 5 | 8: /* sra */ #ifdef DEBUG_EXTRA - debug_out(">>> SRA\n"); - stats[34]++; + debug_out(">>> SRA\n"); + stats[34]++; #endif - val = (int32_t) val >> (val2 & (XLEN - 1)); - break; - case 6: /* or */ + val = (int32_t) val >> (val2 & (XLEN - 1)); + break; + case 6: /* or */ #ifdef DEBUG_EXTRA - debug_out(">>> OR\n"); - stats[35]++; + debug_out(">>> OR\n"); + stats[35]++; #endif - val = val | val2; - break; - case 7: /* and */ + val = val | val2; + break; + case 7: /* and */ #ifdef DEBUG_EXTRA - debug_out(">>> AND\n"); - stats[36]++; + debug_out(">>> AND\n"); + stats[36]++; #endif - val = val & val2; - break; - default: - raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); - return; - } + val = val & val2; + break; + default: + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + return; + } + } + if (rd != 0) + reg[rd] = val; + break; + + case 0x73: /* SYSTEM */ + + funct3 = (insn >> 12) & 7; + imm = insn >> 20; + if (funct3 & 4) + val = rs1; + else + val = reg[rs1]; + funct3 &= 3; + switch (funct3) { + case 1: /* csrrw & csrrwi */ +#ifdef DEBUG_EXTRA + if ((insn >> 12) & 4) { + debug_out(">>> CSRRWI\n"); + stats[44]++; + } else { + debug_out(">>> CSRRW\n"); + stats[41]++; + } +#endif + if (csr_read(&val2, imm, TRUE)) { + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + return; + } + val2 = (int32_t) val2; + err = csr_write(imm, val); + if (err < 0) { + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + return; } if (rd != 0) - reg[rd] = val; + reg[rd] = val2; + if (err > 0) { + /* pc = pc + 4; */ + } break; - case 0x73: /* SYSTEM */ - - funct3 = (insn >> 12) & 7; - imm = insn >> 20; - if (funct3 & 4) - val = rs1; - else - val = reg[rs1]; - funct3 &= 3; - switch (funct3) { - case 1: /* csrrw & csrrwi */ + case 2: /* csrrs & csrrsi */ + case 3: /* csrrc & csrrci */ + if (csr_read(&val2, imm, (rs1 != 0))) { + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + return; + } + val2 = (int32_t) val2; #ifdef DEBUG_EXTRA - if ((insn >> 12) & 4) { - debug_out(">>> CSRRWI\n"); - stats[44]++; + switch ((insn >> 12) & 7) { + case 2: + debug_out(">>> CSRRS\n"); + stats[42]++; + break; + case 3: + debug_out(">>> CSRRC\n"); + stats[43]++; + break; + case 6: + debug_out(">>> CSRRSI\n"); + stats[45]++; + break; + case 7: + debug_out(">>> CSRRCI\n"); + stats[46]++; + break; + } +#endif + if (rs1 != 0) { + if (funct3 == 2) { + val = val2 | val; } else { - debug_out(">>> CSRRW\n"); - stats[41]++; + val = val2 & ~val; } -#endif - if (csr_read(&val2, imm, TRUE)) { - raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); - return; - } - val2 = (int32_t) val2; err = csr_write(imm, val); if (err < 0) { raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); return; } - if (rd != 0) - reg[rd] = val2; - if (err > 0) { - /* pc = pc + 4; */ - } - break; + } else { + err = 0; + } + if (rd != 0) + reg[rd] = val2; + break; - case 2: /* csrrs & csrrsi */ - case 3: /* csrrc & csrrci */ - if (csr_read(&val2, imm, (rs1 != 0))) { + case 0: + switch (imm) { + case 0x000: /* ecall */ +#ifdef DEBUG_EXTRA + debug_out(">>> ECALL\n"); + stats[39]++; +#endif + if (insn & 0x000fff80) { raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); return; } - val2 = (int32_t) val2; -#ifdef DEBUG_EXTRA - switch ((insn >> 12) & 7) { - case 2: - debug_out(">>> CSRRS\n"); - stats[42]++; - break; - case 3: - debug_out(">>> CSRRC\n"); - stats[43]++; - break; - case 6: - debug_out(">>> CSRRSI\n"); - stats[45]++; - break; - case 7: - debug_out(">>> CSRRCI\n"); - stats[46]++; - break; - } -#endif - if (rs1 != 0) { - if (funct3 == 2) { - val = val2 | val; - } else { - val = val2 & ~val; - } - err = csr_write(imm, val); - if (err < 0) { - raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + /* + * compliance test specific: if bit 0 of gp (x3) is 0, it is a + * syscall, otherwise it is the program end, with the exit code + * in the bits 31:1 + */ + if (begin_signature) { + if (reg[3] & 1) { + debug_out("program end, result: %04x\n", reg[3] >> 1); + machine_running = FALSE; return; - } - } else { - err = 0; - } - if (rd != 0) - reg[rd] = val2; - break; - case 0: - switch (imm) { - case 0x000: /* ecall */ -#ifdef DEBUG_EXTRA - debug_out(">>> ECALL\n"); - stats[39]++; -#endif - if (insn & 0x000fff80) { - raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); - return; - } - /* - * compliance test specific: if bit 0 of gp (x3) is 0, it is - * a syscall, otherwise it is the program end, with the exit - * code in the bits 31:1 - */ - if (begin_signature) { - if (reg[3] & 1) { - debug_out("program end, result: %04x\n", - reg[3] >> 1); - machine_running = FALSE; - return; - - } else { - debug_out("syscall: %04x\n", reg[3]); - raise_exception(CAUSE_USER_ECALL + priv, 0); - } } else { - /* on real hardware, an exception is raised, the - * I-ECALL-01 compliance test tests this as well */ + debug_out("syscall: %04x\n", reg[3]); raise_exception(CAUSE_USER_ECALL + priv, 0); - return; } - break; + } else { + /* on real hardware, an exception is raised, the I-ECALL-01 + * compliance test tests this as well */ + raise_exception(CAUSE_USER_ECALL + priv, 0); + return; + } + break; - case 0x001: /* ebreak */ + case 0x001: /* ebreak */ #ifdef DEBUG_EXTRA - debug_out(">>> EBREAK\n"); - stats[40]++; + debug_out(">>> EBREAK\n"); + stats[40]++; #endif - if (insn & 0x000fff80) { - raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); - return; - } - raise_exception(CAUSE_BREAKPOINT, 0); + if (insn & 0x000fff80) { + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); return; + } + raise_exception(CAUSE_BREAKPOINT, 0); + return; - case 0x102: /* sret */ - { + case 0x102: /* sret */ + { #ifdef DEBUG_EXTRA - debug_out(">>> SRET\n"); - stats[59]++; + debug_out(">>> SRET\n"); + stats[59]++; #endif - if ((insn & 0x000fff80) || (priv < PRV_S)) { - raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); - return; - } - handle_sret(); + if ((insn & 0x000fff80) || (priv < PRV_S)) { + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); return; - } break; + } + handle_sret(); + return; + } break; - case 0x105: /* wfi */ + case 0x105: /* wfi */ #ifdef DEBUG_EXTRA - debug_out(">>> WFI\n"); - stats[61]++; + debug_out(">>> WFI\n"); + stats[61]++; #endif - /* wait for interrupt: it is allowed to execute it as nop */ - break; + /* wait for interrupt: it is allowed to execute it as nop */ + break; - case 0x302: /* mret */ - { + case 0x302: /* mret */ + { #ifdef DEBUG_EXTRA - debug_out(">>> MRET\n"); - stats[60]++; + debug_out(">>> MRET\n"); + stats[60]++; #endif - if ((insn & 0x000fff80) || (priv < PRV_M)) { - raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); - return; - } - handle_mret(); + if ((insn & 0x000fff80) || (priv < PRV_M)) { + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); return; - } break; + } + handle_mret(); + return; + } break; - default: - if ((imm >> 5) == 0x09) { + default: + if ((imm >> 5) == 0x09) { #ifdef DEBUG_EXTRA - debug_out(">>> SFENCE.VMA\n"); - stats[62]++; + debug_out(">>> SFENCE.VMA\n"); + stats[62]++; #endif - /* sfence.vma */ - if ((insn & 0x00007f80) || (priv == PRV_U)) { - raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); - return; - } - } else { + /* sfence.vma */ + if ((insn & 0x00007f80) || (priv == PRV_U)) { raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); return; } - break; + } else { + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + return; } break; - - default: - raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); - return; } break; - case 0x0f: /* MISC-MEM */ + default: + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + return; + } + break; - funct3 = (insn >> 12) & 7; - switch (funct3) { - case 0: /* fence */ + case 0x0f: /* MISC-MEM */ + + funct3 = (insn >> 12) & 7; + switch (funct3) { + case 0: /* fence */ #ifdef DEBUG_EXTRA - debug_out(">>> FENCE\n"); - stats[37]++; + debug_out(">>> FENCE\n"); + stats[37]++; #endif - if (insn & 0xf00fff80) { - raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); - return; - } - break; + if (insn & 0xf00fff80) { + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + return; + } + break; - case 1: /* fence.i */ + case 1: /* fence.i */ #ifdef DEBUG_EXTRA - debug_out(">>> FENCE.I\n"); - stats[38]++; + debug_out(">>> FENCE.I\n"); + stats[38]++; #endif - if (insn != 0x0000100f) { - raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); - return; - } - break; - - default: + if (insn != 0x0000100f) { raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); return; } break; -#ifndef STRICT_RV32I + default: + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + return; + } + break; - case 0x2f: /* AMO */ +#ifndef STRICT_RV32I - funct3 = (insn >> 12) & 7; - switch (funct3) { - case 2: { - uint32_t rval; + case 0x2f: /* AMO */ - addr = reg[rs1]; - funct3 = insn >> 27; - switch (funct3) { - case 2: /* lr.w */ -#ifdef DEBUG_EXTRA - debug_out(">>> LR.W\n"); - stats[56]++; -#endif - if (rs2 != 0) { - raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); - return; - } - if (target_read_u32(&rval, addr)) { - raise_exception(pending_exception, pending_tval); - return; - } - val = (int32_t) rval; - load_res = addr; - break; + funct3 = (insn >> 12) & 7; + switch (funct3) { + case 2: { + uint32_t rval; - case 3: /* sc.w */ + addr = reg[rs1]; + funct3 = insn >> 27; + switch (funct3) { + case 2: /* lr.w */ #ifdef DEBUG_EXTRA - debug_out(">>> SC.W\n"); - stats[57]++; + debug_out(">>> LR.W\n"); + stats[56]++; #endif - if (load_res == addr) { - if (target_write_u32(addr, reg[rs2])) { - raise_exception(pending_exception, pending_tval); - return; - } - val = 0; - } else { - val = 1; - } - break; - - case 1: /* amiswap.w */ - case 0: /* amoadd.w */ - case 4: /* amoxor.w */ - case 0xc: /* amoand.w */ - case 0x8: /* amoor.w */ - case 0x10: /* amomin.w */ - case 0x14: /* amomax.w */ - case 0x18: /* amominu.w */ - case 0x1c: /* amomaxu.w */ + if (rs2 != 0) { + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + return; + } + if (target_read_u32(&rval, addr)) { + raise_exception(pending_exception, pending_tval); + return; + } + val = (int32_t) rval; + load_res = addr; + break; + case 3: /* sc.w */ #ifdef DEBUG_EXTRA - debug_out(">>> AM...\n"); - stats[63]++; + debug_out(">>> SC.W\n"); + stats[57]++; #endif - if (target_read_u32(&rval, addr)) { - raise_exception(pending_exception, pending_tval); - return; - } - val = (int32_t) rval; - val2 = reg[rs2]; - switch (funct3) { - case 1: /* amiswap.w */ - break; - case 0: /* amoadd.w */ - val2 = (int32_t)(val + val2); - break; - case 4: /* amoxor.w */ - val2 = (int32_t)(val ^ val2); - break; - case 0xc: /* amoand.w */ - val2 = (int32_t)(val & val2); - break; - case 0x8: /* amoor.w */ - val2 = (int32_t)(val | val2); - break; - case 0x10: /* amomin.w */ - if ((int32_t) val < (int32_t) val2) - val2 = (int32_t) val; - break; - case 0x14: /* amomax.w */ - if ((int32_t) val > (int32_t) val2) - val2 = (int32_t) val; - break; - case 0x18: /* amominu.w */ - if ((uint32_t) val < (uint32_t) val2) - val2 = (int32_t) val; - break; - case 0x1c: /* amomaxu.w */ - if ((uint32_t) val > (uint32_t) val2) - val2 = (int32_t) val; - break; - default: - raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); - return; - } - if (target_write_u32(addr, val2)) { + if (load_res == addr) { + if (target_write_u32(addr, reg[rs2])) { raise_exception(pending_exception, pending_tval); return; } - break; - default: - raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); - return; + val = 0; + } else { + val = 1; } - } break; - default: - raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); - return; - } - if (rd != 0) - reg[rd] = val; - break; + break; + + case 1: /* amiswap.w */ + case 0: /* amoadd.w */ + case 4: /* amoxor.w */ + case 0xc: /* amoand.w */ + case 0x8: /* amoor.w */ + case 0x10: /* amomin.w */ + case 0x14: /* amomax.w */ + case 0x18: /* amominu.w */ + case 0x1c: /* amomaxu.w */ -#endif -#ifdef RV32C - /* Compressed insn */ - case 0: - break; - case 1: - funct3 = (insn >> 13) & 0x7; - midpart = (insn >> 2) & 0x07ff; - switch (funct3) { - case 0: /* C.NOP, C.ADDI */ - if (((midpart >> 5) & 0x1f) == 0) { /* C.NOP*/ #ifdef DEBUG_EXTRA - dprintf(">>> C.NOP\n"); + debug_out(">>> AM...\n"); + stats[63]++; #endif + if (target_read_u32(&rval, addr)) { + raise_exception(pending_exception, pending_tval); return; - } else { - rs1 = rd = ((midpart >> 5) & 0x1f); - imm = (midpart & 0x1f) | ((midpart >> 5) & 0x20); - val = reg[rs1] + imm; -#ifdef DEBUG_EXTRA - dprintf(">>> C.ADDI\n"); - printf("rd: %d, rs1: %d, imm: %d, reg[rd]: %d, val: %d\n", - rd, rs1, imm, reg[rd], val); -#endif } - break; - case 1: /* C.JAL, C.ADDIW */ -#ifdef DEBUG_EXTRA - switch (XLEN) { - case 32: - dprintf(">>> C.JAL\n"); - break; - case 64: - case 128: - dprintf(">>> C.ADDIW\n"); - break; - default: - dprintf(">>> Unknow XLEN\n"); + val = (int32_t) rval; + val2 = reg[rs2]; + switch (funct3) { + case 1: /* amiswap.w */ break; - } -#endif - switch (XLEN) { - case 32: - imm = (midpart & 0x400) | ((midpart << 3) & 0x200) | - (midpart & 0x170) | ((midpart << 2) & 0x40) | - (midpart & 0x20) | ((midpart << 4) & 0x10) | - ((midpart >> 6) & 0x8) | ((midpart >> 1) & 0x7); - imm = (imm << 1) & 0xfffe; - reg[1] = pc + 2; /* Store the link to x1 register */ - next_pc = (int32_t)(pc + imm); - if (next_pc > pc) - forward_counter++; - else - backward_counter++; - jump_counter++; + case 0: /* amoadd.w */ + val2 = (int32_t)(val + val2); break; - case 64: - case 128: - rs1 = rd = ((midpart >> 5) & 0x1f); - imm = (midpart >> (11 - 5)) | (midpart & 0x1f); - val = reg[rs1] + imm; + case 4: /* amoxor.w */ + val2 = (int32_t)(val ^ val2); break; - } - break; - case 2: /* C.LI */ -#ifdef DEBUG_EXTRA - dprintf(">>> C.LI\n"); -#endif - rs1 = rd = ((midpart >> 5) & 0x1f); - imm = ((midpart >> 5) & 0x20) | (midpart & 0x1f); - val = imm; - break; - case 3: /* C.ADDI16SP, C.LUI */ -#ifdef DEBUG_EXTRA - switch (rd) { - case 2: - dprintf(">>> C.ADDI16SP\n"); + case 0xc: /* amoand.w */ + val2 = (int32_t)(val & val2); break; - default: - dprintf(">>> C.LUI\n"); - } -#endif - switch (rd) { /* C.ADDI16SP */ - case 2: - imm = ((midpart >> 4) & 0x1) | ((midpart << 1) & 0x2) | - ((midpart >> 1) & 0x4) | ((midpart << 2) & 0x18) | - ((midpart >> 5) & 0x20); - imm = (imm << 4) << (31 - 9) >> (31 - 9); - val = reg[rd] + imm; + case 0x8: /* amoor.w */ + val2 = (int32_t)(val | val2); break; - default: - imm = (midpart & 0x1f) | ((midpart >> 5) & 0x20); - imm = ((imm << 12) & 0xfffff000); - imm = imm << 14 >> 14; - if (rd != 0) - val = reg[rd] | imm; + case 0x10: /* amomin.w */ + if ((int32_t) val < (int32_t) val2) + val2 = (int32_t) val; break; - } - break; - case 4: /* C.SRLI, C.SRLI64, C.SRAI, C.SRAI64, C.ANDI, C.SUB, C.XOR, - C.OR, C.AND, C.SUBW, C.ADDW*/ - switch (((midpart >> 8) & 0x3)) { - case 0: /* C.SRLI C.SRLI64 */ -#ifdef DEBUG_EXTRA - switch (XLEN) { - case 32: - case 64: - dprintf(">>> C.SRLI\n"); - break; - case 128: - dprintf(">>> C.SRLI64\n"); - break; - } -#endif - switch (XLEN) { - case 32: - case 64: - rs1 = rd = ((midpart >> 5) & 0x1f) + 8; - imm = (midpart & 0xf) | (midpart >> 5 & 0x10); - val = reg[rs1]; - break; - case 128: - rs1 = rd = ((midpart >> 5) & 0x1f) + 8; - imm = 64; - val = reg[rs1]; - break; - } - val = val >> imm; + case 0x14: /* amomax.w */ + if ((int32_t) val > (int32_t) val2) + val2 = (int32_t) val; break; - case 1: /* C.SRAI C.SRAI64 */ -#ifdef DEBUG_EXTRA - switch (XLEN) { - case 32: - case 64: - dprintf(">>> C.SRAI\n"); - case 128: - dprintf(">>> C.SRAI64\n"); - } -#endif - switch (XLEN) { - case 32: - case 64: - rs1 = rd = ((midpart >> 5) & 0x1f) + 8; - imm = (midpart & 0xf) | ((midpart >> 5) & 0x10); - val = reg[rs1]; - break; - case 128: - rs1 = rd = ((midpart >> 5) & 0x1f) + 8; - imm = 64; - val = reg[rs1]; - break; - } - val = val << imm; + case 0x18: /* amominu.w */ + if ((uint32_t) val < (uint32_t) val2) + val2 = (int32_t) val; break; - case 2: /* C.ANDI */ -#ifdef DEBUG_EXTRA - dprintf(">>> C.ANDI\n"); -#endif - rs1 = rd = ((midpart >> 5) & 0x7) + 8; - imm = (midpart & 0x1f) | ((midpart >> 5) & 0x10); - val = reg[rs1]; - val = val & imm; + case 0x1c: /* amomaxu.w */ + if ((uint32_t) val > (uint32_t) val2) + val2 = (int32_t) val; break; - case 3: /* C.SUB, C.XOR, C.OR, C.AND, C.SUBW, C.ADDW */ - rs2 = (midpart & 0x7) + 8; - rs1 = rd = ((midpart >> 5) & 0x7) + 8; - switch (((midpart >> 3) & 0x3) | ((midpart >> 8) & 0x4)) { - case 0: /* C.SUB */ -#ifdef DEBUG_EXTRA - dprintf(">>> C.SUB\n"); -#endif - val = reg[rd] - reg[rs2]; - break; - case 1: /* C.XOR */ -#ifdef DEBUG_EXTRA - dprintf(">>> C.XOR\n"); -#endif - val = reg[rd] ^ reg[rs2]; - break; - case 2: /* C.OR */ -#ifdef DEBUG_EXTRA - dprintf(">>> C.OR\n"); -#endif - val = reg[rd] | reg[rs2]; - break; - case 3: /* C.AND */ -#ifdef DEBUG_EXTRA - dprintf(">>> C.AND\n"); -#endif - val = reg[rd] & reg[rs2]; - break; - case 4: /* C.SUBW */ -#ifdef DEBUG_EXTRA - dprintf(">>> C.SUBW\n"); -#endif - val = reg[rd] - reg[rs2]; - if (XLEN == 128) { - val = (int32_t)(val << 96) >> 96; - } else if (XLEN == 64) { - val = (int32_t)(val << 32) >> 32; - } else { - raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); - } - break; - case 5: /* C.ADDW */ -#ifdef DEBUG_EXTRA - dprintf(">>> C.ADDW\n"); -#endif - val = reg[rd] + reg[rs2]; - if (XLEN == 128) { - val = (int32_t)(val << 96) >> 96; - } else if (XLEN == 64) { - val = (int32_t)(val << 32) >> 32; - } else { - raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); - } - break; - case 6: - case 7: - /* NOP */ - break; - } - } - break; - case 5: /* C.J */ -#ifdef DEBUG_EXTRA - dprintf(">>> C.J\n"); -#endif - rd = 0; - imm = ((midpart >> 1) & 0x7) | ((midpart >> 6) & 0x8) | - ((midpart << 5) & 0x10) | ((midpart) &0x20) | - ((midpart << 2) & 0x40) | ((midpart) &0x180) | - ((midpart << 3) & 0x200) | ((midpart) &0x400); - imm = (imm << 1) << 20 >> 20; - next_pc = (int32_t)(pc + imm); - if (next_pc > pc) - forward_counter++; - else - backward_counter++; - jump_counter++; - break; - case 6: /* C.BEQZ */ -#ifdef DEBUG_EXTRA - dprintf(">>> C.BEQZ\n"); -#endif - rs1 = ((midpart >> 5) & 0x7) + 8; - rd = 0; - if (reg[rs1] == 0) { - imm = ((midpart >> 1) & 0x3) | ((midpart >> 3) & 0xc) | - ((midpart << 4) & 0x10) | ((midpart << 2) & 0x60) | - ((midpart) &0x80); - imm = (imm << 1) << 23 >> 23; - next_pc = (int32_t)(pc + imm); - if (next_pc > pc) - forward_counter++; - else - backward_counter++; - jump_counter++; + default: + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + return; } - break; - case 7: /* C.BNEZ */ -#ifdef DEBUG_EXTRA - dprintf(">>> C.BNEZ\n"); -#endif - rs1 = ((midpart >> 5) & 0x7) + 8; - rd = 0; - imm = 0; - if (reg[rs1] != 0) { - imm = ((midpart >> 1) & 0x3) | ((midpart >> 6) & 0xc) | - ((midpart << 4) & 0x10) | ((midpart << 2) & 0x60) | - ((midpart) &0x80); - imm = (imm << 1) << 23 >> 23; - next_pc = (int32_t)(pc + imm); - if (next_pc > pc) - forward_counter++; - else - backward_counter++; - jump_counter++; + if (target_write_u32(addr, val2)) { + raise_exception(pending_exception, pending_tval); + return; } -#ifdef DEBUG_EXTRA - printf( - "rd : %d, rs1: %d, imm: %d, reg[rs1] : %d, pc: %08x, " - "next_pc: %08x\n", - rd, rs1, imm, reg[rs1]); -#endif break; default: raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); return; } - if (rd != 0) { - reg[rd] = val; - } - break; - case 2: - funct3 = (insn >> 13) & 0x7; - midpart = (insn >> 2) & 0x07ff; - switch (funct3) { - case 6: -#ifdef DEBUG_EXTRA - dprintf(">>> C.SWSP\n"); -#endif - rs2 = midpart & 0x1f; - imm = ((midpart >> 2) & 0x1e0) | ((midpart << 4) & 0x600); - imm = (imm >> 3) & 0xff; - addr = reg[2] + imm; - val = reg[rs2]; - if (target_write_u32(addr, val)) { - raise_exception(pending_exception, pending_tval); - return; - } - break; - } - break; - + } break; default: raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); return; } - } + if (rd != 0) + reg[rd] = val; + break; - /* returns realtime in nanoseconds */ - int64_t get_clock() - { - struct timespec ts; - clock_gettime(CLOCK_MONOTONIC, &ts); - return ts.tv_sec * 1000000000LL + ts.tv_nsec; +#endif + + default: + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + return; } +} +/* returns realtime in nanoseconds */ +int64_t get_clock() +{ + struct timespec ts; + clock_gettime(CLOCK_MONOTONIC, &ts); + return ts.tv_sec * 1000000000LL + ts.tv_nsec; +} - void riscv_cpu_interp_x32() - { - /* we use a single execution loop to keep a simple control flow for - * emscripten */ - while (machine_running) { +void riscv_cpu_interp_x32() +{ + /* we use a single execution loop to keep a simple control flow for + * emscripten */ + while (machine_running) { #if 1 - /* update timer, assuming 10 MHz clock (100 ns period) for the mtime - * counter */ - mtime = get_clock() / 100ll; + /* update timer, assuming 10 MHz clock (100 ns period) for the mtime + * counter */ + mtime = get_clock() / 100ll; - /* for reproducible debug runs, you can use a fixed fixed increment - * per instruction */ + /* for reproducible debug runs, you can use a fixed fixed increment + * per instruction */ #else - mtime += 10; -#endif - /* default value for next PC is next instruction, can be changed by - * branches or exceptions */ - next_pc = pc + 4; - - /* test for timer interrupt */ - if (mtimecmp <= mtime) { - mip |= MIP_MTIP; - } - if ((mip & mie) != 0 && (mstatus & MSTATUS_MIE)) { - raise_interrupt(); - } else { - /* Compressed or normal */ - insn_type = get_insn32(pc, &insn); -#ifdef RV32C - if (insn_type == CINSN) - next_pc = pc + 2; -#endif -#ifdef DEBUG_EXTRA - printf("insn_type : %s\n", - insn_type == CINSN ? "CINSN" : "INSN"); + mtime += 10; #endif - insn_counter++; + /* default value for next PC is next instruction, can be changed by + * branches or exceptions */ + next_pc = pc + 4; - debug_out("[%08x]=%08x, mtime: %lx, mtimecmp: %lx\n", pc, insn, - mtime, mtimecmp); - execute_instruction(); - } + /* test for timer interrupt */ + if (mtimecmp <= mtime) { + mip |= MIP_MTIP; + } + if ((mip & mie) != 0 && (mstatus & MSTATUS_MIE)) { + raise_interrupt(); + } else { + /* normal instruction execution */ + insn = get_insn32(pc); + insn_counter++; - /* test for misaligned fetches , in order to match the compressed - * instruction. */ -#ifdef RV32C - if (next_pc & 0x1) { - raise_exception(CAUSE_MISALIGNED_FETCH, next_pc); - } -#else - if (next_pc & 0x3) { - raise_exception(CAUSE_MISALIGNED_FETCH, next_pc); - } -#endif + debug_out("[%08x]=%08x, mtime: %lx, mtimecmp: %lx\n", pc, insn, + mtime, mtimecmp); + execute_instruction(); + } - /* update current PC */ - pc = next_pc; + if (next_pc & 0x3) { + raise_exception(CAUSE_MISALIGNED_FETCH, next_pc); } - debug_out("done interp %lx int=%x mstatus=%lx prv=%d\n", - (uint64_t) insn_counter, mip & mie, (uint64_t) mstatus, priv); + /* update current PC */ + pc = next_pc; } - int main(int argc, char **argv) - { + debug_out("done interp %lx int=%x mstatus=%lx prv=%d\n", + (uint64_t) insn_counter, mip & mie, (uint64_t) mstatus, priv); +} + +int main(int argc, char **argv) +{ #ifdef DEBUG_OUTPUT - FILE *fo; - char *po, hex_file[100]; -#endif - - /* automatic STDOUT flushing, no fflush needed */ - setvbuf(stdout, NULL, _IONBF, 0); - /* parse command line */ - const char *elf_file = NULL; - int output_flag = 0; - const char *output_file = NULL; - const char *elf_name = NULL; - const char *signature_file = NULL; - int cmd_opt = 0; - struct option opts[] = {{"elf", 1, NULL, 'e'}, - {"verify", 1, NULL, 'v'}, - {"signaturedump", 0, NULL, 's'}}; - const char *optstring = "e:s:o:"; - while ((cmd_opt = getopt_long(argc, argv, optstring, opts, NULL)) != - -1) { - switch (cmd_opt) { - case 'e': - elf_file = optarg; - elf_name = strtok(strdup(elf_file), "."); - printf("%s\n", elf_name); - output_file = malloc(strlen(elf_name) + 30); - memset(output_file, '\0', strlen(elf_name) + 30); - strcat(output_file, elf_name); - strcat(output_file, ".signature.output"); - printf("signature.output : %s\n", output_file); - break; - case 'v': - // signature_file = optarg; - break; - case 's': - // output_file = optarg; - output_flag = 1; - break; - default: - printf("Unknow argument: %s\n", optarg); - break; - } + FILE *fo; + char *po, hex_file[100]; +#endif + + /* automatic STDOUT flushing, no fflush needed */ + setvbuf(stdout, NULL, _IONBF, 0); + /* parse command line */ + const char *elf_file = NULL; + int output_flag = 0; + const char *output_file = NULL; + const char *elf_name = NULL; + const char *signature_file = NULL; + int cmd_opt = 0; + int variant = -1; + + for (int i = 1; i < argc; i++) { + char *arg = argv[i]; + if (arg[0] != '-') { + elf_file = arg; } - if (elf_file == NULL) { - printf("missing ELF file\n"); - return 1; + } + if (elf_file == NULL) { + printf("Missing ELF File"); + } else { + elf_name = strtok(strdup(elf_file), "."); + output_file = malloc(strlen(elf_name) + 30); + memset(output_file, '\0', strlen(elf_name) + 30); + strcat(output_file, elf_name); + strcat(output_file, ".signature.output"); + } + + struct option opts[] = { + {"elf", 1, NULL, 'e'}, + {"signaturedump", 0, NULL, 's'}, + }; + const char *optstring = "e:s:o:"; + while ((cmd_opt = getopt_long(argc, argv, optstring, opts, NULL)) != -1) { + switch (cmd_opt) { + case 'e': + case 'p': + elf_file = optarg; + elf_name = strtok(strdup(elf_file), "."); +#ifdef DEBUG_EXTRA + printf("%s\n", elf_name); + printf("signature.output : %s\n", output_file); +#endif + output_file = malloc(strlen(elf_name) + 30); + memset(output_file, '\0', strlen(elf_name) + 30); + strcat(output_file, elf_name); + strcat(output_file, ".signature.output"); +#ifdef DEBUG_EXTRA + printf("signature.output : %s\n", output_file); +#endif + break; + case 'v': + // signature_file = optarg; + variant = 0; // for RV32I + break; + case 's': + output_flag = 1; + break; + default: + printf("Unknow argument: %s\n", optarg); + break; } + } + if (elf_file == NULL) { + printf("Missing ELF file\n"); + return 1; + } - for (uint32_t u = 0; u < RAM_SIZE; u++) - ram[u] = 0; + for (uint32_t u = 0; u < RAM_SIZE; u++) + ram[u] = 0; #ifdef DEBUG_EXTRA - init_stats(); + init_stats(); #endif - /* open ELF file */ - elf_version(EV_CURRENT); - int fd = open(elf_file, O_RDONLY); - if (fd == -1) { - printf("can't open file %s\n", elf_file); - return 1; - } - Elf *elf = elf_begin(fd, ELF_C_READ, NULL); - - /* scan for symbol table */ - Elf_Scn *scn = NULL; - GElf_Shdr shdr; - while ((scn = elf_nextscn(elf, scn)) != NULL) { - gelf_getshdr(scn, &shdr); - if (shdr.sh_type == SHT_SYMTAB) { - Elf_Data *data = elf_getdata(scn, NULL); - int count = shdr.sh_size / shdr.sh_entsize; - for (int i = 0; i < count; i++) { - GElf_Sym sym; - gelf_getsym(data, i, &sym); - char *name = elf_strptr(elf, shdr.sh_link, sym.st_name); - if (strcmp(name, "begin_signature") == 0) { - begin_signature = sym.st_value; - } - if (strcmp(name, "end_signature") == 0) { - end_signature = sym.st_value; - } + /* open ELF file */ + elf_version(EV_CURRENT); + int fd = open(elf_file, O_RDONLY); + if (fd == -1) { + printf("can't open file %s\n", elf_file); + return 1; + } + Elf *elf = elf_begin(fd, ELF_C_READ, NULL); + + /* scan for symbol table */ + Elf_Scn *scn = NULL; + GElf_Shdr shdr; + while ((scn = elf_nextscn(elf, scn)) != NULL) { + gelf_getshdr(scn, &shdr); + if (shdr.sh_type == SHT_SYMTAB) { + Elf_Data *data = elf_getdata(scn, NULL); + int count = shdr.sh_size / shdr.sh_entsize; + for (int i = 0; i < count; i++) { + GElf_Sym sym; + gelf_getsym(data, i, &sym); + char *name = elf_strptr(elf, shdr.sh_link, sym.st_name); + if (strcmp(name, "begin_signature") == 0) { + begin_signature = sym.st_value; + } + if (strcmp(name, "end_signature") == 0) { + end_signature = sym.st_value; + } - /* for compliance test */ - if (strcmp(name, "_start") == 0) { - start = sym.st_value; - } + /* for compliance test */ + if (strcmp(name, "_start") == 0) { + start = sym.st_value; + } - /* for zephyr */ - if (strcmp(name, "__reset") == 0) { - start = sym.st_value; - } - if (strcmp(name, "__irq_wrapper") == 0) { - mtvec = sym.st_value; - } + /* for zephyr */ + if (strcmp(name, "__reset") == 0) { + start = sym.st_value; + } + if (strcmp(name, "__irq_wrapper") == 0) { + mtvec = sym.st_value; } } } + } - /* set .text section as the base address */ - scn = NULL; - size_t shstrndx; - elf_getshdrstrndx(elf, &shstrndx); - while ((scn = elf_nextscn(elf, scn)) != NULL) { - gelf_getshdr(scn, &shdr); - const char *name = elf_strptr(elf, shstrndx, shdr.sh_name); - printf("section name: %s\n", name); - printf("Type: %d\n", shdr.sh_type); - if (shdr.sh_type == SHT_PROGBITS) { - if (strcmp(name, ".text") == 0) { - ram_start = shdr.sh_addr; - break; - } else if (strcmp(name, ".text.init") == 0) { - ram_start = shdr.sh_addr; - break; - } + /* set .text section as the base address */ + scn = NULL; + size_t shstrndx; + elf_getshdrstrndx(elf, &shstrndx); + while ((scn = elf_nextscn(elf, scn)) != NULL) { + gelf_getshdr(scn, &shdr); + const char *name = elf_strptr(elf, shstrndx, shdr.sh_name); + if (shdr.sh_type == SHT_PROGBITS) { + if (strcmp(name, ".text") == 0) { + ram_start = shdr.sh_addr; + break; + } else if (strcmp(name, ".text.init") == 0) { + ram_start = shdr.sh_addr; + break; } } + } - debug_out("begin_signature: 0x%08x\n", begin_signature); - debug_out("end_signature: 0x%08x\n", end_signature); - debug_out("ram_start: 0x%08x\n", ram_start); - debug_out("entry point: 0x%08x\n", start); - - /* scan for program */ - scn = NULL; - while ((scn = elf_nextscn(elf, scn)) != NULL) { - gelf_getshdr(scn, &shdr); - - /* filter NULL address sections and .bss */ - if (shdr.sh_addr && shdr.sh_type != SHT_NOBITS) { - Elf_Data *data = elf_getdata(scn, NULL); - if (shdr.sh_addr >= ram_start) { - for (size_t i = 0; i < shdr.sh_size; i++) { - ram_curr = shdr.sh_addr + i - ram_start; - if (ram_curr >= RAM_SIZE) { - debug_out( - "memory pointer outside of range 0x%08x " - "(section " - "at address 0x%08x)\n", - ram_curr, (uint32_t) shdr.sh_addr); - /* break; */ - } else { - ram[ram_curr] = ((uint8_t *) data->d_buf)[i]; - if (ram_curr > ram_last) - ram_last = ram_curr; - } + debug_out("begin_signature: 0x%08x\n", begin_signature); + debug_out("end_signature: 0x%08x\n", end_signature); + debug_out("ram_start: 0x%08x\n", ram_start); + debug_out("entry point: 0x%08x\n", start); + + /* scan for program */ + scn = NULL; + while ((scn = elf_nextscn(elf, scn)) != NULL) { + gelf_getshdr(scn, &shdr); + + /* filter NULL address sections and .bss */ + if (shdr.sh_addr && shdr.sh_type != SHT_NOBITS) { + Elf_Data *data = elf_getdata(scn, NULL); + if (shdr.sh_addr >= ram_start) { + for (size_t i = 0; i < shdr.sh_size; i++) { + ram_curr = shdr.sh_addr + i - ram_start; + if (ram_curr >= RAM_SIZE) { + debug_out( + "memory pointer outside of range 0x%08x " + "(section " + "at address 0x%08x)\n", + ram_curr, (uint32_t) shdr.sh_addr); + /* break; */ + } else { + ram[ram_curr] = ((uint8_t *) data->d_buf)[i]; + if (ram_curr > ram_last) + ram_last = ram_curr; } - } else { - debug_out("ignoring section at address 0x%08x\n", - (uint32_t) shdr.sh_addr); } + } else { + debug_out("ignoring section at address 0x%08x\n", + (uint32_t) shdr.sh_addr); } } + } - /* close ELF file */ - elf_end(elf); - close(fd); + /* close ELF file */ + elf_end(elf); + close(fd); #ifdef DEBUG_OUTPUT - printf("codesize: 0x%08x (%i)\n", ram_last + 1, ram_last + 1); - strcpy(hex_file, elf_file); - po = strrchr(hex_file, '.'); - if (po != NULL) - *po = 0; - strcat(hex_file, ".mem"); - fo = fopen(hex_file, "wt"); - if (fo != NULL) { - for (uint32_t u = 0; u <= ram_last; u++) { - fprintf(fo, "%02X ", ram[u]); - if ((u & 15) == 15) - fprintf(fo, "\n"); - } - fprintf(fo, "\n"); - fclose(fo); + printf("codesize: 0x%08x (%i)\n", ram_last + 1, ram_last + 1); + strcpy(hex_file, elf_file); + po = strrchr(hex_file, '.'); + if (po != NULL) + *po = 0; + strcat(hex_file, ".mem"); + fo = fopen(hex_file, "wt"); + if (fo != NULL) { + for (uint32_t u = 0; u <= ram_last; u++) { + fprintf(fo, "%02X ", ram[u]); + if ((u & 15) == 15) + fprintf(fo, "\n"); } + fprintf(fo, "\n"); + fclose(fo); + } #if 1 - fo = fopen("rom.v", "wt"); - if (fo != NULL) { - fprintf(fo, "module rom(addr,data);\n"); - uint32_t romsz = (ram_start & 0xFFFF) + ram_last + 1; - printf("codesize with offset: %i\n", romsz); - if (romsz >= 32768) - fprintf(fo, "input [15:0] addr;\n"); - else if (romsz >= 16384) - fprintf(fo, "input [14:0] addr;\n"); - else if (romsz >= 8192) - fprintf(fo, "input [13:0] addr;\n"); - else if (romsz >= 4096) - fprintf(fo, "input [12:0] addr;\n"); - else if (romsz >= 2048) - fprintf(fo, "input [11:0] addr;\n"); - else if (romsz >= 1024) - fprintf(fo, "input [10:0] addr;\n"); - else if (romsz >= 512) - fprintf(fo, "input [9:0] addr;\n"); - else if (romsz >= 256) - fprintf(fo, "input [8:0] addr;\n"); - else - fprintf(fo, "input [7:0] addr;\n"); - fprintf( - fo, + fo = fopen("rom.v", "wt"); + if (fo != NULL) { + fprintf(fo, "module rom(addr,data);\n"); + uint32_t romsz = (ram_start & 0xFFFF) + ram_last + 1; + printf("codesize with offset: %i\n", romsz); + if (romsz >= 32768) + fprintf(fo, "input [15:0] addr;\n"); + else if (romsz >= 16384) + fprintf(fo, "input [14:0] addr;\n"); + else if (romsz >= 8192) + fprintf(fo, "input [13:0] addr;\n"); + else if (romsz >= 4096) + fprintf(fo, "input [12:0] addr;\n"); + else if (romsz >= 2048) + fprintf(fo, "input [11:0] addr;\n"); + else if (romsz >= 1024) + fprintf(fo, "input [10:0] addr;\n"); + else if (romsz >= 512) + fprintf(fo, "input [9:0] addr;\n"); + else if (romsz >= 256) + fprintf(fo, "input [8:0] addr;\n"); + else + fprintf(fo, "input [7:0] addr;\n"); + fprintf(fo, "output reg [7:0] data;\nalways @(addr) begin\n case(addr)\n"); - for (uint32_t u = 0; u <= ram_last; u++) { - fprintf(fo, " %i : data = 8'h%02X;\n", (ram_start & 0xFFFF) + u, - ram[u]); - } - fprintf(fo, - " default: data = 8'h01; // invalid instruction\n " - "endcase\nend\nendmodule\n"); - fclose(fo); + for (uint32_t u = 0; u <= ram_last; u++) { + fprintf(fo, " %i : data = 8'h%02X;\n", (ram_start & 0xFFFF) + u, + ram[u]); } + fprintf(fo, + " default: data = 8'h01; // invalid instruction\n " + "endcase\nend\nendmodule\n"); + fclose(fo); + } #endif #endif - uint64_t ns1 = get_clock(); + uint64_t ns1 = get_clock(); - /* run program in emulator */ - pc = start; - reg[2] = ram_start + RAM_SIZE; - riscv_cpu_interp_x32(); + /* run program in emulator */ + pc = start; + reg[2] = ram_start + RAM_SIZE; + riscv_cpu_interp_x32(); - uint64_t ns2 = get_clock(); + uint64_t ns2 = get_clock(); - /* write signature */ - /* Check signature */ - if (signature_file) { - FILE *sf = fopen(signature_file, "r"); - if (sf == NULL) { - printf("Error opening file\n"); - return -1; - } - int size = end_signature - begin_signature; - char temp[50], ans[50]; - uint32_t tb = begin_signature; - int err = 0; - for (int i = 0; i < size / 4; i++) { - if (fgets(ans, 30, sf) == NULL) - break; - for (int j = 0; j < 4; j++) { - sprintf(temp + strlen(temp), "%02x", - ram[tb + 3 - j - ram_start]); - } - tb += 4; - if (strncmp(temp, ans, 8) != 0) { - printf("%s -----> %s\n", temp, ans); - err++; - } else { - printf("%s\n", temp); - } - memset(temp, '\0', 50); + /* write signature */ + /* Check signature */ + if (signature_file) { + FILE *sf = fopen(signature_file, "r"); + if (sf == NULL) { + printf("Error opening file\n"); + return -1; + } + int size = end_signature - begin_signature; + char temp[50], ans[50]; + uint32_t tb = begin_signature; + int err = 0; + for (int i = 0; i < size / 4; i++) { + if (fgets(ans, 30, sf) == NULL) + break; + for (int j = 0; j < 4; j++) { + sprintf(temp + strlen(temp), "%02x", + ram[tb + 3 - j - ram_start]); } - if (err == 0) { - printf("%s TEST PASSED\n", elf_file); + tb += 4; + if (strncmp(temp, ans, 8) != 0) { + printf("%s -----> %s\n", temp, ans); + err++; } else { - printf("%s TEST FAILED\n", elf_file); - printf("Number of failed signature : %d\n", err); + printf("%s\n", temp); } - fclose(sf); + memset(temp, '\0', 50); } - if (output_file) { - FILE *of = fopen(output_file, "w"); - int size = end_signature - begin_signature; - for (int i = 0; i < size / 4; i++) { - for (int j = 0; j < 4; j++) { - fprintf(of, "%02x", - ram[begin_signature + 3 - j - ram_start]); - } - begin_signature += 4; - fprintf(of, "\n"); + if (err == 0) { + printf("%s TEST PASSED\n", elf_file); + } else { + printf("%s TEST FAILED\n", elf_file); + printf("Number of failed signature : %d\n", err); + } + fclose(sf); + } + if (output_file) { + FILE *of = fopen(output_file, "w"); + int size = end_signature - begin_signature; + for (int i = 0; i < size / 4; i++) { + for (int j = 0; j < 4; j++) { + fprintf(of, "%02x", ram[begin_signature + 3 - j - ram_start]); } - fclose(of); + begin_signature += 4; + fprintf(of, "\n"); } + fclose(of); + } #ifdef DEBUG_EXTRA - dump_regs(); - print_stats(insn_counter); + dump_regs(); + print_stats(insn_counter); #endif #if 1 - printf("\n"); - printf(">>> Execution time: %llu ns\n", (long long unsigned) ns2 - ns1); - printf(">>> Instruction count: %llu (IPS=%llu)\n", - (long long unsigned) insn_counter, - (long long) insn_counter * 1000000000LL / (ns2 - ns1)); - printf(">>> Jumps: %llu (%2.2lf%%) - %llu forwards, %llu backwards\n", - (long long unsigned) jump_counter, - jump_counter * 100.0 / insn_counter, - (long long unsigned) forward_counter, - (long long unsigned) backward_counter); - printf(">>> Branching T=%llu (%2.2lf%%) F=%llu (%2.2lf%%)\n", - (long long unsigned) true_counter, - true_counter * 100.0 / (true_counter + false_counter), - (long long unsigned) false_counter, - false_counter * 100.0 / (true_counter + false_counter)); - printf("\n"); + printf("\n"); + printf(">>> Execution time: %llu ns\n", (long long unsigned) ns2 - ns1); + printf(">>> Instruction count: %llu (IPS=%llu)\n", + (long long unsigned) insn_counter, + (long long) insn_counter * 1000000000LL / (ns2 - ns1)); + printf(">>> Jumps: %llu (%2.2lf%%) - %llu forwards, %llu backwards\n", + (long long unsigned) jump_counter, + jump_counter * 100.0 / insn_counter, + (long long unsigned) forward_counter, + (long long unsigned) backward_counter); + printf(">>> Branching T=%llu (%2.2lf%%) F=%llu (%2.2lf%%)\n", + (long long unsigned) true_counter, + true_counter * 100.0 / (true_counter + false_counter), + (long long unsigned) false_counter, + false_counter * 100.0 / (true_counter + false_counter)); + printf("\n"); #endif - return 0; - } + return 0; +} From e34f0f44b558e8c7a94db9bfcffe1e3a482a485a Mon Sep 17 00:00:00 2001 From: "f74064054@mail.ncku.edu.tw" Date: Sun, 16 Feb 2020 15:32:22 +0800 Subject: [PATCH 15/19] Remove unnecessary comments --- CSRs.h | 71 ---------------------------------------------------------- 1 file changed, 71 deletions(-) diff --git a/CSRs.h b/CSRs.h index 72a9d8c..2a697ae 100644 --- a/CSRs.h +++ b/CSRs.h @@ -1,74 +1,3 @@ -/* Modified by Nober - 13-DEC-2019 - Define all CSR macro -*/ - -/* -RISCV emulator for the RV32I architecture -based on TinyEMU by Fabrice Bellard, see https://bellard.org/tinyemu/ -stripped down for RV32I only, all "gotos" removed, and fixed some bugs for the -compliance test by Frank Buss, 2018 - -Requires libelf-dev: - -sudo apt-get install libelf-dev - - -Compile it like this: - -gcc -O3 -Wall -lelf emu-rv32i.c -o emu-rv32i - - -It is compatible to Spike for the command line arguments, which means you can -run the compliance test from https://github.com/riscv/riscv-compliance like -this: - -make RISCV_TARGET=spike RISCV_DEVICE=rv32i TARGET_SIM=/full/path/emulator -variant - -It is also compatible with qemu32, as it is used for Zephyr. You can compile the -Zephyr examples for qemu like this: - -cd zephyr -source zephyr-env.sh -cd samples/synchronization -mkdir build && cd build -cmake -GNinja -DBOARD=qemu_riscv32 .. -ninja - -After this you can run it with the emulator like this: - -emu-rv32i zephyr/zephyr.elf - - -original copyright: -*/ - - - -/* - * RISCV emulator - * - * Copyright (c) 2016 Fabrice Bellard - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - #include From a3a72943f0961871d586364ba1747c0d7e32cf9e Mon Sep 17 00:00:00 2001 From: "f74064054@mail.ncku.edu.tw" Date: Sun, 16 Feb 2020 15:33:01 +0800 Subject: [PATCH 16/19] Modify the conformance test command line --- README.md | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/README.md b/README.md index a77f4ed..1a183c5 100644 --- a/README.md +++ b/README.md @@ -21,19 +21,15 @@ Passed RV32I compliance tests from https://github.com/riscv/riscv-compliance - Must install the [risc-v toolchain](https://xpack.github.io/riscv-none-embed-gcc/) ```shell $ git clone https://github.com/riscv/riscv-compliance -$ cd rv32emu -$ cp rv32emu ../riscv-compliance/riscv-target -$ cd ../riscv-compliance -$ make RISCV_PREFIX=riscv-none-embed- RISCV_DEVICE=rv32i TARGET_SIM=emu-rv32i variant +$ cd riscv-compliance +$ make RISCV_PREFIX=riscv-none-embed- RISCV_DEVICE=rv32i TARGET_SIM=/home/nober/git/adv_CO/rv32emu/emu-rv32i RISCV_TARGET=rv32emu TARGETDIR=/abs/to/riscv-target variant ``` - Run RV32IMC compliance tests. Assume `emu-rv32i` in `$PATH` environment variable. ```shell $ git clone https://github.com/riscv/riscv-compliance -$ cd rv32emu -$ cp rv32emu ../riscv-compliance/riscv-target # If having copied the makefile.include to riscv-compliance, it can be ignored. $ cd riscv-compliance -$ make RISCV_PREFIX=riscv-none-embed- RISCV_DEVICE=rv32imc TARGET_SIM=/abs/path/to/emu-rv32i variant +$ make RISCV_PREFIX=riscv-none-embed- RISCV_DEVICE=rv32imc TARGET_SIM=/home/nober/git/adv_CO/rv32emu/emu-rv32i RISCV_TARGET=rv32emu TARGETDIR=/abs/to/riscv-target variant ``` Compiling and running simple code: From d30d12b501f4e92fc6666106d9c6fdac131d0eba Mon Sep 17 00:00:00 2001 From: "f74064054@mail.ncku.edu.tw" Date: Sun, 16 Feb 2020 15:34:05 +0800 Subject: [PATCH 17/19] Put rv32emu folder into riscv-target --- {rv32emu => riscv-target/rv32emu}/compliance_io.h | 0 {rv32emu => riscv-target/rv32emu}/compliance_test.h | 0 {rv32emu => riscv-target/rv32emu}/device/rv32i/Makefile.include | 2 +- 3 files changed, 1 insertion(+), 1 deletion(-) rename {rv32emu => riscv-target/rv32emu}/compliance_io.h (100%) rename {rv32emu => riscv-target/rv32emu}/compliance_test.h (100%) rename {rv32emu => riscv-target/rv32emu}/device/rv32i/Makefile.include (89%) diff --git a/rv32emu/compliance_io.h b/riscv-target/rv32emu/compliance_io.h similarity index 100% rename from rv32emu/compliance_io.h rename to riscv-target/rv32emu/compliance_io.h diff --git a/rv32emu/compliance_test.h b/riscv-target/rv32emu/compliance_test.h similarity index 100% rename from rv32emu/compliance_test.h rename to riscv-target/rv32emu/compliance_test.h diff --git a/rv32emu/device/rv32i/Makefile.include b/riscv-target/rv32emu/device/rv32i/Makefile.include similarity index 89% rename from rv32emu/device/rv32i/Makefile.include rename to riscv-target/rv32emu/device/rv32i/Makefile.include index 136ec00..c272a47 100644 --- a/rv32emu/device/rv32i/Makefile.include +++ b/riscv-target/rv32emu/device/rv32i/Makefile.include @@ -4,7 +4,7 @@ else ARCH := Linux64 endif -TARGET_SIM ?= /home/nober/git/adv_CO/riscv-compliance/riscv-ovpsim/bin/Linux64/riscvOVPsim.exe +TARGET_SIM ?= TARGET_FLAGS ?= $(RISCV_TARGET_FLAGS) ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),) $(error Target simulator executable '$(TARGET_SIM)` not found) From a90eeec11caa6ea8aeb0028130b46f95e0f7e69d Mon Sep 17 00:00:00 2001 From: "f74064054@mail.ncku.edu.tw" Date: Sun, 16 Feb 2020 15:36:02 +0800 Subject: [PATCH 18/19] Slightly modify README.md --- README.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/README.md b/README.md index 1a183c5..e5d3426 100644 --- a/README.md +++ b/README.md @@ -22,14 +22,14 @@ Passed RV32I compliance tests from https://github.com/riscv/riscv-compliance ```shell $ git clone https://github.com/riscv/riscv-compliance $ cd riscv-compliance -$ make RISCV_PREFIX=riscv-none-embed- RISCV_DEVICE=rv32i TARGET_SIM=/home/nober/git/adv_CO/rv32emu/emu-rv32i RISCV_TARGET=rv32emu TARGETDIR=/abs/to/riscv-target variant +$ make RISCV_PREFIX=riscv-none-embed- RISCV_DEVICE=rv32i TARGET_SIM=/abs/to/emu-rv32i RISCV_TARGET=rv32emu TARGETDIR=/abs/to/riscv-target variant ``` - Run RV32IMC compliance tests. Assume `emu-rv32i` in `$PATH` environment variable. ```shell $ git clone https://github.com/riscv/riscv-compliance $ cd riscv-compliance -$ make RISCV_PREFIX=riscv-none-embed- RISCV_DEVICE=rv32imc TARGET_SIM=/home/nober/git/adv_CO/rv32emu/emu-rv32i RISCV_TARGET=rv32emu TARGETDIR=/abs/to/riscv-target variant +$ make RISCV_PREFIX=riscv-none-embed- RISCV_DEVICE=rv32imc TARGET_SIM=/abs/to/rv32emu/emu-rv32i RISCV_TARGET=rv32emu TARGETDIR=/abs/to/riscv-target variant ``` Compiling and running simple code: From 1d5aa673389950b452373e2faff6f1e1ae8afad8 Mon Sep 17 00:00:00 2001 From: "f74064054@mail.ncku.edu.tw" Date: Sun, 16 Feb 2020 20:00:18 +0800 Subject: [PATCH 19/19] Remove specific codes for RV32C --- emu-rv32i.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/emu-rv32i.c b/emu-rv32i.c index 08ef120..fc73577 100644 --- a/emu-rv32i.c +++ b/emu-rv32i.c @@ -160,10 +160,6 @@ int machine_running = TRUE; #define PRV_H 2 #define PRV_M 3 -/* Instruction state*/ -#define CINSN 1 -#define INSN 0 -unsigned char insn_type; /* CPU state */ uint32_t pc;