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AMDGPU: Move R600 test compatability hack
Instead of handling the r600 intrinsics on amdgcn, handle the amdgcn intrinsics on r600.
1 parent f319074 commit 7af7b96

28 files changed

+169
-285
lines changed

‎llvm/lib/Target/AMDGPU/R600ISelLowering.cpp

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -615,21 +615,27 @@ SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const
615615
return LowerImplicitParameter(DAG, VT, DL, 8);
616616

617617
case Intrinsic::r600_read_tgid_x:
618+
case Intrinsic::amdgcn_workgroup_id_x:
618619
return CreateLiveInRegisterRaw(DAG, &R600::R600_TReg32RegClass,
619620
R600::T1_X, VT);
620621
case Intrinsic::r600_read_tgid_y:
622+
case Intrinsic::amdgcn_workgroup_id_y:
621623
return CreateLiveInRegisterRaw(DAG, &R600::R600_TReg32RegClass,
622624
R600::T1_Y, VT);
623625
case Intrinsic::r600_read_tgid_z:
626+
case Intrinsic::amdgcn_workgroup_id_z:
624627
return CreateLiveInRegisterRaw(DAG, &R600::R600_TReg32RegClass,
625628
R600::T1_Z, VT);
626629
case Intrinsic::r600_read_tidig_x:
630+
case Intrinsic::amdgcn_workitem_id_x:
627631
return CreateLiveInRegisterRaw(DAG, &R600::R600_TReg32RegClass,
628632
R600::T0_X, VT);
629633
case Intrinsic::r600_read_tidig_y:
634+
case Intrinsic::amdgcn_workitem_id_y:
630635
return CreateLiveInRegisterRaw(DAG, &R600::R600_TReg32RegClass,
631636
R600::T0_Y, VT);
632637
case Intrinsic::r600_read_tidig_z:
638+
case Intrinsic::amdgcn_workitem_id_z:
633639
return CreateLiveInRegisterRaw(DAG, &R600::R600_TReg32RegClass,
634640
R600::T0_Z, VT);
635641

‎llvm/lib/Target/AMDGPU/SIISelLowering.cpp

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -5807,29 +5807,23 @@ SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
58075807
return lowerImplicitZextParam(DAG, Op, MVT::i16,
58085808
SI::KernelInputOffsets::LOCAL_SIZE_Z);
58095809
case Intrinsic::amdgcn_workgroup_id_x:
5810-
case Intrinsic::r600_read_tgid_x:
58115810
return getPreloadedValue(DAG, *MFI, VT,
58125811
AMDGPUFunctionArgInfo::WORKGROUP_ID_X);
58135812
case Intrinsic::amdgcn_workgroup_id_y:
5814-
case Intrinsic::r600_read_tgid_y:
58155813
return getPreloadedValue(DAG, *MFI, VT,
58165814
AMDGPUFunctionArgInfo::WORKGROUP_ID_Y);
58175815
case Intrinsic::amdgcn_workgroup_id_z:
5818-
case Intrinsic::r600_read_tgid_z:
58195816
return getPreloadedValue(DAG, *MFI, VT,
58205817
AMDGPUFunctionArgInfo::WORKGROUP_ID_Z);
58215818
case Intrinsic::amdgcn_workitem_id_x:
5822-
case Intrinsic::r600_read_tidig_x:
58235819
return loadInputValue(DAG, &AMDGPU::VGPR_32RegClass, MVT::i32,
58245820
SDLoc(DAG.getEntryNode()),
58255821
MFI->getArgInfo().WorkItemIDX);
58265822
case Intrinsic::amdgcn_workitem_id_y:
5827-
case Intrinsic::r600_read_tidig_y:
58285823
return loadInputValue(DAG, &AMDGPU::VGPR_32RegClass, MVT::i32,
58295824
SDLoc(DAG.getEntryNode()),
58305825
MFI->getArgInfo().WorkItemIDY);
58315826
case Intrinsic::amdgcn_workitem_id_z:
5832-
case Intrinsic::r600_read_tidig_z:
58335827
return loadInputValue(DAG, &AMDGPU::VGPR_32RegClass, MVT::i32,
58345828
SDLoc(DAG.getEntryNode()),
58355829
MFI->getArgInfo().WorkItemIDZ);

‎llvm/test/CodeGen/AMDGPU/amdgpu.work-item-intrinsics.deprecated.ll

Lines changed: 0 additions & 97 deletions
Original file line numberDiff line numberDiff line change
@@ -139,95 +139,6 @@ entry:
139139
ret void
140140
}
141141

142-
; Legacy use of r600 intrinsics by GCN
143-
144-
; The tgid values are stored in sgprs offset by the number of user
145-
; sgprs.
146-
147-
; FUNC-LABEL: {{^}}tgid_x_legacy:
148-
; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], s2{{$}}
149-
; GCN-NOHSA: buffer_store_dword [[VVAL]]
150-
151-
; GCN-NOHSA: COMPUTE_PGM_RSRC2:USER_SGPR: 2
152-
; GCN: COMPUTE_PGM_RSRC2:TGID_X_EN: 1
153-
; GCN: COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
154-
; GCN: COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
155-
; GCN: COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
156-
define amdgpu_kernel void @tgid_x_legacy(i32 addrspace(1)* %out) {
157-
entry:
158-
%0 = call i32 @llvm.r600.read.tgid.x() #0
159-
store i32 %0, i32 addrspace(1)* %out
160-
ret void
161-
}
162-
163-
; FUNC-LABEL: {{^}}tgid_y_legacy:
164-
; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], s3
165-
; GCN-NOHSA: buffer_store_dword [[VVAL]]
166-
167-
; GCN-NOHSA: COMPUTE_PGM_RSRC2:USER_SGPR: 2
168-
define amdgpu_kernel void @tgid_y_legacy(i32 addrspace(1)* %out) {
169-
entry:
170-
%0 = call i32 @llvm.r600.read.tgid.y() #0
171-
store i32 %0, i32 addrspace(1)* %out
172-
ret void
173-
}
174-
175-
; FUNC-LABEL: {{^}}tgid_z_legacy:
176-
; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], s3{{$}}
177-
; GCN-NOHSA: buffer_store_dword [[VVAL]]
178-
179-
; GCN-NOHSA: COMPUTE_PGM_RSRC2:USER_SGPR: 2
180-
; GCN: COMPUTE_PGM_RSRC2:TGID_X_EN: 1
181-
; GCN: COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
182-
; GCN: COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
183-
; GCN: COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
184-
define amdgpu_kernel void @tgid_z_legacy(i32 addrspace(1)* %out) {
185-
entry:
186-
%0 = call i32 @llvm.r600.read.tgid.z() #0
187-
store i32 %0, i32 addrspace(1)* %out
188-
ret void
189-
}
190-
191-
; GCN-NOHSA: .section .AMDGPU.config
192-
; GCN-NOHSA: .long 47180
193-
; GCN-NOHSA-NEXT: .long 132{{$}}
194-
195-
; FUNC-LABEL: {{^}}tidig_x_legacy:
196-
; GCN-NOHSA: buffer_store_dword v0
197-
define amdgpu_kernel void @tidig_x_legacy(i32 addrspace(1)* %out) {
198-
entry:
199-
%0 = call i32 @llvm.r600.read.tidig.x() #0
200-
store i32 %0, i32 addrspace(1)* %out
201-
ret void
202-
}
203-
204-
; GCN-NOHSA: .section .AMDGPU.config
205-
; GCN-NOHSA: .long 47180
206-
; GCN-NOHSA-NEXT: .long 2180{{$}}
207-
208-
; FUNC-LABEL: {{^}}tidig_y_legacy:
209-
210-
; GCN-NOHSA: buffer_store_dword v1
211-
define amdgpu_kernel void @tidig_y_legacy(i32 addrspace(1)* %out) {
212-
entry:
213-
%0 = call i32 @llvm.r600.read.tidig.y() #0
214-
store i32 %0, i32 addrspace(1)* %out
215-
ret void
216-
}
217-
218-
; GCN-NOHSA: .section .AMDGPU.config
219-
; GCN-NOHSA: .long 47180
220-
; GCN-NOHSA-NEXT: .long 4228{{$}}
221-
222-
; FUNC-LABEL: {{^}}tidig_z_legacy:
223-
; GCN-NOHSA: buffer_store_dword v2
224-
define amdgpu_kernel void @tidig_z_legacy(i32 addrspace(1)* %out) {
225-
entry:
226-
%0 = call i32 @llvm.r600.read.tidig.z() #0
227-
store i32 %0, i32 addrspace(1)* %out
228-
ret void
229-
}
230-
231142
declare i32 @llvm.r600.read.ngroups.x() #0
232143
declare i32 @llvm.r600.read.ngroups.y() #0
233144
declare i32 @llvm.r600.read.ngroups.z() #0
@@ -240,12 +151,4 @@ declare i32 @llvm.r600.read.local.size.x() #0
240151
declare i32 @llvm.r600.read.local.size.y() #0
241152
declare i32 @llvm.r600.read.local.size.z() #0
242153

243-
declare i32 @llvm.r600.read.tgid.x() #0
244-
declare i32 @llvm.r600.read.tgid.y() #0
245-
declare i32 @llvm.r600.read.tgid.z() #0
246-
247-
declare i32 @llvm.r600.read.tidig.x() #0
248-
declare i32 @llvm.r600.read.tidig.y() #0
249-
declare i32 @llvm.r600.read.tidig.z() #0
250-
251154
attributes #0 = { readnone }

‎llvm/test/CodeGen/AMDGPU/and.ll

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=SI -check-prefix=FUNC %s
33
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
44

5-
declare i32 @llvm.r600.read.tidig.x() #0
5+
declare i32 @llvm.amdgcn.workitem.id.x() #0
66

77
; FUNC-LABEL: {{^}}test2:
88
; EG: AND_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
@@ -96,7 +96,7 @@ define amdgpu_kernel void @s_and_multi_use_constant_i32_1(i32 addrspace(1)* %out
9696
; FUNC-LABEL: {{^}}v_and_i32_vgpr_vgpr:
9797
; SI: v_and_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
9898
define amdgpu_kernel void @v_and_i32_vgpr_vgpr(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr) {
99-
%tid = call i32 @llvm.r600.read.tidig.x() #0
99+
%tid = call i32 @llvm.amdgcn.workitem.id.x() #0
100100
%gep.a = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid
101101
%gep.b = getelementptr i32, i32 addrspace(1)* %bptr, i32 %tid
102102
%gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
@@ -112,7 +112,7 @@ define amdgpu_kernel void @v_and_i32_vgpr_vgpr(i32 addrspace(1)* %out, i32 addrs
112112
; SI-DAG: {{buffer|flat}}_load_dword [[VB:v[0-9]+]]
113113
; SI: v_and_b32_e32 v{{[0-9]+}}, [[SA]], [[VB]]
114114
define amdgpu_kernel void @v_and_i32_sgpr_vgpr(i32 addrspace(1)* %out, i32 %a, i32 addrspace(1)* %bptr) {
115-
%tid = call i32 @llvm.r600.read.tidig.x() #0
115+
%tid = call i32 @llvm.amdgcn.workitem.id.x() #0
116116
%gep.b = getelementptr i32, i32 addrspace(1)* %bptr, i32 %tid
117117
%gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
118118
%b = load i32, i32 addrspace(1)* %gep.b
@@ -126,7 +126,7 @@ define amdgpu_kernel void @v_and_i32_sgpr_vgpr(i32 addrspace(1)* %out, i32 %a, i
126126
; SI-DAG: {{buffer|flat}}_load_dword [[VB:v[0-9]+]]
127127
; SI: v_and_b32_e32 v{{[0-9]+}}, [[SA]], [[VB]]
128128
define amdgpu_kernel void @v_and_i32_vgpr_sgpr(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr, i32 %b) {
129-
%tid = call i32 @llvm.r600.read.tidig.x() #0
129+
%tid = call i32 @llvm.amdgcn.workitem.id.x() #0
130130
%gep.a = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid
131131
%gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
132132
%a = load i32, i32 addrspace(1)* %gep.a
@@ -138,7 +138,7 @@ define amdgpu_kernel void @v_and_i32_vgpr_sgpr(i32 addrspace(1)* %out, i32 addrs
138138
; FUNC-LABEL: {{^}}v_and_constant_i32
139139
; SI: v_and_b32_e32 v{{[0-9]+}}, 0x12d687, v{{[0-9]+}}
140140
define amdgpu_kernel void @v_and_constant_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr) {
141-
%tid = call i32 @llvm.r600.read.tidig.x() #0
141+
%tid = call i32 @llvm.amdgcn.workitem.id.x() #0
142142
%gep = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid
143143
%a = load i32, i32 addrspace(1)* %gep, align 4
144144
%and = and i32 %a, 1234567
@@ -149,7 +149,7 @@ define amdgpu_kernel void @v_and_constant_i32(i32 addrspace(1)* %out, i32 addrsp
149149
; FUNC-LABEL: {{^}}v_and_inline_imm_64_i32
150150
; SI: v_and_b32_e32 v{{[0-9]+}}, 64, v{{[0-9]+}}
151151
define amdgpu_kernel void @v_and_inline_imm_64_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr) {
152-
%tid = call i32 @llvm.r600.read.tidig.x() #0
152+
%tid = call i32 @llvm.amdgcn.workitem.id.x() #0
153153
%gep = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid
154154
%a = load i32, i32 addrspace(1)* %gep, align 4
155155
%and = and i32 %a, 64
@@ -160,7 +160,7 @@ define amdgpu_kernel void @v_and_inline_imm_64_i32(i32 addrspace(1)* %out, i32 a
160160
; FUNC-LABEL: {{^}}v_and_inline_imm_neg_16_i32
161161
; SI: v_and_b32_e32 v{{[0-9]+}}, -16, v{{[0-9]+}}
162162
define amdgpu_kernel void @v_and_inline_imm_neg_16_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr) {
163-
%tid = call i32 @llvm.r600.read.tidig.x() #0
163+
%tid = call i32 @llvm.amdgcn.workitem.id.x() #0
164164
%gep = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid
165165
%a = load i32, i32 addrspace(1)* %gep, align 4
166166
%and = and i32 %a, -16
@@ -251,7 +251,7 @@ define amdgpu_kernel void @s_and_multi_use_inline_imm_i64(i64 addrspace(1)* %out
251251
; SI: v_and_b32
252252
; SI: v_and_b32
253253
define amdgpu_kernel void @v_and_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) {
254-
%tid = call i32 @llvm.r600.read.tidig.x() #0
254+
%tid = call i32 @llvm.amdgcn.workitem.id.x() #0
255255
%gep.a = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid
256256
%a = load i64, i64 addrspace(1)* %gep.a, align 8
257257
%gep.b = getelementptr i64, i64 addrspace(1)* %bptr, i32 %tid
@@ -266,7 +266,7 @@ define amdgpu_kernel void @v_and_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %
266266
; SI-DAG: v_and_b32_e32 {{v[0-9]+}}, 0x11e, {{v[0-9]+}}
267267
; SI: buffer_store_dwordx2
268268
define amdgpu_kernel void @v_and_constant_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) {
269-
%tid = call i32 @llvm.r600.read.tidig.x() #0
269+
%tid = call i32 @llvm.amdgcn.workitem.id.x() #0
270270
%gep.a = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid
271271
%a = load i64, i64 addrspace(1)* %gep.a, align 8
272272
%and = and i64 %a, 1231231234567
@@ -322,7 +322,7 @@ define amdgpu_kernel void @v_and_multi_use_inline_imm_i64(i64 addrspace(1)* %out
322322
; SI-NOT: and
323323
; SI: buffer_store_dwordx2
324324
define amdgpu_kernel void @v_and_i64_32_bit_constant(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) {
325-
%tid = call i32 @llvm.r600.read.tidig.x() #0
325+
%tid = call i32 @llvm.amdgcn.workitem.id.x() #0
326326
%gep.a = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid
327327
%a = load i64, i64 addrspace(1)* %gep.a, align 8
328328
%and = and i64 %a, 1234567
@@ -337,7 +337,7 @@ define amdgpu_kernel void @v_and_i64_32_bit_constant(i64 addrspace(1)* %out, i64
337337
; SI-NOT: and
338338
; SI: buffer_store_dwordx2
339339
define amdgpu_kernel void @v_and_inline_imm_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) {
340-
%tid = call i32 @llvm.r600.read.tidig.x() #0
340+
%tid = call i32 @llvm.amdgcn.workitem.id.x() #0
341341
%gep.a = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid
342342
%a = load i64, i64 addrspace(1)* %gep.a, align 8
343343
%and = and i64 %a, 64
@@ -353,7 +353,7 @@ define amdgpu_kernel void @v_and_inline_imm_i64(i64 addrspace(1)* %out, i64 addr
353353
; SI-NOT: and
354354
; SI: buffer_store_dwordx2 v{{\[}}[[VAL_LO]]:[[VAL_HI]]{{\]}}
355355
define amdgpu_kernel void @v_and_inline_neg_imm_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) {
356-
%tid = call i32 @llvm.r600.read.tidig.x() #0
356+
%tid = call i32 @llvm.amdgcn.workitem.id.x() #0
357357
%gep.a = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid
358358
%a = load i64, i64 addrspace(1)* %gep.a, align 8
359359
%and = and i64 %a, -8

‎llvm/test/CodeGen/AMDGPU/ctlz.ll

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,7 @@ declare i64 @llvm.ctlz.i64(i64, i1) nounwind readnone
1515
declare <2 x i64> @llvm.ctlz.v2i64(<2 x i64>, i1) nounwind readnone
1616
declare <4 x i64> @llvm.ctlz.v4i64(<4 x i64>, i1) nounwind readnone
1717

18-
declare i32 @llvm.r600.read.tidig.x() nounwind readnone
18+
declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
1919

2020
define amdgpu_kernel void @s_ctlz_i32(i32 addrspace(1)* noalias %out, i32 %val) nounwind {
2121
; SI-LABEL: s_ctlz_i32:
@@ -120,7 +120,7 @@ define amdgpu_kernel void @v_ctlz_i32(i32 addrspace(1)* noalias %out, i32 addrsp
120120
; EG-NEXT: CNDE_INT T0.X, T0.X, literal.x, PV.W,
121121
; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,
122122
; EG-NEXT: 32(4.484155e-44), 2(2.802597e-45)
123-
%tid = call i32 @llvm.r600.read.tidig.x()
123+
%tid = call i32 @llvm.amdgcn.workitem.id.x()
124124
%in.gep = getelementptr i32, i32 addrspace(1)* %valptr, i32 %tid
125125
%val = load i32, i32 addrspace(1)* %in.gep, align 4
126126
%ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 false) nounwind readnone
@@ -195,7 +195,7 @@ define amdgpu_kernel void @v_ctlz_v2i32(<2 x i32> addrspace(1)* noalias %out, <2
195195
; EG-NEXT: CNDE_INT T0.X, T0.X, literal.x, PV.W,
196196
; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,
197197
; EG-NEXT: 32(4.484155e-44), 2(2.802597e-45)
198-
%tid = call i32 @llvm.r600.read.tidig.x()
198+
%tid = call i32 @llvm.amdgcn.workitem.id.x()
199199
%in.gep = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %valptr, i32 %tid
200200
%val = load <2 x i32>, <2 x i32> addrspace(1)* %in.gep, align 8
201201
%ctlz = call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %val, i1 false) nounwind readnone
@@ -288,7 +288,7 @@ define amdgpu_kernel void @v_ctlz_v4i32(<4 x i32> addrspace(1)* noalias %out, <4
288288
; EG-NEXT: CNDE_INT T0.X, T0.X, literal.x, PV.W,
289289
; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,
290290
; EG-NEXT: 32(4.484155e-44), 2(2.802597e-45)
291-
%tid = call i32 @llvm.r600.read.tidig.x()
291+
%tid = call i32 @llvm.amdgcn.workitem.id.x()
292292
%in.gep = getelementptr <4 x i32>, <4 x i32> addrspace(1)* %valptr, i32 %tid
293293
%val = load <4 x i32>, <4 x i32> addrspace(1)* %in.gep, align 16
294294
%ctlz = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %val, i1 false) nounwind readnone
@@ -576,7 +576,7 @@ define amdgpu_kernel void @v_ctlz_i64(i64 addrspace(1)* noalias %out, i64 addrsp
576576
; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, T0.W,
577577
; EG-NEXT: LSHR * T1.X, PV.W, literal.x,
578578
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
579-
%tid = call i32 @llvm.r600.read.tidig.x()
579+
%tid = call i32 @llvm.amdgcn.workitem.id.x()
580580
%in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
581581
%out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %tid
582582
%val = load i64, i64 addrspace(1)* %in.gep
@@ -663,7 +663,7 @@ define amdgpu_kernel void @v_ctlz_i64_trunc(i32 addrspace(1)* noalias %out, i64
663663
; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, PV.Z,
664664
; EG-NEXT: LSHR * T1.X, PV.W, literal.x,
665665
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
666-
%tid = call i32 @llvm.r600.read.tidig.x()
666+
%tid = call i32 @llvm.amdgcn.workitem.id.x()
667667
%in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
668668
%out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
669669
%val = load i64, i64 addrspace(1)* %in.gep
@@ -729,7 +729,7 @@ define amdgpu_kernel void @v_ctlz_i32_sel_eq_neg1(i32 addrspace(1)* noalias %out
729729
; EG-NEXT: CNDE_INT T0.X, T0.X, literal.x, PV.W,
730730
; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,
731731
; EG-NEXT: -1(nan), 2(2.802597e-45)
732-
%tid = call i32 @llvm.r600.read.tidig.x()
732+
%tid = call i32 @llvm.amdgcn.workitem.id.x()
733733
%in.gep = getelementptr i32, i32 addrspace(1)* %valptr, i32 %tid
734734
%val = load i32, i32 addrspace(1)* %in.gep
735735
%ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 false) nounwind readnone
@@ -795,7 +795,7 @@ define amdgpu_kernel void @v_ctlz_i32_sel_ne_neg1(i32 addrspace(1)* noalias %out
795795
; EG-NEXT: CNDE_INT T0.X, T0.X, literal.x, PV.W,
796796
; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,
797797
; EG-NEXT: -1(nan), 2(2.802597e-45)
798-
%tid = call i32 @llvm.r600.read.tidig.x()
798+
%tid = call i32 @llvm.amdgcn.workitem.id.x()
799799
%in.gep = getelementptr i32, i32 addrspace(1)* %valptr, i32 %tid
800800
%val = load i32, i32 addrspace(1)* %in.gep
801801
%ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 false) nounwind readnone
@@ -872,7 +872,7 @@ define amdgpu_kernel void @v_ctlz_i32_sel_eq_bitwidth(i32 addrspace(1)* noalias
872872
; EG-NEXT: CNDE_INT T0.X, PV.W, T0.W, literal.x,
873873
; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,
874874
; EG-NEXT: -1(nan), 2(2.802597e-45)
875-
%tid = call i32 @llvm.r600.read.tidig.x()
875+
%tid = call i32 @llvm.amdgcn.workitem.id.x()
876876
%in.gep = getelementptr i32, i32 addrspace(1)* %valptr, i32 %tid
877877
%val = load i32, i32 addrspace(1)* %in.gep
878878
%ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 false) nounwind readnone
@@ -948,7 +948,7 @@ define amdgpu_kernel void @v_ctlz_i32_sel_ne_bitwidth(i32 addrspace(1)* noalias
948948
; EG-NEXT: CNDE_INT T0.X, PV.W, literal.x, T0.W,
949949
; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,
950950
; EG-NEXT: -1(nan), 2(2.802597e-45)
951-
%tid = call i32 @llvm.r600.read.tidig.x()
951+
%tid = call i32 @llvm.amdgcn.workitem.id.x()
952952
%in.gep = getelementptr i32, i32 addrspace(1)* %valptr, i32 %tid
953953
%val = load i32, i32 addrspace(1)* %in.gep
954954
%ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 false) nounwind readnone
@@ -1017,7 +1017,7 @@ define amdgpu_kernel void @v_ctlz_i32_sel_ne_bitwidth(i32 addrspace(1)* noalias
10171017
; EG-NEXT: MOV * T0.Z, 0.0,
10181018
; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
10191019
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
1020-
%tid = call i32 @llvm.r600.read.tidig.x()
1020+
%tid = call i32 @llvm.amdgcn.workitem.id.x()
10211021
%valptr.gep = getelementptr i8, i8 addrspace(1)* %valptr, i32 %tid
10221022
%val = load i8, i8 addrspace(1)* %valptr.gep
10231023
%ctlz = call i8 @llvm.ctlz.i8(i8 %val, i1 false) nounwind readnone
@@ -1160,7 +1160,7 @@ define amdgpu_kernel void @v_ctlz_i7_sel_eq_neg1(i7 addrspace(1)* noalias %out,
11601160
; EG-NEXT: MOV * T0.Z, 0.0,
11611161
; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
11621162
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
1163-
%tid = call i32 @llvm.r600.read.tidig.x()
1163+
%tid = call i32 @llvm.amdgcn.workitem.id.x()
11641164
%valptr.gep = getelementptr i7, i7 addrspace(1)* %valptr, i32 %tid
11651165
%val = load i7, i7 addrspace(1)* %valptr.gep
11661166
%ctlz = call i7 @llvm.ctlz.i7(i7 %val, i1 false) nounwind readnone

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