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Try #148:
2 parents c49f50f + da50da0 commit dcf3270

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  • compiler/rustc_codegen_ssa/src

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compiler/rustc_codegen_ssa/src/sir.rs

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -120,10 +120,10 @@ impl SirFuncCx<'tcx> {
120120
instance: &Instance<'tcx>,
121121
mir: &'tcx mir::Body<'tcx>,
122122
) -> Self {
123-
let mut flags = 0;
123+
let mut flags = ykpack::BodyFlags::empty();
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for attr in tcx.get_attrs(instance.def_id()).iter() {
125125
if tcx.sess.check_name(attr, sym::do_not_trace) {
126-
flags |= ykpack::bodyflags::DO_NOT_TRACE;
126+
flags |= ykpack::BodyFlags::DO_NOT_TRACE;
127127
} else if tcx.sess.check_name(attr, sym::interp_step) {
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// Check various properties of the interp_step at compile time.
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if !tcx.upvars_mentioned(instance.def_id()).is_none() {
@@ -161,9 +161,9 @@ impl SirFuncCx<'tcx> {
161161
);
162162
}
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164-
flags |= ykpack::bodyflags::INTERP_STEP;
164+
flags |= ykpack::BodyFlags::INTERP_STEP;
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} else if tcx.sess.check_name(attr, sym::trace_debug) {
166-
flags |= ykpack::bodyflags::TRACE_DEBUG;
166+
flags |= ykpack::BodyFlags::TRACE_DEBUG;
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}
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}
169169

@@ -183,7 +183,7 @@ impl SirFuncCx<'tcx> {
183183

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let crate_name = tcx.crate_name(instance.def_id().krate).as_str();
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if crate_name == "core" || crate_name == "alloc" {
186-
flags |= ykpack::bodyflags::DO_NOT_TRACE;
186+
flags |= ykpack::BodyFlags::DO_NOT_TRACE;
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}
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let var_map: FxHashMap<mir::Local, ykpack::IPlace> = FxHashMap::default();
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