diff --git a/Documentation/devicetree/bindings/display/panel/visionox,g2647fb105.yaml b/Documentation/devicetree/bindings/display/panel/visionox,g2647fb105.yaml new file mode 100644 index 00000000000000..19170742cf5d1e --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/visionox,g2647fb105.yaml @@ -0,0 +1,78 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/visionox,g2647fb105.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Visionox G2647FB105 6.47" 1080x2340 MIPI-DSI Panel + +maintainers: + - Alexander Baransky + +description: + The Visionox G2647FB105 is a 6.47 inch 1080x2340 MIPI-DSI CMD mode OLED panel. + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + const: visionox,g2647fb105 + + reg: + maxItems: 1 + + vdd3p3-supply: + description: 3.3V source voltage rail + + vddio-supply: + description: I/O source voltage rail + + vsn-supply: + description: Negative source voltage rail + + vsp-supply: + description: Positive source voltage rail + + reset-gpios: true + port: true + +required: + - compatible + - reg + - vdd3p3-supply + - vddio-supply + - vsn-supply + - vsp-supply + - reset-gpios + - port + +additionalProperties: false + +examples: + - | + #include + dsi { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "visionox,g2647fb105"; + reg = <0>; + + vdd3p3-supply = <&vreg_l7c_3p0>; + vddio-supply = <&vreg_l13a_1p8>; + vsn-supply = <&vreg_ibb>; + vsp-supply = <&vreg_lab>; + + reset-gpios = <&pm6150l_gpios 9 GPIO_ACTIVE_LOW>; + + port { + panel_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/input/awinic,aw8695-haptics.yaml b/Documentation/devicetree/bindings/input/awinic,aw8695-haptics.yaml new file mode 100644 index 00000000000000..9f573daaba0e98 --- /dev/null +++ b/Documentation/devicetree/bindings/input/awinic,aw8695-haptics.yaml @@ -0,0 +1,133 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/input/awinic,aw8695-haptics.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Awinic AW8695 LRA Haptic Driver + +maintainers: + - Luca Weiss + +properties: + compatible: + const: awinic,aw8695 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + description: GPIO connected to INTN pin (edge falling) + + reset-gpios: + maxItems: 1 + description: GPIO connected to RSTN pin (active high) + + awinic,f0-preset: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Default value for the f0 of LRA + + awinic,f0-coefficient: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Coefficient between actual f0 and the value in the registers + + awinic,f0-calibration-percent: + maxItems: 1 + description: Limit of f0 deviation from awinic,f0-preset + + awinic,drive-level: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Level of drive waveform in normal driving + + awinic,f0-detection-play-time: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Drive waveform play times in the first period in the f0 detection + + awinic,f0-detection-wait-time: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Waveform wait times in the f0 detection + + awinic,f0-detection-repeat: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Repeat times in the f0 detection + + awinic,f0-detection-trace: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Drive waveform play times in the second period and later in the f0 detection + + awinic,boost-debug: + $ref: /schemas/types.yaml#/definitions/uint8-array + minItems: 3 + maxItems: 3 + description: Values for BSTDBG1-3 registers + + awinic,tset: + $ref: /schemas/types.yaml#/definitions/uint8 + description: Value for TSET register + + awinic,r-spare: + $ref: /schemas/types.yaml#/definitions/uint8 + description: Value for R_SPARE register + + awinic,bemf-upper-threshold: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Back EMF (electromotive force) upper threshold + + awinic,bemf-lower-threshold: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Back EMF (electromotive force) lower threshold + +required: + - compatible + - reg + - interrupts + - reset-gpios + - awinic,f0-preset + - awinic,f0-coefficient + - awinic,f0-calibration-percent + - awinic,drive-level + - awinic,f0-detection-play-time + - awinic,f0-detection-wait-time + - awinic,f0-detection-repeat + - awinic,f0-detection-trace + - awinic,boost-debug + - awinic,tset + - awinic,r-spare + - awinic,bemf-upper-threshold + - awinic,bemf-lower-threshold + +additionalProperties: false + +examples: + - | + #include + #include + i2c { + #address-cells = <1>; + #size-cells = <0>; + + haptics@5a { + compatible = "awinic,aw8695"; + reg = <0x5a>; + interrupts-extended = <&tlmm 85 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&tlmm 90 GPIO_ACTIVE_HIGH>; + + awinic,f0-preset = <2350>; + awinic,f0-coefficient = <260>; + awinic,f0-calibration-percent = <7>; + awinic,drive-level = <125>; + + awinic,f0-detection-play-time = <5>; + awinic,f0-detection-wait-time = <3>; + awinic,f0-detection-repeat = <2>; + awinic,f0-detection-trace = <15>; + + awinic,boost-debug = /bits/ 8 <0x30 0xeb 0xd4>; + awinic,tset = /bits/ 8 <0x12>; + awinic,r-spare = /bits/ 8 <0x68>; + + awinic,bemf-upper-threshold = <4104>; + awinic,bemf-lower-threshold = <1016>; + }; + }; diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 6ca8db4b8afe30..19c74539b785f1 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -243,6 +243,17 @@ dtb-$(CONFIG_ARCH_QCOM) += sm6350-sony-xperia-lena-pdx213.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6375-sony-xperia-murray-pdx225.dtb dtb-$(CONFIG_ARCH_QCOM) += sm7125-xiaomi-curtana.dtb dtb-$(CONFIG_ARCH_QCOM) += sm7125-xiaomi-joyeuse.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm7150-google-sunfish.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm7150-samsung-a715f.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm7150-xiaomi-courbet.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm7150-xiaomi-davinci.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm7150-xiaomi-phoenix.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm7150-xiaomi-surya-huaxing.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm7150-xiaomi-surya-tianma.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm7150-xiaomi-sweet.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm7150-xiaomi-sweet_k6a.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm7150-xiaomi-toco.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm7150-xiaomi-tucana.dtb dtb-$(CONFIG_ARCH_QCOM) += sm7225-fairphone-fp4.dtb dtb-$(CONFIG_ARCH_QCOM) += sm7325-nothing-spacewar.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8150-hdk.dtb diff --git a/arch/arm64/boot/dts/qcom/pm6150.dtsi b/arch/arm64/boot/dts/qcom/pm6150.dtsi index 59524609fb1e8e..0ef02123209a86 100644 --- a/arch/arm64/boot/dts/qcom/pm6150.dtsi +++ b/arch/arm64/boot/dts/qcom/pm6150.dtsi @@ -130,6 +130,22 @@ reg = ; label = "die_temp"; }; + + bat_therm@4a { + reg = ; + label = "bat_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + bat_id@4b { + reg = ; + label = "bat_id"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; }; pm6150_adc_tm: adc-tm@3500 { @@ -142,6 +158,20 @@ status = "disabled"; }; + pm6150_qgauge: qgauge@4800 { + compatible = "qcom,pm6150-qg"; + reg = <0x4800>; + + io-channels = <&pm6150_adc ADC5_BAT_THERM_100K_PU>, + <&pm6150_adc ADC5_BAT_ID_100K_PU>; + io-channel-names = "batt-therm", + "batt-id"; + + nvmem = <&pm6150_qg_sdam>; + + status = "disabled"; + }; + pm6150_rtc: rtc@6000 { compatible = "qcom,pm8941-rtc"; reg = <0x6000>, <0x6100>; @@ -150,6 +180,14 @@ status = "disabled"; }; + pm6150_qg_sdam: nvram@b600 { + compatible = "qcom,spmi-sdam"; + reg = <0xb600>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xb600 0x100>; + }; + pm6150_gpios: gpio@c000 { compatible = "qcom,pm6150-gpio", "qcom,spmi-gpio"; reg = <0xc000>; diff --git a/arch/arm64/boot/dts/qcom/sm7150-google-sunfish.dts b/arch/arm64/boot/dts/qcom/sm7150-google-sunfish.dts new file mode 100644 index 00000000000000..99044a32ec0b30 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm7150-google-sunfish.dts @@ -0,0 +1,1164 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * SM7150-AB Google Pixel 4a specific device tree + * + * Copyright (c) 2024, Danila Tikhonov + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "sm7150.dtsi" +#include "pm6150.dtsi" +#include "pm6150l.dtsi" + +/delete-node/ &mpss_mem; +/delete-node/ &venus_mem; +/delete-node/ &cdsp_mem; +/delete-node/ &adsp_mem; +/delete-node/ &wlan_msa_mem; +/delete-node/ &npu_mem; +/delete-node/ &ipa_fw_mem; +/delete-node/ &ipa_gsi_mem; +/delete-node/ &gpu_mem; + +/* + * Sunfish uses the SM7150-AB SoC. + * Limit CPU clock to 2.2 GHz + */ +&cpu6_opp14 { + status = "disabled"; +}; + +/ { + model = "Google Pixel 4a"; + compatible = "google,sunfish", "qcom,sm7150"; + chassis-type = "handset"; + + qcom,msm-id = ; + qcom,board-id = <0xe2805 0>; + + aliases { + bluetooth0 = &bluetooth; + hsuart0 = &uart3; + serial0 = &uart8; + wifi0 = &wifi; + }; + + battery: battery { + compatible = "simple-battery"; + + charge-full-design-microamp-hours = <3080000>; + voltage-min-design-microvolt = <3400000>; + voltage-max-design-microvolt = <4400000>; + }; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + stdout-path = "serial0:115200n8"; + bootargs = "earlycon console=tty0 PMOS_NOSPLASH"; + + framebuffer@9c000000 { + compatible = "simple-framebuffer"; + reg = <0x0 0x9c000000 0x0 (1080 * 2340 * 4)>; + width = <1080>; + height = <2340>; + stride = <(1080 * 4)>; + format = "a8r8g8b8"; + + display = <&panel>; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>; + }; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&vol_up_n>; + + key-volume-up { + label = "Volume Up"; + linux,code = ; + gpios = <&pm6150l_gpios 2 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + }; + }; + + vreg_ibb: regulator-ibb { + compatible = "regulator-fixed"; + regulator-name = "ibb"; + regulator-min-microvolt = <6000000>; + regulator-max-microvolt = <6000000>; + }; + + vreg_lab: regulator-lab { + compatible = "regulator-fixed"; + regulator-name = "lab"; + regulator-min-microvolt = <6100000>; + regulator-max-microvolt = <6100000>; + }; + + reserved-memory { + mpss_mem: memory@8b000000 { + reg = <0x0 0x8b000000 0x0 0x9800000>; + no-map; + }; + + venus_mem: memory@94800000 { + reg = <0x0 0x94800000 0x0 0x500000>; + no-map; + }; + + cdsp_mem: memory@94d00000 { + reg = <0x0 0x94d00000 0x0 0x1e00000>; + no-map; + }; + + adsp_mem: memory@96b00000 { + reg = <0x00 0x96b00000 0x00 0x2200000>; + no-map; + }; + + wlan_msa_mem: memory@98d00000 { + reg = <0x0 0x98d00000 0x0 0x200000>; + no-map; + }; + + npu_mem: memory@98f00000 { + reg = <0x0 0x98f00000 0x0 0x80000>; + no-map; + }; + + ipa_fw_mem: memory@98f80000 { + reg = <0x0 0x98f80000 0x0 0x10000>; + no-map; + }; + + ipa_gsi_mem: memory@98f90000 { + reg = <0x0 0x98f90000 0x0 0x5000>; + no-map; + }; + + gpu_mem: memory@98f95000 { + reg = <0x0 0x98f95000 0x0 0x2000>; + no-map; + }; + + framebuffer_region@9c000000 { + reg = <0x0 0x9c000000 0x0 (1080 * 2340 * 4)>; + no-map; + }; + + ramoops@a481f000 { + compatible = "ramoops"; + reg = <0x0 0xa481f000 0x0 0x400000>; + + record-size = <0x40000>; + pmsg-size = <0x200000>; + console-size = <0x100000>; + }; + + rmtfs_mem: rmtfs@fde01000 { + compatible = "qcom,rmtfs-mem"; + reg = <0 0xfde01000 0 0x600000>; + no-map; + + qcom,client-id = <1>; + qcom,vmid = ; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + }; + + // S3A is really mx.lvl but it's there for supply map completeness sake. + vreg_s3a_0p8: smpa3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vreg_s3a_0p8"; + + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-always-on; + vin-supply = <&vph_pwr>; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm6150-rpmh-regulators"; + qcom,pmic-id = "a"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + + vdd-l1-supply = <&vreg_s8c_1p2>; + vdd-l2-l3-supply = <&vreg_s4a_1p1>; + vdd-l4-l7-l8-supply = <&vreg_s4a_1p1>; + vdd-l5-l16-l17-l18-l19-supply = <&vreg_bob>; + vdd-l6-supply = <&vreg_s8c_1p2>; + vdd-l9-supply = <&vreg_s3a_0p8>; + vdd-l10-l14-l15-supply = <&vreg_s5a_2p0>; + vdd-l11-l12-l13-supply = <&vreg_s5a_2p0>; + + /* + * S1, S4, S5 are unused. + * S2-S3 and L7-L8 are ARCs: + * S2 - gfx.lvl, + * S3 - mx.lvl, + * L7 - lmx.lvl, + * L8 - lcx.lvl. + */ + + vreg_s4a_1p1: smps4 { + regulator-min-microvolt = <824000>; + regulator-max-microvolt = <1120000>; + regulator-initial-mode = ; + }; + + vreg_s5a_2p0: smps5 { + regulator-min-microvolt = <1744000>; + regulator-max-microvolt = <2040000>; + regulator-initial-mode = ; + }; + + vreg_l1a_1p2: ldo1 { + regulator-min-microvolt = <1096000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l2a_1p0: ldo2 { + regulator-min-microvolt = <944000>; + regulator-max-microvolt = <1056000>; + regulator-initial-mode = ; + }; + + vdda_pll_cc_ebi01: + vreg_l3a_1p0: ldo3 { + regulator-min-microvolt = <968000>; + regulator-max-microvolt = <1064000>; + regulator-initial-mode = ; + }; + + vdd_qlink_lv: + vdd_qlink_lv_ck: + vdd_usb_hs_core: + vdda_mipi_csi0_0p9: + vdda_mipi_csi1_0p9: + vdda_mipi_csi2_0p9: + vdda_mipi_csi3_0p9: + vdda_mipi_dsi0_pll: + vdda_qrefs_0p9: + vdda_ufs_core: + vdda_usb_ss_dp_core: + vreg_l4a_0p88: ldo4 { + regulator-min-microvolt = <824000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l5a_2p7: ldo5 { + regulator-min-microvolt = <2600000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + + vreg_l6a_1p2: ldo6 { + regulator-min-microvolt = <1096000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vdd_wcss_cx: + vreg_l9a_0p8: ldo9 { + regulator-min-microvolt = <624000>; + regulator-max-microvolt = <760000>; + regulator-initial-mode = ; + }; + + vddpx_3: + vreg_l10a_1p8: ldo10 { + regulator-min-microvolt = <1720000>; + regulator-max-microvolt = <1832000>; + regulator-initial-mode = ; + }; + + vdd_qfprom: + vdda_apc1_cs_1p8: + vdda_qrefs_1p8: + vdda_usb_hs_1p8: + vddpx_11: + vreg_l11a_1p8: ldo11 { + regulator-min-microvolt = <1696000>; + regulator-max-microvolt = <1984000>; + regulator-initial-mode = ; + }; + + vreg_l12a_1p8: ldo12 { + regulator-min-microvolt = <1696000>; + regulator-max-microvolt = <1952000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l13a_1p8: ldo13 { + regulator-min-microvolt = <1696000>; + regulator-max-microvolt = <1904000>; + regulator-initial-mode = ; + }; + + vreg_l14a_1p8: ldo14 { + regulator-min-microvolt = <1720000>; + regulator-max-microvolt = <1856000>; + regulator-initial-mode = ; + }; + + vreg_l15a_1p8: ldo15 { + regulator-min-microvolt = <1696000>; + regulator-max-microvolt = <1904000>; + regulator-initial-mode = ; + }; + + vreg_l16a_2p8: ldo16 { + regulator-min-microvolt = <2424000>; + regulator-max-microvolt = <2976000>; + regulator-initial-mode = ; + }; + + vdda_usb_hs_3p1: + vreg_l17a_3p1: ldo17 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3232000>; + regulator-initial-mode = ; + }; + + vreg_l19a_2p85: ldo19 { + regulator-min-microvolt = <2944000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; + + regulators-1 { + compatible = "qcom,pm6150l-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + + /* + * There should be: + * vdd-l1-l8-supply = <&vreg_s5a_2p0>; + * But pm7150l doesn't have access to S5A. + */ + vdd-l2-l3-supply = <&vreg_s8c_1p2>; + vdd-l4-l5-l6-supply = <&vreg_bob>; + vdd-l7-l11-supply = <&vreg_bob>; + vdd-l9-l10-supply = <&vreg_bob>; + + vdd-bob-supply = <&vph_pwr>; + vdd-flash-supply = <&vreg_bob>; + vdd-rgb-supply = <&vreg_bob>; + + /* + * S4, S5 are unused. + * S2, S3, S7 are ARCs: + * S2-S3 - cx.lvl, + * S7 - mss.lvl. + */ + + vreg_s1c_1p13: smps1 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + // always-on not supported + vreg_s8c_1p2: smps8 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1730000>; + regulator-initial-mode = ; + //regulator-always-on; + }; + + vreg_l1c_1p8: ldo1 { + regulator-min-microvolt = <1616000>; + regulator-max-microvolt = <1984000>; + regulator-initial-mode = ; + }; + + vdd_wcss_adc_dac: + vreg_l2c_1p3: ldo2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1352000>; + regulator-initial-mode = ; + }; + + vdda_csi0_1p25: + vdda_csi1_1p25: + vdda_csi2_1p25: + vdda_csi3_1p25: + vdda_hv_ebi0: + vdda_mipi_dsi0_1p2: + vdda_ufs_1p2: + vdda_usb_ss_dp_1p2: + vddpx_10: + vreg_l3c_1p23: ldo3 { + regulator-min-microvolt = <1144000>; + regulator-max-microvolt = <1256000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vddpx_5: + vreg_l4c_1p8: ldo4 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <2950000>; + regulator-initial-mode = ; + }; + + vddpx_6: + vreg_l5c_1p8: ldo5 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <2950000>; + regulator-initial-mode = ; + }; + + vddpx_2: + vreg_l6c_3p0: ldo6 { + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = ; + }; + + vreg_l7c_3p0: ldo7 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = ; + }; + + vreg_l8c_1p8: ldo8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1900000>; + regulator-initial-mode = ; + }; + + vreg_l9c_3p1: ldo9 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = ; + }; + + vreg_l10c_3p3: ldo10 { + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = ; + }; + + vreg_l11c_3p3: ldo11 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <3400000>; + regulator-initial-mode = ; + }; + + vreg_bob: bob { + regulator-min-microvolt = <3296000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + regulator-allow-bypass; + }; + }; +}; + +&camss { + vdda-supply = <&vdda_csi0_1p25>; + status = "okay"; +}; + +&cci0 { + status = "okay"; +}; + +&cci1 { + status = "okay"; +}; + +&dispcc { + status = "okay"; +}; + +&gpi_dma0 { + status = "okay"; +}; + +&gpi_dma1 { + status = "okay"; +}; + +&gpu { + zap-shader { + firmware-name = "qcom/sm7150/sunfish/a615_zap.mbn"; + }; +}; + +&i2c2 { + status = "okay"; + clock-frequency = <400000>; + + st21nfc: nfc@8 { + compatible = "st,st21nfcb-i2c"; + reg = <0x8>; + + interrupt-parent = <&tlmm>; + interrupts = <37 IRQ_TYPE_NONE>; + reset-gpios = <&tlmm 67 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&nfc_default>; + pinctrl-1 = <&nfc_sleep>; + pinctrl-names = "default", "sleep"; + + ese-present; + uicc-present; + }; + + rt5514_i2c: codec@57 { + compatible = "realtek,rt5514"; + reg = <0x57>; + + //interrupt-parent = <&tlmm>; + //interrupts = <33 IRQ_TYPE_NONE>; + + reset-gpio = <&tlmm 33 0>; + pinctrl-0 = <&rt5514_i2c_reset>; + pinctrl-names = "default"; + }; +}; + +&i2c7 { + status = "okay"; + clock-frequency = <1000000>; + + /* st,fts (touchscreen) @ 49 */ +}; + +&i2c9 { + status= "okay"; + clock-frequency = <400000>; + + pac1934: power-monitor@10 { + compatible = "microchip,pac1934"; + reg = <0x10>; + + #address-cells = <1>; + #size-cells = <0>; + + /* FIXME (Add a trigger to the driver) */ + avdd-supply = <&vreg_l6c_3p0>; + + channel@1 { + reg = <0x1>; + shunt-resistor-micro-ohms = <10000>; + label = "VDDCX_WITH_NPU"; + }; + + channel@2 { + reg = <0x2>; + shunt-resistor-micro-ohms = <10000>; + label = "VDD_APC0"; + }; + + channel@3 { + reg = <0x3>; + shunt-resistor-micro-ohms = <10000>; + label = "VDD_APC1"; + }; + + channel@4 { + reg = <0x4>; + shunt-resistor-micro-ohms = <10000>; + label = "OLED"; + }; + }; + + cs35l41_l: speaker-amp@40 { /* EAR */ + compatible = "cirrus,cs35l41"; + reg = <0x40>; + interrupt-parent = <&tlmm>; + interrupts = <64 IRQ_TYPE_NONE>; + reset-gpios = <&pm6150l_gpios 8 GPIO_ACTIVE_HIGH>; + + cirrus,boost-peak-milliamp = <3700>; + cirrus,boost-ind-nanohenry = <1000>; + cirrus,boost-cap-microfarad = <15>; + cirrus,asp-sdout-hiz = <3>; + cirrus,gpio2-src-select = <5>; + cirrus,gpio2-output-enable; + + #sound-dai-cells = <1>; + }; + + cs35l41_r: speaker-amp@41 { /* SPK */ + compatible = "cirrus,cs35l41"; + reg = <0x41>; + interrupt-parent = <&tlmm>; + interrupts = <65 IRQ_TYPE_NONE>; + reset-gpios = <&pm6150l_gpios 11 GPIO_ACTIVE_HIGH>; + + cirrus,boost-peak-milliamp = <3700>; + cirrus,boost-ind-nanohenry = <1000>; + cirrus,boost-cap-microfarad = <15>; + cirrus,asp-sdout-hiz = <3>; + cirrus,gpio2-src-select = <5>; + cirrus,gpio2-output-enable; + + #sound-dai-cells = <1>; + }; + + fsa4480: switcher@43 { + compatible = "fcs,fsa4480"; + reg = <0x43>; + + interrupts-extended = <&tlmm 42 IRQ_TYPE_LEVEL_LOW>; + + vcc-supply = <&vreg_bob>; + + mode-switch; + orientation-switch; + + port { + fsa4480_sbu_mux: endpoint { + remote-endpoint = <&pm6150_typec_sbu_out>; + }; + }; + }; + + /* st,m24c08 (e2prom) @ 50 */ + /* ti,drv2624 (haptic) @ 5a */ + + slg51000: pmic@75 { + compatible = "dlg,slg51000"; + reg = <0x75>; + dlg,cs-gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>, + <&tlmm 6 GPIO_ACTIVE_HIGH>; + dlg,enable-gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>, + <&tlmm 5 GPIO_ACTIVE_HIGH>; + + regulators { + slg51000_a_ldo1: ldo1 { + regulator-name = "slg51000_a_ldo1"; + regulator-min-microvolt = <2250000>; + regulator-max-microvolt = <3300000>; + }; + + slg51000_a_ldo2: ldo2 { + regulator-name = "slg51000_a_ldo2"; + regulator-min-microvolt = <2250000>; + regulator-max-microvolt = <3300000>; + }; + + slg51000_a_ldo3: ldo3 { + regulator-name = "slg51000_a_ldo3"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3750000>; + }; + + slg51000_a_ldo4: ldo4 { + regulator-name = "slg51000_a_ldo4"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3750000>; + }; + + slg51000_a_ldo5: ldo5 { + regulator-name = "slg51000_a_ldo5"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1200000>; + }; + + slg51000_a_ldo6: ldo6 { + regulator-name = "slg51000_a_ldo6"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1200000>; + }; + + slg51000_a_ldo7: ldo7 { + regulator-name = "slg51000_a_ldo7"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3750000>; + }; + }; + }; +}; + +&ipa { + memory-region = <&ipa_fw_mem>; + firmware-name = "qcom/sm7150/sunfish/ipa_fws.mbn"; + status = "okay"; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { + vdda-supply = <&vdda_mipi_dsi0_1p2>; + status = "okay"; + + panel: panel@0 { + compatible = "samsung,ams581vf01"; + reg = <0>; + + vddio-supply = <&vreg_l13a_1p8>; + vdd3p3-supply = <&vreg_l7c_3p0>; + vsn-supply = <&vreg_ibb>; + vsp-supply = <&vreg_lab>; + + reset-gpios = <&pm6150l_gpios 9 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&panel_reset_pin &panel_te_pin>; + pinctrl-names = "default"; + + port { + panel_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + data-lanes = <0 1 2 3>; + remote-endpoint = <&panel_in>; + status = "okay"; +}; + +&mdss_dsi0_phy { + vdds-supply = <&vdda_mipi_dsi0_pll>; + status = "okay"; +}; + +&pm6150_qgauge { + monitored-battery = <&battery>; + status = "okay"; +}; + +&pm6150_resin { + linux,code = ; + status = "okay"; +}; + +&pm6150_rtc { + status = "okay"; +}; + +&pm6150_typec { + vdd-vbus-supply = <&pm6150_vbus>; + vdd-pdphy-supply = <&vdda_usb_hs_3p1>; + status = "okay"; + + connector { + compatible = "usb-c-connector"; + + power-role = "source"; + data-role = "dual"; + self-powered; + + source-pdos = ; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + pm6150_hs_in: endpoint { + remote-endpoint = <&usb_1_dwc3_hs>; + }; + }; + + /*port@1 { + reg = <1>; + pm6150_typec_mux_in: endpoint { + remote-endpoint = <&usb_1_qmpphy_out>; + }; + };*/ + + port@2 { + reg = <2>; + pm6150_typec_sbu_out: endpoint { + remote-endpoint = <&fsa4480_sbu_mux>; + }; + }; + }; + }; +}; + +&pm6150_vbus { + regulator-min-microamp = <500000>; + regulator-max-microamp = <3000000>; + status = "okay"; +}; + +&pm6150l_flash { + status = "okay"; + + led-1 { + function = LED_FUNCTION_FLASH; + color = ; + led-sources = <1>; + led-max-microamp = <150000>; + flash-max-microamp = <1000000>; + flash-max-timeout-us = <1280000>; + }; +}; + +&pm6150l_gpios { + vol_up_n: vol-up-n-state { + pins = "gpio2"; + function = PMIC_GPIO_FUNC_NORMAL; + input-enable; + bias-pull-up; + power-source = <0>; + }; + + panel_reset_pin: panel-reset-state { + pins = "gpio9"; + function = PMIC_GPIO_FUNC_FUNC1; + qcom,drive-strength = ; + bias-disable; + output-low; + power-source = <1>; + }; +}; + +&qfprom { + vcc-supply = <&vdd_qfprom>; +}; + +&qup_uart3_cts { + bias-pull-down; +}; + +&qup_uart3_rts { + drive-strength = <2>; + bias-disable; +}; + +&qup_uart3_tx { + drive-strength = <2>; + bias-disable; +}; + +&qup_uart3_rx { + bias-pull-up; +}; + +&qup_uart8_tx { + drive-strength = <2>; + bias-disable; +}; + +&qup_uart8_rx { + drive-strength = <2>; + bias-pull-up; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&q6afedai { + qi2s@20 { + reg = ; + qcom,sd-lines = <0>; + }; + + qi2s@21 { + reg = ; + qcom,sd-lines = <1>; + }; +}; + +&q6asmdai { + dai@0 { + reg = <0>; + }; + + dai@1 { + reg = <1>; + }; +}; + +&remoteproc_adsp { + firmware-name = "qcom/sm7150/sunfish/adsp.mbn"; + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/sm7150/sunfish/cdsp.mbn"; + status = "okay"; +}; + +&remoteproc_mpss { + firmware-name = "qcom/sm7150/sunfish/modem.mbn"; + status = "okay"; +}; + +&sound { + compatible = "qcom,sm8250-sndcard"; + pinctrl-0 = <&ter_mi2s_active>; + pinctrl-names = "default"; + model = "Google Pixel 4a"; + + mm1-dai-link { + link-name = "MultiMedia1"; + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>; + }; + }; + + i2s-dai-link { + link-name = "Speakers Playback"; + cpu { + sound-dai = <&q6afedai TERTIARY_MI2S_RX>; + }; + + platform { + sound-dai = <&q6routing>; + }; + + codec { + sound-dai = <&cs35l41_l 0>, <&cs35l41_r 1>; + }; + }; +}; + +&spi0 { + clock-frequency = <20000000>; + status = "okay"; + + rt5514_spi: codec@0 { + compatible = "realtek,rt5514"; + reg = <0>; + + interrupt-parent = <&tlmm>; + interrupts = <58 IRQ_TYPE_NONE>; + + pinctrl-0 = <&rt5514_spi_default>; + pinctrl-names = "default"; + }; +}; + +&spi1 { + clock-frequency = <8000000>; + status = "okay"; + + /* google,citadel @ 0 */ + /* st,st54j_se @ 1 */ +}; + +&tlmm { + gpio-reserved-ranges = <59 4>; + + panel_te_pin: panel-te-state { + pins = "gpio10"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-pull-down; + }; + + haptic_reset: haptic-reset-state { + pins = "gpio11"; + function = "gpio"; + drive-strength = <2>; + output-low; + bias-disable; + }; + + nfc_default: nfc-default-state { + pins = "gpio31", "gpio37", "gpio67", "gpio94"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + nfc_sleep: nfc-sleep-state { + pins = "gpio31", "gpio67", "gpio94"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + rt5514_i2c_reset: rt5514-reset-state { + pins = "gpio33"; + function = "gpio"; + drive-strength = <2>; + output-high; + }; + + rt5514_spi_default: rt5514-spi-default-state { + handshake-ack-pins { + pins = "gpio30"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + input-enable; + }; + + handshake-pins { + pins = "gpio57"; + function = "gpio"; + drive-strength = <2>; + output-low; + }; + + irq-pins { + pins = "gpio58"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + input-enable; + }; + }; + + qup_uart3_sleep: qup-uart3-sleep-state { + cts-pins { + pins = "gpio38"; + function = "gpio"; + bias-pull-down; + }; + + rts-pins { + pins = "gpio39"; + function = "gpio"; + bias-pull-down; + }; + + tx-pins { + pins = "gpio40"; + function = "gpio"; + bias-pull-up; + }; + + rx-pins { + pins = "gpio41"; + function = "gpio"; + bias-pull-up; + }; + }; +}; + +&uart3 { + /delete-property/interrupts; + interrupts-extended = <&intc GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, + <&tlmm 41 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-names = "default", "sleep"; + pinctrl-1 = <&qup_uart3_sleep>; + status = "okay"; + + bluetooth: bluetooth { + compatible = "qcom,wcn3990-bt"; + + vddio-supply = <&vreg_l10a_1p8>; + vddxo-supply = <&vreg_l1c_1p8>; + vddrf-supply = <&vdd_wcss_adc_dac>; + vddch0-supply = <&vreg_l10c_3p3>; + max-speed = <3200000>; + }; +}; + +&uart8 { + status = "okay"; +}; + +&ufs_mem_hc { + reset-gpios = <&tlmm 119 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l19a_2p85>; + vcc-max-microamp = <600000>; + vccq2-supply = <&vreg_l12a_1p8>; + vccq2-max-microamp = <600000>; + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vdda_ufs_core>; + vdda-pll-supply = <&vdda_ufs_1p2>; + status = "okay"; +}; + +&usb_1 { + qcom,select-utmi-as-pipe-clk; + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "otg"; + usb-role-switch; + maximum-speed = "high-speed"; +}; + +&usb_1_dwc3_hs { + remote-endpoint = <&pm6150_hs_in>; +}; + +&usb_1_hsphy { + vdd-supply = <&vdd_usb_hs_core>; + vdda-pll-supply = <&vdda_usb_hs_1p8>; + vdda-phy-dpdm-supply = <&vdda_usb_hs_3p1>; + status = "okay"; +}; + +&venus { + firmware-name = "qcom/sm7150/sunfish/venus.mbn"; + //status = "okay"; +}; + +&wifi { + vdd-0.8-cx-mx-supply = <&vdd_wcss_cx>; + vdd-1.8-xo-supply = <&vreg_l1c_1p8>; + vdd-1.3-rfa-supply = <&vdd_wcss_adc_dac>; + vdd-3.3-ch0-supply = <&vreg_l10c_3p3>; + vdd-3.3-ch1-supply = <&vreg_l11c_3p3>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/sm7150-samsung-a715f.dts b/arch/arm64/boot/dts/qcom/sm7150-samsung-a715f.dts new file mode 100644 index 00000000000000..21d9f370176f78 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm7150-samsung-a715f.dts @@ -0,0 +1,467 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023, Danila Tikhonov + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include + +#include "sm7150.dtsi" +#include "pm6150.dtsi" +#include "pm6150l.dtsi" + +/delete-node/ &camera_mem; +/delete-node/ &mpss_mem; +/delete-node/ &venus_mem; +/delete-node/ &cdsp_mem; +/delete-node/ &adsp_mem; +/delete-node/ &wlan_msa_mem; +/delete-node/ &npu_mem; +/delete-node/ &ipa_fw_mem; +/delete-node/ &ipa_gsi_mem; +/delete-node/ &gpu_mem; +/delete-node/ &sec_cdsp_mem; + +/* Increase the size */ +&tz_mem { + reg = <0x0 0x86200000 0x0 0x5600000>; +}; + +&qseecom_mem { + reg = <0x0 0x9e400000 0x0 0x2400000>; +}; + +/* Limit CPU clock to 2.2 GHz */ + &cpu6_opp14 { + status = "disabled"; +}; + +/ { + model = "Samsung A71"; + compatible = "samsung,a715f", "qcom,sm7150"; + chassis-type = "handset"; + + qcom,msm-id = ; + qcom,board-id = <34 0>, /* Rev0.0 */ + <34 1>, /* Rev0.1 */ + <34 2>, /* Rev0.2 */ + <34 3>, /* Rev0.3 */ + <34 4>, /* Rev0.4 */ + <34 5>, /* Rev0.5 */ + <34 6>, /* Rev0.6 */ + <34 7>; /* Rev0.7 */ + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + framebuffer@9c000000 { + compatible = "simple-framebuffer"; + reg = <0x0 0x9c000000 0x0 (1080 * 2400 * 4)>; + width = <1080>; + height = <2400>; + stride = <(1080 * 4)>; + format = "a8r8g8b8"; + clocks = <&gcc GCC_DISP_HF_AXI_CLK>; + }; + }; + + reserved-memory { + camera_mem: memory@8cb00000 { + reg = <0x0 0x8cb00000 0x0 0x500000>; + no-map; + }; + + mpss_mem: memory@8d000000 { + reg = <0x0 0x8d000000 0x0 0x8c00000>; + no-map; + }; + + venus_mem: memory@95c00000 { + reg = <0x0 0x95c00000 0x0 0x500000>; + no-map; + }; + + cdsp_mem: memory@96100000 { + reg = <0x0 0x96100000 0x0 0x1e00000>; + no-map; + }; + + adsp_mem: memory@95700000 { + reg = <0x0 0x97f00000 0x0 0x2800000>; + no-map; + }; + + wlan_msa_mem: memory@9a700000 { + reg = <0x0 0x9a700000 0x0 0x180000>; + no-map; + }; + + npu_mem: memory@97680000 { + reg = <0x0 0x9a880000 0x0 0x80000>; + no-map; + }; + + ipa_fw_mem: memory@9a900000 { + reg = <0x0 0x9a900000 0x0 0x10000>; + no-map; + }; + + ipa_gsi_mem: memory@9a910000 { + reg = <0x0 0x9a910000 0x0 0x5000>; + no-map; + }; + + gpu_mem: memory@9a915000 { + reg = <0x0 0x9a915000 0x0 0x2000>; + no-map; + }; + + framebuffer_region@9c000000 { + reg = <0x0 0x9c000000 0x0 (1080 * 2400 * 4)>; + no-map; + }; + + ramoops@a1300000 { + compatible = "ramoops"; + reg = <0x0 0xa1300000 0x0 0x100000>; + + record-size = <0x40000>; + pmsg-size = <0x40000>; + console-size = <0x40000>; + }; + + sec_cdsp_mem: memory@a4000000 { + reg = <0x0 0xa4000000 0x0 0xc00000>; + no-map; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm6150-rpmh-regulators"; + qcom,pmic-id = "a"; + + vreg_s4a_1p1: smps4 { + regulator-min-microvolt = <824000>; + regulator-max-microvolt = <1120000>; + }; + + vreg_s5a_2p0: smps5 { + regulator-min-microvolt = <1744000>; + regulator-max-microvolt = <2040000>; + }; + + vreg_l1a_1p2: ldo1 { + regulator-min-microvolt = <1096000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l2a_1p0: ldo2 { + regulator-min-microvolt = <944000>; + regulator-max-microvolt = <1056000>; + regulator-initial-mode = ; + }; + + vreg_l3a_1p0: ldo3 { + regulator-min-microvolt = <968000>; + regulator-max-microvolt = <1064000>; + regulator-initial-mode = ; + }; + + vreg_l4a_0p88: ldo4 { + regulator-min-microvolt = <824000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l5a_2p7: ldo5 { + regulator-min-microvolt = <2600000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + + vreg_l6a_1p2: ldo6 { + regulator-min-microvolt = <1096000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l9a_0p8: ldo9 { + regulator-min-microvolt = <624000>; + regulator-max-microvolt = <760000>; + regulator-initial-mode = ; + }; + + vreg_l10a_1p8: ldo10 { + regulator-min-microvolt = <1720000>; + regulator-max-microvolt = <1832000>; + regulator-initial-mode = ; + }; + + vreg_l11a_1p8: ldo11 { + regulator-min-microvolt = <1696000>; + regulator-max-microvolt = <1984000>; + regulator-initial-mode = ; + }; + + vreg_l12a_1p8: ldo12 { + regulator-min-microvolt = <1696000>; + regulator-max-microvolt = <1952000>; + regulator-initial-mode = ; + }; + + vreg_l13a_1p8: ldo13 { + regulator-min-microvolt = <1696000>; + regulator-max-microvolt = <1904000>; + regulator-initial-mode = ; + }; + + vreg_l14a_1p8: ldo14 { + regulator-min-microvolt = <1720000>; + regulator-max-microvolt = <1856000>; + regulator-initial-mode = ; + }; + + vreg_l15a_1p8: ldo15 { + regulator-min-microvolt = <1696000>; + regulator-max-microvolt = <1904000>; + regulator-initial-mode = ; + }; + + vreg_l16a_2p8: ldo16 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = ; + }; + + vreg_l17a_3p1: ldo17 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3232000>; + regulator-initial-mode = ; + }; + + vreg_l18a_2p8: ldo18 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + }; + + vreg_l19a_2p85: ldo19 { + regulator-min-microvolt = <2944000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = ; + }; + }; + + regulators-1 { + compatible = "qcom,pm6150l-rpmh-regulators"; + qcom,pmic-id = "c"; + + vreg_s1c_1p13: smps1 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; + }; + + vreg_s8c_1p35: smps8 { + regulator-min-microvolt = <1120000>; + regulator-max-microvolt = <1408000>; + }; + + vreg_l1c_1p8: ldo1 { + regulator-min-microvolt = <1616000>; + regulator-max-microvolt = <1984000>; + regulator-initial-mode = ; + }; + + vreg_l2c_1p3: ldo2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1352000>; + regulator-initial-mode = ; + }; + + vreg_l3c_1p23: ldo3 { + regulator-min-microvolt = <1144000>; + regulator-max-microvolt = <1256000>; + regulator-initial-mode = ; + }; + + vreg_l4c_1p8: ldo4 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <2950000>; + regulator-initial-mode = ; + }; + + vreg_l5c_1p8: ldo5 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <2950000>; + regulator-initial-mode = ; + }; + + vreg_l6c_3p0: ldo6 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <3100000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l7c_3p0: ldo7 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = ; + }; + + vreg_l8c_1p8: ldo8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1900000>; + regulator-initial-mode = ; + }; + + /* + * Downstream specifies a range of 2950-3312mV. + * Tighten the range to 2950-3100mV. + */ + vreg_l9c_3p1: ldo9 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <3100000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l10c_3p3: ldo10 { + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = ; + }; + + vreg_l11c_3p3: ldo11 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = ; + }; + + vreg_bob: bob { + regulator-min-microvolt = <3296000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + regulator-allow-bypass; + }; + }; +}; + +&sdhc_2 { + cd-gpios = <&tlmm 69 GPIO_ACTIVE_HIGH>; + + vmmc-supply = <&vreg_l9c_3p1>; + vqmmc-supply = <&vreg_l6c_3p0>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <0 4>, <59 4>; + + sdc2_on: sdc2-on-state { + clk-pins { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd-pins { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data-pins { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <10>; + }; + + sd-cd-pins { + pins = "gpio69"; + function = "gpio"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + sdc2_off: sdc1-off-state { + clk-pins { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd-pins { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data-pins { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <2>; + }; + + sd-cd-pins { + pins = "gpio69"; + function = "gpio"; + bias-pull-up; + drive-strength = <2>; + }; + }; +}; + +&ufs_mem_hc { + vcc-supply = <&vreg_l19a_2p85>; + vcc-max-microamp = <600000>; + vccq2-supply = <&vreg_l12a_1p8>; + vccq2-max-microamp = <600000>; + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l4a_0p88>; + vdda-pll-supply = <&vreg_l3c_1p23>; + vdda-phy-max-microamp = <62900>; + vdda-pll-max-microamp = <18300>; + status = "okay"; +}; + +&usb_1 { + qcom,select-utmi-as-pipe-clk; + status = "okay"; +}; + +&usb_1_dwc3 { + maximum-speed = "high-speed"; + dr_mode = "peripheral"; + status = "okay"; +}; + +&usb_1_hsphy { + vdd-supply = <&vreg_l4a_0p88>; + vdda-pll-supply = <&vreg_l11a_1p8>; + vdda-phy-dpdm-supply = <&vreg_l17a_3p1>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/sm7150-xiaomi-common.dtsi b/arch/arm64/boot/dts/qcom/sm7150-xiaomi-common.dtsi new file mode 100644 index 00000000000000..3edf1b5ccc7aba --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm7150-xiaomi-common.dtsi @@ -0,0 +1,891 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024, Danila Tikhonov + * Copyright (c) 2024, David Wronek + * Copyright (c) 2024, Jens Reidel + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "sm7150.dtsi" +#include "pm6150.dtsi" +#include "pm6150l.dtsi" + +/ { + chassis-type = "handset"; + + qcom,msm-id = ; + + aliases { + bluetooth0 = &bluetooth; + hsuart0 = &uart3; + serial0 = &uart8; + wifi0 = &wifi; + }; + + battery: battery { + compatible = "simple-battery"; + + voltage-min-design-microvolt = <3400000>; + voltage-max-design-microvolt = <4400000>; + }; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + stdout-path = "serial0:115200n8"; + bootargs = "earlycon console=ttyMSM0,115200"; + + framebuffer: framebuffer@9c000000 { + compatible = "simple-framebuffer"; + reg = <0x0 0x9c000000 0x0 (1080 * 2400 * 4)>; + width = <1080>; + height = <2400>; + stride = <(1080 * 4)>; + format = "a8r8g8b8"; + + display = <&panel>; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>; + }; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&vol_up_n>; + + key-volume-up { + label = "Volume Up"; + linux,code = ; + gpios = <&pm6150l_gpios 2 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + }; + }; + + reserved-memory { + cont_splash_mem: splash_region@9c000000 { + reg = <0x0 0x9c000000 0x0 (1080 * 2400 * 4)>; + no-map; + }; + + ramoops@9d800000 { + compatible = "ramoops"; + reg = <0x0 0x9d800000 0x0 0x400000>; + + record-size = <0x80000>; + pmsg-size = <0x200000>; + console-size = <0x100000>; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + }; + + // S3A is really mx.lvl but it's there for supply map completeness sake. + vreg_s3a_0p8: smpa3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vreg_s3a_0p8"; + + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-always-on; + vin-supply = <&vph_pwr>; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm6150-rpmh-regulators"; + qcom,pmic-id = "a"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + + vdd-l1-supply = <&vreg_s8c_1p35>; + vdd-l2-l3-supply = <&vreg_s4a_1p1>; + vdd-l4-l7-l8-supply = <&vreg_s4a_1p1>; + vdd-l5-l16-l17-l18-l19-supply = <&vreg_bob>; + vdd-l6-supply = <&vreg_s8c_1p35>; + vdd-l9-supply = <&vreg_s3a_0p8>; + vdd-l10-l14-l15-supply = <&vreg_s5a_2p0>; + vdd-l11-l12-l13-supply = <&vreg_s5a_2p0>; + + /* + * S1 are unused. + * S2-S3, L7-L8 are ARCs: + * S2 - gfx.lvl, + * S3 - mx.lvl, + * L7 - lmx.lvl, + * L8 - lcx.lvl. + */ + + vreg_s4a_1p1: smps4 { + regulator-min-microvolt = <824000>; + regulator-max-microvolt = <1120000>; + }; + + vreg_s5a_2p0: smps5 { + regulator-min-microvolt = <1744000>; + regulator-max-microvolt = <2040000>; + }; + + vreg_l1a_1p2: ldo1 { + regulator-min-microvolt = <1096000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l2a_1p0: ldo2 { + regulator-min-microvolt = <944000>; + regulator-max-microvolt = <1056000>; + regulator-initial-mode = ; + }; + + vdda_pll_cc_ebi01: + vreg_l3a_1p0: ldo3 { + regulator-min-microvolt = <968000>; + regulator-max-microvolt = <1064000>; + regulator-initial-mode = ; + }; + + vdd_qlink_lv: + vdd_qlink_lv_ck: + vdd_usb_hs_core: + vdda_mipi_csi0_0p9: + vdda_mipi_csi1_0p9: + vdda_mipi_csi2_0p9: + vdda_mipi_csi3_0p9: + vdda_mipi_dsi0_pll: + vdda_mipi_dsi1_pll: + vdda_qrefs_0p9: + vdda_ufs_core: + vdda_usb_ss_dp_core: + vreg_l4a_0p88: ldo4 { + regulator-min-microvolt = <824000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l5a_2p7: ldo5 { + regulator-min-microvolt = <2600000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + + vreg_l6a_1p2: ldo6 { + regulator-min-microvolt = <1096000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vdd_wcss_cx: + vreg_l9a_0p8: ldo9 { + regulator-min-microvolt = <624000>; + regulator-max-microvolt = <760000>; + regulator-initial-mode = ; + }; + + vddpx_3: + vreg_l10a_1p8: ldo10 { + regulator-min-microvolt = <1720000>; + regulator-max-microvolt = <1832000>; + regulator-initial-mode = ; + }; + + vdd_qfprom: + vdda_apc1_cs_1p8: + vdda_qrefs_1p8: + vdda_usb_hs_1p8: + vddpx_11: + vreg_l11a_1p8: ldo11 { + regulator-min-microvolt = <1696000>; + regulator-max-microvolt = <1984000>; + regulator-initial-mode = ; + }; + + vreg_l12a_1p8: ldo12 { + regulator-min-microvolt = <1696000>; + regulator-max-microvolt = <1952000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l13a_1p8: ldo13 { + regulator-min-microvolt = <1696000>; + regulator-max-microvolt = <1904000>; + regulator-initial-mode = ; + }; + + vreg_l14a_1p8: ldo14 { + regulator-min-microvolt = <1720000>; + regulator-max-microvolt = <1856000>; + regulator-initial-mode = ; + }; + + vreg_l15a_1p8: ldo15 { + regulator-min-microvolt = <1696000>; + regulator-max-microvolt = <1904000>; + regulator-initial-mode = ; + }; + + vreg_l16a_2p8: ldo16 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vdda_usb_hs_3p1: + vreg_l17a_3p1: ldo17 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3232000>; + regulator-initial-mode = ; + }; + + vreg_l18a_2p8: ldo18 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + }; + + vreg_l19a_2p85: ldo19 { + regulator-min-microvolt = <2944000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; + + regulators-1 { + compatible = "qcom,pm6150l-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + + /* + * There should be: + * vdd-l1-l8-supply = <&vreg_s5a_2p0>; + * But pm7150l doesn't have access to S5A. + */ + vdd-l2-l3-supply = <&vreg_s8c_1p35>; + vdd-l4-l5-l6-supply = <&vreg_bob>; + vdd-l7-l11-supply = <&vreg_bob>; + vdd-l9-l10-supply = <&vreg_bob>; + + vdd-bob-supply = <&vph_pwr>; + vdd-flash-supply = <&vreg_bob>; + vdd-rgb-supply = <&vreg_bob>; + + /* + * S4, S5 are unused. + * S2, S3, S7 are ARCs: + * S2-S3 - cx.lvl, + * S7 - mss.lvl. + */ + + vreg_s1c_1p13: smps1 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; + }; + + vreg_s8c_1p35: smps8 { + regulator-min-microvolt = <1120000>; + regulator-max-microvolt = <1408000>; + }; + + vreg_l1c_1p8: ldo1 { + regulator-min-microvolt = <1616000>; + regulator-max-microvolt = <1984000>; + regulator-initial-mode = ; + }; + + vdd_wcss_adc_dac: + vreg_l2c_1p3: ldo2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1352000>; + regulator-initial-mode = ; + }; + + vdda_csi0_1p25: + vdda_csi1_1p25: + vdda_csi2_1p25: + vdda_csi3_1p25: + vdda_hv_ebi0: + vdda_mipi_dsi0_1p2: + vdda_mipi_dsi1_1p2: + vdda_ufs_1p2: + vdda_usb_ss_dp_1p2: + vddpx_10: + vreg_l3c_1p23: ldo3 { + regulator-min-microvolt = <1144000>; + regulator-max-microvolt = <1256000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vddpx_5: + vreg_l4c_1p8: ldo4 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <2950000>; + regulator-initial-mode = ; + }; + + vddpx_6: + vreg_l5c_1p8: ldo5 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <2950000>; + regulator-initial-mode = ; + }; + + vddpx_2: + vreg_l6c_3p0: ldo6 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <3100000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l7c_3p0: ldo7 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = ; + }; + + vreg_l8c_1p8: ldo8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1900000>; + regulator-initial-mode = ; + }; + + /* + * Downstream specifies a range of 2950-3312mV. + * Tighten the range to 2950-3100mV. + */ + vreg_l9c_3p1: ldo9 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <3100000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l10c_3p3: ldo10 { + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = ; + }; + + vreg_l11c_3p3: ldo11 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <3400000>; + regulator-initial-mode = ; + }; + + vreg_bob: bob { + regulator-min-microvolt = <3296000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + regulator-allow-bypass; + }; + }; +}; + +&camss { + vdda-supply = <&vdda_csi0_1p25>; + status = "okay"; +}; + +&cci0 { + status = "okay"; +}; + +&cci1 { + status = "okay"; +}; + +&dispcc { + status = "okay"; +}; + +&gpi_dma0 { + status = "okay"; +}; + +&gpi_dma1 { + status = "okay"; +}; + +&i2c2 { + clock-frequency = <100000>; + status = "okay"; + + nxp: nfc@28 { + compatible = "nxp,nxp-nci-i2c"; + + reg = <0x28>; + + interrupt-parent = <&tlmm>; + interrupts = <37 IRQ_TYPE_LEVEL_HIGH>; + + enable-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>; + firmware-gpios = <&tlmm 36 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&nfc_default>; + pinctrl-1 = <&nfc_sleep>; + }; +}; + +&ipa { + memory-region = <&ipa_fw_mem>; + status = "okay"; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { + vdda-supply = <&vdda_mipi_dsi0_1p2>; + status = "okay"; + + panel: panel@0 { + reg = <0>; + + vddio-supply = <&vreg_l13a_1p8>; + vdd3p3-supply = <&vreg_l18a_2p8>; + + reset-gpios = <&pm6150l_gpios 9 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&panel_reset_pin &panel_te_pin>; + pinctrl-names = "default"; + + port { + panel_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + data-lanes = <0 1 2 3>; + remote-endpoint = <&panel_in>; + status = "okay"; +}; + +&mdss_dsi0_phy { + vdds-supply = <&vdda_mipi_dsi0_pll>; + status = "okay"; +}; + +&pm6150_qgauge { + monitored-battery = <&battery>; + status = "okay"; +}; + +&pm6150_resin { + linux,code = ; + status = "okay"; +}; + +&pm6150_rtc { + status = "okay"; +}; + +&pm6150_typec { + vdd-vbus-supply = <&pm6150_vbus>; + vdd-pdphy-supply = <&vdda_usb_hs_3p1>; + status = "okay"; + + connector { + compatible = "usb-c-connector"; + + power-role = "source"; + data-role = "dual"; + self-powered; + + source-pdos = ; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + pm6150_role_switch_in: endpoint { + remote-endpoint = <&usb_1_dwc3_hs>; + }; + }; + }; + }; +}; + +&pm6150_vbus { + regulator-min-microamp = <500000>; + regulator-max-microamp = <3000000>; + status = "okay"; +}; + +&pm6150l_flash { + led-1 { + function = LED_FUNCTION_FLASH; + color = ; + led-sources = <1>; + led-max-microamp = <150000>; + flash-max-microamp = <1000000>; + flash-max-timeout-us = <1280000>; + }; +}; + +&pm6150l_gpios { + vol_up_n: vol-up-n-state { + pins = "gpio2"; + function = PMIC_GPIO_FUNC_NORMAL; + input-enable; + bias-pull-up; + power-source = <0>; + }; + + panel_reset_pin: panel-reset-state { + pins = "gpio9"; + function = PMIC_GPIO_FUNC_FUNC1; + qcom,drive-strength = ; + bias-disable; + output-low; + power-source = <1>; + }; +}; + +&pm6150l_lpg { + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_STATUS; + }; +}; + +&pm6150l_wled { + qcom,cabc; + qcom,cabc-sel = <1>; + qcom,num-strings = <3>; +}; + +&qfprom { + vcc-supply = <&vdd_qfprom>; +}; + +&qup_uart3_cts { + bias-pull-down; +}; + +&qup_uart3_rts { + drive-strength = <2>; + bias-disable; +}; + +&qup_uart3_tx { + drive-strength = <2>; + bias-disable; +}; + +&qup_uart3_rx { + bias-pull-up; +}; + +&qup_uart8_tx { + drive-strength = <2>; + bias-disable; +}; + +&qup_uart8_rx { + drive-strength = <2>; + bias-pull-up; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&remoteproc_adsp { + status = "okay"; +}; + +&remoteproc_cdsp { + status = "okay"; +}; + +&remoteproc_mpss { + status = "okay"; +}; + +&sdhc_2 { + cd-gpios = <&tlmm 69 GPIO_ACTIVE_HIGH>; + + vmmc-supply = <&vreg_l9c_3p1>; + vqmmc-supply = <&vreg_l6c_3p0>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; +}; + +&tlmm { + /* Reserved I/Os for NFC and FP */ + gpio-reserved-ranges = <0 4>, <59 4>; + + panel_esd_pin: panel-esd-state { + pins = "gpio4"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + ts_reset_active: ts-reset-active-state { + pins = "gpio8"; + function = "gpio"; + drive-strength = <16>; + bias-pull-up; + }; + + ts_reset_suspend: ts-reset-suspend-state { + pins = "gpio8"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-high; + }; + + ts_int_active: ts-int-active-state { + pins = "gpio9"; + function = "gpio"; + drive-strength = <16>; + bias-pull-up; + }; + + ts_int_suspend: ts-int-suspend-state { + pins = "gpio9"; + function = "gpio"; + drive-strength = <16>; + input-enable; + bias-disable; + }; + + panel_te_pin: panel-te-state { + pins = "gpio10"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-pull-down; + }; + + nfc_default: nfc-default-state { + pins = "gpio12", "gpio31", "gpio36"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + nfc_sleep: nfc-sleep-state { + pins = "gpio12", "gpio31", "gpio36"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + qup_uart3_sleep: qup-uart3-sleep-state { + cts-pins { + pins = "gpio38"; + function = "gpio"; + bias-pull-down; + }; + + rts-pins { + pins = "gpio39"; + function = "gpio"; + bias-pull-down; + }; + + tx-pins { + pins = "gpio40"; + function = "gpio"; + bias-pull-up; + }; + + rx-pins { + pins = "gpio41"; + function = "gpio"; + bias-pull-up; + }; + }; + + sdc2_on: sdc2-on-state { + clk-pins { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd-pins { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data-pins { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <10>; + }; + + sd-cd-pins { + pins = "gpio69"; + function = "gpio"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + sdc2_off: sdc1-off-state { + clk-pins { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd-pins { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data-pins { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <2>; + }; + + sd-cd-pins { + pins = "gpio69"; + function = "gpio"; + bias-pull-up; + drive-strength = <2>; + }; + }; +}; + +&uart3 { + /delete-property/interrupts; + interrupts-extended = <&intc GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, + <&tlmm 41 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-names = "default", "sleep"; + pinctrl-1 = <&qup_uart3_sleep>; + status = "okay"; + + bluetooth: bluetooth { + compatible = "qcom,wcn3990-bt"; + + vddio-supply = <&vreg_l10a_1p8>; + vddxo-supply = <&vreg_l1c_1p8>; + vddrf-supply = <&vdd_wcss_adc_dac>; + vddch0-supply = <&vreg_l10c_3p3>; + max-speed = <3200000>; + }; +}; + +&uart8 { + status = "okay"; +}; + +&ufs_mem_hc { + reset-gpios = <&tlmm 119 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l19a_2p85>; + vcc-max-microamp = <600000>; + vccq2-supply = <&vreg_l12a_1p8>; + vccq2-max-microamp = <600000>; + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vdda_ufs_core>; + vdda-pll-supply = <&vdda_ufs_1p2>; + status = "okay"; +}; + +&usb_1 { + qcom,select-utmi-as-pipe-clk; + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "otg"; + usb-role-switch; + maximum-speed = "high-speed"; +}; + +&usb_1_dwc3_hs { + remote-endpoint = <&pm6150_role_switch_in>; +}; + +&usb_1_hsphy { + vdd-supply = <&vdd_usb_hs_core>; + vdda-pll-supply = <&vdda_usb_hs_1p8>; + vdda-phy-dpdm-supply = <&vdda_usb_hs_3p1>; + status = "okay"; +}; + +&venus { + //status = "okay"; +}; + +&wifi { + vdd-0.8-cx-mx-supply = <&vdd_wcss_cx>; + vdd-1.8-xo-supply = <&vreg_l1c_1p8>; + vdd-1.3-rfa-supply = <&vdd_wcss_adc_dac>; + vdd-3.3-ch0-supply = <&vreg_l10c_3p3>; + vdd-3.3-ch1-supply = <&vreg_l11c_3p3>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/sm7150-xiaomi-courbet.dts b/arch/arm64/boot/dts/qcom/sm7150-xiaomi-courbet.dts new file mode 100644 index 00000000000000..4e63c105e46f87 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm7150-xiaomi-courbet.dts @@ -0,0 +1,144 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024, Danila Tikhonov + */ + +/dts-v1/; + +#include "sm7150-xiaomi-common.dtsi" + +/delete-node/ &adsp_mem; +/delete-node/ &wlan_msa_mem; +/delete-node/ &npu_mem; +/delete-node/ &ipa_fw_mem; +/delete-node/ &ipa_gsi_mem; +/delete-node/ &gpu_mem; + +/ { + model = "Xiaomi Mi 11 Lite 4G"; + compatible = "xiaomi,courbet", "qcom,sm7150"; + + qcom,board-id = <45 0>; + + reserved-memory { + adsp_mem: adsp@95700000 { + reg = <0x0 0x95700000 0x0 0x2600000>; + no-map; + }; + + wlan_msa_mem: wlan_msa@97d00000 { + reg = <0x0 0x97d00000 0x0 0x180000>; + no-map; + }; + + npu_mem: npu@97e80000 { + reg = <0x0 0x97e80000 0x0 0x80000>; + no-map; + }; + + ipa_fw_mem: ipa_fw@97f00000 { + reg = <0x0 0x97f00000 0x0 0x10000>; + no-map; + }; + + ipa_gsi_mem: ipa_gsi@97f10000 { + reg = <0x0 0x97f10000 0x0 0x5000>; + no-map; + }; + + gpu_mem: gpu@97f15000 { + reg = <0x0 0x97f15000 0x0 0x2000>; + no-map; + }; + + rmtfs_mem: rmtfs@fe201000 { + compatible = "qcom,rmtfs-mem"; + reg = <0 0xfe201000 0 0x200000>; + no-map; + + qcom,client-id = <1>; + qcom,vmid = ; + }; + }; +}; + +&gpu { + zap-shader { + firmware-name = "qcom/sm7150/courbet/a615_zap.mbn"; + }; +}; + +&ipa { + firmware-name = "qcom/sm7150/courbet/ipa_fws.mbn"; +}; + +&i2c7 { + clock-frequency = <100000>; + status = "okay"; + + /* qcom,pm8008 (pmic) @ 8 */ + /* qcom,pm8008 (pmic) @ 9 */ + /* tfa,tfa98xx (speaker amplifier) @ 34 */ + /* tfa,tfa98xx (speaker amplifier) @ 35 */ + /* st,fts (ts) @ 49 */ + /* goodix,gt9886 (ts) @ 5d */ +}; + +&i2c9 { + clock-frequency = <400000>; + status = "okay"; + + /* qcom,fsa4480 (usb switcher) @ 42 */ + /* awinic,aw8624 (haptic) @ 5a */ + /* ti,bq25968 (charger) @ 66 */ +}; + +&panel { + compatible = "mdss,k9a-36-02-0a-mp-dsc"; +}; + +&nfc_default { + pins = "gpio12", "gpio31", "gpio36", "gpio100"; +}; + +&nfc_sleep { + pins = "gpio12", "gpio31", "gpio36", "gpio100"; +}; + +&nxp { + enable-gpios = <&tlmm 100 GPIO_ACTIVE_HIGH>; +}; + +&remoteproc_adsp { + firmware-name = "qcom/sm7150/courbet/adsp.mbn"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/sm7150/courbet/cdsp.mbn"; +}; + +&remoteproc_mpss { + firmware-name = "qcom/sm7150/courbet/modem.mbn"; +}; + +&sdhc_2 { + status = "okay"; +}; + +&spi4 { + clock-frequency = <8000000>; + status = "okay"; + + /* xiaomi,spits (spi ts) @ 0 */ +}; + +&spi8 { + clock-frequency = <19200000>; + status = "okay"; + + /* ir-spi @ 0 */ +}; + +&venus { + firmware-name = "qcom/sm7150/courbet/venus.mbn"; +}; \ No newline at end of file diff --git a/arch/arm64/boot/dts/qcom/sm7150-xiaomi-davinci.dts b/arch/arm64/boot/dts/qcom/sm7150-xiaomi-davinci.dts new file mode 100644 index 00000000000000..1ee5426d737b89 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm7150-xiaomi-davinci.dts @@ -0,0 +1,576 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * SM7150-AA Xiaomi Mi 9T / Redmi K20 specific device tree + * + * Copyright (c) 2024, Danila Tikhonov + * Copyright (c) 2024, Jens Reidel + */ + +/dts-v1/; + +#include "sm7150-xiaomi-common.dtsi" + +/delete-node/ &wlan_msa_mem; +/delete-node/ &npu_mem; +/delete-node/ &ipa_fw_mem; +/delete-node/ &ipa_gsi_mem; +/delete-node/ &gpu_mem; +/delete-node/ &tz_mem; +/* The NFC reset-gpio is shared with the pinctrl of the amplifier. Disable NFC so that audio works. */ +/delete-node/ &nxp; + +&adsp_mem { + reg = <0x0 0x95700000 0x0 0x2600000>; +}; + +&cont_splash_mem { + reg = <0x0 0x9c000000 0x0 (1080 * 2340 * 4)>; +}; + +/ { + /* + * Xiaomi Mi 9T + * Xiaomi Redmi K20 + */ + model = "Xiaomi Mi 9T"; + compatible = "xiaomi,davinci", "qcom,sm7150"; + + qcom,board-id = <40 0>; + + vreg_ibb: regulator-ibb { + compatible = "regulator-fixed"; + regulator-name = "ibb"; + regulator-min-microvolt = <6000000>; + regulator-max-microvolt = <6000000>; + }; + + vreg_lab: regulator-lab { + compatible = "regulator-fixed"; + regulator-name = "lab"; + regulator-min-microvolt = <6000000>; + regulator-max-microvolt = <6000000>; + }; + + reserved-memory { + wlan_msa_mem: wlan_msa@97d00000 { + reg = <0x0 0x97d00000 0x0 0x180000>; + no-map; + }; + + npu_mem: npu@97e80000 { + reg = <0x0 0x97e80000 0x0 0x80000>; + no-map; + }; + + ipa_fw_mem: ipa_fw@97f00000 { + reg = <0x0 0x97f00000 0x0 0x10000>; + no-map; + }; + + ipa_gsi_mem: ipa_gsi@97f10000 { + reg = <0x0 0x97f10000 0x0 0x5000>; + no-map; + }; + + gpu_mem: gpu@97f15000 { + reg = <0x0 0x97f15000 0x0 0x2000>; + no-map; + }; + + rmtfs_mem: rmtfs@f2e01000 { + compatible = "qcom,rmtfs-mem"; + reg = <0 0xf2e01000 0 0x600000>; + no-map; + + qcom,client-id = <1>; + qcom,vmid = ; + }; + + tz_mem: trust-zone@86200000 { + reg = <0x0 0x86200000 0x0 0x4900000>; + no-map; + }; + }; +}; + +&battery { + charge-full-design-microamp-hours = <4000000>; +}; + +&camss { + ports { + port@2 { + csiphy2_ep: endpoint { + data-lanes = <0 1>; + remote-endpoint = <&s5k3l6xx_ep>; + }; + }; + + port@3 { + csiphy3_ep: endpoint { + data-lanes = <0 1>; + remote-endpoint = <&ov8856_ep>; + }; + }; + }; +}; + +&cci0 { + pinctrl-names = "default"; + pinctrl-0 = <&cci0_default>, + <&cci1_default>, + <&mclk3_active>; +}; + +&cci0_i2c1 { + camera@36 { + compatible = "ovti,ov8856"; + reg = <0x36>; + + reset-gpios = <&pm6150l_gpios 8 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&tele_active &tele_ldo_active>; + + clocks = <&camcc CAMCC_MCLK3_CLK>; + clock-names = "xvclk"; + clock-frequency = <19200000>; + + dovdd-supply = <&vreg_l16a_2p8>; + avdd-supply = <&vreg_l9c_3p1>; + dvdd-supply = <&vreg_s8c_1p35>; + + port { + ov8856_ep: endpoint { + link-frequencies = /bits/ 64 + <720000000 360000000>; + data-lanes = <1 2>; + remote-endpoint = <&csiphy3_ep>; + }; + }; + }; +}; + +&cci1 { + pinctrl-names = "default"; + pinctrl-0 = <&cci2_default>, + <&mclk1_active>; +}; + +&cci1_i2c0 { + camera@10 { + compatible = "samsung,s5k3l6xx"; + reg = <0x10>; + + rstn-gpios = <&tlmm 29 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&ultra_ldo_active &ultra_active>; + + clocks = <&camcc CAMCC_MCLK1_CLK>; + clock-names = "mclk"; + clock-frequency = <19200000>; + + vdda-supply = <&vreg_l9c_3p1>; + vddd-supply = <&vreg_s8c_1p35>; + vddio-supply = <&vreg_l16a_2p8>; + + port { + s5k3l6xx_ep: endpoint { + data-lanes = <1 2>; + remote-endpoint = <&csiphy2_ep>; + }; + }; + }; +}; + +&framebuffer { + reg = <0x0 0x9c000000 0x0 (1080 * 2340 * 4)>; + height = <2340>; +}; + +&gpu { + zap-shader { + firmware-name = "qcom/sm7150/davinci/a615_zap.mbn"; + }; +}; + +&i2c4 { + clock-frequency = <100000>; + status = "okay"; + + tfa9874: codec@34 { + compatible = "nxp,tfa9874"; + reg = <0x34>; + + reset-gpio = <&tlmm 12 GPIO_ACTIVE_HIGH>; + irq-gpio = <&tlmm 56 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&_reset_default &_int_default>; + + sound-name-prefix = "Speaker"; + #sound-dai-cells = <0>; + }; +}; + +&i2c7 { + clock-frequency = <100000>; + status = "okay"; + + touchscreen: goodix@5d { + compatible = "goodix,gt9889"; + reg = <0x5d>; + interrupt-parent = <&tlmm>; + interrupts = <9 0x2800>; + vtouch-supply = <&vreg_l6c_3p0>; /* 3v3 */ + vtouch-load = <600000>; + pinctrl-0 = <&ts_int_active &ts_reset_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-names = "default", "sleep"; + goodix,reset-gpio = <&tlmm 8 GPIO_ACTIVE_HIGH>; + goodix,irq-gpio = <&tlmm 9 0x2800>; + goodix,avdd-name = "vtouch"; + goodix,irq-flags = <2>; /* trigger falling;*/ + goodix,panel-max-x = <1079>; + goodix,panel-max-y = <2339>; + goodix,panel-max-w = <127>; + goodix,power-on-delay-us = <300000>; /* 300ms */ + goodix,power-off-delay-us = <5000>; /* 50ms */ + }; +}; + +&i2c9 { + clock-frequency = <100000>; + status = "okay"; + + /* asahi-kasei,akm09970 (magnetometer) @ 0c */ + /* qcom,smb1390 (charger) @ 10 */ +}; + +&ipa { + firmware-name = "qcom/sm7150/davinci/ipa_fws.mbn"; +}; + +&lpass_tlmm { + gpio-line-names = "SWR_TX_CLK", /* GPIO_0 */ + "SWR_TX_DATA1", + "SWR_TX_DATA2", + "SWR_RX_CLK", + "SWR_RX_DATA1", + "SWR_RX_DATA2", + "WCD9375_RST_N", + "NC", + "NC", + "NC", + "NC", /* GPIO_10 */ + "NC", + "BT_FM_SLIMBUS_DATA", + "BT_FM_SLIMBUS_CLK"; +}; + +&panel { + compatible = "samsung,ams639rq08"; // or visionox,g1639fp106 + + vsn-supply = <&vreg_ibb>; + vsp-supply = <&vreg_lab>; +}; + +&pm6150_gpios { + gpio-line-names = "NC", /* GPIO_1 */ + "NC", + "SMB_STAT", + "NC", + "SLB", + "NC", + "WCSS_PWR_REQ", + "NC", + "FORCED_USB_BOOT", + "NC"; /* GPIO_10 */ +}; + +&pm6150_vib { + status = "okay"; +}; + +&pm6150l_flash { + status = "okay"; + + led-2 { + function = LED_FUNCTION_FLASH; + color = ; + led-sources = <2>; + led-max-microamp = <150000>; + flash-max-microamp = <1000000>; + flash-max-timeout-us = <1280000>; + }; +}; + +&pm6150l_gpios { + gpio-line-names = "NC", /* GPIO_1 */ + "KYPD_VOLP_N", + "CAMW_LDO_EN", + "NC", + "NC", + "NC", + "SLB", + "CAMT_LDO_EN", + "LCD_RESET_N", + "MOTOR_STEP_CLK", /* GPIO_10 */ + "CAMT_VCM_2P8_EN", + "NC"; + + tele_ldo_active: tele-ldo-active { + pins = "gpio8"; + function = "normal"; + power-source = <0>; + output-low; + }; +}; + +&pm6150l_lpg { + status = "okay"; + + led@1 { + status = "disabled"; + }; + + led@2 { + reg = <2>; + color = ; + function = LED_FUNCTION_STATUS; + function-enumerator = <0>; + }; + + led@3 { + reg = <3>; + color = ; + function = LED_FUNCTION_STATUS; + function-enumerator = <1>; + }; +}; + +&q6afedai { + qi2s@16 { + reg = ; + qcom,sd-lines = <0>; + }; +}; + +&q6asmdai { + dai@0 { + reg = <0>; + }; +}; + +&remoteproc_adsp { + firmware-name = "qcom/sm7150/davinci/adsp.mbn"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/sm7150/davinci/cdsp.mbn"; +}; + +&remoteproc_mpss { + firmware-name = "qcom/sm7150/davinci/modem.mbn"; +}; + +&sound { + compatible = "qcom,sm8250-sndcard"; + pinctrl-0 = <&pri_mi2s_active &pri_mi2s_ws_active>; + pinctrl-names = "default"; + model = "Xiaomi Mi 9T"; + + mm1-dai-link { + link-name = "MultiMedia1"; + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>; + }; + }; + + speaker_playback_dai { + link-name = "Primary Spkr Playback"; + cpu { + sound-dai = <&q6afedai PRIMARY_MI2S_RX>; + }; + + platform { + sound-dai = <&q6routing>; + }; + + codec { + sound-dai = <&tfa9874>; + }; + }; +}; + +&tlmm { + gpio-line-names = "NFC_ESE_SPI_MISO", /* GPIO_0 */ + "NFC_ESE_SPI_MOSI", + "NFC_ESE_SPI_CLK", + "NFC_ESE_SPI_CS_N", + "NC", + "NC", + "TS_I2C_SDA", + "TS_I2C_SCL", + "TS_RESET_N", + "TS_INT_N", + "MDP_VSYNC_P", /* GPIO_10 */ + "NC", + "NFC_ENABLE_SPKR_PA_RST", + "CAMF_MCLK0", + "CAMU_MCLK1", + "CAMW_MCLK2", + "CAMT_MCLK3", + "CCI_I2C_SDA0", + "CCI_I2C_SCL0", + "CCI_I2C_SDA1", + "CCI_I2C_SCL1", /* GPIO_20 */ + "NC", + "FL_STROBE_TRIG", + "CAMF_RSTN", + "CAMT_RSTN", + "CAMU_RSTN", + "CAMW_RSTN", + "CCI_I2C_SDA2", + "CCI_I2C_SCL2", + "CAMU_LDO_EN", + "NC", /* GPIO_30 */ + "NFC_LABBCLK3_EN", + "ERR_INT_N", + "AUDIO_SWITCH_EN", + "NFC_I2C_SDA", + "NFC_I2C_SCL", + "NFC_DWL_REQ", + "NFC_IRQ", + "BT_UART_CTS", + "BT_UART_RFR", + "BT_UART_TX", /* GPIO_40 */ + "BT_UART_RX", + "LCD_ID_DET1", + "MOTOR_FAULT", + "BLSP2_UART_TX", + "BLSP2_UART_RX", + "APPS_I2C_SDA", + "APPS_I2C_SCL", + "FORCED_USB_BOOT", + "SPKR_I2S_BCK", + "SPKR_I2S_WS", /* GPIO_50 */ + "SPKR_I2S_DOUT", + "SPKR_I2S_DIN1", + "SPKR_I2C_SDA", + "SPKR_I2C_SCL", + "MOTOR_DIR", + "SPKR_INT", + "CAMF_LDO_EN", + "NC", + "FOD_SPI_MISO", + "FOD_SPI_MOSI", /* GPIO_60 */ + "FOD_SPI_SCLK", + "FOD_SPI_CS_N", + "FOD_LDO_EN", + "DIGITAL_HALL1_RSTN", + "FOD_RST", + "MOTOR_M1", + "SPKR_PA_RST_NFC_ENABLE", + "TS_TA", + "FOD_INT", + "RFFE6_CLK", /* GPIO_70 */ + "RFFE6_DATA", + "FM_GPIO", + "WLAN_SW_CTRL", + "GRFC_4", + "UIM2_DATA", + "UIM2_CLK", + "UIM2_RESET", + "UIM2_PRESENT", + "UIM1_DATA", + "UIM1_CLK", /* GPIO_80 */ + "UIM1_RESET", + "UIM1_PRESENT", + "GRFC_8", + "GRFC_9", + "WMSS_RESET_N", + "ACCEL_INT", + "GYRO_INT", + "MOTOR_SLEEP", + "ALS_INT_N", + "MOTOR_EN", /* GPIO_90 */ + "MOTOR_M0", + "RFFE4_CLK", + "DIGITAL_HALL1_INT", + "NC", + "GRFC_3", + "QLINK_REQUEST", + "QLINK_ENABLE", + "GRFC_2", + "NC", + "GRFC_1", /* GPIO_100 */ + "RFFE3_DATA", + "RFFE3_CLK", + "RFFE4_DATA", + "USB_PHY_PS", + "RFFE5_DATA", + "RFFE5_CLK", + "NC", + "WLAN_COEX_UART_TXD", + "WLAN_COEX_UART_RXD", + "NC", /* GPIO_110 */ + "NC", + "RFFE1_DATA", + "RFFE1_CLK"; + + amp_reset_default: amp-reset-default-state { + pins = "gpio12"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + bias-pull-down; + output-low; + }; + + mclk1_active: mclk1-active { + pins = "gpio14"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + + mclk3_active: mclk3-active { + pins = "gpio16"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + + tele_active: tele-active { + pins = "gpio24"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + ultra_active: ultra-active { + pins = "gpio25"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + ultra_ldo_active: ultra-ldo-active { + pins = "gpio29"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + amp_int_default: amp-int-default-state { + pins = "gpio56"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + input-enable; + }; +}; + +&venus { + firmware-name = "qcom/sm7150/davinci/venus.mbn"; +}; diff --git a/arch/arm64/boot/dts/qcom/sm7150-xiaomi-phoenix.dts b/arch/arm64/boot/dts/qcom/sm7150-xiaomi-phoenix.dts new file mode 100644 index 00000000000000..3e04c71c820a83 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm7150-xiaomi-phoenix.dts @@ -0,0 +1,282 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024, Danila Tikhonov + */ + +/dts-v1/; + +#include "sm7150-xiaomi-common.dtsi" + +/delete-node/ &adsp_mem; +/delete-node/ &wlan_msa_mem; +/delete-node/ &npu_mem; +/delete-node/ &ipa_fw_mem; +/delete-node/ &ipa_gsi_mem; +/delete-node/ &gpu_mem; + +/ { + /* + * Xiaomi POCO X2 + * Xiaomi Redmi K30 4G + */ + model = "Xiaomi POCO X2"; + compatible = "xiaomi,phoenix", "qcom,sm7150"; + + qcom,board-id = <43 0>; + + reserved-memory { + adsp_mem: adsp@95700000 { + reg = <0x0 0x95700000 0x0 0x2600000>; + no-map; + }; + + wlan_msa_mem: wlan_msa@97d00000 { + reg = <0x0 0x97d00000 0x0 0x180000>; + no-map; + }; + + npu_mem: npu@97e80000 { + reg = <0x0 0x97e80000 0x0 0x80000>; + no-map; + }; + + ipa_fw_mem: ipa_fw@97f00000 { + reg = <0x0 0x97f00000 0x0 0x10000>; + no-map; + }; + + ipa_gsi_mem: ipa_gsi@97f10000 { + reg = <0x0 0x97f10000 0x0 0x5000>; + no-map; + }; + + gpu_mem: gpu@97f15000 { + reg = <0x0 0x97f15000 0x0 0x2000>; + no-map; + }; + + rmtfs_mem: rmtfs@f2e01000 { + compatible = "qcom,rmtfs-mem"; + reg = <0 0xf2e01000 0 0x200000>; + no-map; + + qcom,client-id = <1>; + qcom,vmid = ; + }; + }; +}; + +&gpu { + zap-shader { + firmware-name = "qcom/sm7150/phoenix/a615_zap.mbn"; + }; +}; + +&ipa { + firmware-name = "qcom/sm7150/phoenix/ipa_fws.mbn"; +}; + +&lpass_tlmm { + gpio-line-names = "SWR_TX_CLK", /* GPIO_0 */ + "SWR_TX_DATA1", + "SWR_TX_DATA2", + "SWR_RX_CLK", + "SWR_RX_DATA1", + "SWR_RX_DATA2", + "WCD9375_RST_N", + "NC", + "NC", + "NC", + "NC", /* GPIO_10 */ + "NC", + "BT_FM_SLIMBUS_DATA", + "BT_FM_SLIMBUS_CLK"; +}; + +&nfc_default { + pins = "gpio31", "gpio36", "gpio67"; +}; + +&nfc_sleep { + pins = "gpio31", "gpio36", "gpio67"; +}; + +&nxp { + enable-gpios = <&tlmm 67 GPIO_ACTIVE_HIGH>; +}; + +&pm6150_gpios { + gpio-line-names = "NC", /* GPIO_1 */ + "NC", + "SMB_STAT", + "NC", + "NC", + "NC", + "WCSS_PWR_REQ", + "CAMF2_MCLK", + "FORCED_USB_BOOT", + "NC"; /* GPIO_10 */ +}; + +&pm6150l_gpios { + gpio-line-names = "CAMW_DVDD_EN", /* GPIO_1 */ + "KYPD_VOLP_N", + "CAMU_AVDD_EN", + "CAMM_AVDD_EN", + "NC", + "NC", + "NC", + "CAMW_AVDD_EN", + "LCD_RESET_N", + "INFARED_SPI_MOSI", /* GPIO_10 */ + "NC", + "NC"; +}; + +&pm6150l_lpg { + status = "okay"; +}; + +&pm6150l_wled { + qcom,current-limit-microamp = <22500>; + qcom,ovp-millivolt = <28000>; + + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/sm7150/phoenix/adsp.mbn"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/sm7150/phoenix/cdsp.mbn"; +}; + +&remoteproc_mpss { + firmware-name = "qcom/sm7150/phoenix/modem.mbn"; +}; + +&sdhc_2 { + status = "okay"; +}; + +&tlmm { + gpio-line-names = "NFC_ESE_SPI_MISO", /* GPIO_0 */ + "NFC_ESE_SPI_MOSI", + "NFC_ESE_SPI_CLK", + "NFC_ESE_SPI_CS_N", + "CAM_DOVDD_EN", + "NC", + "SPKR_I2C_SDA", + "SPKR_I2C_SCL", + "TP_RESET_N", + "TP_INT_N", + "MDP_VSYNC_P", /* GPIO_10 */ + "CAMF2_MCLK_EN", + "FRONT2_I2C_SEL", + "CAMF1_MCLK0", + "CAMW_MCLK1", + "CAMUM_MCLK2", + "CAMD_MCLK3", + "CCI_I2C_SDA0", + "CCI_I2C_SCL0", + "CCI_I2C_SDA1", + "CCI_I2C_SCL1", /* GPIO_20 */ + "CAMD_RSTN", + "FL_STROBE_TRIG", + "CAMF1_RSTN", + "CAMM_RSTN", + "CAMU_RSTN", + "CAMW_RSTN", + "CCI_I2C_SDA2", + "CCI_I2C_SCL2", + "CAMU_DVDD_EN", + "CAMF2_RSTN", /* GPIO_30 */ + "NFC_LABBCLK3_EN", + "ERR_INT_N", + "LCD_ID_DET1", + "NFC_I2C_SDA", + "NFC_I2C_SCL", + "NFC_DWL_REQ", + "NFC_IRQ", + "BT_UART_CTS", + "BT_UART_RFR", + "BT_UART_TX", /* GPIO_40 */ + "BT_UART_RX", + "NC", + "INFARED_SPI_MOSI", + "BLSP2_UART_TX", + "BLSP2_UART_RX", + "APPS_I2C_SDA", + "APPS_I2C_SCL", + "FORCED_USB_BOOT", + "SPKR_I2S_BCK", + "SPKR_I2S_WS", /* GPIO_50 */ + "SPKR_I2S_DOUT", + "SPKR_I2S_DIN1", + "TP_SPI_MISO", + "TP_SPI_MOSI", + "TP_SPI_CLK", + "TP_SPI_CS", + "FP_INT_N", + "FP_RESET_N", + "FP_SPI_MISO", + "FP_SPI_MOSI", /* GPIO_60 */ + "FP_SPI_CLK", + "FP_SPI_CS_N", + "FP_LDO_EN", + "CAMF2_TEST_INT", + "LCD_ID_DET2", + "SPKR_PA_RST", + "NFC_ENABLE", + "VBUS_DIS_EN", + "SD_CARD_DET_N", + "NC", /* GPIO_70 */ + "NC", + "CAMF1_DVDD_AVDD_EN", + "WLAN_SW_CTRL", + "GRFC_4", + "UIM2_DATA", + "UIM2_CLK", + "UIM2_RESET", + "UIM2_PRESENT", + "UIM1_DATA", + "UIM1_CLK", /* GPIO_80 */ + "UIM1_RESET", + "UIM1_PRESENT", + "NC", + "NC", + "WMSS_RESET_N", + "ACCEL_INT", + "GYRO_INT", + "MIPI_SEL", + "ALS_INT_N", + "PS_INT_N", /* GPIO_90 */ + "SW_IO", + "RFFE4_CLK", + "SPKR_INT", + "CAMF2_INT", + "GRFC_3", + "QLINK_REQUEST", + "QLINK_ENABLE", + "GRFC_2", + "GRFC_0", + "GRFC_1", /* GPIO_100 */ + "RFFE3_DATA", + "RFFE3_CLK", + "RFFE4_DATA", + "USB_PHY_PS", + "RFFE5_DATA", + "RFFE5_CLK", + "GRFC_5", + "WLAN_COEX_UART_TXD", + "WLAN_COEX_UART_RXD", + "NC", /* GPIO_110 */ + "NC", + "RFFE1_DATA", + "RFFE1_CLK"; +}; + +&venus { + firmware-name = "qcom/sm7150/phoenix/venus.mbn"; +}; diff --git a/arch/arm64/boot/dts/qcom/sm7150-xiaomi-surya-huaxing.dts b/arch/arm64/boot/dts/qcom/sm7150-xiaomi-surya-huaxing.dts new file mode 100644 index 00000000000000..bb9df9947c0561 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm7150-xiaomi-surya-huaxing.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024, Danila Tikhonov + */ + +/dts-v1/; + +#include "sm7150-xiaomi-surya.dtsi" + +/ { + /* + * Xiaomi POCO X3 (karna) + * Xiaomi POCO X3 NFC (surya) + */ + model = "Xiaomi POCO X3 NFC (Huaxing)"; + compatible = "xiaomi,surya", "qcom,sm7150"; +}; + +&nt36xxx { + firmware-name = "novatek_ts_huaxing_fw.bin"; +}; + +&panel { + compatible = "huaxing,nt36672c"; +}; diff --git a/arch/arm64/boot/dts/qcom/sm7150-xiaomi-surya-tianma.dts b/arch/arm64/boot/dts/qcom/sm7150-xiaomi-surya-tianma.dts new file mode 100644 index 00000000000000..ef0dce466041bf --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm7150-xiaomi-surya-tianma.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024, Danila Tikhonov + */ + +/dts-v1/; + +#include "sm7150-xiaomi-surya.dtsi" + +/ { + /* + * Xiaomi POCO X3 (karna) + * Xiaomi POCO X3 NFC (surya) + */ + model = "Xiaomi POCO X3 NFC (Tianma)"; + compatible = "xiaomi,surya", "qcom,sm7150"; +}; + +&nt36xxx { + firmware-name = "novatek_ts_tianma_fw.bin"; +}; + +&panel { + compatible = "tianma,nt36672c"; +}; diff --git a/arch/arm64/boot/dts/qcom/sm7150-xiaomi-surya.dtsi b/arch/arm64/boot/dts/qcom/sm7150-xiaomi-surya.dtsi new file mode 100644 index 00000000000000..a82f25b87e4b8a --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm7150-xiaomi-surya.dtsi @@ -0,0 +1,462 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024, Danila Tikhonov + * Copyright (c) 2024, David Wronek + */ + +/dts-v1/; + +#include "sm7150-xiaomi-common.dtsi" + +/ { + qcom,board-id = <34 0>; + + vreg_wide_ldo_avdd2: regulator-wide-ldo-avdd2 { + compatible = "regulator-fixed"; + regulator-name = "wide_ldo_avdd2"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + gpio = <&pm6150l_gpios 4 GPIO_ACTIVE_HIGH>; + startup-delay-us = <100>; + enable-active-high; + + vin-supply = <&vreg_bob>; + }; + + vreg_uw_ldo_ois_drv: regulator-vreg-uw-ldo-ois-drv { + compatible = "regulator-fixed"; + regulator-name = "uw_ldo_ois_drv"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + gpio = <&tlmm 65 GPIO_ACTIVE_HIGH>; + startup-delay-us = <100>; + enable-active-high; + + vin-supply = <&vreg_bob>; + }; + + vreg_camera_vdig: regulator-camera-vdig { + compatible = "regulator-fixed"; + regulator-name = "camera_vdig"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + gpio = <&pm6150l_gpios 12 GPIO_ACTIVE_HIGH>; + startup-delay-us = <233>; + enable-active-high; + + vin-supply = <&vreg_bob>; + }; + + vreg_camera_mipi_switch_en: gpio-camera-mipi-switch-en { + compatible = "regulator-fixed"; + regulator-name = "camera_mipi_switch_en"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + gpio = <&pm6150_gpios 2 GPIO_ACTIVE_HIGH>; + startup-delay-us = <233>; + enable-active-high; + + vin-supply = <&vreg_bob>; + }; + + reserved-memory { + rmtfs_mem: rmtfs@fde01000 { + compatible = "qcom,rmtfs-mem"; + reg = <0 0xfde01000 0 0x200000>; + no-map; + + qcom,client-id = <1>; + qcom,vmid = ; + }; + }; +}; + +&battery { + charge-full-design-microamp-hours = <5160000>; +}; + +&cci0_i2c0 { + /* Sony IMX682 Main @ 50 */ +}; + +&cci0_i2c1 { + /* OmniVision ov02b1b Depth @ 50 */ +}; + +&cci1_i2c0 { + /* Samsung S5K3T2 Front @ ? */ + /* Sk Hynix Hi-259 Macro @ ? */ + /* Sk Hynix Hi-1337 Ultrawide @ ? */ +}; + +&gpu { + zap-shader { + firmware-name = "qcom/sm7150/surya/a615_zap.mbn"; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + status = "okay"; + + haptics@5a { + compatible = "awinic,aw8624"; + reg = <0x5a>; + interrupts-extended = <&tlmm 26 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&tlmm 63 GPIO_ACTIVE_HIGH>; + + awinic,f0-preset = <2050>; + awinic,f0-coefficient = <260>; + awinic,f0-calibration-percent = <7>; + awinic,drive-level = <100>; + + awinic,f0-detection-play-time = <9>; + awinic,f0-detection-wait-time = <5>; + awinic,f0-detection-repeat = <1>; + awinic,f0-detection-trace = <15>; + + awinic,boost-debug = /bits/ 8 <0x1b 0x1b 0x16>; // ? + awinic,tset = /bits/ 8 <0x11>; + awinic,r-spare = /bits/ 8 <0x68>; + + awinic,bemf-upper-threshold = <4000>; // ? + awinic,bemf-lower-threshold = <2500>; // ? + }; +}; + +&i2c9 { + clock-frequency = <100000>; + status = "okay"; + + /* ovti,wl2866d (cam regulator) @ 28 */ + + tas2562: codec@4c { /* SPK */ + compatible = "ti,tas2562"; + reg = <0x4c>; + #sound-dai-cells = <1>; + interrupt-parent = <&tlmm>; + interrupts = <30 IRQ_TYPE_NONE>; + shutdown-gpios = <&tlmm 91 GPIO_ACTIVE_HIGH>; + ti,imon-slot-no = <0>; + ti,vmon-slot-no = <2>; + sound-name-prefix = "Right"; + }; + + tas2564: codec@4d { /* EAR */ + compatible = "ti,tas2564"; + reg = <0x4d>; + #sound-dai-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&audio_pa_reset_pin>; + interrupt-parent = <&tlmm>; + interrupts = <58 IRQ_TYPE_NONE>; + shutdown-gpios = <&pm6150l_gpios 8 GPIO_ACTIVE_HIGH>; + ti,imon-slot-no = <1>; + ti,vmon-slot-no = <3>; + sound-name-prefix = "Left"; + }; + + /* ti,bq25968 (charger) @ 65 */ +}; + +&ipa { + firmware-name = "qcom/sm7150/surya/ipa_fws.mbn"; +}; + +&lpass_tlmm { + gpio-line-names = "SWR_TX_CLK", /* GPIO_0 */ + "SWR_TX_DATA0", + "SWR_TX_DATA1", + "SWR_RX_CLK", + "SWR_RX_DATA0", + "SWR_RX_DATA1", + "WCD9375_RST_N", + "NC", + "NC", + "NC", + "NC", /* GPIO_10 */ + "NC", + "LPI_QCA_SB_DATA", + "LPI_QCA_SB_CLK"; +}; + +&nfc_default { + pins = "gpio12", "gpio31", "gpio36", "gpio94"; +}; + +&nfc_sleep { + pins = "gpio12", "gpio31", "gpio36", "gpio94"; +}; + +&panel { + vddio-supply = <&vreg_l18a_2p8>; + /delete-property/ vdd3p3-supply; + + backlight = <&pm6150l_wled>; + + pinctrl-0 = <&panel_reset_pin &panel_te_pin &panel_esd_pin>; +}; + +&pm6150_gpios { + gpio-line-names = "BOARD_ADC0", /* GPIO_1 */ + "NC", + "CAM_SW2_OE_2", + "CAM_2M_DEPTH_IOVDD1P8_EN", + "SLB", + "PWDN", + "NC", + "WCSS_PWR_REQ", + "NC", + "PL_EN"; /* GPIO_10 */ +}; + +&pm6150l_flash { + status = "okay"; +}; + +&pm6150l_gpios { + gpio-line-names = "8M/13M_DVDD_1P1_EN", /* GPIO_1 */ + "KYPD_VOLP_N", + "NC", + "64M_AVDD0_1P8_EN", + "LCD_NTC", + "BOARD_ADC1", + "SLB", + "AUDIO_PA_RST2", + "DISP0_RESET_N", + "NVM_THERM", /* GPIO_10 */ + "GPIO11_ID", + "20M_DVDD1_1P05_EN"; + + audio_pa_reset_pin: audio-pa-reset-state { + pins = "gpio8"; + function = PMIC_GPIO_FUNC_NORMAL; + output-high; + input-disable; + power-source = <1>; + }; +}; + +&pm6150l_lpg { + status = "okay"; +}; + +&pm6150l_wled { + qcom,current-limit-microamp = <25000>; + + status = "okay"; +}; + +&q6afedai { + qi2s@20 { + reg = ; + qcom,sd-lines = <0>; + }; +}; + +&q6asmdai { + dai@0 { + reg = <0>; + }; +}; + +&remoteproc_adsp { + firmware-name = "qcom/sm7150/surya/adsp.mbn"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/sm7150/surya/cdsp.mbn"; +}; + +&remoteproc_mpss { + firmware-name = "qcom/sm7150/surya/modem.mbn"; +}; + +&sdhc_2 { + status = "okay"; +}; + +&sound { + compatible = "qcom,sm8250-sndcard"; + pinctrl-0 = <&ter_mi2s_active>; + pinctrl-names = "default"; + model = "POCO X3"; + + mm1-dai-link { + link-name = "MultiMedia1"; + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>; + }; + }; + + i2s-dai-link { + link-name = "I2S Playback"; + cpu { + sound-dai = <&q6afedai TERTIARY_MI2S_RX>; + }; + + platform { + sound-dai = <&q6routing>; + }; + + codec { + sound-dai = <&tas2562 0>, <&tas2564 0>; + }; + }; +}; + +&spi0 { + clock-frequency = <8000000>; + status = "okay"; + + nt36xxx: touchscreen@0 { + compatible = "novatek,nt36xxx-spi"; + reg = <0>; + + spi-max-frequency = <8000000>; + + pinctrl-0 = <&ts_int_active &ts_reset_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-names = "default", "sleep"; + + reset-gpio = <&tlmm 8 GPIO_ACTIVE_HIGH>; + irq-gpio = <&tlmm 9 IRQ_TYPE_EDGE_FALLING>; + + vio-supply = <&vreg_l18a_2p8>; + + panel = <&panel>; + }; +}; + +&tlmm { + /* Reserved I/Os for FP */ + gpio-reserved-ranges = <59 4>; + + gpio-line-names = "GP_HP_SDA", /* GPIO_0 */ + "GP_HP_SCL", + "NC", + "NC", + "LCD_ERR_INT_N", + "ANT_CHECK", + "DS28E16_1_WIRE", + "LDM_ID1", + "TP_RST", + "TP_INT", + "LCD_TE", /* GPIO_10 */ + "ALSPG_INT_N", + "NFC_ENABLE", + "CAM_MCLK0", + "CAM_MCLK1", + "CAM_MCLK2", + "CAM_MCLK3", + "CC_I2C_SDA0", + "CC_I2C_SCL0", + "CC_I2C_SDA1", + "CC_I2C_SCL1", /* GPIO_20 */ + "CLK_BUFFER_2", + "NC", + "CAM4_RST_N", + "CAM3_RST_N", + "CAM1_RST_N", + "HAPTIC_INT_N", + "CC_I2C_SDA2", + "CC_I2C_SCL2", + "NC", + "AUDIO_INT1", /* GPIO_30 */ + "NFC_CLK_REQ", + "CLK_BUFFER_3", + "CLK_BUFFER_4", + "NFC_I2C_SDA", + "NFC_I2C_SCL", + "NFC_DWL_REQ", + "NFC_IRQ", + "BT_UART_CTS", + "BT_UART_RFR", + "BT_UART_TX", /* GPIO_40 */ + "BT_UART_RX", + "SVDD_PWR_REQ", + "CHARGER_INT", + "DBG_UART_TX", + "DBG_UART_RX", + "AUDIO_I2C_SDA", + "AUDIO_I2C_SCL", + "FORCE_USB_BOOT", + "TS_SPI_MISO", + "TS_SPI_MOSI", /* GPIO_50 */ + "TS_SPI_CLK", + "TS_SPI_CS_N", + "LPI_MI2S_1_SCK", + "LPI_MI2S_1_WS", + "LPI_MI2S_1_DATA0", + "LPI_MI2S_1_DATA1", + "CHIP_EN", + "AUDIO_INT2", + "FP_SPI_MISO", + "FP_SPI_MOSI", /* GPIO_60 */ + "FP_SPI_CLK", + "FP_SPI_CS", + "HAPTIC_RST_N", + "CAM5_RST_N", + "DRV_VDD2P8_EN", + "64M_AF_EN", + "SAR_CAP_INI", + "CLK_BUFFER_1", + "SD_CARD_DET_N", + "NC", /* GPIO_70 */ + "LDM_IDO", + "CAM0_RST_N", + "WLAN_SW_CTRL", + "PRX_TUNER_SW3", + "UIM2_DATA", + "UIM2_CLK", + "UIM2_RESET", + "UIM2_PRESENT", + "UIM1_DATA", + "UIM1_CLK", /* GPIO_80 */ + "UIM1_RESET", + "UIM1_PRESENT", + "PRX_TUNER_SW1", + "ANT_CHECK_DIV", + "WMSS_RESET_N", + "GINT1", + "GINT2", + "8M_AFVDD_2P8_EN", + "FP_INT_N", + "FP_RESET_N", /* GPIO_90 */ + "AUDIO_PA_RST1", + "NC", + "CAM2_RST_N", + "SWITCH_SEL1", + "DPDT_TUNER_SW", + "QLINK_REQUEST", + "QLINK_ENABLE", + "LNA_PRX_B1_EN", + "DRX_TUNER_SW4", + "DRX_ANT_EN", /* GPIO_100 */ + "NC", + "IR_EN_SPI_MOSI", + "NC", + "USB_PHY_PS", + "RFFE5_DATA", + "RFFE5_CLK", + "LNA_DRX_B7B38B41_EN_v2", + "MSS_LTE_COXM_TXD", + "MSS_LTE_COXM_RXD", + "RFFE2_DATA", /* GPIO_110 */ + "RFFE2_CLK", + "RFFE1_DATA", + "RFFE1_CLK"; +}; + +&venus { + firmware-name = "qcom/sm7150/surya/venus.mbn"; +}; + +&vreg_l18a_2p8 { + regulator-min-microvolt = <1696000>; + regulator-max-microvolt = <1904000>; +}; diff --git a/arch/arm64/boot/dts/qcom/sm7150-xiaomi-sweet.dts b/arch/arm64/boot/dts/qcom/sm7150-xiaomi-sweet.dts new file mode 100644 index 00000000000000..56a76fe6598bbe --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm7150-xiaomi-sweet.dts @@ -0,0 +1,184 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024, Danila Tikhonov + * Copyright (c) 2024, Kali Prasad + * Copyright (c) 2024, Salvatore Stella + */ + +/dts-v1/; + +#include "sm7150-xiaomi-common.dtsi" + +/delete-node/ &wlan_msa_mem; +/delete-node/ &npu_mem; +/delete-node/ &ipa_fw_mem; +/delete-node/ &ipa_gsi_mem; +/delete-node/ &gpu_mem; + +&adsp_mem { + reg = <0x0 0x95700000 0x0 0x2600000>; +}; + +/ { + model = "Xiaomi Redmi Note 10 Pro"; + compatible = "xiaomi,sweet", "qcom,sm7150"; + + qcom,board-id = <46 0>; + + reserved-memory { + wlan_msa_mem: wlan@97d00000 { + reg = <0x0 0x97d00000 0x0 0x180000>; + no-map; + }; + + npu_mem: npu@97e80000 { + reg = <0x0 0x97e80000 0x0 0x80000>; + no-map; + }; + + ipa_fw_mem: ipa_fw@97f00000 { + reg = <0x0 0x97f00000 0x0 0x10000>; + no-map; + }; + + ipa_gsi_mem: ipa_gsi@97f10000 { + reg = <0x0 0x97f10000 0x0 0x5000>; + no-map; + }; + + gpu_mem: gpu@97f15000 { + reg = <0x0 0x97f15000 0x0 0x2000>; + no-map; + }; + + rmtfs_mem: rmtfs@fde01000 { + compatible = "qcom,rmtfs-mem"; + reg = <0 0xfde01000 0 0x200000>; + no-map; + + qcom,client-id = <1>; + qcom,vmid = ; + }; + }; +}; + +&dispcc { + status = "okay"; +}; + +&gpu { + zap-shader { + firmware-name = "qcom/sm7150/sweet/a615_zap.mbn"; + }; +}; + +&i2c4 { + clock-frequency = <100000>; + status = "okay"; + + /* awinic,aw882xx (speaker amplifier) @ 34 */ + /* awinic,aw882xx (speaker amplifier) @ 35 */ +}; + +&i2c7 { + clock-frequency = <100000>; + status = "okay"; + + touchscreen: goodix@5d { + compatible = "goodix,gt9896"; + reg = <0x5d>; + interrupt-parent = <&tlmm>; + interrupts = <9 IRQ_TYPE_NONE>; + pinctrl-0 = <&ts_int_active &ts_reset_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-names = "default", "sleep"; + vtouch-supply = <&vreg_l11c_3p3>; + vtouch-load = <600000>; + goodix,vdd-gpio = <&tlmm 90 GPIO_ACTIVE_HIGH>; + goodix,avdd-name = "vtouch"; + goodix,reset-gpio = <&tlmm 8 GPIO_ACTIVE_HIGH>; + goodix,irq-gpio = <&tlmm 9 IRQ_TYPE_NONE>; + goodix,irq-flags = <2>; /* trigger falling;*/ + goodix,panel-max-x = <1079>; + goodix,panel-max-y = <2399>; + goodix,panel-max-w = <256>; + goodix,power-on-delay-us = <100>; /* 0.1ms */ + goodix,power-off-delay-us = <5000>; /* 50ms */ + }; +}; + +&i2c9 { + clock-frequency = <100000>; + status = "okay"; + + /* ovti,wl2866d (cam regulator) @ 28 */ + /* lionsemi,ln8000 (charger) @ 51 */ + + haptics@5a { + compatible = "awinic,aw8624"; + reg = <0x5a>; + interrupts-extended = <&pm6150l_gpios 10 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>; + + awinic,f0-preset = <2050>; + awinic,f0-coefficient = <260>; + awinic,f0-calibration-percent = <7>; + awinic,drive-level = <106>; + + awinic,f0-detection-play-time = <9>; + awinic,f0-detection-wait-time = <5>; + awinic,f0-detection-repeat = <1>; + awinic,f0-detection-trace = <15>; + + //upstrem suggests these values rather than the next + //awinic,boost-debug = /bits/ 8 <0x30 0xeb 0xd4>; + awinic,boost-debug = /bits/ 8 <0x1b 0x1b 0x16>; // ? + awinic,tset = /bits/ 8 <0x11>; + awinic,r-spare = /bits/ 8 <0x68>; + + awinic,bemf-upper-threshold = <4000>; // ? + awinic,bemf-lower-threshold = <2500>; // ? + }; + + /* ti,bq2597x (charger) @ 66 */ +}; + +&ipa { + firmware-name = "qcom/sm7150/sweet/ipa_fws.mbn"; +}; + +&nfc_default { + pins = "gpio31", "gpio36", "gpio66"; +}; + +&nfc_sleep { + pins = "gpio31", "gpio36", "gpio66"; +}; + +&nxp { + enable-gpios = <&tlmm 66 GPIO_ACTIVE_HIGH>; +}; + +&panel { + compatible = "mdss,k6-38-0c-0a-dsc"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/sm7150/sweet/adsp.mbn"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/sm7150/sweet/cdsp.mbn"; +}; + +&remoteproc_mpss { + firmware-name = "qcom/sm7150/sweet/modem.mbn"; +}; + +&sdhc_2 { + status = "okay"; +}; + +&venus { + firmware-name = "qcom/sm7150/sweet/venus.mbn"; +}; diff --git a/arch/arm64/boot/dts/qcom/sm7150-xiaomi-sweet_k6a.dts b/arch/arm64/boot/dts/qcom/sm7150-xiaomi-sweet_k6a.dts new file mode 100644 index 00000000000000..438fb237a5c9af --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm7150-xiaomi-sweet_k6a.dts @@ -0,0 +1,191 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include "sm7150-xiaomi-common.dtsi" + +/delete-node/ &wlan_msa_mem; +/delete-node/ &npu_mem; +/delete-node/ &ipa_fw_mem; +/delete-node/ &ipa_gsi_mem; +/delete-node/ &gpu_mem; + +&adsp_mem { + reg = <0x0 0x95700000 0x0 0x2600000>; +}; + +&tz_mem { + reg = <0x0 0x86200000 0x0 0x4900000>; +}; + +/ { + model = "Xiaomi Redmi Note 12 Pro"; + compatible = "xiaomi,sweet_k6a", "qcom,sm7150"; + + qcom,board-id = <46 0>; + + reserved-memory { + wlan_msa_mem: wlan_msa@97d00000 { + reg = <0x0 0x97d00000 0x0 0x180000>; + no-map; + }; + + npu_mem: npu@97e80000 { + reg = <0x0 0x97e80000 0x0 0x80000>; + no-map; + }; + + ipa_fw_mem: ipa_fw@97f00000 { + reg = <0x0 0x97f00000 0x0 0x10000>; + no-map; + }; + + ipa_gsi_mem: ipa_gsi@97f10000 { + reg = <0x00 0x97f10000 0x00 0x5000>; + no-map; + }; + + gpu_mem: gpu@97f15000 { + reg = <0x00 0x97f15000 0x00 0x2000>; + no-map; + }; + + rmtfs_mem: rmtfs@f2e01000 { /* recheck in twrp */ + compatible = "qcom,rmtfs-mem"; + reg = <0 0xf2b01000 0 0x300000>; + no-map; + + qcom,client-id = <1>; + qcom,vmid = ; + }; + + }; +}; + +&battery { + voltage-min-design-microvolt = <3500000>; + energy-full-design-microwatt-hours = <18500000>; + charge-full-design-microamp-hours = <5000000>; +}; + +&gpu { + zap-shader { + firmware-name = "qcom/sm7150/sweet_k6a/a615_zap.mbn"; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + status = "okay"; + + bq27z561: fuel-gauge@55 { + compatible = "ti,bq27z561"; + reg = <0x55>; + monitored-battery = <&battery>; + }; +}; + +&i2c4 { + clock-frequency = <100000>; + status = "okay"; + + /* foursemi,fs16xx (speaker amplifier) @ 34 */ + /* foursemi,fs16xx (speaker amplifier) @ 35 */ + /* lionsemi,ln8000 (charger-slave) @ 51 */ + /* ti,bq25968 (charger-slave) @ 66 */ +}; + +&i2c7 { + clock-frequency = <100000>; + status = "okay"; + + /* focaltech,fts_K6 @ 38 */ + + touchscreen: goodix@5d { + compatible = "goodix,gt9896"; + reg = <0x5d>; + interrupt-parent = <&tlmm>; + interrupts = <9 IRQ_TYPE_NONE>; + pinctrl-0 = <&ts_int_active &ts_reset_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-names = "default", "sleep"; + vtouch-supply = <&vreg_l7c_3p0>; + vtouch-load = <600000>; + goodix,vdd-gpio = <&tlmm 90 GPIO_ACTIVE_HIGH>; + goodix,avdd-name = "vtouch"; + goodix,reset-gpio = <&tlmm 8 GPIO_ACTIVE_HIGH>; + goodix,irq-gpio = <&tlmm 9 IRQ_TYPE_NONE>; + goodix,irq-flags = <2>; /* trigger falling;*/ + goodix,panel-max-x = <8639>; + goodix,panel-max-y = <19199>; + goodix,panel-max-w = <256>; + goodix,power-on-delay-us = <100>; /* 0.1ms */ + goodix,power-off-delay-us = <5000>; /* 50ms */ + }; +}; + +&i2c9 { + clock-frequency = <100000>; + status = "okay"; + + /* ovti,wl2866d (cam regulator) @ 28 */ + /* lionsemi,ln8000 (charger-master) @ 51 */ + /* awinic,awinic_haptic @ 58 */ + /* ti,bq25968 (charger-master) @ 66 */ +}; + +&ipa { + firmware-name = "qcom/sm7150/sweet_k6a/ipa_fws.mbn"; +}; + +&nfc_default { + pins = "gpio31", "gpio36", "gpio66"; +}; + +&nfc_sleep { + pins = "gpio31", "gpio36", "gpio66"; +}; + +&nxp { + enable-gpios = <&tlmm 66 GPIO_ACTIVE_HIGH>; +}; + +&panel { + compatible = "mdss,k6-38-0e-0b-dsc"; +}; + +&pm6150l_flash { + status = "okay"; +}; + +&pm6150_qgauge { + /* sweet_k6a uses bq27z561 */ + status = "disabled"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/sm7150/sweet_k6a/adsp.mbn"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/sm7150/sweet_k6a/cdsp.mbn"; +}; + +&remoteproc_mpss { + firmware-name = "qcom/sm7150/sweet_k6a/modem.mbn"; +}; + +&sdhc_2 { + status = "okay"; +}; + +&spi0 { + clock-frequency = <50000000>; + status = "okay"; + + /* qcom,spi-msm-ir (ir-led) @ 1 */ +}; + +&venus { + firmware-name = "qcom/sm7150/sweet_k6a/venus.mbn"; +}; diff --git a/arch/arm64/boot/dts/qcom/sm7150-xiaomi-toco.dts b/arch/arm64/boot/dts/qcom/sm7150-xiaomi-toco.dts new file mode 100644 index 00000000000000..13f2ca8d0a2e1c --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm7150-xiaomi-toco.dts @@ -0,0 +1,175 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024, Danila Tikhonov + */ + +/dts-v1/; + +#include "sm7150-xiaomi-common.dtsi" + +/delete-node/ &adsp_mem; +/delete-node/ &wlan_msa_mem; +/delete-node/ &npu_mem; +/delete-node/ &ipa_fw_mem; +/delete-node/ &ipa_gsi_mem; +/delete-node/ &gpu_mem; + +&cont_splash_mem { + reg = <0x0 0x9c000000 0x0 (1080 * 2340 * 4)>; +}; + +/ { + model = "Xiaomi Mi Note 10 Lite"; + compatible = "xiaomi,toco", "qcom,sm7150"; + + qcom,board-id = <44 0>; + + reserved-memory { + adsp_mem: adsp@95700000 { + reg = <0x0 0x95700000 0x0 0x2600000>; + no-map; + }; + + wlan_msa_mem: wlan_msa@97d00000 { + reg = <0x0 0x97d00000 0x0 0x180000>; + no-map; + }; + + npu_mem: npu@97e80000 { + reg = <0x0 0x97e80000 0x0 0x80000>; + no-map; + }; + + ipa_fw_mem: ipa_fw@97f00000 { + reg = <0x0 0x97f00000 0x0 0x10000>; + no-map; + }; + + ipa_gsi_mem: ipa_gsi@97f10000 { + reg = <0x0 0x97f10000 0x0 0x5000>; + no-map; + }; + + gpu_mem: gpu@97f15000 { + reg = <0x0 0x97f15000 0x0 0x2000>; + no-map; + }; + + rmtfs_mem: rmtfs@fde01000 { + compatible = "qcom,rmtfs-mem"; + reg = <0 0xfde01000 0 0x200000>; + no-map; + + qcom,client-id = <1>; + qcom,vmid = ; + }; + }; + + vreg_ibb: regulator-ibb { + compatible = "regulator-fixed"; + regulator-name = "ibb"; + regulator-min-microvolt = <6000000>; + regulator-max-microvolt = <6000000>; + }; + + vreg_lab: regulator-lab { + compatible = "regulator-fixed"; + regulator-name = "lab"; + regulator-min-microvolt = <6000000>; + regulator-max-microvolt = <6000000>; + }; +}; + +&framebuffer { + reg = <0x0 0x9c000000 0x0 (1080 * 2340 * 4)>; + height = <2340>; +}; + +&gpu { + zap-shader { + firmware-name = "qcom/sm7150/toco/a615_zap.mbn"; + }; +}; + +&i2c4 { + clock-frequency = <100000>; + status = "okay"; + + /* ti,drv2605l (haptic) @ 5a */ + /* awinic,aw3644 (flash led) @ 63 */ +}; + +&i2c7 { + clock-frequency = <100000>; + status = "okay"; + + /* st,fts (touchscreen) @ 49 */ + + touchscreen: goodix@5d { + compatible = "goodix,gt9886"; + reg = <0x5d>; + interrupt-parent = <&tlmm>; + interrupts = <9 0x2800>; + vtouch-supply = <&vreg_l6c_3p0>; /* 3v3 */ + vtouch-load = <600000>; + pinctrl-0 = <&ts_int_active &ts_reset_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-names = "default", "sleep"; + goodix,reset-gpio = <&tlmm 8 GPIO_ACTIVE_HIGH>; + goodix,irq-gpio = <&tlmm 9 0x2800>; + goodix,avdd-name = "vtouch"; + goodix,irq-flags = <2>; /* trigger falling;*/ + goodix,panel-max-x = <1079>; + goodix,panel-max-y = <2339>; + goodix,panel-max-w = <127>; + goodix,power-on-delay-us = <300000>; /* 300ms */ + goodix,power-off-delay-us = <5000>; /* 50ms */ + }; +}; + +&i2c9 { + clock-frequency = <100000>; + status = "okay"; + + /* nxp,tfa98xx (amplifire) @ 34 */ + /* ti,bq2597x (charger) @ 66 */ +}; + +&ipa { + firmware-name = "qcom/sm7150/toco/ipa_fws.mbn"; +}; + +&nfc_default { + pins = "gpio31", "gpio36", "gpio67"; +}; + +&nfc_sleep { + pins = "gpio31", "gpio36", "gpio67"; +}; + +&nxp { + enable-gpios = <&tlmm 67 GPIO_ACTIVE_HIGH>; +}; + +&panel { + compatible = "visionox,g2647fb105"; + + vsn-supply = <&vreg_ibb>; + vsp-supply = <&vreg_lab>; +}; + +&remoteproc_adsp { + firmware-name = "qcom/sm7150/toco/adsp.mbn"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/sm7150/toco/cdsp.mbn"; +}; + +&remoteproc_mpss { + firmware-name = "qcom/sm7150/toco/modem.mbn"; +}; + +&venus { + firmware-name = "qcom/sm7150/toco/venus.mbn"; +}; diff --git a/arch/arm64/boot/dts/qcom/sm7150-xiaomi-tucana.dts b/arch/arm64/boot/dts/qcom/sm7150-xiaomi-tucana.dts new file mode 100644 index 00000000000000..e3c99c8b6f6666 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm7150-xiaomi-tucana.dts @@ -0,0 +1,485 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024, Danila Tikhonov + * Copyright (c) 2024, Alexander Baransky + */ + +/dts-v1/; + +#include "sm7150-xiaomi-common.dtsi" +#include + +/delete-node/ &wlan_msa_mem; +/delete-node/ &npu_mem; +/delete-node/ &ipa_fw_mem; +/delete-node/ &ipa_gsi_mem; +/delete-node/ &gpu_mem; + +&adsp_mem { + reg = <0x0 0x95700000 0x0 0x2600000>; +}; + +&cont_splash_mem { + reg = <0x0 0x9c000000 0x0 (1080 * 2340 * 4)>; +}; + +&tz_mem { + reg = <0x0 0x86200000 0x0 0x4900000>; +}; + +/ { + /* + * Xiaomi Mi Note 10 (Xiaomi Mi CC9 Pro) + * Xiaomi Mi Note 10 Pro (Xiaomi Mi CC9 Pro Premium Edition) + */ + model = "Xiaomi Mi Note 10"; + compatible = "xiaomi,tucana", "qcom,sm7150"; + + qcom,board-id = <42 0>; + + reserved-memory { + wlan_msa_mem: wlan_msa@97d00000 { + reg = <0x0 0x97d00000 0x0 0x180000>; + no-map; + }; + + npu_mem: npu@97e80000 { + reg = <0x0 0x97e80000 0x0 0x80000>; + no-map; + }; + + ipa_fw_mem: ipa_fw@97f00000 { + reg = <0x0 0x97f00000 0x0 0x10000>; + no-map; + }; + + ipa_gsi_mem: ipa_gsi@97f10000 { + reg = <0x0 0x97f10000 0x0 0x5000>; + no-map; + }; + + gpu_mem: gpu@97f15000 { + reg = <0x0 0x97f15000 0x0 0x2000>; + no-map; + }; + + rmtfs_mem: rmtfs@f2e01000 { + compatible = "qcom,rmtfs-mem"; + reg = <0 0xf2e01000 0 0x200000>; + no-map; + + qcom,client-id = <1>; + qcom,vmid = ; + }; + }; + + vreg_ibb: regulator-ibb { + compatible = "regulator-fixed"; + regulator-name = "ibb"; + regulator-min-microvolt = <6000000>; + regulator-max-microvolt = <6000000>; + }; + + vreg_lab: regulator-lab { + compatible = "regulator-fixed"; + regulator-name = "lab"; + regulator-min-microvolt = <6000000>; + regulator-max-microvolt = <6000000>; + }; + + vreg_touch_vdd: regulator-touch-vdd { + compatible = "regulator-fixed"; + regulator-name = "touch_vdd"; + gpio = <&tlmm 72 GPIO_ACTIVE_HIGH>; + startup-delay-us = <4000>; + enable-active-high; + regulator-boot-on; + }; +}; + +&battery { + charge-full-design-microamp-hours = <5260000>; +}; + +&framebuffer { + reg = <0x0 0x9c000000 0x0 (1080 * 2340 * 4)>; + height = <2340>; +}; + +&gpu { + zap-shader { + firmware-name = "qcom/sm7150/tucana/a615_zap.mbn"; + }; +}; + +&i2c4 { + clock-frequency = <100000>; + status = "okay"; + + haptics@5a { + compatible = "ti,drv2605l"; + reg = <0x5a>; + enable-gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>; + mode = ; + library-sel = ; + vib-rated-mv = <3200>; + vib-overdrive-mv = <3200>; + }; + + softlight: aw3644@63 { + compatible = "awinic,aw3644"; + reg = <0x63>; + aw3644,hwen-gpio = <&pm6150l_gpios 12 GPIO_ACTIVE_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + function = LED_FUNCTION_FLASH; + function-enumerator = <2>; + color = ; + }; + + led@1 { + reg = <1>; + function = LED_FUNCTION_FLASH; + function-enumerator = <3>; + color = ; + }; + }; +}; + +&i2c7 { + clock-frequency = <100000>; + status = "okay"; + + touchscreen: fts@49 { + compatible = "st,fts"; + reg = <0x49>; + + interrupt-parent = <&tlmm>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-0 = <&ts_int_active &ts_reset_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-names = "default", "sleep"; + + vdd-supply = <&vreg_touch_vdd>; + avdd-supply = <&vreg_l6c_3p0>; + fts,regulator_dvdd = "vdd"; + fts,regulator_avdd = "avdd"; + + fts,irq-gpio = <&tlmm 9 GPIO_TRANSITORY>; + fts,irq-flags = <0x2008>; /* oneshot and trigger low */ + + fts,reset-gpio-enable; + fts,reset-gpio = <&tlmm 8 GPIO_ACTIVE_HIGH>; + + fts,x-max = <1080>; + fts,y-max = <2340>; + }; + /* goodix,gt9886 (touchscreen) @ 5d */ +}; + +&i2c9 { + clock-frequency = <100000>; + status = "okay"; + + tfa9874: codec@34 { + compatible = "nxp,tfa9874"; + reg = <0x34>; + + reset-gpio = <&tlmm 12 GPIO_ACTIVE_HIGH>; + irq-gpio = <&tlmm 56 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&spkr_reset &spkr_int>; + + #sound-dai-cells = <0>; + }; + /* ti,bq2597x (charger) @ 66 */ +}; + +&ipa { + firmware-name = "qcom/sm7150/tucana/ipa_fws.mbn"; +}; + +&lpass_tlmm { + gpio-line-names = "SWR_TX_CLK", /* GPIO_0 */ + "SWR_TX_DATA1", + "SWR_TX_DATA2", + "SWR_RX_CLK", + "SWR_RX_DATA1", + "SWR_RX_DATA2", + "WCD9375_RST_N", + "NC", + "NC", + "NC", + "NC", /* GPIO_10 */ + "NC", + "BT_FM_SLIMBUS_DATA", + "BT_FM_SLIMBUS_CLK"; +}; + +&nfc_default { + pins = "gpio31", "gpio36", "gpio67"; +}; + +&nfc_sleep { + pins = "gpio31", "gpio36", "gpio67"; +}; + +&nxp { + enable-gpios = <&tlmm 67 GPIO_ACTIVE_HIGH>; +}; + +&panel { + compatible = "visionox,g2647fb105"; + + vsn-supply = <&vreg_ibb>; + vsp-supply = <&vreg_lab>; +}; + +&pm6150l_flash { + status = "okay"; + + led-0 { + function = LED_FUNCTION_FLASH; + function-enumerator = <0>; + color = ; + led-sources = <1>; + led-max-microamp = <150000>; + flash-max-microamp = <1000000>; + flash-max-timeout-us = <1280000>; + }; + + led-1 { + function = LED_FUNCTION_FLASH; + function-enumerator = <1>; + color = ; + led-sources = <2>; + led-max-microamp = <150000>; + flash-max-microamp = <1000000>; + flash-max-timeout-us = <1280000>; + }; +}; + +&pm6150_gpios { + gpio-line-names = "FOD_LDO_EN1", /* GPIO_1 */ + "FOD_LDO_EN2", + "NC", + "VBUS_NTC_CTRL", + "SLB", + "NC", + "NC", + "NC", + "FORCED_USB_BOOT", + "NC"; /* GPIO_10 */ +}; + +&pm6150l_gpios { + gpio-line-names = "NC", /* GPIO_1 */ + "KYPD_VOLP_N", + "CAMW_LDO_EN", + "SF_DRV_STR", + "NC", + "NC", + "SLB", + "CAMT1_LDO_EN", + "LCD_RESET_N", + "PWM_HAPTICS", /* GPIO_10 */ + "CAMT2_LDO_EN", + "SF_DRV_HWEN"; +}; + +&q6afedai { + dai@16 { + reg = ; + qcom,sd-lines = <0>; + }; +}; + +&q6asmdai { + dai@0 { + reg = <0>; + }; +}; + +&remoteproc_adsp { + firmware-name = "qcom/sm7150/tucana/adsp.mbn"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/sm7150/tucana/cdsp.mbn"; +}; + +&remoteproc_mpss { + firmware-name = "qcom/sm7150/tucana/modem.mbn"; +}; + +&sound { + compatible = "qcom,sm8250-sndcard"; + pinctrl-0 = <&pri_mi2s_active &pri_mi2s_ws_active>; + pinctrl-names = "default"; + model = "Xiaomi Mi Note 10"; + + mm1-dai-link { + link-name = "MultiMedia1"; + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>; + }; + }; + + speaker_playback_dai { + link-name = "Primary Spkr Playback"; + cpu { + sound-dai = <&q6afedai PRIMARY_MI2S_RX>; + }; + + platform { + sound-dai = <&q6routing>; + }; + + codec { + sound-dai = <&tfa9874>; + }; + }; +}; + +&tlmm { + gpio-line-names = "NFC_ESE_SPI_MISO", /* GPIO_0 */ + "NFC_ESE_SPI_MOSI", + "NFC_ESE_SPI_CLK", + "NFC_ESE_SPI_CS_N", + "HAPTICS_EN", + "CAM_DOVDD_EN", + "TS_I2C_SDA", + "TS_I2C_SCL", + "TS_RESET_N", + "TS_INT_N", + "MDP_VSYNC_P", /* GPIO_10 */ + "CAMT1_RSTN", + "SPKR_PA_RST", + "CAM_MCLK0", + "CAM_MCLK1", + "CAM_MCLK2", + "CAM_MCLK3", + "CCI_I2C_SDA0", + "CCI_I2C_SCL0", + "CCI_I2C_SDA1", + "CCI_I2C_SCL1", /* GPIO_20 */ + "CAMM_LDO_EN", + "FL_STROBE_TRIG", + "CAMF_RSTN", + "CAMM_RSTN", + "CAMU_RSTN", + "CAMW_RSTN", + "CCI_I2C_SDA2", + "CCI_I2C_SCL2", + "CAMU_LDO_EN", + "CAMT2_RSTN", /* GPIO_30 */ + "NFC_LABBCLK3_EN", + "ERR_INT_N", + "LCD_ID_DET1", + "NFC_I2C_SDA", + "NFC_I2C_SCL", + "NFC_DWL_REQ", + "NFC_IRQ", + "BT_UART_CTS", + "BT_UART_RFR", + "BT_UART_TX", /* GPIO_40 */ + "BT_UART_RX", + "NC", + "INFARED_SPI_MOSI", + "BLSP2_UART_TX", + "BLSP2_UART_RX", + "APPS_I2C_SDA", + "APPS_I2C_SCL", + "FORCED_USB_BOOT", + "SPKR_I2S_BCK", + "SPKR_I2S_WS", /* GPIO_50 */ + "SPKR_I2S_DOUT", + "SPKR_I2S_DIN1", + "TYPC_I2C_SDA", + "TYPC_I2C_SCL", + "LCD_ID_DET2", + "SPKR_INT", + "CAMF_LDO_EN", + "BQ25970_MASTER_INT", + "FOD_SPI_MISO", + "FOD_SPI_MOSI", /* GPIO_60 */ + "FOD_SPI_SCLK", + "FOD_SPI_CS_N", + "FOD_LDO_EN", + "GPOUT", + "FOD_RST", + "SF_DRV_TX", + "NFC_ENABLE", + "TOF_INT", + "FOD_INT", + "RFFE6_CLK", /* GPIO_70 */ + "RFFE6_DATA", + "TP_VDDI_EN", + "WLAN_SW_CTRL", + "GRFC_4", + "UIM2_DATA", + "UIM2_CLK", + "UIM2_RESET", + "UIM2_PRESENT", + "UIM1_DATA", + "UIM1_CLK", /* GPIO_80 */ + "UIM1_RESET", + "UIM1_PRESENT", + "GRFC_8", + "GRFC_9", + "WMSS_RESET_N", + "ACCEL_INT", + "GYRO_INT", + "MIPI_SEL1", + "ALS_INT_N", + "MIPI_SEL2", /* GPIO_90 */ + "SF_DRV_TORCH", + "RFFE4_CLK", + "NC", + "SW_IO", + "GRFC_3", + "QLINK_REQUEST", + "QLINK_ENABLE", + "GRFC_2", + "NC", + "NC", /* GPIO_100 */ + "RFFE3_DATA", + "RFFE3_CLK", + "RFFE4_DATA", + "USB_PHY_PS", + "RFFE5_DATA", + "RFFE5_CLK", + "GRFC_5", + "WLAN_COEX_UART_TXD", + "WLAN_COEX_UART_RXD", + "GRFC_34", /* GPIO_110 */ + "GRFC_33", + "RFFE1_DATA", + "RFFE1_CLK"; + + spkr_reset: spkr-reset-state { + pins = "gpio12"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + bias-pull-down; + output-low; + }; + + spkr_int: spkr-int-state { + pins = "gpio56"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + input-enable; + }; +}; + +&venus { + firmware-name = "qcom/sm7150/tucana/venus.mbn"; +}; diff --git a/arch/arm64/boot/dts/qcom/sm7150.dtsi b/arch/arm64/boot/dts/qcom/sm7150.dtsi new file mode 100644 index 00000000000000..90d18740766e5c --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm7150.dtsi @@ -0,0 +1,5132 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023, Danila Tikhonov + * Copyright (c) 2023, David Wronek + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + aliases { + mmc1 = &sdhc_1; + mmc2 = &sdhc_2; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c6 = &i2c6; + i2c7 = &i2c7; + i2c8 = &i2c8; + i2c9 = &i2c9; + i2c10 = &i2c10; + i2c11 = &i2c11; + spi0 = &spi0; + spi1 = &spi1; + spi3 = &spi3; + spi4 = &spi4; + spi6 = &spi6; + spi7 = &spi7; + spi8 = &spi8; + spi10 = &spi10; + spi11 = &spi11; + }; + + chosen { }; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + clock-frequency = <38400000>; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32000>; + #clock-cells = <0>; + }; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,kryo470"; + reg = <0x0 0x0>; + clocks = <&cpufreq_hw 0>; + enable-method = "psci"; + capacity-dmips-mhz = <488>; + dynamic-power-coefficient = <137>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + next-level-cache = <&l2_0>; + power-domains = <&cpu_pd0>; + power-domain-names = "psci"; + #cooling-cells = <2>; + qcom,freq-domain = <&cpufreq_hw 0>; + l2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_0>; + l3_0: l3-cache { + compatible = "cache"; + cache-level = <3>; + cache-unified; + }; + }; + }; + + cpu1: cpu@100 { + device_type = "cpu"; + compatible = "qcom,kryo470"; + reg = <0x0 0x100>; + clocks = <&cpufreq_hw 0>; + enable-method = "psci"; + capacity-dmips-mhz = <488>; + dynamic-power-coefficient = <137>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + next-level-cache = <&l2_100>; + power-domains = <&cpu_pd1>; + power-domain-names = "psci"; + #cooling-cells = <2>; + qcom,freq-domain = <&cpufreq_hw 0>; + l2_100: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_0>; + }; + }; + + cpu2: cpu@200 { + device_type = "cpu"; + compatible = "qcom,kryo470"; + reg = <0x0 0x200>; + clocks = <&cpufreq_hw 0>; + enable-method = "psci"; + capacity-dmips-mhz = <488>; + dynamic-power-coefficient = <137>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + next-level-cache = <&l2_200>; + power-domains = <&cpu_pd2>; + power-domain-names = "psci"; + #cooling-cells = <2>; + qcom,freq-domain = <&cpufreq_hw 0>; + l2_200: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_0>; + }; + }; + + cpu3: cpu@300 { + device_type = "cpu"; + compatible = "qcom,kryo470"; + reg = <0x0 0x300>; + clocks = <&cpufreq_hw 0>; + enable-method = "psci"; + capacity-dmips-mhz = <488>; + dynamic-power-coefficient = <137>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + next-level-cache = <&l2_300>; + power-domains = <&cpu_pd3>; + power-domain-names = "psci"; + #cooling-cells = <2>; + qcom,freq-domain = <&cpufreq_hw 0>; + l2_300: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_0>; + }; + }; + + cpu4: cpu@400 { + device_type = "cpu"; + compatible = "qcom,kryo470"; + reg = <0x0 0x400>; + clocks = <&cpufreq_hw 0>; + enable-method = "psci"; + capacity-dmips-mhz = <488>; + dynamic-power-coefficient = <137>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + next-level-cache = <&l2_400>; + power-domains = <&cpu_pd4>; + power-domain-names = "psci"; + #cooling-cells = <2>; + qcom,freq-domain = <&cpufreq_hw 0>; + l2_400: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_0>; + }; + }; + + cpu5: cpu@500 { + device_type = "cpu"; + compatible = "qcom,kryo470"; + reg = <0x0 0x500>; + clocks = <&cpufreq_hw 0>; + enable-method = "psci"; + capacity-dmips-mhz = <488>; + dynamic-power-coefficient = <137>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + next-level-cache = <&l2_500>; + power-domains = <&cpu_pd5>; + power-domain-names = "psci"; + #cooling-cells = <2>; + qcom,freq-domain = <&cpufreq_hw 0>; + l2_500: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_0>; + }; + }; + + cpu6: cpu@600 { + device_type = "cpu"; + compatible = "qcom,kryo470"; + reg = <0x0 0x600>; + clocks = <&cpufreq_hw 1>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <480>; + operating-points-v2 = <&cpu6_opp_table>; + interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + next-level-cache = <&l2_600>; + power-domains = <&cpu_pd6>; + power-domain-names = "psci"; + #cooling-cells = <2>; + qcom,freq-domain = <&cpufreq_hw 1>; + l2_600: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_0>; + }; + }; + + cpu7: cpu@700 { + device_type = "cpu"; + compatible = "qcom,kryo470"; + reg = <0x0 0x700>; + clocks = <&cpufreq_hw 1>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <480>; + operating-points-v2 = <&cpu6_opp_table>; + interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + next-level-cache = <&l2_700>; + power-domains = <&cpu_pd7>; + power-domain-names = "psci"; + #cooling-cells = <2>; + qcom,freq-domain = <&cpufreq_hw 1>; + l2_700: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_0>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + + core3 { + cpu = <&cpu3>; + }; + + core4 { + cpu = <&cpu4>; + }; + + core5 { + cpu = <&cpu5>; + }; + + core6 { + cpu = <&cpu6>; + }; + + core7 { + cpu = <&cpu7>; + }; + }; + }; + + cpu_idle_states: idle-states { + entry-method = "psci"; + + little_cpu_sleep_0: cpu-sleep-0-0 { + compatible = "arm,idle-state"; + idle-state-name = "little-power-collapse"; + arm,psci-suspend-param = <0x40000003>; + entry-latency-us = <549>; + exit-latency-us = <901>; + min-residency-us = <1774>; + local-timer-stop; + }; + + little_cpu_sleep_1: cpu-sleep-0-1 { + compatible = "arm,idle-state"; + idle-state-name = "little-rail-power-collapse"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <702>; + exit-latency-us = <915>; + min-residency-us = <4001>; + local-timer-stop; + }; + + big_cpu_sleep_0: cpu-sleep-1-0 { + compatible = "arm,idle-state"; + idle-state-name = "big-power-collapse"; + arm,psci-suspend-param = <0x40000003>; + entry-latency-us = <523>; + exit-latency-us = <1244>; + min-residency-us = <2207>; + local-timer-stop; + }; + + big_cpu_sleep_1: cpu-sleep-1-1 { + compatible = "arm,idle-state"; + idle-state-name = "big-rail-power-collapse"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <526>; + exit-latency-us = <1854>; + min-residency-us = <5555>; + local-timer-stop; + }; + }; + + domain-idle-states { + cluster_sleep_pc: cluster-sleep-0 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x41000044>; + entry-latency-us = <2752>; + exit-latency-us = <3048>; + min-residency-us = <6118>; + }; + + cluster_sleep_cx_ret: cluster-sleep-1 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x41001244>; + entry-latency-us = <3638>; + exit-latency-us = <4562>; + min-residency-us = <8467>; + }; + + cluster_aoss_sleep: cluster-sleep-2 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x4100b244>; + entry-latency-us = <3263>; + exit-latency-us = <6562>; + min-residency-us = <9826>; + }; + }; + }; + + firmware { + scm { + compatible = "qcom,scm-sm7150", "qcom,scm"; + interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>; + }; + }; + + memory@80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0 0x80000000 0 0>; + }; + + cpu0_opp_table: opp-table-cpu0 { + compatible = "operating-points-v2"; + opp-shared; + + cpu0_opp1: opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + /* DDR: 4-wide, 2 channels, double data rate, L3: 16-wide, 2 channels */ + opp-peak-kBps = <(200000 * 4 * 2 * 2) (300000 * 16 * 2)>; + }; + + cpu0_opp2: opp-576000000 { + opp-hz = /bits/ 64 <576000000>; + opp-peak-kBps = <(200000 * 4 * 2 * 2) (556800 * 16 * 2)>; + }; + + cpu0_opp3: opp-768000000 { + opp-hz = /bits/ 64 <768000000>; + opp-peak-kBps = <(300000 * 4 * 2 * 2) (768000 * 16 * 2)>; + }; + + cpu0_opp4: opp-1017600000 { + opp-hz = /bits/ 64 <1017600000>; + opp-peak-kBps = <(300000 * 4 * 2 * 2) (940800 * 16 * 2)>; + }; + + cpu0_opp5: opp-1248000000 { + opp-hz = /bits/ 64 <1248000000>; + opp-peak-kBps = <(451000 * 4 * 2 * 2) (1190400 * 16 * 2)>; + }; + + cpu0_opp6: opp-1324800000 { + opp-hz = /bits/ 64 <1324800000>; + opp-peak-kBps = <(451000 * 4 * 2 * 2) (1305600 * 16 * 2)>; + }; + + cpu0_opp7: opp-1497600000 { + opp-hz = /bits/ 64 <1497600000>; + opp-peak-kBps = <(547000 * 4 * 2 * 2) (1459200 * 16 * 2)>; + }; + + cpu0_opp8: opp-1612800000 { + opp-hz = /bits/ 64 <1612800000>; + opp-peak-kBps = <(547000 * 4 * 2 * 2) (1459200 * 16 * 2)>; + }; + + cpu0_opp9: opp-1708800000 { + opp-hz = /bits/ 64 <1708800000>; + opp-peak-kBps = <(547000 * 4 * 2 * 2) (1459200 * 16 * 2)>; + }; + + cpu0_opp10: opp-1804800000 { + opp-hz = /bits/ 64 <1804800000>; + opp-peak-kBps = <(768000 * 4 * 2 * 2) (1459200 * 16 * 2)>; + }; + }; + + cpu6_opp_table: opp-table-cpu6 { + compatible = "operating-points-v2"; + opp-shared; + + cpu6_opp1: opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-peak-kBps = <(200000 * 4 * 2 * 2) (300000 * 16 * 2)>; + }; + + cpu6_opp2: opp-652800000 { + opp-hz = /bits/ 64 <652800000>; + opp-peak-kBps = <(200000 * 4 * 2 * 2) (652800 * 16 * 2)>; + }; + + cpu6_opp3: opp-806400000 { + opp-hz = /bits/ 64 <806400000>; + opp-peak-kBps = <(200000 * 4 * 2 * 2) (768000 * 16 * 2)>; + }; + + cpu6_opp4: opp-979200000 { + opp-hz = /bits/ 64 <979200000>; + opp-peak-kBps = <(200000 * 4 * 2 * 2) (940800 * 16 * 2)>; + }; + + cpu6_opp5: opp-1094400000 { + opp-hz = /bits/ 64 <1094400000>; + opp-peak-kBps = <(300000 * 4 * 2 * 2) (940800 * 16 * 2)>; + }; + + cpu6_opp6: opp-1209600000 { + opp-hz = /bits/ 64 <1209600000>; + opp-peak-kBps = <(300000 * 4 * 2 * 2) (1190400 * 16 * 2)>; + }; + + cpu6_opp7: opp-1324800000 { + opp-hz = /bits/ 64 <1324800000>; + opp-peak-kBps = <(547000 * 4 * 2 * 2) (1305600 * 16 * 2)>; + }; + + cpu6_opp8: opp-1555200000 { + opp-hz = /bits/ 64 <1555200000>; + opp-peak-kBps = <(768000 * 4 * 2 * 2) (1459200 * 16 * 2)>; + }; + + cpu6_opp9: opp-1708800000 { + opp-hz = /bits/ 64 <1708800000>; + opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1459200 * 16 * 2)>; + }; + + cpu6_opp10: opp-1843200000 { + opp-hz = /bits/ 64 <1843200000>; + opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1459200 * 16 * 2)>; + }; + + cpu6_opp11: opp-1939200000 { + opp-hz = /bits/ 64 <1939200000>; + opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1459200 * 16 * 2)>; + }; + + cpu6_opp12: opp-2169600000 { + opp-hz = /bits/ 64 <2169600000>; + opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1459200 * 16 * 2)>; + }; + + cpu6_opp13: opp-2208000000 { + opp-hz = /bits/ 64 <2208000000>; + opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1459200 * 16 * 2)>; + }; + + cpu6_opp14: opp-2304000000 { + opp-hz = /bits/ 64 <2304000000>; + opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1459200 * 16 * 2)>; + }; + }; + + mdss_dsi_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-180000000 { + opp-hz = /bits/ 64 <180000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-275000000 { + opp-hz = /bits/ 64 <275000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + + qup_opp_table: opp-table-qup { + compatible = "operating-points-v2"; + + opp-75000000 { + opp-hz = /bits/ 64 <75000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-128000000 { + opp-hz = /bits/ 64 <128000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + + pmu-a55 { + compatible = "arm,cortex-a55-pmu"; + interrupts = ; + }; + + pmu-a76 { + compatible = "arm,cortex-a78-pmu"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + + cpu_pd0: power-domain-cpu0 { + #power-domain-cells = <0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&little_cpu_sleep_0 + &little_cpu_sleep_1>; + }; + + cpu_pd1: power-domain-cpu1 { + #power-domain-cells = <0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&little_cpu_sleep_0 + &little_cpu_sleep_1>; + }; + + cpu_pd2: power-domain-cpu2 { + #power-domain-cells = <0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&little_cpu_sleep_0 + &little_cpu_sleep_1>; + }; + + cpu_pd3: power-domain-cpu3 { + #power-domain-cells = <0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&little_cpu_sleep_0 + &little_cpu_sleep_1>; + }; + + cpu_pd4: power-domain-cpu4 { + #power-domain-cells = <0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&little_cpu_sleep_0 + &little_cpu_sleep_1>; + }; + + cpu_pd5: power-domain-cpu5 { + #power-domain-cells = <0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&little_cpu_sleep_0 + &little_cpu_sleep_1>; + }; + + cpu_pd6: power-domain-cpu6 { + #power-domain-cells = <0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&big_cpu_sleep_0 + &big_cpu_sleep_1>; + }; + + cpu_pd7: power-domain-cpu7 { + #power-domain-cells = <0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&big_cpu_sleep_0 + &big_cpu_sleep_1>; + }; + + cluster_pd: power-domain-cpu-cluster0 { + #power-domain-cells = <0>; + domain-idle-states = <&cluster_sleep_pc + &cluster_sleep_cx_ret + &cluster_aoss_sleep>; + }; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_mem: hypervisor@85700000 { + reg = <0x0 0x85700000 0x0 0x600000>; + no-map; + }; + + /* XBL and AOP are splitted */ + xbl_mem: xbl@85d00000 { + reg = <0x0 0x85d00000 0x0 0x200000>; + no-map; + }; + + aop_mem: aop@85f00000 { + reg = <0x0 0x85f00000 0x0 0x20000>; + no-map; + }; + + aop_cmd_db_mem: aop-cmd-db@85f20000 { + compatible = "qcom,cmd-db"; + reg = <0x0 0x85f20000 0x0 0x20000>; + no-map; + }; + + sec_apps_mem: sec-apps@85fff000 { + reg = <0x0 0x85fff000 0x0 0x1000>; + no-map; + }; + + smem_mem: smem@86000000 { + reg = <0x0 0x86000000 0x0 0x200000>; + no-map; + }; + + tz_mem: trust-zone@86200000 { + reg = <0x0 0x86200000 0x0 0x2d00000>; + no-map; + }; + + camera_mem: camera@8ab00000 { + reg = <0x0 0x8ab00000 0x0 0x500000>; + no-map; + }; + + mpss_mem: mpss@8b000000 { + reg = <0x0 0x8b000000 0x0 0x8400000>; + no-map; + }; + + venus_mem: venus@93400000 { + reg = <0x0 0x93400000 0x0 0x500000>; + no-map; + }; + + cdsp_mem: cdsp@93900000 { + reg = <0x0 0x93900000 0x0 0x1e00000>; + no-map; + }; + + adsp_mem: adsp@95700000 { + reg = <0x0 0x95700000 0x0 0x1e00000>; + no-map; + }; + + wlan_msa_mem: wlan-msa@97500000 { + reg = <0x0 0x97500000 0x0 0x180000>; + no-map; + }; + + npu_mem: npu@97680000 { + reg = <0x0 0x97680000 0x0 0x80000>; + no-map; + }; + + ipa_fw_mem: ipa-fw@97700000 { + reg = <0x0 0x97700000 0x0 0x10000>; + no-map; + }; + + ipa_gsi_mem: ipa-gsi@97710000 { + reg = <0x0 0x97710000 0x0 0x5000>; + no-map; + }; + + gpu_mem: gpu@97715000 { + reg = <0x0 0x97715000 0x0 0x2000>; + no-map; + }; + + qseecom_mem: qseecom@9e400000 { + reg = <0x0 0x9e400000 0x0 0x1400000>; + no-map; + }; + + sec_cdsp_mem: sec-cdsp@9f800000 { + reg = <0x0 0x9f800000 0x0 0x1e00000>; + no-map; + }; + + dfps_data_mem: dfps-data@9e300000 { + reg = <0x0 0x9d700000 0x0 0x0100000>; + no-map; + }; + }; + + smem: smem { + compatible = "qcom,smem"; + + memory-region = <&smem_mem>; + hwlocks = <&tcsr_mutex 3>; + }; + + smp2p-adsp { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + + interrupts = ; + + mboxes = <&apss_shared 26>; + + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + smp2p_adsp_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_adsp_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-cdsp { + compatible = "qcom,smp2p"; + qcom,smem = <94>, <432>; + + interrupts = ; + + mboxes = <&apss_shared 6>; + + qcom,local-pid = <0>; + qcom,remote-pid = <5>; + + smp2p_cdsp_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_cdsp_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-modem { + compatible = "qcom,smp2p"; + + interrupts = ; + + mboxes = <&apss_shared 14>; + + qcom,smem = <435>, <428>; + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + smp2p_modem_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_modem_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_ipa_out: ipa-ap-to-modem { + qcom,entry-name = "ipa"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_ipa_in: ipa-modem-to-ap { + qcom,entry-name = "ipa"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + soc: soc@0 { + compatible = "simple-bus"; + + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0 0 0 0x10 0>; + dma-ranges = <0 0 0 0 0x10 0>; + + gcc: clock-controller@100000 { + compatible = "qcom,sm7150-gcc"; + reg = <0 0x00100000 0 0x1f0000>; + + power-domains = <&rpmhpd RPMHPD_CX>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + qfprom: efuse@784000 { + compatible = "qcom,sm7150-qfprom", "qcom,qfprom"; + reg = <0 0x00784000 0 0x8ff>; + + #address-cells = <1>; + #size-cells = <1>; + + gpu_speed_bin: gpu-speed-bin@1a2 { + reg = <0x1a2 0x2>; + bits = <5 8>; + }; + }; + + gpi_dma0: dma-controller@800000 { + compatible = "qcom,sm7150-gpi-dma", + "qcom,sdm845-gpi-dma"; + reg = <0 0x00800000 0 0x60000>; + + interrupts = , + , + , + , + , + , + , + ; + + dma-channels = <8>; + dma-channel-mask = <0x0f>; + #dma-cells = <3>; + + iommus = <&apps_smmu 0x216 0x0>; + + dma-coherent; + + status = "disabled"; + }; + + qupv3_id_0: geniqup@8c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0 0x008c0000 0 0x6000>; + + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + clock-names = "m-ahb", + "s-ahb"; + + iommus = <&apps_smmu 0x203 0x0>; + + dma-coherent; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + i2c0: i2c@880000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00880000 0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names = "se"; + + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; + + interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, + <&gpi_dma0 1 0 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c0_default>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi0: spi@880000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00880000 0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names = "se"; + + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table>; + + interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, + <&gpi_dma0 1 0 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi0_spi>, <&qup_spi0_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c1: i2c@884000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00884000 0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names = "se"; + + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; + + interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, + <&gpi_dma0 1 1 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c1_default>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi1: spi@884000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00884000 0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names = "se"; + + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table>; + + interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, + <&gpi_dma0 1 1 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi1_spi>, <&qup_spi1_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c2: i2c@888000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00888000 0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; + + interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, + <&gpi_dma0 1 2 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c2_default>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c3: i2c@88c000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x0088c000 0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names = "se"; + + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; + + interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, + <&gpi_dma0 1 3 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c3_default>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi3: spi@88c000 { + compatible = "qcom,geni-spi"; + reg = <0 0x0088c000 0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names = "se"; + + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table>; + + interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, + <&gpi_dma0 1 3 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi3_spi>, <&qup_spi3_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + uart3: serial@88c000 { + compatible = "qcom,geni-uart"; + reg = <0 0x0088c000 0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names = "se"; + + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table>; + + interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&system_noc A1NOC_SNOC_MAS QCOM_ICC_TAG_ALWAYS + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&qup_uart3_default>; + pinctrl-names = "default"; + + status = "disabled"; + }; + + i2c4: i2c@890000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00890000 0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + clock-names = "se"; + + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; + + interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, + <&gpi_dma0 1 4 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c4_default>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi4: spi@890000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00890000 0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + clock-names = "se"; + + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table>; + + interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, + <&gpi_dma0 1 4 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi4_spi>, <&qup_spi4_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + uart4: serial@890000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00890000 0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + clock-names = "se"; + + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table>; + + interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&system_noc A1NOC_SNOC_MAS QCOM_ICC_TAG_ALWAYS + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart4_default>; + + status = "disabled"; + }; + }; + + gpi_dma1: dma-controller@a00000 { + compatible = "qcom,sm7150-gpi-dma", + "qcom,sdm845-gpi-dma"; + reg = <0 0x00a00000 0 0x60000>; + + interrupts = , + , + , + , + , + , + , + ; + + dma-channels = <8>; + dma-channel-mask = <0x0f>; + #dma-cells = <3>; + + iommus = <&apps_smmu 0x4d6 0x0>; + + dma-coherent; + + status = "disabled"; + }; + + qupv3_id_1: geniqup@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0 0x00ac0000 0 0x6000>; + + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + clock-names = "m-ahb", + "s-ahb"; + + iommus = <&apps_smmu 0x4c3 0x0>; + + dma-coherent; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + i2c6: i2c@a80000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a80000 0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names = "se"; + + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; + + interconnects = <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, + <&gpi_dma1 1 0 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c6_default>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi6: spi@a80000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a80000 0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names = "se"; + + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table>; + + interconnects = <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, + <&gpi_dma1 1 0 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi6_spi>, <&qup_spi6_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c7: i2c@a84000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a84000 0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + clock-names = "se"; + + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; + + interconnects = <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, + <&gpi_dma1 1 1 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c7_default>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi7: spi@a84000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a84000 0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + clock-names = "se"; + + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table>; + + interconnects = <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, + <&gpi_dma1 1 1 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi7_spi>, <&qup_spi7_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c8: i2c@a88000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a88000 0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names = "se"; + + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; + + interconnects = <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, + <&gpi_dma1 1 2 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c8_default>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi8: spi@a88000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a88000 0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names = "se"; + + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table>; + + interconnects = <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, + <&gpi_dma1 1 2 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi8_spi>, <&qup_spi8_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + uart8: serial@a88000 { + compatible = "qcom,geni-debug-uart"; + reg = <0 0x00a88000 0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names = "se"; + + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table>; + + interconnects = <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&system_noc A1NOC_SNOC_MAS QCOM_ICC_TAG_ALWAYS + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&qup_uart8_default>; + pinctrl-names = "default"; + + status = "disabled"; + }; + + i2c9: i2c@a8c000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a8c000 0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + clock-names = "se"; + + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; + + interconnects = <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, + <&gpi_dma1 1 3 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c9_default>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c10: i2c@a90000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a90000 0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names = "se"; + + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; + + interconnects = <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, + <&gpi_dma1 1 4 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c10_default>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi10: spi@a90000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a90000 0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names = "se"; + + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table>; + + interconnects = <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, + <&gpi_dma1 1 4 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi10_spi>, <&qup_spi10_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + uart10: serial@a90000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00a90000 0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names = "se"; + + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table>; + + interconnects = <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&system_noc A1NOC_SNOC_MAS QCOM_ICC_TAG_ALWAYS + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&qup_uart10_default>; + pinctrl-names = "default"; + + status = "disabled"; + }; + + i2c11: i2c@a94000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a94000 0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names = "se"; + + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; + + interconnects = <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, + <&gpi_dma1 1 5 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c11_default>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi11: spi@a94000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a94000 0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names = "se"; + + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table>; + + interconnects = <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, + <&gpi_dma1 1 5 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi11_spi>, <&qup_spi11_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + uart11: serial@a94000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00a94000 0 0x4000>; + + interrupts = ; + + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table>; + + interconnects = <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&system_noc A1NOC_SNOC_MAS QCOM_ICC_TAG_ALWAYS + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&qup_uart11_default>; + pinctrl-names = "default"; + + status = "disabled"; + }; + }; + + mc_virt: interconnect@1380000 { + compatible = "qcom,sm7150-mc-virt"; + reg = <0 0x01380000 0 0x40000>; + + qcom,bcm-voters = <&apps_bcm_voter>; + + #interconnect-cells = <2>; + }; + + config_noc: interconnect@1500000 { + compatible = "qcom,sm7150-config-noc"; + reg = <0 0x01500000 0 0x28000>; + + qcom,bcm-voters = <&apps_bcm_voter>; + + #interconnect-cells = <2>; + }; + + system_noc: interconnect@1620000 { + compatible = "qcom,sm7150-system-noc"; + reg = <0 0x01620000 0 0x40000>; + + qcom,bcm-voters = <&apps_bcm_voter>; + + #interconnect-cells = <2>; + + camnoc_virt: interconnect-0 { + compatible = "qcom,sm7150-camnoc-virt"; + + qcom,bcm-voters = <&apps_bcm_voter>; + + #interconnect-cells = <2>; + }; + }; + + aggre1_noc: interconnect@16e0000 { + compatible = "qcom,sm7150-aggre1-noc"; + reg = <0 0x016e0000 0 0x11080>; + + qcom,bcm-voters = <&apps_bcm_voter>; + + #interconnect-cells = <2>; + + clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; + }; + + aggre2_noc: interconnect@1700000 { + compatible = "qcom,sm7150-aggre2-noc"; + reg = <0 0x01700000 0 0x1f080>; + + qcom,bcm-voters = <&apps_bcm_voter>; + + #interconnect-cells = <2>; + + clocks = <&rpmhcc RPMH_IPA_CLK>; + }; + + mmss_noc: interconnect@1740000 { + compatible = "qcom,sm7150-mmss-noc"; + reg = <0 0x01740000 0 0x1c100>; + + qcom,bcm-voters = <&apps_bcm_voter>; + + #interconnect-cells = <2>; + }; + + ufs_mem_hc: ufshc@1d84000 { + compatible = "qcom,sm7150-ufshc", "qcom,ufshc", + "jedec,ufs-2.0"; + reg = <0 0x01d84000 0 0x3000>; + + interrupts = ; + + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>; + clock-names = "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk"; + freq-table-hz = <50000000 200000000>, + <0 0>, + <0 0>, + <37500000 150000000>, + <0 0>, + <0 0>, + <0 0>; + + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + + interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "ufs-ddr", "cpu-ufs"; + + power-domains = <&gcc UFS_PHY_GDSC>; + required-opps = <&rpmhpd_opp_nom>; // RETEST ME + + iommus = <&apps_smmu 0x300 0x0>; + + lanes-per-direction = <1>; + qcom,ice = <&ice>; + + phys = <&ufs_mem_phy>; + phy-names = "ufsphy"; + + #reset-cells = <1>; + + status = "disabled"; + }; + + ufs_mem_phy: phy@1d87000 { + compatible = "qcom,sm7150-qmp-ufs-phy"; + reg = <0 0x01d87000 0 0x1000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&gcc GCC_UFS_MEM_CLKREF_CLK>; + clock-names = "ref", + "ref_aux", + "qref"; + + resets = <&ufs_mem_hc 0>; + reset-names = "ufsphy"; + + power-domains = <&gcc UFS_PHY_GDSC>; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + + ice: crypto@1d90000 { + compatible = "qcom,sm7150-inline-crypto-engine", + "qcom,inline-crypto-engine"; + reg = <0 0x01d90000 0 0x8000>; + + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + }; + + ipa: ipa@1e40000 { + compatible = "qcom,sm7150-ipa", + "qcom,sc7180-ipa"; + reg = <0 0x01e40000 0 0x7000>, + <0 0x01e47000 0 0x2000>, + <0 0x01e04000 0 0x2c000>; + reg-names = "ipa-reg", + "ipa-shared", + "gsi"; + + iommus = <&apps_smmu 0x520 0x0>, + <&apps_smmu 0x522 0x0>; + + interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, + <&smp2p_ipa_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_ipa_in 1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ipa", + "gsi", + "ipa-clock-query", + "ipa-setup-ready"; + + clocks = <&rpmhcc RPMH_IPA_CLK>; + clock-names = "core"; + + interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI_CH0 0>, + <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_OCIMEM 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_IPA_CFG 0>; + interconnect-names = "memory", "imem", "config"; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&smp2p_ipa_out 0>, + <&smp2p_ipa_out 1>; + qcom,smem-state-names = "ipa-clock-enabled-valid", + "ipa-clock-enabled"; + + status = "disabled"; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + reg = <0 0x01f40000 0 0x20000>; + + #hwlock-cells = <1>; + }; + + tcsr_regs_1: syscon@1f60000 { + compatible = "qcom,sm7150-tcsr", "syscon"; + reg = <0 0x01f60000 0 0x20000>; + }; + + tcsr_regs_2: syscon@1fc0000 { + compatible = "qcom,sm7150-tcsr", "syscon"; + reg = <0 0x01fc0000 0 0x40000>; + }; + + tlmm: pinctrl@3500000 { + compatible = "qcom,sm7150-tlmm"; + reg = <0 0x03500000 0 0x300000>, + <0 0x03900000 0 0x300000>, + <0 0x03d00000 0 0x300000>; + reg-names = "west", "north", "south"; + + interrupts = ; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + + gpio-ranges = <&tlmm 0 0 120>; + + wakeup-parent = <&pdc>; + + cci0_default: cci0-default-state { + pins = "gpio17", "gpio18"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up; + }; + + cci0_sleep: cci0-sleep-state { + pins = "gpio17", "gpio18"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + + cci1_default: cci1-default-state { + pins = "gpio19", "gpio20"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up; + }; + + cci1_sleep: cci1-sleep-state { + pins = "gpio19", "gpio20"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + + cci2_default: cci2-default-state { + pins = "gpio27", "gpio28"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up; + }; + + cci2_sleep: cci2-sleep-state { + pins = "gpio27", "gpio28"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + + qup_i2c0_default: qup-i2c0-default-state { + pins = "gpio49", "gpio50"; + function = "qup00"; + }; + + qup_i2c1_default: qup-i2c1-default-state { + pins = "gpio0", "gpio1"; + function = "qup01"; + }; + + qup_i2c2_default: qup-i2c2-default-state { + pins = "gpio34", "gpio35"; + function = "qup02"; + }; + + qup_i2c3_default: qup-i2c3-default-state { + pins = "gpio38", "gpio39"; + function = "qup03"; + }; + + qup_i2c4_default: qup-i2c4-default-state { + pins = "gpio53", "gpio54"; + function = "qup04"; + }; + + qup_i2c6_default: qup-i2c6-default-state { + pins = "gpio59", "gpio60"; + function = "qup10"; + }; + + qup_i2c7_default: qup-i2c7-default-state { + pins = "gpio6", "gpio7"; + function = "qup11"; + }; + + qup_i2c8_default: qup-i2c8-default-state { + pins = "gpio42", "gpio43"; + function = "qup12"; + }; + + qup_i2c9_default: qup-i2c9-default-state { + pins = "gpio46", "gpio47"; + function = "qup13"; + }; + + qup_i2c10_default: qup-i2c10-default-state { + pins = "gpio110", "gpio111"; + function = "qup14"; + }; + + qup_i2c11_default: qup-i2c11-default-state { + pins = "gpio101", "gpio102"; + function = "qup15"; + }; + + qup_spi0_spi: qup-spi0-spi-state { + pins = "gpio49", "gpio50", "gpio51"; + function = "qup00"; + }; + + qup_spi0_cs: qup-spi0-cs-state { + pins = "gpio52"; + function = "qup00"; + }; + + qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { + pins = "gpio52"; + function = "gpio"; + }; + + qup_spi1_spi: qup-spi1-spi-state { + pins = "gpio0", "gpio1", "gpio2"; + function = "qup01"; + }; + + qup_spi1_cs: qup-spi1-cs-state { + pins = "gpio3"; + function = "qup01"; + }; + + qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { + pins = "gpio3"; + function = "gpio"; + }; + + qup_spi3_spi: qup-spi3-spi-state { + pins = "gpio38", "gpio39", "gpio40"; + function = "qup03"; + }; + + qup_spi3_cs: qup-spi3-cs-state { + pins = "gpio41"; + function = "qup03"; + }; + + qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { + pins = "gpio41"; + function = "gpio"; + }; + + qup_spi4_spi: qup-spi4-spi-state { + pins = "gpio53", "gpio54", "gpio55"; + function = "qup04"; + }; + + qup_spi4_cs: qup-spi4-cs-state { + pins = "gpio56"; + function = "qup04"; + }; + + qup_spi4_cs_gpio: qup-spi4-cs-gpio-state { + pins = "gpio56"; + function = "gpio"; + }; + + qup_spi6_spi: qup-spi6-spi-state { + pins = "gpio59", "gpio60", "gpio61"; + function = "qup10"; + }; + + qup_spi6_cs: qup-spi6-cs-state { + pins = "gpio62"; + function = "qup10"; + }; + + qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { + pins = "gpio62"; + function = "gpio"; + }; + + qup_spi7_spi: qup-spi7-spi-state { + pins = "gpio6", "gpio7", "gpio8"; + function = "qup11"; + }; + + qup_spi7_cs: qup-spi7-cs-state { + pins = "gpio9"; + function = "qup11"; + }; + + qup_spi7_cs_gpio: qup-spi7-cs-gpio-state { + pins = "gpio9"; + function = "gpio"; + }; + + qup_spi8_spi: qup-spi8-spi-state { + pins = "gpio42", "gpio43", "gpio44"; + function = "qup12"; + }; + + qup_spi8_cs: qup-spi8-cs-state { + pins = "gpio45"; + function = "qup12"; + }; + + qup_spi8_cs_gpio: qup-spi8-cs-gpio-state { + pins = "gpio45"; + function = "gpio"; + }; + + qup_spi10_spi: qup-spi10-spi-state { + pins = "gpio110", "gpio111", "gpio112"; + function = "qup14"; + }; + + qup_spi10_cs: qup-spi10-cs-state { + pins = "gpio113"; + function = "qup14"; + }; + + qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { + pins = "gpio113"; + function = "gpio"; + }; + + qup_spi11_spi: qup-spi11-spi-state { + pins = "gpio101", "gpio102", "gpio103"; + function = "qup15"; + }; + + qup_spi11_cs: qup-spi11-cs-state { + pins = "gpio92", "gpio102", "gpio103"; + function = "qup15"; + }; + + qup_spi11_cs_gpio: qup-spi11-cs-gpio-state { + pins = "gpio92"; + function = "gpio"; + }; + + qup_uart0_default: qup-uart0-default-state { + qup_uart0_cts: cts-pins { + pins = "gpio34"; + function = "qup00"; + }; + + qup_uart0_rts: rts-pins { + pins = "gpio35"; + function = "qup00"; + }; + + qup_uart0_tx: tx-pins { + pins = "gpio36"; + function = "qup00"; + }; + + qup_uart0_rx: rx-pins { + pins = "gpio37"; + function = "qup00"; + }; + }; + + qup_uart3_default: qup-uart3-default-state { + qup_uart3_cts: cts-pins { + pins = "gpio38"; + function = "qup03"; + }; + + qup_uart3_rts: rts-pins { + pins = "gpio39"; + function = "qup03"; + }; + + qup_uart3_tx: tx-pins { + pins = "gpio40"; + function = "qup03"; + }; + + qup_uart3_rx: rx-pins { + pins = "gpio41"; + function = "qup03"; + }; + }; + + qup_uart4_default: qup-uart4-default-state { + qup_uart4_tx: tx-pins { + pins = "gpio53"; + function = "qup04"; + }; + + qup_uart4_rx: rx-pins { + pins = "gpio56"; + function = "qup04"; + }; + }; + + qup_uart8_default: qup-uart8-default-state { + qup_uart8_tx: tx-pins { + pins = "gpio44"; + function = "qup12"; + }; + + qup_uart8_rx: rx-pins { + pins = "gpio45"; + function = "qup12"; + }; + }; + + qup_uart10_default: qup-uart10-default-state { + qup_uart10_tx: tx-pins { + pins = "gpio110"; + function = "qup14"; + }; + + qup_uart10_rx: rx-pins { + pins = "gpio113"; + function = "qup14"; + }; + }; + + qup_uart11_default: qup-uart11-default-state { + qup_uart11_tx: tx-pins { + pins = "gpio101"; + function = "qup15"; + }; + + qup_uart11_rx: rx-pins { + pins = "gpio92"; + function = "qup15"; + }; + }; + + pri_mi2s_active: pri-mi2s-active-state { + pins = "gpio49", "gpio51", "gpio52"; + function = "pri_mi2s"; + }; + + pri_mi2s_ws_active: pri-mi2s-ws-active-state { + pins = "gpio50"; + function = "pri_mi2s_ws"; + }; + + ter_mi2s_active: ter-mi2s-active-state { + pins = "gpio53", "gpio54", "gpio55", "gpio56"; + function = "ter_mi2s"; + }; + + sec_mi2s_active: sec-mi2s-active-state { + pins = "gpio57"; + function = "sec_mi2s"; + }; + + qua_mi2s_active: qua-mi2s-active-state { + pins = "gpio58"; + function = "qua_mi2s"; + }; + }; + + remoteproc_adsp: remoteproc@62400000 { + compatible = "qcom,sm7150-adsp-pas", + "qcom,sc7180-adsp-pas"; + reg = <0 0x62400000 0 0x100>; + + interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd RPMHPD_LCX>, + <&rpmhpd RPMHPD_LMX>; + power-domain-names = "lcx", + "lmx"; + + memory-region = <&adsp_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&smp2p_adsp_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + remoteproc_adsp_glink: glink-edge { + interrupts = ; + + mboxes = <&apss_shared 24>; + qcom,remote-pid = <2>; + + label = "lpass"; + + apr { + compatible = "qcom,apr-v2"; + + qcom,glink-channels = "apr_audio_svc"; + + qcom,domain = ; + + #address-cells = <1>; + #size-cells = <0>; + + service@3 { + compatible = "qcom,q6core"; + reg = ; + + qcom,protection-domain = "avs/audio", + "msm/adsp/audio_pd"; + }; + + q6afe: service@4 { + compatible = "qcom,q6afe"; + reg = ; + + qcom,protection-domain = "avs/audio", + "msm/adsp/audio_pd"; + + q6afedai: dais { + compatible = "qcom,q6afe-dais"; + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <1>; + }; + + q6afecc: clock-controller { + compatible = "qcom,q6afe-clocks"; + #clock-cells = <2>; + }; + }; + + q6asm: service@7 { + compatible = "qcom,q6asm"; + reg = ; + + qcom,protection-domain = "avs/audio", + "msm/adsp/audio_pd"; + + q6asmdai: dais { + compatible = "qcom,q6asm-dais"; + + iommus = <&apps_smmu 0x1b21 0x0>; + + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <1>; + }; + }; + + q6adm: service@8 { + compatible = "qcom,q6adm"; + reg = ; + + qcom,protection-domain = "avs/audio", + "msm/adsp/audio_pd"; + + q6routing: routing { + compatible = "qcom,q6adm-routing"; + + #sound-dai-cells = <0>; + }; + }; + }; + + fastrpc { + compatible = "qcom,fastrpc"; + + qcom,glink-channels = "fastrpcglink-apps-dsp"; + + label = "adsp"; + + qcom,non-secure-domain; + + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x1b23 0x0>; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x1b24 0x0>; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x1b25 0x0>; + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + iommus = <&apps_smmu 0x1b26 0x0>; + }; + + compute-cb@7 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <7>; + iommus = <&apps_smmu 0x1b27 0x0>; + }; + + compute-cb@8 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <8>; + iommus = <&apps_smmu 0x1b28 0x0>; + qcom,nsessions = <3>; + }; + }; + }; + }; + + remoteproc_cdsp: remoteproc@8300000 { + compatible = "qcom,sm7150-cdsp-pas", + "qcom,sc7180-cdsp-pas"; + reg = <0 0x08300000 0 0x10000>; + + interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, + <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MX>; + power-domain-names = "cx", + "mx"; + + memory-region = <&cdsp_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&smp2p_cdsp_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts = ; + label = "cdsp"; + qcom,remote-pid = <5>; + mboxes = <&apss_shared 4>; + + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "cdsp"; + qcom,non-secure-domain; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@1 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <1>; + iommus = <&apps_smmu 0x1421 0x0>, + <&apps_smmu 0x1441 0x0>; + }; + + compute-cb@2 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <2>; + iommus = <&apps_smmu 0x1422 0x0>, + <&apps_smmu 0x1442 0x0>; + }; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x1423 0x0>, + <&apps_smmu 0x1443 0x0>; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x1424 0x0>, + <&apps_smmu 0x1444 0x0>; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x1425 0x0>, + <&apps_smmu 0x1445 0x0>; + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + iommus = <&apps_smmu 0x1406 0x60>; + }; + + /* note: secure cb9 in downstream */ + }; + }; + }; + + remoteproc_mpss: remoteproc@4080000 { + compatible = "qcom,sm7150-mpss-pas", + "qcom,sc7180-mpss-pas"; + reg = <0 0x04080000 0 0x4040>; + + interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", "handover", + "stop-ack", "shutdown-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MX>, + <&rpmhpd RPMHPD_MSS>; + power-domain-names = "cx", "mx", "mss"; + + memory-region = <&mpss_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&smp2p_modem_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts = ; + label = "modem"; + qcom,remote-pid = <1>; + mboxes = <&apss_shared 12>; + }; + }; + + gpu: gpu@5000000 { + compatible = "qcom,adreno-618.0", "qcom,adreno"; + reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>, + <0 0x05061000 0 0x800>; + reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc"; + interrupts = ; + iommus = <&adreno_smmu 0>; + operating-points-v2 = <&gpu_opp_table>; + qcom,gmu = <&gmu>; + + #cooling-cells = <2>; + + nvmem-cells = <&gpu_speed_bin>; + nvmem-cell-names = "speed_bin"; + + interconnects = <&gem_noc MASTER_GRAPHICS_3D 0 &mc_virt SLAVE_EBI_CH0 0>; + interconnect-names = "gfx-mem"; + + zap-shader { + memory-region = <&gpu_mem>; + }; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-825000000 { + opp-hz = /bits/ 64 <825000000>; + opp-level = ; + opp-supported-hw = <0x11>; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-level = ; + opp-supported-hw = <0x19>; + }; + + opp-700000000 { + opp-hz = /bits/ 64 <700000000>; + opp-level = ; + opp-supported-hw = <0x04>; + }; + + opp-650000000 { + opp-hz = /bits/ 64 <650000000>; + opp-level = ; + opp-supported-hw = <0x1d>; + }; + + opp-610000000 { + opp-hz = /bits/ 64 <610000000>; + opp-level = ; + opp-supported-hw = <0x02>; + }; + + opp-565000000 { + opp-hz = /bits/ 64 <565000000>; + opp-level = ; + opp-supported-hw = <0x1f>; + }; + + opp-430000000 { + opp-hz = /bits/ 64 <430000000>; + opp-level = ; + opp-supported-hw = <0x1f>; + }; + + opp-355000000 { + opp-hz = /bits/ 64 <355000000>; + opp-level = ; + opp-supported-hw = <0x1f>; + }; + + opp-267000000 { + opp-hz = /bits/ 64 <267000000>; + opp-level = ; + opp-supported-hw = <0x1f>; + }; + + opp-180000000 { + opp-hz = /bits/ 64 <180000000>; + opp-level = ; + opp-supported-hw = <0x1f>; + }; + }; + }; + + adreno_smmu: iommu@5040000 { + compatible = "qcom,sm7150-smmu-v2", "qcom,adreno-smmu", + "qcom,smmu-v2"; + reg = <0 0x05040000 0 0x10000>; + #iommu-cells = <1>; + #global-interrupts = <2>; + interrupts = , + , + , + , + , + , + , + , + , + ; + + clocks = <&gpucc GPU_CC_AHB_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; + clock-names = "ahb", "bus", "iface"; + + power-domains = <&gpucc CX_GDSC>; + }; + + gmu: gmu@506a000 { + compatible = "qcom,adreno-gmu-618.0", "qcom,adreno-gmu"; + reg = <0 0x0506a000 0 0x31000>, + <0 0x0b290000 0 0x10000>, + <0 0x0b490000 0 0x10000>; + reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; + interrupts = , + ; + interrupt-names = "hfi", "gmu"; + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>; + clock-names = "gmu", "cxo", "axi", "memnoc"; + power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>; + power-domain-names = "cx", "gx"; + iommus = <&adreno_smmu 5>; + operating-points-v2 = <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-level = ; + }; + }; + }; + + gpucc: clock-controller@5090000 { + compatible = "qcom,sc7180-gpucc"; + reg = <0 0x05090000 0 0x9000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + clock-names = "bi_tcxo", + "gcc_gpu_gpll0_clk_src", + "gcc_gpu_gpll0_div_clk_src"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + dma@10a2000 { + compatible = "qcom,sm7150-dcc", "qcom,dcc"; + reg = <0x0 0x010a2000 0x0 0x1000>, + <0x0 0x010ae000 0x0 0x2000>; + }; + + sdhc_1: mmc@7c4000 { + compatible = "qcom,sm7150-sdhci", "qcom,sdhci-msm-v5"; + reg = <0 0x007c4000 0 0x1000>, + <0 0x007c5000 0 0x1000>; + reg-names = "hc", "cqhci"; + + iommus = <&apps_smmu 0x340 0x0>; + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "core", "xo"; + + interconnects = <&aggre1_noc MASTER_EMMC QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_EMMC_CFG QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "sdhc-ddr", + "cpu-sdhc"; + + qcom,dll-config = <0x000f642c>; + qcom,ddr-config = <0x80040868>; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&sdhc1_opp_table>; + + bus-width = <8>; + non-removable; + supports-cqe; + + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + + status = "disabled"; + + sdhc1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <200000 100000>; + opp-avg-kBps = <100000 50000>; + }; + + opp-384000000 { + opp-hz = /bits/ 64 <384000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <2718822 1359411>; + opp-avg-kBps = <261438 300000>; + }; + }; + }; + + sdhc_2: mmc@8804000 { + compatible = "qcom,sm7150-sdhci", "qcom,sdhci-msm-v5"; + reg = <0 0x08804000 0 0x1000>; + + iommus = <&apps_smmu 0x2a0 0x0>; + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "core", "xo"; + + interconnects = <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "sdhc-ddr", + "cpu-sdhc"; + + qcom,dll-config = <0x0007642c>; + qcom,ddr-config = <0x80040868>; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&sdhc2_opp_table>; + + bus-width = <4>; + + status = "disabled"; + + sdhc2_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <120000 80000>; + opp-avg-kBps = <60000 40000>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_svs>; + opp-peak-kBps = <160000 100000>; + opp-avg-kBps = <80000 50000>; + }; + + opp-208000000 { + opp-hz = /bits/ 64 <208000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <200000 120000>; + opp-avg-kBps = <100000 60000>; + }; + }; + }; + + usb_1_hsphy: phy@88e2000 { + compatible = "qcom,sm7150-qusb2-phy", + "qcom,qusb2-v2-phy"; + reg = <0 0x088e2000 0 0x400>; + status = "disabled"; + #phy-cells = <0>; + clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "cfg_ahb", "ref"; + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + }; + + pmu@90b6300 { + compatible = "qcom,sm7150-cpu-bwmon", + "qcom,sdm845-bwmon"; + reg = <0 0x090b6300 0 0x600>; + + interrupts = ; + + interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; + + operating-points-v2 = <&cpu_bwmon_opp_table>; + + cpu_bwmon_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-0 { + opp-peak-kBps = <4577000>; + }; + + opp-1 { + opp-peak-kBps = <7110000>; + }; + + opp-2 { + opp-peak-kBps = <9155000>; + }; + + opp-3 { + opp-peak-kBps = <12298000>; + }; + + opp-4 { + opp-peak-kBps = <14236000>; + }; + }; + }; + + pmu@90cd000 { + compatible = "qcom,sm7150-llcc-bwmon", + "qcom,sc7280-llcc-bwmon"; + reg = <0 0x090cd000 0 0x1000>; + + interrupts = ; + + interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>; + + operating-points-v2 = <&llcc_bwmon_opp_table>; + + llcc_bwmon_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-0 { + opp-peak-kBps = <762000>; + }; + + opp-1 { + opp-peak-kBps = <1144000>; + }; + + opp-2 { + opp-peak-kBps = <1720000>; + }; + + opp-3 { + opp-peak-kBps = <2086000>; + }; + + opp-4 { + opp-peak-kBps = <2597000>; + }; + + opp-5 { + opp-peak-kBps = <2929000>; + }; + + opp-6 { + opp-peak-kBps = <3879000>; + }; + + opp-7 { + opp-peak-kBps = <5161000>; + }; + + opp-8 { + opp-peak-kBps = <5931000>; + }; + + opp-9 { + opp-peak-kBps = <6881000>; + }; + }; + }; + + compute_noc: interconnect@80a8000 { + compatible = "qcom,sm7150-compute-noc"; + reg = <0 0x080a8000 0 0x1400>; + + qcom,bcm-voters = <&apps_bcm_voter>; + + #interconnect-cells = <2>; + }; + + dc_noc: interconnect@9160000 { + compatible = "qcom,sm7150-dc-noc"; + reg = <0 0x09160000 0 0x3200>; + + qcom,bcm-voters = <&apps_bcm_voter>; + + #interconnect-cells = <2>; + }; + + system-cache-controller@9200000 { + compatible = "qcom,sm7150-llcc"; + reg = <0 0x09200000 0 0x50000>, + <0 0x09280000 0 0x50000>, + <0 0x09600000 0 0x50000>; + reg-names = "llcc0_base", "llcc1_base", + "llcc_broadcast_base"; + interrupts = ; + }; + + gem_noc: interconnect@9680000 { + compatible = "qcom,sm7150-gem-noc"; + reg = <0 0x09680000 0 0x3e200>; + + qcom,bcm-voters = <&apps_bcm_voter>; + + #interconnect-cells = <2>; + }; + + usb_1: usb@a6f8800 { + compatible = "qcom,sm7150-dwc3", "qcom,dwc3"; + reg = <0 0x0a6f8800 0 0x400>; + status = "disabled"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + dma-ranges; + + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi"; + + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, <150000000>; + + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 9 IRQ_TYPE_EDGE_BOTH>, + <&pdc 8 IRQ_TYPE_EDGE_BOTH>, + <&pdc 6 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "hs_phy_irq", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; + + power-domains = <&gcc USB30_PRIM_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + + wakeup-source; + + interconnects = <&aggre2_noc MASTER_USB3 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_USB3 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "usb-ddr", + "apps-usb"; + + usb_1_dwc3: usb@a600000 { + compatible = "snps,dwc3"; + reg = <0 0x0a600000 0 0xe000>; + interrupts = ; + iommus = <&apps_smmu 0x540 0>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + phys = <&usb_1_hsphy>; + phy-names = "usb2-phy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usb_1_dwc3_hs: endpoint { }; + }; + + port@1 { + reg = <1>; + usb_1_dwc3_ss: endpoint { }; + }; + }; + }; + }; + + cci0: cci@ac4a000 { + compatible = "qcom,sm7150-cci", "qcom,msm8996-cci"; + reg = <0 0x0ac4a000 0 0x1000>; + interrupts = ; + power-domains = <&camcc TITAN_TOP_GDSC>; + + clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, + <&camcc CAMCC_SLOW_AHB_CLK_SRC>, + <&camcc CAMCC_CPAS_AHB_CLK>, + <&camcc CAMCC_CCI_0_CLK>, + <&camcc CAMCC_CCI_0_CLK_SRC>; + clock-names = "camnoc_axi", + "slow_ahb_src", + "cpas_ahb", + "cci", + "cci_src"; + + pinctrl-0 = <&cci0_default &cci1_default>; + pinctrl-1 = <&cci0_sleep &cci1_sleep>; + pinctrl-names = "default", "sleep"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + cci0_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci0_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + cci1: cci@ac4b000 { + compatible = "qcom,sm7150-cci", "qcom,msm8996-cci"; + reg = <0 0x0ac4b000 0 0x1000>; + interrupts = ; + power-domains = <&camcc TITAN_TOP_GDSC>; + + clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, + <&camcc CAMCC_SLOW_AHB_CLK_SRC>, + <&camcc CAMCC_CPAS_AHB_CLK>, + <&camcc CAMCC_CCI_1_CLK>, + <&camcc CAMCC_CCI_1_CLK_SRC>; + clock-names = "camnoc_axi", + "slow_ahb_src", + "cpas_ahb", + "cci", + "cci_src"; + + pinctrl-0 = <&cci2_default>; + pinctrl-1 = <&cci2_sleep>; + pinctrl-names = "default", "sleep"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + cci1_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + venus: video-codec@aa00000 { + compatible = "qcom,sm7150-venus"; + reg = <0 0x0aa00000 0 0xff000>; + interrupts = ; + power-domains = <&videocc VENUS_GDSC>, + <&videocc VCODEC0_GDSC>, + <&videocc VCODEC1_GDSC>, + <&rpmhpd RPMHPD_CX>; + power-domain-names = "venus", "vcodec0", + "vcodec1", "cx"; + operating-points-v2 = <&venus_opp_table>; + clocks = <&videocc VIDEOCC_MVSC_CORE_CLK>, + <&videocc VIDEOCC_VENUS_AHB_CLK>, + <&videocc VIDEOCC_MVSC_CTL_AXI_CLK>, + <&videocc VIDEOCC_MVS0_CORE_CLK>, + <&videocc VIDEOCC_MVS0_AXI_CLK>, + <&videocc VIDEOCC_MVS1_CORE_CLK>, + <&videocc VIDEOCC_MVS1_AXI_CLK>; + clock-names = "core", "iface", "bus", + "vcodec0_core", "vcodec0_bus", + "vcodec1_core", "vcodec1_bus"; + + interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_VENUS_CFG 0>, + <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI_CH0 0>; + interconnect-names = "cpu-cfg", "video-mem"; + + iommus = <&apps_smmu 0x1080 0x60>; + memory-region = <&venus_mem>; + + status = "disabled"; + + video-decoder { + compatible = "venus-decoder"; + }; + + video-encoder { + compatible = "venus-encoder"; + }; + + venus_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-240000000 { + opp-hz = /bits/ 64 <240000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-338000000 { + opp-hz = /bits/ 64 <338000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-365000000 { + opp-hz = /bits/ 64 <365000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-444000000 { + opp-hz = /bits/ 64 <444000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + + opp-533000000 { + opp-hz = /bits/ 64 <533000000>; + required-opps = <&rpmhpd_opp_turbo>; + }; + }; + }; + + videocc: clock-controller@ab00000 { + compatible = "qcom,sm7150-videocc"; + reg = <0 0x0ab00000 0 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>; + power-domains = <&rpmhpd RPMHPD_CX>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + camss: camss@ace0000 { + compatible = "qcom,sm7150-camss"; + reg = <0 0x0ace0000 0 0x2000>, + <0 0x0ace2000 0 0x2000>, + <0 0x0ace4000 0 0x2000>, + <0 0x0ace6000 0 0x2000>, + <0 0x0acaf000 0 0x5200>, + <0 0x0acb6000 0 0x5200>, + <0 0x0acc4000 0 0x4000>; + reg-names = "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "vfe0", + "vfe1", + "vfe_lite"; + + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "csid0", + "csid1", + "vfe0", + "vfe1", + "vfe_lite"; + + power-domains = <&camcc IFE_0_GDSC>, + <&camcc IFE_1_GDSC>, + <&camcc TITAN_TOP_GDSC>; + + clocks = <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&gcc GCC_CAMERA_SF_AXI_CLK>, + <&camcc CAMCC_CAMNOC_AXI_CLK>, + <&camcc CAMCC_CAMNOC_AXI_CLK_SRC>, + <&camcc CAMCC_CPAS_AHB_CLK>, + <&camcc CAMCC_CPHY_RX_CLK_SRC>, + <&camcc CAMCC_CSIPHY0_CLK>, + <&camcc CAMCC_CSI0PHYTIMER_CLK>, + <&camcc CAMCC_CSI0PHYTIMER_CLK_SRC>, + <&camcc CAMCC_CSIPHY1_CLK>, + <&camcc CAMCC_CSI1PHYTIMER_CLK>, + <&camcc CAMCC_CSI1PHYTIMER_CLK_SRC>, + <&camcc CAMCC_CSIPHY2_CLK>, + <&camcc CAMCC_CSI2PHYTIMER_CLK>, + <&camcc CAMCC_CSI2PHYTIMER_CLK_SRC>, + <&camcc CAMCC_CSIPHY3_CLK>, + <&camcc CAMCC_CSI3PHYTIMER_CLK>, + <&camcc CAMCC_CSI3PHYTIMER_CLK_SRC>, + <&camcc CAMCC_SLOW_AHB_CLK_SRC>, + <&camcc CAMCC_IFE_0_AXI_CLK>, + <&camcc CAMCC_IFE_0_CLK>, + <&camcc CAMCC_IFE_0_CLK_SRC>, + <&camcc CAMCC_IFE_0_CPHY_RX_CLK>, + <&camcc CAMCC_IFE_0_CSID_CLK>, + <&camcc CAMCC_IFE_0_CSID_CLK_SRC>, + <&camcc CAMCC_IFE_1_AXI_CLK>, + <&camcc CAMCC_IFE_1_CLK>, + <&camcc CAMCC_IFE_1_CLK_SRC>, + <&camcc CAMCC_IFE_1_CPHY_RX_CLK>, + <&camcc CAMCC_IFE_1_CSID_CLK>, + <&camcc CAMCC_IFE_1_CSID_CLK_SRC>, + <&camcc CAMCC_IFE_LITE_CLK>, + <&camcc CAMCC_IFE_LITE_CLK_SRC>, + <&camcc CAMCC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAMCC_IFE_LITE_CSID_CLK>, + <&camcc CAMCC_IFE_LITE_CSID_CLK_SRC>; + + clock-names = "cam_hf_axi", + "cam_sf_axi", + "camnoc_axi", + "camnoc_axi_src", + "cpas_ahb", + "cphy_rx_src", + "csiphy0", + "csiphy0_timer", + "csiphy0_timer_src", + "csiphy1", + "csiphy1_timer", + "csiphy1_timer_src", + "csiphy2", + "csiphy2_timer", + "csiphy2_timer_src", + "csiphy3", + "csiphy3_timer", + "csiphy3_timer_src", + "slow_ahb_src", + "vfe0_axi", + "vfe0", + "vfe0_src", + "vfe0_cphy_rx", + "vfe0_csid", + "vfe0_csid_src", + "vfe1_axi", + "vfe1", + "vfe1_src", + "vfe1_cphy_rx", + "vfe1_csid", + "vfe1_csid_src", + "vfe_lite", + "vfe_lite_src", + "vfe_lite_cphy_rx", + "vfe_lite_csid", + "vfe_lite_csid_src"; + + iommus = <&apps_smmu 0x900 0x460>, + <&apps_smmu 0xD00 0x460>, + <&apps_smmu 0x880 0x460>, + <&apps_smmu 0xC80 0x460>, + <&apps_smmu 0x820 0x440>, + <&apps_smmu 0xC20 0x440>, + <&apps_smmu 0x920 0x460>, + <&apps_smmu 0xD20 0x460>, + <&apps_smmu 0x8A0 0x460>, + <&apps_smmu 0xCA0 0x460>, + <&apps_smmu 0x940 0x460>, + <&apps_smmu 0xD40 0x460>, + <&apps_smmu 0x8C0 0x460>, + <&apps_smmu 0xCC0 0x460>; + + /*interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_CAMERA_CFG 0>, + <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI_CH0 0>, + <&mmss_noc MASTER_CAMNOC_SF 0 &mc_virt SLAVE_EBI_CH0 0>, + <&mmss_noc MASTER_CAMNOC_ICP 0 &mc_virt SLAVE_EBI_CH0 0>; + interconnect-names = "cam_ahb", + "cam_hf_0_mnoc", + "cam_sf_0_mnoc", + "cam_sf_icp_mnoc";*/ + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + }; + + port@2 { + reg = <2>; + }; + + port@3 { + reg = <3>; + }; + + /*port@4 { + reg = <4>; + }; + + port@5 { + reg = <5>; + };*/ + }; + }; + + camcc: clock-controller@ad00000 { + compatible = "qcom,sm7150-camcc"; + reg = <0 0x0ad00000 0 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + power-domains = <&rpmhpd RPMHPD_CX>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + mdss: display-subsystem@ae00000 { + compatible = "qcom,sm7150-mdss"; + reg = <0 0x0ae00000 0 0x1000>; + reg-names = "mdss"; + + power-domains = <&dispcc MDSS_GDSC>; + + clocks = <&dispcc DISPCC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISPCC_MDSS_MDP_CLK>; + clock-names = "iface", "bus", "nrt_bus", "core"; + + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + interconnects = <&mmss_noc MASTER_MDP_PORT0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc MASTER_MDP_PORT1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "mdp0-mem", + "mdp1-mem", + "cpu-cfg"; + + iommus = <&apps_smmu 0x800 0x440>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + mdp: display-controller@ae01000 { + compatible = "qcom,sm7150-dpu"; + reg = <0 0x0ae01000 0 0x8f000>, + <0 0x0aeb0000 0 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISPCC_MDSS_AHB_CLK>, + <&dispcc DISPCC_MDSS_ROT_CLK>, + <&dispcc DISPCC_MDSS_MDP_LUT_CLK>, + <&dispcc DISPCC_MDSS_MDP_CLK>, + <&dispcc DISPCC_MDSS_VSYNC_CLK>; + clock-names = "bus", "iface", "rot", "lut", + "core", "vsync"; + assigned-clocks = <&dispcc DISPCC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd RPMHPD_CX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&mdss_dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf2_out: endpoint { + remote-endpoint = <&mdss_dsi1_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-19200000 { + opp-hz = /bits/ 64 <19200000>; + required-opps = <&rpmhpd_opp_min_svs>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-344000000 { + opp-hz = /bits/ 64 <344000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-430000000 { + opp-hz = /bits/ 64 <430000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + mdss_dsi0: dsi@ae94000 { + compatible = "qcom,sm7150-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae94000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc DISPCC_MDSS_BYTE0_CLK>, + <&dispcc DISPCC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISPCC_MDSS_PCLK0_CLK>, + <&dispcc DISPCC_MDSS_ESC0_CLK>, + <&dispcc DISPCC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISPCC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISPCC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>; + + operating-points-v2 = <&mdss_dsi_opp_table>; + power-domains = <&rpmhpd RPMHPD_CX>; + + phys = <&mdss_dsi0_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dsi0_out: endpoint { + }; + }; + }; + }; + + mdss_dsi0_phy: phy@ae94400 { + compatible = "qcom,dsi-phy-10nm"; + reg = <0 0x0ae94400 0 0x200>, + <0 0x0ae94600 0 0x280>, + <0 0x0ae94a00 0 0x1e0>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISPCC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + + mdss_dsi1: dsi@ae96000 { + compatible = "qcom,sm7150-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae96000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <5>; + + clocks = <&dispcc DISPCC_MDSS_BYTE1_CLK>, + <&dispcc DISPCC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISPCC_MDSS_PCLK1_CLK>, + <&dispcc DISPCC_MDSS_ESC1_CLK>, + <&dispcc DISPCC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISPCC_MDSS_BYTE1_CLK_SRC>, + <&dispcc DISPCC_MDSS_PCLK1_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi1_phy 0>, + <&mdss_dsi1_phy 1>; + + operating-points-v2 = <&mdss_dsi_opp_table>; + power-domains = <&rpmhpd RPMHPD_CX>; + + phys = <&mdss_dsi1_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dsi1_in: endpoint { + remote-endpoint = <&dpu_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dsi1_out: endpoint { + }; + }; + }; + }; + + mdss_dsi1_phy: phy@ae96400 { + compatible = "qcom,dsi-phy-10nm"; + reg = <0 0x0ae96400 0 0x200>, + <0 0x0ae96600 0 0x280>, + <0 0x0ae96a00 0 0x1e0>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISPCC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + }; + + dispcc: clock-controller@af00000 { + compatible = "qcom,sm7150-dispcc"; + reg = <0 0x0af00000 0 0x200000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&gcc GCC_DISP_GPLL0_CLK_SRC>, + <&sleep_clk>, + <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>, + <&mdss_dsi1_phy 0>, + <&mdss_dsi1_phy 1>, + <0>, //dp + <0>; + power-domains = <&rpmhpd RPMHPD_CX>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + status = "disabled"; + }; + + pdc: interrupt-controller@b220000 { + compatible = "qcom,sm7150-pdc", "qcom,pdc"; + reg = <0 0x0b220000 0 0x30000>; + qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + + tsens0: thermal-sensor@c263000 { + compatible = "qcom,sm7150-tsens","qcom,tsens-v2"; + reg = <0 0x0c263000 0 0x1ff>, /* TM */ + <0 0x0c222000 0 0x1ff>; /* SROT */ + #qcom,sensors = <15>; + interrupts = , + ; + interrupt-names = "uplow","critical"; + #thermal-sensor-cells = <1>; + }; + + tsens1: thermal-sensor@c265000 { + compatible = "qcom,sm7150-tsens","qcom,tsens-v2"; + reg = <0 0x0c265000 0 0x1ff>, /* TM */ + <0 0x0c223000 0 0x1ff>; /* SROT */ + #qcom,sensors = <10>; + interrupts = , + ; + interrupt-names = "uplow","critical"; + #thermal-sensor-cells = <1>; + }; + + aoss_qmp: power-management@c300000 { + compatible = "qcom,sm7150-aoss-qmp", "qcom,aoss-qmp"; + reg = <0 0x0c300000 0 0x400>; + interrupts = ; + mboxes = <&apss_shared 0>; + + #clock-cells = <0>; + }; + + sram@c3f0000 { + compatible = "qcom,rpmh-stats"; + reg = <0 0x0c3f0000 0 0x400>; + }; + + spmi_bus: spmi@c440000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0 0x0c440000 0 0x0001100>, + <0 0x0c600000 0 0x2000000>, + <0 0x0e600000 0 0x0100000>, + <0 0x0e700000 0 0x00a0000>, + <0 0x0c40a000 0 0x0026000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + }; + + sram@146aa000 { + compatible = "qcom,sm7150-imem", "syscon", "simple-mfd"; + reg = <0 0x146aa000 0 0x2000>; + + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0 0 0x146aa000 0x2000>; + + pil-reloc@94c { + compatible = "qcom,pil-reloc-info"; + reg = <0x94c 0xc8>; + }; + }; + + apps_smmu: iommu@15000000 { + compatible = "qcom,sm7150-smmu-500", "qcom,smmu-500", + "arm,mmu-500"; + reg = <0 0x15000000 0 0x100000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + dma-coherent; + }; + + intc: interrupt-controller@17a00000 { + compatible = "arm,gic-v3"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0 0x17a00000 0 0x10000>, /* GICD */ + <0 0x17a60000 0 0x100000>; /* GICR * 8 */ + interrupts = ; + + msi-controller@17a40000 { + compatible = "arm,gic-v3-its"; + msi-controller; + #msi-cells = <1>; + reg = <0 0x17a40000 0 0x20000>; + status = "disabled"; + }; + }; + + apss_shared: mailbox@17c00000 { + compatible = "qcom,sm7150-apss-shared", + "qcom,sdm845-apss-shared"; + reg = <0 0x17c00000 0 0x1000>; + #mbox-cells = <1>; + }; + + watchdog@17c10000 { + compatible = "qcom,apss-wdt-sm7150", "qcom,kpss-wdt"; + reg = <0 0x17c10000 0 0x1000>; + clocks = <&sleep_clk>; + interrupts = ; + }; + + sound: sound { }; + + timer@17c20000 { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0x20000000>; + compatible = "arm,armv7-timer-mem"; + reg = <0 0x17c20000 0 0x1000>; + + frame@17c21000 { + frame-number = <0>; + interrupts = , + ; + reg = <0x17c21000 0x1000>, + <0x17c22000 0x1000>; + }; + + frame@17c23000 { + frame-number = <1>; + interrupts = ; + reg = <0x17c23000 0x1000>; + status = "disabled"; + }; + + frame@17c25000 { + frame-number = <2>; + interrupts = ; + reg = <0x17c25000 0x1000>; + status = "disabled"; + }; + + frame@17c27000 { + frame-number = <3>; + interrupts = ; + reg = <0x17c27000 0x1000>; + status = "disabled"; + }; + + frame@17c29000 { + frame-number = <4>; + interrupts = ; + reg = <0x17c29000 0x1000>; + status = "disabled"; + }; + + frame@17c2b000 { + frame-number = <5>; + interrupts = ; + reg = <0x17c2b000 0x1000>; + status = "disabled"; + }; + + frame@17c2d000 { + frame-number = <6>; + interrupts = ; + reg = <0x17c2d000 0x1000>; + status = "disabled"; + }; + }; + + apps_rsc: rsc@18200000 { + compatible = "qcom,rpmh-rsc"; + reg = <0 0x18200000 0 0x10000>, + <0 0x18210000 0 0x10000>, + <0 0x18220000 0 0x10000>; + reg-names = "drv-0", + "drv-1", + "drv-2"; + + interrupts = , + , + ; + + power-domains = <&cluster_pd>; + + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <2>; + qcom,tcs-config = , , + , ; + + label = "apps_rsc"; + + apps_bcm_voter: bcm-voter { + compatible = "qcom,bcm-voter"; + }; + + rpmhcc: clock-controller { + compatible = "qcom,sm7150-rpmh-clk", + "qcom,sc7180-rpmh-clk"; + + clocks = <&xo_board>; + clock-names = "xo"; + + #clock-cells = <1>; + }; + + rpmhpd: power-controller { + compatible = "qcom,sm7150-rpmhpd"; + + operating-points-v2 = <&rpmhpd_opp_table>; + + #power-domain-cells = <1>; + + rpmhpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmhpd_opp_ret: opp1 { + opp-level = ; + }; + + rpmhpd_opp_min_svs: opp2 { + opp-level = ; + }; + + rpmhpd_opp_low_svs: opp3 { + opp-level = ; + }; + + rpmhpd_opp_svs: opp4 { + opp-level = ; + }; + + rpmhpd_opp_svs_l1: opp5 { + opp-level = ; + }; + + rpmhpd_opp_svs_l2: opp6 { + opp-level = ; + }; + + rpmhpd_opp_nom: opp7 { + opp-level = ; + }; + + rpmhpd_opp_nom_l1: opp8 { + opp-level = ; + }; + + rpmhpd_opp_nom_l2: opp9 { + opp-level = ; + }; + + rpmhpd_opp_turbo: opp10 { + opp-level = ; + }; + + rpmhpd_opp_turbo_l1: opp11 { + opp-level = ; + }; + }; + }; + }; + + osm_l3: interconnect@18321000 { + compatible = "qcom,sm7150-osm-l3", "qcom,osm-l3"; + reg = <0 0x18321000 0 0x1400>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + + #interconnect-cells = <1>; + }; + + cpufreq_hw: cpufreq@18323000 { + compatible = "qcom,sm7150-cpufreq-hw", + "qcom,cpufreq-hw"; + reg = <0 0x18323000 0 0x1400>, + <0 0x18325800 0 0x1400>; + reg-names = "freq-domain0", + "freq-domain1"; + + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + + #freq-domain-cells = <1>; + #clock-cells = <1>; + }; + + wifi: wifi@18800000 { + compatible = "qcom,wcn3990-wifi"; + reg = <0 0x18800000 0 0x800000>; + reg-names = "membase"; + iommus = <&apps_smmu 0x240 0x1>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + memory-region = <&wlan_msa_mem>; + + status = "disabled"; + }; + + lpass_tlmm: pinctrl@62b52000 { + compatible = "qcom,sm7150-lpass-lpi-pinctrl"; + reg = <0 0x62b52000 0 0xe000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpass_tlmm 0 0 14>; + + clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "core"; + + tx_swr_active: tx-swr-active-state { + clk-pins { + pins = "gpio0"; + function = "swr_tx_clk"; + drive-strength = <8>; + bias-bus-hold; + }; + + data1-pins { + pins = "gpio1"; + function = "swr_tx_data"; + drive-strength = <8>; + bias-bus-hold; + }; + + data2-pins { + pins = "gpio2"; + function = "swr_tx_data"; + drive-strength = <8>; + bias-bus-hold; + }; + }; + + tx_swr_sleep: tx-swr-sleep-state { + clk-pins { + pins = "gpio0"; + function = "swr_tx_clk"; + drive-strength = <2>; + bias-bus-hold; + }; + + data1-pins { + pins = "gpio1"; + function = "swr_tx_data"; + drive-strength = <2>; + bias-bus-hold; + }; + + data2-pins { + pins = "gpio2"; + function = "swr_tx_data"; + drive-strength = <2>; + bias-bus-hold; + }; + }; + + rx_swr_active: rx-swr-active-state { + clk-pins { + pins = "gpio3"; + function = "swr_rx_clk"; + drive-strength = <8>; + bias-bus-hold; + }; + + data-pins { + pins = "gpio4", "gpio5"; + function = "swr_rx_data"; + drive-strength = <8>; + bias-bus-hold; + }; + }; + + + rx_swr_sleep: rx-swr-sleep-state { + clk-pins { + pins = "gpio3"; + function = "swr_rx_clk"; + drive-strength = <2>; + bias-bus-hold; + }; + + data-pins { + pins = "gpio4", "gpio5"; + function = "swr_rx_data"; + drive-strength = <2>; + bias-bus-hold; + }; + }; + + wcd9375_reset_active: wcd9375-reset-active-state { + pins = "gpio6"; + function = "cdc_pdm_rx"; + drive-strength = <16>; + output-high; + }; + + wcd9375_reset_sleep: wcd9375-reset-sleep-state { + pins = "gpio6"; + function = "cdc_pdm_rx"; + drive-strength = <16>; + bias-disable; + output-low; + }; + + dmic01_active: dmic01-active-state { + clk-pins { + pins = "gpio8"; + function = "dmic1_clk"; + drive-strength = <8>; + output-high; + }; + + data-pins { + pins = "gpio9"; + function = "dmic1_data"; + drive-strength = <8>; + input-enable; + }; + }; + + dmic01_sleep: dmic01-sleep-state { + clk-pins { + pins = "gpio8"; + function = "dmic1_clk"; + drive-strength = <2>; + bias-disable; + }; + + data-pins { + pins = "gpio9"; + function = "dmic1_data"; + drive-strength = <2>; + pull-down; + input-enable; + }; + }; + + dmic23_active: dmic23-active-state { + clk-pins { + pins = "gpio10"; + function = "dmic2_clk"; + drive-strength = <8>; + output-high; + }; + + data-pins { + pins = "gpio11"; + function = "dmic2_data"; + drive-strength = <8>; + input-enable; + }; + }; + + dmic23_sleep: dmic23-sleep-state { + clk-pins { + pins = "gpio10"; + function = "dmic2_clk"; + drive-strength = <2>; + bias-disable; + output-low; + }; + + data-pins { + pins = "gpio11"; + function = "dmic2_data"; + drive-strength = <2>; + pull-down; + input-enable; + }; + }; + }; + }; + + thermal-zones { + cpu0_thermal: cpu0-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens0 1>; + + trips { + cpu0_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu0_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu0_crit: cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu0_alert0>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu0_alert1>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu1_thermal: cpu1-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens0 2>; + + trips { + cpu1_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu1_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu1_crit: cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu1_alert0>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu1_alert1>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu2_thermal: cpu2-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens0 3>; + + trips { + cpu2_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu2_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu2_crit: cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu2_alert0>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu2_alert1>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu3_thermal: cpu3-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens0 4>; + + trips { + cpu3_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu3_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu3_crit: cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu3_alert0>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu3_alert1>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu4_thermal: cpu4-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens0 5>; + + trips { + cpu4_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu4_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu4_crit: cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu4_alert0>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu4_alert1>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu5_thermal: cpu5-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens0 6>; + + trips { + cpu5_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu5_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu5_crit: cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu5_alert0>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu5_alert1>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu6_thermal: cpu6-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens0 9>; + + trips { + cpu6_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu6_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu6_crit: cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu6_alert0>; + cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu6_alert1>; + cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu7_thermal: cpu7-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens0 10>; + + trips { + cpu7_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu7_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu7_crit: cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu7_alert0>; + cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu7_alert1>; + cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu8_thermal: cpu8-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens0 11>; + + trips { + cpu8_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu8_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu8_crit: cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu8_alert0>; + cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu8_alert1>; + cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu9_thermal: cpu9-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens0 12>; + + trips { + cpu9_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu9_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu9_crit: cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu9_alert0>; + cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu9_alert1>; + cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + aoss0-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens0 0>; + + trips { + aoss0_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + aoss0_crit: aoss0-crit { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpuss0-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens0 7>; + + trips { + cpuss0_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + cpuss0_crit: cluster0-crit { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpuss1-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens0 8>; + + trips { + cpuss1_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + cpuss1_crit: cluster0-crit { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + gpuss0-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens0 13>; + + trips { + gpuss0_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + gpuss0_crit: gpuss0-crit { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&gpuss0_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gpuss1-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens0 14>; + + trips { + gpuss1_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + gpuss1_crit: gpuss1-crit { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&gpuss1_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + aoss1-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens1 0>; + + trips { + aoss1_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + aoss1_crit: aoss1-crit { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cwlan-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens1 1>; + + trips { + cwlan_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + cwlan_crit: cwlan-crit { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + audio-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens1 2>; + + trips { + audio_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + audio_crit: audio-crit { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + ddr-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens1 3>; + + trips { + ddr_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + ddr_crit: ddr-crit { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + q6-hvx-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens1 4>; + + trips { + q6_hvx_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + q6_hvx_crit: q6-hvx-crit { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + camera-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens1 5>; + + trips { + camera_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + camera_crit: camera-crit { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + mdm-core-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens1 6>; + + trips { + mdm_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + mdm_crit: mdm-crit { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + mdm-dsp-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens1 7>; + + trips { + mdm_dsp_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + mdm_dsp_crit: mdm-dsp-crit { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + npu-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens1 8>; + + trips { + npu_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + npu_crit: npu-crit { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + video-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens1 9>; + + trips { + video_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + video_crit: video-crit { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + + interrupts = , + , + , + ; + }; +}; diff --git a/arch/arm64/configs/sm7150.config b/arch/arm64/configs/sm7150.config new file mode 100644 index 00000000000000..d593c23e0ef17e --- /dev/null +++ b/arch/arm64/configs/sm7150.config @@ -0,0 +1,824 @@ +# Qualcomm Snapdragon SM7150 config fragment +CONFIG_LOCALVERSION="-sm7150" +# CONFIG_LOCALVERSION_AUTO is not set + +# Common for SM7150 devices +CONFIG_NFC_SHDLC=y +CONFIG_NFC_NXP_NCI=m +CONFIG_NFC_NXP_NCI_I2C=m +CONFIG_TOUCHSCREEN_GOODIX_GTX8=m +CONFIG_TOUCHSCREEN_ST_FTS_V521=m +CONFIG_INPUT_AW8695_HAPTICS=m +CONFIG_BATTERY_QCOM_QG=m +CONFIG_TYPEC_MUX_FSA4480=m + +# Google Pixel 4a (Sunfish) +CONFIG_DRM_PANEL_SAMSUNG_AMS581VF01=m +CONFIG_SND_SOC_RT5514=m +CONFIG_SND_SOC_RT5514_SPI=m +CONFIG_SND_SOC_CS35L41_I2C=m +CONFIG_PAC1934=m +CONFIG_REGULATOR_SLG51000=m +CONFIG_NFC_ST21NFCA_I2C=m + +# Xiaomi Mi 9T / Redmi K20 (Davinci) +CONFIG_DRM_PANEL_SAMSUNG_AMS639RQ08=m +CONFIG_SND_SOC_TFA9872=m +CONFIG_VIDEO_S5K3L6XX=m +CONFIG_VIDEO_OV8856=m + +# Xiaomi Mi Note 10 (Tucana) and Mi Note 10 Lite (Toco) +CONFIG_DRM_PANEL_VISIONOX_G2647FB105=m +CONFIG_INPUT_DRV260X_HAPTICS=m +CONFIG_LEDS_AW3644=m + +# Xiaomi Mi 11 Lite 4G (Courbet) +CONFIG_DRM_PANEL_K9A_36_02_0A=m + +# Xiaomi POCO X3 NFC (Surya) +CONFIG_TOUCHSCREEN_NT36XXX_SPI=m +CONFIG_DRM_PANEL_HUAXING_NT36672C=m +CONFIG_DRM_PANEL_TIANMA_NT36672C=m +CONFIG_SND_SOC_TAS2562=m + +# Xiaomi Redmi Note 10 Pro (Sweet) +CONFIG_DRM_PANEL_K6_38_0C_0A=m + +# Xiaomi Redmi Note 12 Pro (Sweet_k6a) +CONFIG_BATTERY_BQ27XXX=m +CONFIG_BATTERY_BQ27XXX_I2C=m +CONFIG_DRM_PANEL_K6_38_0E_0B=m + +# SM7150 SoC +CONFIG_INTERCONNECT_QCOM_OSM_L3=y +CONFIG_INTERCONNECT_QCOM_SM7150=y +CONFIG_PINCTRL_SM7150=y +CONFIG_SC_GPUCC_7180=y +CONFIG_SM_CAMCC_7150=y +CONFIG_SM_DISPCC_7150=y +CONFIG_SM_GCC_7150=y +CONFIG_SM_VIDEOCC_7150=y + +# Qualcomm SoC drivers +CONFIG_QCOM_LLCC=y +CONFIG_QCOM_OCMEM=y +CONFIG_QCOM_RMTFS_MEM=y +CONFIG_QCOM_SOCINFO=y +CONFIG_QCOM_APR=y + +# Qualcomm TZ memory +CONFIG_QCOM_TZMEM_MODE_GENERIC=y + +# Console ramoops & USB debug +CONFIG_PSTORE=y +CONFIG_PSTORE_CONSOLE=y +CONFIG_PSTORE_PMSG=y +CONFIG_PSTORE_RAM=y +CONFIG_U_SERIAL_CONSOLE=y + +# Remoteproc +CONFIG_SLIMBUS=y +CONFIG_SLIM_QCOM_CTRL=y +CONFIG_SLIM_QCOM_NGD_CTRL=y +CONFIG_REMOTEPROC_CDEV=y + +# Graphics +CONFIG_FB_SIMPLE=y +CONFIG_DRM=y +CONFIG_DRM_DISPLAY_HELPER=y +CONFIG_DRM_MSM=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_QCOM_WLED=m + +# Power management +CONFIG_PM_AUTOSLEEP=y +CONFIG_PM_WAKELOCKS=y + +# I2C system bus drivers +CONFIG_I2C_QCOM_GENI=y + +# SPI Master Controller Drivers +CONFIG_SPI_QCOM_GENI=y + +# DMA Devices +CONFIG_QCOM_GPI_DMA=y + +# Input Device Drivers +#CONFIG_INPUT_UINPUT=m + +# Generic Driver Options +CONFIG_UEVENT_HELPER=y + +# MMC/SD/SDIO Host Controller Drivers +CONFIG_SCSI_UFS_QCOM=y + +# PHY Subsystem +CONFIG_PHY_QCOM_QMP=y +CONFIG_PHY_QCOM_QMP_COMBO=y +CONFIG_PHY_QCOM_QMP_UFS=y +CONFIG_PHY_QCOM_QMP_USB=y +CONFIG_PHY_QCOM_QUSB2=y +CONFIG_PHY_QCOM_USB_HS=y +CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2=y +CONFIG_PHY_QCOM_USB_SS=y + +# USB +CONFIG_USB_CONFIGFS=y +CONFIG_USB_CONFIGFS_F_HID=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y + +# USB Type-C +CONFIG_TYPEC=y +CONFIG_TYPEC_TCPM=y +CONFIG_TYPEC_QCOM_PMIC=y + +# REGULATOR +CONFIG_REGULATOR_QCOM_USB_VBUS=y +CONFIG_REGULATOR_VCTRL=n + +# Bluetooth device drivers +CONFIG_BT_RFCOMM=m +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=m +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HS=y +CONFIG_BT_LE=y + +# HID +CONFIG_HID_BATTERY_STRENGTH=y +CONFIG_HIDRAW=y + +# HID/Input +CONFIG_HID_GENERIC=m +CONFIG_UHID=m +CONFIG_USB_HID=m +CONFIG_INPUT_EVDEV=y +CONFIG_BT_HIDP=m +CONFIG_INPUT_JOYDEV=m + +# Sound +CONFIG_SND_SOC_WCD937X_SDW=m +CONFIG_SND_SOC_LPASS_RX_MACRO=m +CONFIG_SND_SOC_LPASS_TX_MACRO=m + +# LED Triggers +CONFIG_LEDS_TRIGGER_ONESHOT=y +CONFIG_LEDS_TRIGGER_BACKLIGHT=y +CONFIG_LEDS_TRIGGER_ACTIVITY=y + +# Misc useful things +CONFIG_POWER_RESET_QCOM_PON=y +CONFIG_SCHED_CLUSTER=y +CONFIG_SCSI_SCAN_ASYNC=y +CONFIG_BLK_DEV_RAM=y + +# Needed for mounting userdata on android +CONFIG_QFMT_V2=y + +# Anbox +CONFIG_BRIDGE_NETFILTER=y +CONFIG_CHECKPOINT_RESTORE=y +CONFIG_PACKET_DIAG=y +CONFIG_UNIX_DIAG=y +CONFIG_NETLINK_DIAG=m +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_ANDROID=y +CONFIG_ANDROID_BINDER_IPC=y +CONFIG_SQUASHFS_XATTR=y +CONFIG_SQUASHFS_LZ4=y +CONFIG_SQUASHFS_LZO=y +CONFIG_SQUASHFS_XZ=y + +# Waydroid +CONFIG_PSI=y + +# WLAN +CONFIG_QRTR=y + +# WLAN debugging +CONFIG_ATH10K_DEBUG=y +CONFIG_ATH10K_DEBUGFS=y +CONFIG_ATH10K_SPECTRAL=y + +CONFIG_NET_SCH_HTB=y +CONFIG_NET_SCH_PRIO=y +CONFIG_NET_SCH_MULTIQ=y + +# Debugging stuff +CONFIG_STACKTRACE=y + +# Firmware loading +CONFIG_FW_LOADER_COMPRESS=y +CONFIG_FW_LOADER_COMPRESS_XZ=n +CONFIG_FW_LOADER_COMPRESS_ZSTD=y + +#pmOS Related +CONFIG_VT=y +CONFIG_CRYPTO_XTS=y +CONFIG_TMPFS_XATTR=y +CONFIG_DM_CRYPT=y +CONFIG_BLK_DEV_DM=y +CONFIG_BINFMT_MISC=m + +CONFIG_NF_TABLES=m +CONFIG_NF_TABLES_INET=y +CONFIG_NFT_CT=m +CONFIG_NFT_COUNTER=m +CONFIG_NFT_LOG=m +CONFIG_NFT_LIMIT=m +CONFIG_NFT_MASQ=m +CONFIG_NFT_NAT=m +CONFIG_NFT_REJECT=m +CONFIG_NF_TABLES_IPV4=y +CONFIG_NF_TABLES_IPV6=y + +CONFIG_WIREGUARD=m +CONFIG_DRM_GUD=m + +# pmos containers kconfig +CONFIG_CGROUP_FREEZER=y +CONFIG_NETFILTER_XT_MATCH_IPVS=m +CONFIG_NETFILTER_XT_MARK=m +CONFIG_DUMMY=m +CONFIG_BLK_DEV_THROTTLING=y +CONFIG_NET_CLS_CGROUP=m +CONFIG_RT_GROUP_SCHED=y +CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_IP_VS=m +CONFIG_IP_VS_NFCT=y +CONFIG_IP_VS_PROTO_TCP=y +CONFIG_IP_VS_PROTO_UDP=y +CONFIG_IP_VS_RR=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_CFS_BANDWIDTH=y +CONFIG_DM_THIN_PROVISIONING=y +CONFIG_VXLAN=m +CONFIG_CGROUP_NET_PRIO=y +CONFIG_IPVLAN=m + +# pmOS ZRAM kconfig +CONFIG_ZSMALLOC=m +CONFIG_ZSMALLOC_STAT=y +CONFIG_ZRAM=m +CONFIG_ZRAM_MEMORY_TRACKING=y +CONFIG_CRYPTO_LZ4=m +CONFIG_LZ4_COMPRESS=m +CONFIG_CRYPTO_LZO=m +CONFIG_CRYPTO_ZSTD=m + +# pmOS iwd kconfig +CONFIG_CRYPTO_USER_API_HASH=m +CONFIG_CRYPTO_USER_API_SKCIPHER=m +CONFIG_KEY_DH_OPERATIONS=y +CONFIG_CRYPTO_KPP=y +CONFIG_PKCS8_PRIVATE_KEY_PARSER=y + +# LEDs +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_CLASS_FLASH=y +CONFIG_LEDS_QCOM_FLASH=y + +#Sony PlayStation controllers +CONFIG_HID_SONY=m +CONFIG_SONY_FF=y + +# Disable all unrelated stuffs afaik +CONFIG_ACPI=n +CONFIG_VIRTUALIZATION=n +CONFIG_PSTORE_DEFLATE_COMPRESS=n +CONFIG_HIBERNATION=n +CONFIG_FW_LOADER_USER_HELPER=n +CONFIG_FW_LOADER_USER_HELPER_FALLBACK=n +CONFIG_BLK_DEV_NVME=n +CONFIG_ATA=n +CONFIG_MTD=n +CONFIG_SRAM=n +CONFIG_MEGARAID_SAS=n +CONFIG_EEPROM_AT25=n +CONFIG_SCSI_MPT3SAS=n +CONFIG_BLK_DEV_MD=n +CONFIG_DM_MIRROR=n +CONFIG_DM_ZERO=n +CONFIG_EXT2_FS=n +CONFIG_EXT3_FS=n +CONFIG_BTRFS_FS=n +CONFIG_USB_DWC2=n +CONFIG_USB_CHIPIDEA=n +CONFIG_USB_MUSB_HDRC=n +CONFIG_USB_ISP1760=n +CONFIG_USB_HSIC_USB3503=n +CONFIG_USB_NET_PLUSB=n +CONFIG_TYPEC_FUSB302=n +CONFIG_TYPEC_MUX_NB7VPQ904M=n +CONFIG_EXTCON_PTN5150=n +CONFIG_REALTEK_PHY=n +CONFIG_NET_VENDOR_NI=n +CONFIG_NET_9P=n +CONFIG_CAN=n +CONFIG_BNX2X=n +CONFIG_MACB=n +CONFIG_IGB=n +CONFIG_IGBVF=n +CONFIG_SMC91X=n +CONFIG_MLX4_EN=n +CONFIG_MLX5_CORE=n +CONFIG_STMMAC_ETH=n +CONFIG_ATL1C=n +CONFIG_BRCMFMAC=n +CONFIG_WL18XX=n +CONFIG_WLCORE=n +CONFIG_ATH10K_PCI=n +CONFIG_NET_SCH_CBS=n +CONFIG_NET_SCH_ETF=n +CONFIG_NET_SCH_TAPRIO=n +CONFIG_NET_SCH_MQPRIO=n +CONFIG_NET_CLS_BASIC=n +CONFIG_NET_CLS_FLOWER=n +CONFIG_NET_CLS_ACT=n +CONFIG_NET_ACT_GACT=n +CONFIG_NET_ACT_MIRRED=n +CONFIG_NET_ACT_GATE=n +CONFIG_MDIO_BUS_MUX_MMIOREG=n +CONFIG_MDIO_BUS_MUX_MULTIPLEXER=n +CONFIG_GPIO_AGGREGATOR=n +CONFIG_GPIO_DWAPB=n +CONFIG_COMMON_CLK_XGENE=n +CONFIG_TCG_TPM=n +CONFIG_BATTERY_SBS=n +CONFIG_THUNDER_NIC_BGX=n +CONFIG_THUNDER_NIC_RGX=n +CONFIG_MDIO_THUNDER=n +CONFIG_HW_RANDOM_CAVIUM=n +CONFIG_EEPROM_AT24=n +CONFIG_NET_DSA=n +CONFIG_VITESSE_PHY=n +CONFIG_PCI_PASID=n +CONFIG_UACCE=n +CONFIG_NOP_USB_XCEIV=n +CONFIG_SURFACE_PLATFORMS=n +CONFIG_USB_CONN_GPIO=n +CONFIG_MICREL_PHY=n +CONFIG_COMMON_CLK_VC5=n +CONFIG_CRYPTO_DEV_CCREE=n +CONFIG_SND_SIMPLE_CARD=n +CONFIG_SND_SIMPLE_CARD_UTILS=n +CONFIG_SND_AUDIO_GRAPH_CARD=n +CONFIG_TYPEC_HD3SS3220=n +CONFIG_COMMON_CLK_CS2000_CP=n +CONFIG_PL330_DMA=n +CONFIG_NET_VENDOR_SOCIONEXT=n + +# Disable Native drivers +CONFIG_SENSORS_ARM_SCPI=n +CONFIG_SENSORS_LM90=n +CONFIG_SENSORS_INA2XX=n +CONFIG_SENSORS_LM75=n +CONFIG_SENSORS_PWM_FAN=n +CONFIG_SENSORS_INA3221=n +CONFIG_SENSORS_ISL29018=n + +# Disable Batteries +CONFIG_BATTERY_QCOM_BATTMGR=n +CONFIG_BATTERY_MAX17042=n + +# Disable Chargers +CONFIG_CHARGER_BQ25890=n +CONFIG_CHARGER_BQ25980=n +CONFIG_CHARGER_RK817=n + +# Disable MII PHY device drivers +CONFIG_AQUANTIA_PHY=n +CONFIG_MICROSEMI_PHY=n + +# Disable Multiplexer I2C Chip support +CONFIG_I2C_MUX_PCA954x=n + +# Disable pressure sensors +CONFIG_MPL3115=n + +# Disable Display Panels +CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=n +CONFIG_DRM_PANEL_ILITEK_ILI9882T=n +CONFIG_DRM_PANEL_LVDS=n +CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=n +CONFIG_DRM_PANEL_RAYDIUM_RM67191=n +CONFIG_DRM_PANEL_SITRONIX_ST7703=n +CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=n +CONFIG_DRM_PANEL_VISIONOX_VTDR6130=n + +# Disable I2C GPIO expanders +CONFIG_GPIO_MAX732X=n +CONFIG_GPIO_PCA953X=n + +# Disable Backlight & LCD device support +CONFIG_BACKLIGHT_LP855X=n + +# Disable IR I2C driver auto-selected by 'Autoselect ancillary drivers' +CONFIG_VIDEO_IMX219=n +CONFIG_VIDEO_IMX412=n +CONFIG_VIDEO_OV5640=n +CONFIG_VIDEO_OV5645=n + +# Disable Common SoC Audio options for Freescale CPUs: +CONFIG_SND_SOC_FSL_ASRC=n +CONFIG_SND_SOC_FSL_SAI=n +CONFIG_SND_SOC_FSL_AUDMIX=n +CONFIG_SND_SOC_FSL_SPDIF=n +CONFIG_SND_SOC_FSL_MICFIL=n + +# Disable Input Device Drivers +CONFIG_KEYBOARD_ADC=n +CONFIG_KEYBOARD_GPIO_POLLED=n +CONFIG_MOUSE_ELAN_I2C=n +CONFIG_TOUCHSCREEN_ATMEL_MXT=n +CONFIG_TOUCHSCREEN_GOODIX=n +CONFIG_TOUCHSCREEN_ELAN=n +CONFIG_TOUCHSCREEN_EDT_FT5X06=n + +# Disable I2C RTC drivers +CONFIG_RTC_DRV_DS1307=n +CONFIG_RTC_DRV_RK808=n +CONFIG_RTC_DRV_HYM8563=n +CONFIG_RTC_DRV_ISL1208=n +CONFIG_RTC_DRV_PCF85063=n +CONFIG_RTC_DRV_PCF85363=n +CONFIG_RTC_DRV_PCF8563=n +CONFIG_RTC_DRV_M41T80=n +CONFIG_RTC_DRV_BQ32K=n +CONFIG_RTC_DRV_RX8581=n +CONFIG_RTC_DRV_RV3028=n +CONFIG_RTC_DRV_RV8803=n + +# Disable SPI and I2C RTC drivers +CONFIG_RTC_DRV_DS3232=n +CONFIG_RTC_DRV_PCF2127=n + +# Disable on-CPU RTC drivers +CONFIG_RTC_DRV_PL031=n + +# Disable ARM errata workarounds via the alternatives framework +CONFIG_CAVIUM_ERRATUM_22375=n +CONFIG_CAVIUM_ERRATUM_23144=n +CONFIG_CAVIUM_ERRATUM_23154=n +CONFIG_CAVIUM_ERRATUM_27456=n +CONFIG_CAVIUM_ERRATUM_30115=n +CONFIG_CAVIUM_TX2_ERRATUM_219=n +CONFIG_FUJITSU_ERRATUM_010001=n +CONFIG_HISILICON_ERRATUM_161600802=n +CONFIG_NVIDIA_CARMEL_CNP_ERRATUM=n +CONFIG_ROCKCHIP_ERRATUM_3588001=n +CONFIG_SOCIONEXT_SYNQUACER_PREITS=n + +# Disable platforms +CONFIG_ARCH_ACTIONS=n +CONFIG_ARCH_SUNXI=n +CONFIG_ARCH_ALPINE=n +CONFIG_ARCH_APPLE=n +CONFIG_ARCH_BCM=n +CONFIG_ARCH_BCM2835=n +CONFIG_ARCH_BCM_IPROC=n +CONFIG_ARCH_BCMBCA=n +CONFIG_ARCH_BRCMSTB=n +CONFIG_ARCH_BERLIN=n +CONFIG_ARCH_BITMAIN=n +CONFIG_ARCH_EXYNOS=n +CONFIG_ARCH_SPARX5=n +CONFIG_ARCH_K3=n +CONFIG_ARCH_LG1K=n +CONFIG_ARCH_HISI=n +CONFIG_ARCH_KEEMBAY=n +CONFIG_ARCH_MEDIATEK=n +CONFIG_ARCH_MESON=n +CONFIG_ARCH_MVEBU=n +CONFIG_ARCH_NXP=n +CONFIG_ARCH_LAYERSCAPE=n +CONFIG_ARCH_MXC=n +CONFIG_ARCH_S32=n +CONFIG_ARCH_MA35=n +CONFIG_ARCH_NPCM=n +CONFIG_ARCH_REALTEK=n +CONFIG_ARCH_RENESAS=n +CONFIG_ARCH_ROCKCHIP=n +CONFIG_ARCH_SEATTLE=n +CONFIG_ARCH_INTEL_SOCFPGA=n +CONFIG_ARCH_STM32=n +CONFIG_ARCH_SYNQUACER=n +CONFIG_ARCH_TEGRA=n +CONFIG_ARCH_SPRD=n +CONFIG_ARCH_THUNDER=n +CONFIG_ARCH_THUNDER2=n +CONFIG_ARCH_UNIPHIER=n +CONFIG_ARCH_VEXPRESS=n +CONFIG_ARCH_VISCONTI=n +CONFIG_ARCH_XGENE=n +CONFIG_ARCH_ZYNQMP=n + +# Disable PCI controller drivers +CONFIG_PCIE_ALTERA=n +CONFIG_PCI_HOST_THUNDER_PEM=n +CONFIG_PCI_HOST_THUNDER_ECAM=n +CONFIG_PCI_XGENE=n + +# Disable DesignWare-based PCIe controllers +CONFIG_PCI_MESON=n +CONFIG_PCI_HISI=n +CONFIG_PCIE_KIRIN=n + +CONFIG_HIX5HD2_GMAC=n +CONFIG_HNS_DSAF=n +CONFIG_HNS_ENET=n +CONFIG_HNS3=n + +# Disable serial drivers +CONFIG_SERIAL_XILINX_PS_UART=n +CONFIG_SERIAL_FSL_LPUART=n +CONFIG_SERIAL_FSL_LINFLEXUART=n + +# Disable I2C system bus drivers (mostly embedded / system-on-chip) +CONFIG_I2C_DESIGNWARE_PLATFORM=n +CONFIG_I2C_RK3X=n + +# Disable SPI Master Controller Drivers +CONFIG_SPI_CADENCE_QUADSPI=n +CONFIG_SPI_DESIGNWARE=n +CONFIG_SPI_PL022=n + +# Disable pinctrls +CONFIG_PINCTRL_RK805=n +CONFIG_PINCTRL_IPQ5018=n +CONFIG_PINCTRL_IPQ5332=n +CONFIG_PINCTRL_IPQ8074=n +CONFIG_PINCTRL_IPQ6018=n +CONFIG_PINCTRL_IPQ9574=n +CONFIG_PINCTRL_MSM8916=n +CONFIG_PINCTRL_MSM8953=n +CONFIG_PINCTRL_MSM8976=n +CONFIG_PINCTRL_MSM8994=n +CONFIG_PINCTRL_MSM8996=n +CONFIG_PINCTRL_MSM8998=n +CONFIG_PINCTRL_QCM2290=n +CONFIG_PINCTRL_QCS404=n +CONFIG_PINCTRL_QDU1000=n +CONFIG_PINCTRL_SA8775P=n +CONFIG_PINCTRL_SC7180=n +CONFIG_PINCTRL_SC7280=n +CONFIG_PINCTRL_SC8180X=n +CONFIG_PINCTRL_SC8280XP=n +CONFIG_PINCTRL_SDM660=n +CONFIG_PINCTRL_SDM670=n +CONFIG_PINCTRL_SDM845=n +CONFIG_PINCTRL_SDX75=n +CONFIG_PINCTRL_SM4450=n +CONFIG_PINCTRL_SM6115=n +CONFIG_PINCTRL_SM6125=n +CONFIG_PINCTRL_SM6350=n +CONFIG_PINCTRL_SM6375=n +CONFIG_PINCTRL_SM8150=n +CONFIG_PINCTRL_SM8250=n +CONFIG_PINCTRL_SM8350=n +CONFIG_PINCTRL_SM8450=n +CONFIG_PINCTRL_SM8550=n +CONFIG_PINCTRL_SM8650=n +CONFIG_PINCTRL_X1E80100=n +CONFIG_PINCTRL_SC7280_LPASS_LPI=n +CONFIG_PINCTRL_SM6115_LPASS_LPI=n +CONFIG_PINCTRL_SM8250_LPASS_LPI=n +CONFIG_PINCTRL_SM8350_LPASS_LPI=n +CONFIG_PINCTRL_SM8450_LPASS_LPI=n +CONFIG_PINCTRL_SC8280XP_LPASS_LPI=n +CONFIG_PINCTRL_SM8550_LPASS_LPI=n +CONFIG_PINCTRL_SM8650_LPASS_LPI=n + +# Disable clock drivers +CONFIG_CLK_X1E80100_CAMCC=n +CONFIG_CLK_X1E80100_DISPCC=n +CONFIG_CLK_X1E80100_GCC=n +CONFIG_CLK_X1E80100_GPUCC=n +CONFIG_CLK_X1E80100_TCSRCC=n +CONFIG_QCOM_CLK_APCS_MSM8916=n +CONFIG_QCOM_CLK_APCC_MSM8996=n +CONFIG_IPQ_GCC_5018=n +CONFIG_IPQ_GCC_5332=n +CONFIG_IPQ_GCC_6018=n +CONFIG_IPQ_GCC_8074=n +CONFIG_IPQ_GCC_9574=n +CONFIG_MSM_GCC_8916=n +CONFIG_MSM_MMCC_8994=n +CONFIG_MSM_GCC_8994=n +CONFIG_MSM_GCC_8996=n +CONFIG_MSM_MMCC_8996=n +CONFIG_MSM_GCC_8998=n +CONFIG_MSM_MMCC_8998=n +CONFIG_QCM_GCC_2290=n +CONFIG_QCM_DISPCC_2290=n +CONFIG_QCS_GCC_404=n +CONFIG_QDU_GCC_1000=n +CONFIG_SC_CAMCC_8280XP=n +CONFIG_SC_DISPCC_8280XP=n +CONFIG_SA_GCC_8775P=n +CONFIG_SA_GPUCC_8775P=n +CONFIG_SC_GCC_7180=n +CONFIG_SC_GCC_7280=n +CONFIG_SC_GCC_8180X=n +CONFIG_SC_GCC_8280XP=n +CONFIG_SC_GPUCC_8280XP=n +CONFIG_SC_LPASSCC_8280XP=n +CONFIG_SDM_CAMCC_845=n +CONFIG_SDM_GCC_845=n +CONFIG_SDM_GPUCC_845=n +CONFIG_SDM_VIDEOCC_845=n +CONFIG_SDM_DISPCC_845=n +CONFIG_SDM_LPASSCC_845=n +CONFIG_SDX_GCC_75=n +CONFIG_SM_CAMCC_8250=n +CONFIG_SM_DISPCC_6115=n +CONFIG_SM_DISPCC_8250=n +CONFIG_SM_DISPCC_8450=n +CONFIG_SM_DISPCC_8550=n +CONFIG_SM_GCC_6115=n +CONFIG_SM_GCC_8150=n +CONFIG_SM_GCC_8250=n +CONFIG_SM_GCC_8350=n +CONFIG_SM_GCC_8450=n +CONFIG_SM_GCC_8550=n +CONFIG_SM_GCC_8650=n +CONFIG_SM_GPUCC_6115=n +CONFIG_SM_GPUCC_8150=n +CONFIG_SM_GPUCC_8250=n +CONFIG_SM_GPUCC_8450=n +CONFIG_SM_GPUCC_8550=n +CONFIG_SM_GPUCC_8650=n +CONFIG_SM_TCSRCC_8550=n +CONFIG_SM_TCSRCC_8650=n +CONFIG_SM_VIDEOCC_8250=n +CONFIG_CLK_GFM_LPASS_SM8250=n + +# Disable interconnect drivers +CONFIG_INTERCONNECT_QCOM_MSM8916=n +CONFIG_INTERCONNECT_QCOM_MSM8996=n +CONFIG_INTERCONNECT_QCOM_QCM2290=n +CONFIG_INTERCONNECT_QCOM_QCS404=n +CONFIG_INTERCONNECT_QCOM_SA8775P=n +CONFIG_INTERCONNECT_QCOM_SC7180=n +CONFIG_INTERCONNECT_QCOM_SC7280=n +CONFIG_INTERCONNECT_QCOM_SC8180X=n +CONFIG_INTERCONNECT_QCOM_SC8280XP=n +CONFIG_INTERCONNECT_QCOM_SDM845=n +CONFIG_INTERCONNECT_QCOM_SDX75=n +CONFIG_INTERCONNECT_QCOM_SM8150=n +CONFIG_INTERCONNECT_QCOM_SM8250=n +CONFIG_INTERCONNECT_QCOM_SM8350=n +CONFIG_INTERCONNECT_QCOM_SM8450=n +CONFIG_INTERCONNECT_QCOM_SM8550=n +CONFIG_INTERCONNECT_QCOM_SM8650=n +CONFIG_INTERCONNECT_QCOM_X1E80100=n + +# Disable memory mapped GPIO drivers +CONFIG_GPIO_ALTERA=n +CONFIG_GPIO_MB86S7X=n +CONFIG_GPIO_PL061=n +CONFIG_GPIO_WCD934X=n +CONFIG_GPIO_XGENE=n + +# Disable Virtual GPIO drivers +CONFIG_POWER_RESET_XGENE=n +CONFIG_POWER_RESET_SYSCON=n +CONFIG_GNSS_MTK_SERIAL=n + +# Disable Watchdog Device Drivers +CONFIG_ARM_SP805_WATCHDOG=n +CONFIG_ARM_SBSA_WATCHDOG=n +CONFIG_DW_WATCHDOG=n +CONFIG_ARM_SMC_WATCHDOG=n + +# Disable Multifunction device drivers +CONFIG_MFD_BD9571MWV=n +CONFIG_MFD_AXP20X_I2C=n +CONFIG_MFD_HI6421_PMIC=n +CONFIG_MFD_MAX77620=n +CONFIG_MFD_MT6360=n +CONFIG_MFD_MT6397=n +CONFIG_MFD_RK8XX=n +CONFIG_MFD_SEC_CORE=n +CONFIG_MFD_TI_AM335X_TSCADC=n +CONFIG_MFD_TPS65219=n +CONFIG_MFD_TPS6594_I2C=n +CONFIG_MFD_WM8994=n +CONFIG_MFD_ROHM_BD718XX=n +CONFIG_MFD_WCD934X=n + +CONFIG_REGULATOR_FAN53555=n +CONFIG_REGULATOR_MAX8973=n +CONFIG_REGULATOR_MP8859=n +CONFIG_REGULATOR_MT6315=n +CONFIG_REGULATOR_MT6360=n +CONFIG_REGULATOR_PCA9450=n +CONFIG_REGULATOR_PF8X00=n +CONFIG_REGULATOR_PFUZE100=n +CONFIG_REGULATOR_RAA215300=n +CONFIG_REGULATOR_RK808=n +CONFIG_REGULATOR_TPS65132=n +CONFIG_REGULATOR_TPS65219=n + +# Disable media device types +CONFIG_MEDIA_ANALOG_TV_SUPPORT=n +CONFIG_MEDIA_DIGITAL_TV_SUPPORT=n +CONFIG_MEDIA_SDR_SUPPORT=n + +# Disable I2C encoder or helper chips +CONFIG_DRM_I2C_NXP_TDA998X=n + +# Disable ARM devices +CONFIG_DRM_MALI_DISPLAY=n +CONFIG_DRM_KOMEDA=n + +# Disable DRM Drivers +CONFIG_DRM_NOUVEAU=n + +# Disable display Interface Bridges +CONFIG_DRM_LONTIUM_LT8912B=n +CONFIG_DRM_LONTIUM_LT9611=n +CONFIG_DRM_LONTIUM_LT9611UXC=n +CONFIG_DRM_ITE_IT66121=n +CONFIG_DRM_NWL_MIPI_DSI=n +CONFIG_DRM_PARADE_PS8640=n +CONFIG_DRM_SAMSUNG_DSIM=n +CONFIG_DRM_SII902X=n +CONFIG_DRM_THINE_THC63LVD1024=n +CONFIG_DRM_TOSHIBA_TC358768=n +CONFIG_DRM_TI_TFP410=n +CONFIG_DRM_TI_SN65DSI83=n +CONFIG_DRM_TI_SN65DSI86=n +CONFIG_DRM_ANALOGIX_ANX7625=n +CONFIG_DRM_I2C_ADV7511=n +CONFIG_DRM_CDNS_MHDP8546=n + +CONFIG_DRM_ETNAVIV=n +CONFIG_DRM_HISI_HIBMC=n +CONFIG_DRM_HISI_KIRIN=n +CONFIG_DRM_PL111=n +CONFIG_DRM_LIMA=n +CONFIG_DRM_PANFROST=n + +# Disable CODEC drivers +CONFIG_SND_SOC_ADAU7002=n +CONFIG_SND_SOC_AK4613=n +CONFIG_SND_SOC_DA7213=n +CONFIG_SND_SOC_ES7134=n +CONFIG_SND_SOC_ES7241=n +CONFIG_SND_SOC_ES8316=n +CONFIG_SND_SOC_GTM601=n +CONFIG_SND_SOC_MAX98357A=n +CONFIG_SND_SOC_MAX98927=n +CONFIG_SND_SOC_MSM8916_WCD_ANALOG=n +CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=n +CONFIG_SND_SOC_PCM3168A_I2C=n +CONFIG_SND_SOC_RK817=n +CONFIG_SND_SOC_RL6231=n +CONFIG_SND_SOC_RT5640=n +CONFIG_SND_SOC_RT5659=n +CONFIG_SND_SOC_RT5663=n +CONFIG_SND_SOC_RT5682=n +CONFIG_SND_SOC_SGTL5000=n +CONFIG_SND_SOC_TAS2552=n +CONFIG_SND_SOC_TAS571X=n +CONFIG_SND_SOC_TLV320AIC31XX=n +CONFIG_SND_SOC_TLV320AIC32X4=n +CONFIG_SND_SOC_TLV320AIC3X=n +CONFIG_SND_SOC_TS3A227E=n +CONFIG_SND_SOC_WCD9335=n +CONFIG_SND_SOC_WCD934X=n +CONFIG_SND_SOC_WCD938X=n +CONFIG_SND_SOC_WM8524=n +CONFIG_SND_SOC_WM8904=n +CONFIG_SND_SOC_WM8960=n +CONFIG_SND_SOC_WM8962=n +CONFIG_SND_SOC_WM8978=n +CONFIG_SND_SOC_WSA881X=n +CONFIG_SND_SOC_MT6358=n +CONFIG_SND_SOC_NAU8822=n + +# Disable USB Host Controller Drivers +CONFIG_USB_XHCI_PCI_RENESAS=n + +# Disable MMC/SD/SDIO Host Controller Drivers +CONFIG_MMC_SDHCI_OF_ARASAN=n +CONFIG_MMC_SDHCI_CADENCE=n +CONFIG_MMC_SDHCI_F_SDH30=n +CONFIG_MMC_DW_EXYNOS=n +CONFIG_MMC_DW_HI3798CV200=n +CONFIG_MMC_DW_K3=n +CONFIG_MMC_MTK=n +CONFIG_MMC_SDHCI_XENON=n +CONFIG_MMC_SDHCI_AM654=n + +CONFIG_FSL_EDMA=n +CONFIG_MV_XOR_V2=n +CONFIG_COMMON_CLK_RK808=n +CONFIG_FSL_RCPM=n +CONFIG_ARCH_R9A07G044=n +CONFIG_MAX9611=n +CONFIG_NVMEM_RMEM=n +CONFIG_FPGA=n diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S index 5ab1970ee54367..a8d0dadd227245 100644 --- a/arch/arm64/kernel/head.S +++ b/arch/arm64/kernel/head.S @@ -60,7 +60,7 @@ */ efi_signature_nop // special NOP to identity as PE/COFF executable b primary_entry // branch to kernel start, magic - .quad 0 // Image load offset from start of RAM, little-endian + le64sym _kernel_offset_le // Image load offset from start of RAM, little-endian le64sym _kernel_size_le // Effective size of kernel image, little-endian le64sym _kernel_flags_le // Informative flags, little-endian .quad 0 // reserved diff --git a/arch/arm64/kernel/image.h b/arch/arm64/kernel/image.h index 7bc3ba89790191..0297e5d3e9af4d 100644 --- a/arch/arm64/kernel/image.h +++ b/arch/arm64/kernel/image.h @@ -62,6 +62,7 @@ */ #define HEAD_SYMBOLS \ DEFINE_IMAGE_LE64(_kernel_size_le, _end - _text); \ + DEFINE_IMAGE_LE64(_kernel_offset_le, 0x00080000); \ DEFINE_IMAGE_LE64(_kernel_flags_le, __HEAD_FLAGS); #endif /* __ARM64_KERNEL_IMAGE_H */ diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c index 2a3e8bd317c9d2..ae0c489418bcca 100644 --- a/drivers/cpufreq/cpufreq-dt-platdev.c +++ b/drivers/cpufreq/cpufreq-dt-platdev.c @@ -166,6 +166,7 @@ static const struct of_device_id blocklist[] __initconst = { { .compatible = "qcom,sm6115", }, { .compatible = "qcom,sm6350", }, { .compatible = "qcom,sm6375", }, + { .compatible = "qcom,sm7150", }, { .compatible = "qcom,sm7225", }, { .compatible = "qcom,sm7325", }, { .compatible = "qcom,sm8150", }, diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c index 0c560e84ad5a53..1f9024c0da2f94 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c @@ -737,6 +737,7 @@ static const struct adreno_info a6xx_gpus[] = { .machine = "qcom,sm7150", .chip_ids = ADRENO_CHIP_IDS(0x06010800), .family = ADRENO_6XX_GEN1, + .revn = 618, .fw = { [ADRENO_FW_SQE] = "a630_sqe.fw", [ADRENO_FW_GMU] = "a630_gmu.bin", diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 83de7564e2c1fe..88b22cc38136aa 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -622,9 +622,8 @@ bool dpu_encoder_use_dsc_merge(struct drm_encoder *drm_enc) if (dpu_enc->phys_encs[i]) intf_count++; - /* See dpu_encoder_get_topology, we only support 2:2:1 topology */ if (dpu_enc->dsc) - num_dsc = 2; + num_dsc = 1; return (num_dsc > 0) && (num_dsc > intf_count); } @@ -691,8 +690,8 @@ static struct msm_display_topology dpu_encoder_get_topology( * this is power optimal and can drive up to (including) 4k * screens */ - topology.num_dsc = 2; - topology.num_lm = 2; + topology.num_dsc = 1; + topology.num_lm = 1; topology.num_intf = 1; } @@ -2020,32 +2019,33 @@ static void dpu_encoder_dsc_pipe_cfg(struct dpu_hw_ctl *ctl, static void dpu_encoder_prep_dsc(struct dpu_encoder_virt *dpu_enc, struct drm_dsc_config *dsc) { - /* coding only for 2LM, 2enc, 1 dsc config */ struct dpu_encoder_phys *enc_master = dpu_enc->cur_master; struct dpu_hw_ctl *ctl = enc_master->hw_ctl; struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC]; struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC]; int this_frame_slices; int intf_ip_w, enc_ip_w; - int dsc_common_mode; + int dsc_common_mode = 0; int pic_width; u32 initial_lines; int i; + int num_dsc = 0; for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) { hw_pp[i] = dpu_enc->hw_pp[i]; hw_dsc[i] = dpu_enc->hw_dsc[i]; if (!hw_pp[i] || !hw_dsc[i]) { - DPU_ERROR_ENC(dpu_enc, "invalid params for DSC\n"); - return; + break; } + num_dsc++; } dsc_common_mode = 0; pic_width = dsc->pic_width; - dsc_common_mode = DSC_MODE_SPLIT_PANEL; + if (num_dsc > 1) + dsc_common_mode |= DSC_MODE_SPLIT_PANEL; if (dpu_encoder_use_dsc_merge(enc_master->parent)) dsc_common_mode |= DSC_MODE_MULTIPLEX; if (enc_master->intf_mode == INTF_MODE_VIDEO) @@ -2054,14 +2054,10 @@ static void dpu_encoder_prep_dsc(struct dpu_encoder_virt *dpu_enc, this_frame_slices = pic_width / dsc->slice_width; intf_ip_w = this_frame_slices * dsc->slice_width; - /* - * dsc merge case: when using 2 encoders for the same stream, - * no. of slices need to be same on both the encoders. - */ - enc_ip_w = intf_ip_w / 2; + enc_ip_w = intf_ip_w / num_dsc; initial_lines = dpu_encoder_dsc_initial_line_calc(dsc, enc_ip_w); - for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) + for (i = 0; i < num_dsc; i++) dpu_encoder_dsc_pipe_cfg(ctl, hw_dsc[i], hw_pp[i], dsc, dsc_common_mode, initial_lines); } @@ -2221,7 +2217,6 @@ static void dpu_encoder_dsc_pipe_clr(struct dpu_hw_ctl *ctl, static void dpu_encoder_unprep_dsc(struct dpu_encoder_virt *dpu_enc) { - /* coding only for 2LM, 2enc, 1 dsc config */ struct dpu_encoder_phys *enc_master = dpu_enc->cur_master; struct dpu_hw_ctl *ctl = enc_master->hw_ctl; struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC]; diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index a98d24b7cb00b4..44083b795234c4 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -1767,11 +1767,6 @@ static int dsi_populate_dsc_params(struct msm_dsi_host *msm_host, struct drm_dsc return -EINVAL; } - if (dsc->bits_per_component != 8) { - DRM_DEV_ERROR(&msm_host->pdev->dev, "DSI does not support bits_per_component != 8 yet\n"); - return -EOPNOTSUPP; - } - dsc->simple_422 = 0; dsc->convert_rgb = 1; dsc->vbr_enable = 0; @@ -1779,7 +1774,6 @@ static int dsi_populate_dsc_params(struct msm_dsi_host *msm_host, struct drm_dsc drm_dsc_set_const_params(dsc); drm_dsc_set_rc_buf_thresh(dsc); - /* handle only bpp = bpc = 8, pre-SCR panels */ ret = drm_dsc_setup_rc_params(dsc, DRM_DSC_1_1_PRE_SCR); if (ret) { DRM_DEV_ERROR(&msm_host->pdev->dev, "could not find DSC RC parameters\n"); diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig index d7469c565d1db8..dc570c4c88ad55 100644 --- a/drivers/gpu/drm/panel/Kconfig +++ b/drivers/gpu/drm/panel/Kconfig @@ -185,6 +185,26 @@ config DRM_PANEL_HIMAX_HX8394 If M is selected the module will be called panel-himax-hx8394. +config DRM_PANEL_HUAXING_NT36672C + tristate "Huaxing FHD panel with NT36672C controller" + depends on OF + depends on DRM_MIPI_DSI + depends on BACKLIGHT_CLASS_DEVICE + select VIDEOMODE_HELPERS + help + Say Y or M here if you want to enable support for the Huaxing FHD + (2400x1080@120Hz) video mode panel. + +config DRM_PANEL_TIANMA_NT36672C + tristate "Tianma FHD panel with NT36672C controller" + depends on OF + depends on DRM_MIPI_DSI + depends on BACKLIGHT_CLASS_DEVICE + select VIDEOMODE_HELPERS + help + Say Y or M here if you want to enable support for the Tianma FHD + (2400x1080@120Hz) video mode panel. + config DRM_PANEL_ILITEK_IL9322 tristate "Ilitek ILI9322 320x240 QVGA panels" depends on OF && SPI @@ -302,6 +322,36 @@ config DRM_PANEL_JDI_R63452 Say Y here if you want to enable support for the JDI R63452 DSI command mode panel as found in Xiaomi Mi 5 Devices. +config DRM_PANEL_K6_38_0C_0A + tristate "K6 38 0C 0A DSC video mode panel" + depends on OF + depends on DRM_MIPI_DSI + depends on BACKLIGHT_CLASS_DEVICE + select VIDEOMODE_HELPERS + help + Say Y or M here if you want to enable support for the K6_38_0C_0A + (2400x1080@120Hz) DSC video mode panel. + +config DRM_PANEL_K6_38_0E_0B + tristate "K6 38 0E 0B DSC video mode panel" + depends on OF + depends on DRM_MIPI_DSI + depends on BACKLIGHT_CLASS_DEVICE + select VIDEOMODE_HELPERS + help + Say Y or M here if you want to enable support for the K6_38_0E_0B + (2400x1080@120Hz) DSC video mode panel. + +config DRM_PANEL_K9A_36_02_0A + tristate "K9A 36 02 0A DSC cmd mode panel" + depends on OF + depends on DRM_MIPI_DSI + depends on BACKLIGHT_CLASS_DEVICE + select VIDEOMODE_HELPERS + help + Say Y or M here if you want to enable support for the K9A_36_02_0A + (2400x1080@90Hz) DSC video mode panel. + config DRM_PANEL_KHADAS_TS050 tristate "Khadas TS050 panel" depends on OF @@ -977,6 +1027,15 @@ config DRM_PANEL_TRULY_NT35597_WQXGA Say Y here if you want to enable support for Truly NT35597 WQXGA Dual DSI Video Mode panel +config DRM_PANEL_VISIONOX_G2647FB105 + tristate "Visionox G2647FB105" + depends on OF + depends on DRM_MIPI_DSI + depends on BACKLIGHT_CLASS_DEVICE + help + Say Y or M here if you want to enable support for the Visionox + G2647FB105 (2340x1080@60Hz) AMOLED DSI cmd mode panel. + config DRM_PANEL_VISIONOX_R66451 tristate "Visionox R66451" depends on OF diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile index 7dcf72646cacff..3b965a274605e8 100644 --- a/drivers/gpu/drm/panel/Makefile +++ b/drivers/gpu/drm/panel/Makefile @@ -19,6 +19,8 @@ obj-$(CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D) += panel-feiyang-fy07024di26a30d obj-$(CONFIG_DRM_PANEL_HIMAX_HX83102) += panel-himax-hx83102.o obj-$(CONFIG_DRM_PANEL_HIMAX_HX83112A) += panel-himax-hx83112a.o obj-$(CONFIG_DRM_PANEL_HIMAX_HX8394) += panel-himax-hx8394.o +obj-$(CONFIG_DRM_PANEL_HUAXING_NT36672C) += panel-huaxing-nt36672c.o +obj-$(CONFIG_DRM_PANEL_TIANMA_NT36672C) += panel-nt36672c-tianma.o obj-$(CONFIG_DRM_PANEL_ILITEK_IL9322) += panel-ilitek-ili9322.o obj-$(CONFIG_DRM_PANEL_ILITEK_ILI9341) += panel-ilitek-ili9341.o obj-$(CONFIG_DRM_PANEL_ILITEK_ILI9805) += panel-ilitek-ili9805.o @@ -31,6 +33,9 @@ obj-$(CONFIG_DRM_PANEL_JADARD_JD9365DA_H3) += panel-jadard-jd9365da-h3.o obj-$(CONFIG_DRM_PANEL_JDI_LT070ME05000) += panel-jdi-lt070me05000.o obj-$(CONFIG_DRM_PANEL_JDI_LPM102A188A) += panel-jdi-lpm102a188a.o obj-$(CONFIG_DRM_PANEL_JDI_R63452) += panel-jdi-fhd-r63452.o +obj-$(CONFIG_DRM_PANEL_K6_38_0C_0A) += panel-k6-38-0c-0a-dsc.o +obj-$(CONFIG_DRM_PANEL_K6_38_0E_0B) += panel-k6-38-0e-0b-dsc.o +obj-$(CONFIG_DRM_PANEL_K9A_36_02_0A) += panel-k9a-36-02-0a-mp-dsc.o obj-$(CONFIG_DRM_PANEL_KHADAS_TS050) += panel-khadas-ts050.o obj-$(CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04) += panel-kingdisplay-kd097d04.o obj-$(CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W) += panel-leadtek-ltk050h3146w.o @@ -99,6 +104,7 @@ obj-$(CONFIG_DRM_PANEL_TPO_TD028TTEC1) += panel-tpo-td028ttec1.o obj-$(CONFIG_DRM_PANEL_TPO_TD043MTEA1) += panel-tpo-td043mtea1.o obj-$(CONFIG_DRM_PANEL_TPO_TPG110) += panel-tpo-tpg110.o obj-$(CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA) += panel-truly-nt35597.o +obj-$(CONFIG_DRM_PANEL_VISIONOX_G2647FB105) += panel-visionox-g2647fb105.o obj-$(CONFIG_DRM_PANEL_VISIONOX_RM69299) += panel-visionox-rm69299.o obj-$(CONFIG_DRM_PANEL_VISIONOX_VTDR6130) += panel-visionox-vtdr6130.o obj-$(CONFIG_DRM_PANEL_VISIONOX_R66451) += panel-visionox-r66451.o diff --git a/drivers/gpu/drm/panel/panel-huaxing-nt36672c.c b/drivers/gpu/drm/panel/panel-huaxing-nt36672c.c new file mode 100644 index 00000000000000..d513574d93de05 --- /dev/null +++ b/drivers/gpu/drm/panel/panel-huaxing-nt36672c.c @@ -0,0 +1,426 @@ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright (c) 2023 FIXME +// Generated with linux-mdss-dsi-panel-driver-generator from vendor device tree: +// Copyright (c) 2013, The Linux Foundation. All rights reserved. (FIXME) + +#include +#include +#include +#include +#include + +#include