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Bug fixes
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2 files changed

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-5
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2 files changed

+5
-5
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devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup3.vhd

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -95,9 +95,9 @@ architecture rtl of Ad9249ReadoutGroup3 is
9595
relock => '0',
9696
axilWriteSlave => AXI_LITE_WRITE_SLAVE_INIT_C,
9797
axilReadSlave => AXI_LITE_READ_SLAVE_INIT_C,
98-
frameDelay => (others => '0'),
98+
frameDelay => DEFAULT_DELAY_G,
9999
frameDelaySet => '0',
100-
dataDelay => (others => (others => '0')),
100+
dataDelay => (others => DEFAULT_DELAY_G),
101101
dataDelaySet => (others => '0'),
102102
freezeDebug => '0',
103103
readoutDebug0 => (others => (others => '0')),
@@ -317,7 +317,7 @@ begin
317317
axiSlaveRegister(axilEp, X"00"+toSlv(i*4, 8), 9, v.dataDelaySet(i), '1');
318318
end loop;
319319
axiSlaveRegister(axilEp, X"20", 0, v.frameDelay);
320-
axiSlaveRegisterR(axilEp, X"20", 9, v.frameDelaySet);
320+
axiSlaveRegister(axilEp, X"20", 9, v.frameDelaySet, '1');
321321

322322
-- Debug output to see how many times the shift has needed a relock
323323
axiSlaveRegisterR(axilEp, X"30", 0, r.lostLockCount);

python/surf/devices/analog_devices/_Ad9249.py

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -592,7 +592,7 @@ def __init__(self,
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bitOffset = 0,
593593
base = pr.UInt,
594594
mode = 'RW',
595-
verify = False,
595+
verify = True,
596596
))
597597

598598
self.add(pr.RemoteVariable(
@@ -603,7 +603,7 @@ def __init__(self,
603603
bitOffset = 0,
604604
base = pr.UInt,
605605
mode = 'RW',
606-
verify = False,
606+
verify = True,
607607
))
608608

609609
self.add(pr.RemoteVariable(

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