Auto merge of #151183 - jhpratt:rollup-GxmJbns, r=jhpratt

Rollup of 5 pull requests

Successful merges:

 - #150607 (Add amdgpu_dispatch_ptr intrinsic)
 - #150611 (Unify and deduplicate From<T> float tests)
 - #151082 (Silence unused type param error on struct parse error)
 - #151159 (Tidying up `tests/ui/issues` 15 tests [8/N])
 - #151164 (Stabilise `EULER_GAMMA` and `GOLDEN_RATIO` constants for `f32` and `f64`.)

r? @ghost

Author: bors

compiler/rustc_codegen_llvm/src/intrinsic.rs

@@ -560,6 +560,12 @@ impl<'ll, 'tcx> IntrinsicCallBuilderMethods<'tcx> for Builder<'_, 'll, 'tcx> {
                 return Ok(());
             }
 
+            sym::amdgpu_dispatch_ptr => {
+                let val = self.call_intrinsic("llvm.amdgcn.dispatch.ptr", &[], &[]);
+                // Relying on `LLVMBuildPointerCast` to produce an addrspacecast
+                self.pointercast(val, self.type_ptr())
+            }
+
             _ if name.as_str().starts_with("simd_") => {
                 // Unpack non-power-of-2 #[repr(packed, simd)] arguments.
                 // This gives them the expected layout of a regular #[repr(simd)] vector.

compiler/rustc_codegen_ssa/src/mir/intrinsic.rs

@@ -112,6 +112,7 @@ impl<'a, 'tcx, Bx: BuilderMethods<'a, 'tcx>> FunctionCx<'a, 'tcx, Bx> {
                 | sym::unreachable
                 | sym::cold_path
                 | sym::breakpoint
+                | sym::amdgpu_dispatch_ptr
                 | sym::assert_zero_valid
                 | sym::assert_mem_uninitialized_valid
                 | sym::assert_inhabited

compiler/rustc_hir/src/hir.rs

@@ -4525,6 +4525,26 @@ impl ItemKind<'_> {
             _ => return None,
         })
     }
+
+    pub fn recovered(&self) -> bool {
+        match self {
+            ItemKind::Struct(
+                _,
+                _,
+                VariantData::Struct { recovered: ast::Recovered::Yes(_), .. },
+            ) => true,
+            ItemKind::Union(
+                _,
+                _,
+                VariantData::Struct { recovered: ast::Recovered::Yes(_), .. },
+            ) => true,
+            ItemKind::Enum(_, _, def) => def.variants.iter().any(|v| match v.data {
+                VariantData::Struct { recovered: ast::Recovered::Yes(_), .. } => true,
+                _ => false,
+            }),
+            _ => false,
+        }
+    }
 }
 
 // The bodies for items are stored "out of line", in a separate

compiler/rustc_hir_analysis/src/check/intrinsic.rs

@@ -70,6 +70,7 @@ fn intrinsic_operation_unsafety(tcx: TyCtxt<'_>, intrinsic_id: LocalDefId) -> hi
         | sym::add_with_overflow
         | sym::aggregate_raw_ptr
         | sym::align_of
+        | sym::amdgpu_dispatch_ptr
         | sym::assert_inhabited
         | sym::assert_mem_uninitialized_valid
         | sym::assert_zero_valid
@@ -286,6 +287,7 @@ pub(crate) fn check_intrinsic_type(
     let (n_tps, n_cts, inputs, output) = match intrinsic_name {
         sym::autodiff => (4, 0, vec![param(0), param(1), param(2)], param(3)),
         sym::abort => (0, 0, vec![], tcx.types.never),
+        sym::amdgpu_dispatch_ptr => (0, 0, vec![], Ty::new_imm_ptr(tcx, tcx.types.unit)),
         sym::unreachable => (0, 0, vec![], tcx.types.never),
         sym::breakpoint => (0, 0, vec![], tcx.types.unit),
         sym::size_of | sym::align_of | sym::variant_count => (1, 0, vec![], tcx.types.usize),

compiler/rustc_hir_analysis/src/check/wfcheck.rs

@@ -2160,7 +2160,12 @@ fn report_bivariance<'tcx>(
         const_param_help,
     });
     diag.code(E0392);
-    diag.emit()
+    if item.kind.recovered() {
+        // Silence potentially redundant error, as the item had a parse error.
+        diag.delay_as_bug()
+    } else {
+        diag.emit()
+    }
 }
 
 /// Detects cases where an ADT/LTA is trivially cyclical -- we want to detect this so

compiler/rustc_span/src/symbol.rs

@@ -458,6 +458,7 @@ symbols! {
         alu32,
         always,
         amdgpu,
+        amdgpu_dispatch_ptr,
         analysis,
         and,
         and_then,

compiler/rustc_trait_selection/src/error_reporting/infer/need_type_info.rs

@@ -488,7 +488,30 @@ impl<'a, 'tcx> TypeErrCtxt<'a, 'tcx> {
         }
 
         let Some(InferSource { span, kind }) = local_visitor.infer_source else {
-            return self.bad_inference_failure_err(failure_span, arg_data, error_code);
+            let silence = if let DefKind::AssocFn = self.tcx.def_kind(body_def_id)
+                && let parent = self.tcx.parent(body_def_id.into())
+                && self.tcx.is_automatically_derived(parent)
+                && let Some(parent) = parent.as_local()
+                && let hir::Node::Item(item) = self.tcx.hir_node_by_def_id(parent)
+                && let hir::ItemKind::Impl(imp) = item.kind
+                && let hir::TyKind::Path(hir::QPath::Resolved(_, path)) = imp.self_ty.kind
+                && let Res::Def(DefKind::Struct | DefKind::Enum | DefKind::Union, def_id) = path.res
+                && let Some(def_id) = def_id.as_local()
+                && let hir::Node::Item(item) = self.tcx.hir_node_by_def_id(def_id)
+            {
+                // We have encountered an inference error within an automatically derived `impl`,
+                // from a `#[derive(..)]` on an item that had a parse error. Because the parse
+                // error might have caused the expanded code to be malformed, we silence the
+                // inference error.
+                item.kind.recovered()
+            } else {
+                false
+            };
+            let mut err = self.bad_inference_failure_err(failure_span, arg_data, error_code);
+            if silence {
+                err.downgrade_to_delayed_bug();
+            }
+            return err;
         };
 
         let (source_kind, name, long_ty_path) = kind.ty_localized_msg(self);

library/core/src/intrinsics/gpu.rs

@@ -0,0 +1,23 @@
+//! Intrinsics for GPU targets.
+//!
+//! Intrinsics in this module are intended for use on GPU targets.
+//! They can be target specific but in general GPU targets are similar.
+
+#![unstable(feature = "gpu_intrinsics", issue = "none")]
+
+/// Returns a pointer to the HSA kernel dispatch packet.
+///
+/// A `gpu-kernel` on amdgpu is always launched through a kernel dispatch packet.
+/// The dispatch packet contains the workgroup size, launch size and other data.
+/// The content is defined by the [HSA Platform System Architecture Specification],
+/// which is implemented e.g. in AMD's [hsa.h].
+/// The intrinsic returns a unit pointer so that rustc does not need to know the packet struct.
+/// The pointer is valid for the whole lifetime of the program.
+///
+/// [HSA Platform System Architecture Specification]: https://hsafoundation.com/wp-content/uploads/2021/02/HSA-SysArch-1.2.pdf
+/// [hsa.h]: https://github.com/ROCm/rocm-systems/blob/rocm-7.1.0/projects/rocr-runtime/runtime/hsa-runtime/inc/hsa.h#L2959
+#[rustc_nounwind]
+#[rustc_intrinsic]
+#[cfg(target_arch = "amdgpu")]
+#[must_use = "returns a pointer that does nothing unless used"]
+pub fn amdgpu_dispatch_ptr() -> *const ();

library/core/src/intrinsics/mod.rs

@@ -60,6 +60,7 @@ use crate::{mem, ptr};
 
 mod bounds;
 pub mod fallback;
+pub mod gpu;
 pub mod mir;
 pub mod simd;
 

library/core/src/num/f128.rs

@@ -34,13 +34,13 @@ pub mod consts {
 
     /// The golden ratio (φ)
     #[unstable(feature = "f128", issue = "116909")]
-    // Also, #[unstable(feature = "more_float_constants", issue = "146939")]
-    pub const PHI: f128 = 1.61803398874989484820458683436563811772030917980576286213545_f128;
+    pub const GOLDEN_RATIO: f128 =
+        1.61803398874989484820458683436563811772030917980576286213545_f128;
 
     /// The Euler-Mascheroni constant (γ)
     #[unstable(feature = "f128", issue = "116909")]
-    // Also, #[unstable(feature = "more_float_constants", issue = "146939")]
-    pub const EGAMMA: f128 = 0.577215664901532860606512090082402431042159335939923598805767_f128;
+    pub const EULER_GAMMA: f128 =
+        0.577215664901532860606512090082402431042159335939923598805767_f128;
 
     /// π/2
     #[unstable(feature = "f128", issue = "116909")]