[wasm-simd] Remove PrefetchTemporal and PrefetchNonTemporal operations

Removing prefetch operations as per the vote in the github issue:
WebAssembly/simd#352

Bug:v8:11168

Change-Id: Ia72684e68ce886f8f26a7d3b5bea601be416dfab
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2771758
Reviewed-by: Jakob Kummerow <[email protected]>
Reviewed-by: Maya Lekova <[email protected]>
Reviewed-by: Zhi An Ng <[email protected]>
Commit-Queue: Deepti Gandluri <[email protected]>
Cr-Commit-Position: refs/heads/master@{#73578}

Author: dtig

src/codegen/arm64/assembler-arm64.cc

@@ -1429,37 +1429,6 @@ void Assembler::stlxrh(const Register& rs, const Register& rt,
   Emit(STLXR_h | Rs(rs) | Rt2(x31) | RnSP(rn) | Rt(rt));
 }
 
-void Assembler::prfm(int prfop, const MemOperand& addr) {
-  // Restricted support for prfm, only register offset.
-  // This can probably be merged with Assembler::LoadStore as we expand support.
-  DCHECK(addr.IsRegisterOffset());
-  DCHECK(is_uint5(prfop));
-  Instr memop = PRFM | prfop | RnSP(addr.base());
-
-  Extend ext = addr.extend();
-  Shift shift = addr.shift();
-  unsigned shift_amount = addr.shift_amount();
-
-  // LSL is encoded in the option field as UXTX.
-  if (shift == LSL) {
-    ext = UXTX;
-  }
-
-  // Shifts are encoded in one bit, indicating a left shift by the memory
-  // access size.
-  DCHECK((shift_amount == 0) ||
-         (shift_amount == static_cast<unsigned>(CalcLSDataSize(PRFM))));
-
-  Emit(LoadStoreRegisterOffsetFixed | memop | Rm(addr.regoffset()) |
-       ExtendMode(ext) | ImmShiftLS((shift_amount > 0) ? 1 : 0));
-}
-
-void Assembler::prfm(PrefetchOperation prfop, const MemOperand& addr) {
-  // Restricted support for prfm, only register offset.
-  // This can probably be merged with Assembler::LoadStore as we expand support.
-  prfm(static_cast<int>(prfop), addr);
-}
-
 void Assembler::NEON3DifferentL(const VRegister& vd, const VRegister& vn,
                                 const VRegister& vm, NEON3DifferentOp vop) {
   DCHECK(AreSameFormat(vn, vm));

src/codegen/arm64/assembler-arm64.h

@@ -880,9 +880,6 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
   // Store-release exclusive half-word.
   void stlxrh(const Register& rs, const Register& rt, const Register& rn);
 
-  void prfm(int prfop, const MemOperand& addr);
-  void prfm(PrefetchOperation prfop, const MemOperand& addr);
-
   // Move instructions. The default shift of -1 indicates that the move
   // instruction will calculate an appropriate 16-bit immediate and left shift
   // that is equal to the 64-bit immediate argument. If an explicit left shift

src/codegen/arm64/constants-arm64.h

@@ -159,9 +159,6 @@ using float16 = uint16_t;
                         /* store second source.      */ \
   V_(Rs, 20, 16, Bits)  /* Store-exclusive status    */ \
   V_(PrefetchMode, 4, 0, Bits)                          \
-  V_(PrefetchHint, 4, 3, Bits)                          \
-  V_(PrefetchTarget, 2, 1, Bits)                        \
-  V_(PrefetchStream, 0, 0, Bits)                        \
                                                         \
   /* Common bits */                                     \
   V_(SixtyFourBits, 31, 31, Bits)                       \
@@ -219,7 +216,6 @@ using float16 = uint16_t;
   V_(LSOpc, 23, 22, Bits)                               \
   V_(LSVector, 26, 26, Bits)                            \
   V_(LSSize, 31, 30, Bits)                              \
-  V_(ImmPrefetchOperation, 4, 0, Bits)                  \
                                                         \
   /* NEON generic fields */                             \
   V_(NEONQ, 30, 30, Bits)                               \
@@ -447,27 +443,6 @@ enum SystemRegister {
          ImmSystemRegister_offset
 };
 
-enum PrefetchOperation {
-  PLDL1KEEP = 0x00,
-  PLDL1STRM = 0x01,
-  PLDL2KEEP = 0x02,
-  PLDL2STRM = 0x03,
-  PLDL3KEEP = 0x04,
-  PLDL3STRM = 0x05,
-  PLIL1KEEP = 0x08,
-  PLIL1STRM = 0x09,
-  PLIL2KEEP = 0x0a,
-  PLIL2STRM = 0x0b,
-  PLIL3KEEP = 0x0c,
-  PLIL3STRM = 0x0d,
-  PSTL1KEEP = 0x10,
-  PSTL1STRM = 0x11,
-  PSTL2KEEP = 0x12,
-  PSTL2STRM = 0x13,
-  PSTL3KEEP = 0x14,
-  PSTL3STRM = 0x15,
-};
-
 // Instruction enumerations.
 //
 // These are the masks that define a class of instructions, and the list of

src/codegen/x64/assembler-x64.cc

@@ -1202,16 +1202,6 @@ void Assembler::cpuid() {
   emit(0xA2);
 }
 
-void Assembler::prefetch(Operand src, int level) {
-  DCHECK(is_uint2(level));
-  EnsureSpace ensure_space(this);
-  emit(0x0F);
-  emit(0x18);
-  // Emit hint number in Reg position of RegR/M.
-  XMMRegister code = XMMRegister::from_code(level);
-  emit_sse_operand(code, src);
-}
-
 void Assembler::cqo() {
   EnsureSpace ensure_space(this);
   emit_rex_64();

src/codegen/x64/assembler-x64.h

@@ -786,7 +786,6 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
   void ret(int imm16);
   void ud2();
   void setcc(Condition cc, Register reg);
-  void prefetch(Operand src, int level);
 
   void pblendw(XMMRegister dst, Operand src, uint8_t mask);
   void pblendw(XMMRegister dst, XMMRegister src, uint8_t mask);

src/compiler/backend/arm64/code-generator-arm64.cc

@@ -1501,10 +1501,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       }
       break;
     }
-    case kArm64Prfm: {
-      __ prfm(MiscField::decode(opcode), i.MemoryOperand(0));
-      break;
-    }
     case kArm64Clz:
       __ Clz(i.OutputRegister64(), i.InputRegister64(0));
       break;

src/compiler/backend/arm64/instruction-codes-arm64.h

@@ -93,7 +93,6 @@ namespace compiler {
   V(Arm64Poke)                              \
   V(Arm64PokePair)                          \
   V(Arm64Peek)                              \
-  V(Arm64Prfm)                              \
   V(Arm64Float32Cmp)                        \
   V(Arm64Float32Add)                        \
   V(Arm64Float32Sub)                        \

src/compiler/backend/arm64/instruction-scheduler-arm64.cc

@@ -391,7 +391,6 @@ int InstructionScheduler::GetTargetInstructionFlags(
     case kArm64StrCompressTagged:
     case kArm64DmbIsh:
     case kArm64DsbIsb:
-    case kArm64Prfm:
     case kArm64StoreLane:
       return kHasSideEffect;
 

src/compiler/backend/arm64/instruction-selector-arm64.cc

@@ -622,26 +622,6 @@ void EmitLoad(InstructionSelector* selector, Node* node, InstructionCode opcode,
   selector->Emit(opcode, arraysize(outputs), outputs, input_count, inputs);
 }
 
-void InstructionSelector::VisitPrefetchTemporal(Node* node) {
-  Arm64OperandGenerator g(this);
-  InstructionOperand inputs[2] = {g.UseRegister(node->InputAt(0)),
-                                  g.UseRegister(node->InputAt(1))};
-  InstructionCode opcode = kArm64Prfm;
-  opcode |= AddressingModeField::encode(kMode_MRR);
-  opcode |= MiscField::encode(PLDL1KEEP);
-  Emit(opcode, 0, nullptr, 2, inputs);
-}
-
-void InstructionSelector::VisitPrefetchNonTemporal(Node* node) {
-  Arm64OperandGenerator g(this);
-  InstructionOperand inputs[2] = {g.UseRegister(node->InputAt(0)),
-                                  g.UseRegister(node->InputAt(1))};
-  InstructionCode opcode = kArm64Prfm;
-  opcode |= AddressingModeField::encode(kMode_MRR);
-  opcode |= MiscField::encode(PLDL1STRM);
-  Emit(opcode, 0, nullptr, 2, inputs);
-}
-
 namespace {
 // Manually add base and index into a register to get the actual address.
 // This should be used prior to instructions that only support

src/compiler/backend/ia32/code-generator-ia32.cc

@@ -4067,12 +4067,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       ASSEMBLE_SIMD_ALL_TRUE(pcmpeqb);
       break;
     }
-    case kIA32Prefetch:
-      __ prefetch(i.MemoryOperand(), 1);
-      break;
-    case kIA32PrefetchNta:
-      __ prefetch(i.MemoryOperand(), 0);
-      break;
     case kIA32Word32AtomicPairLoad: {
       XMMRegister tmp = i.ToDoubleRegister(instr->TempAt(0));
       __ movq(tmp, i.MemoryOperand());