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Regenerate stale files
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-92
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7 files changed

+704
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‎csharp/src/Google.Protobuf.Test.TestProtos/UnittestFeatures.pb.cs‎

Lines changed: 499 additions & 60 deletions
Large diffs are not rendered by default.

‎csharp/src/Google.Protobuf.Test/testprotos.pb‎

827 Bytes
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‎php/ext/google/protobuf/php-upb.c‎

Lines changed: 79 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -388,6 +388,27 @@ Error, UINTPTR_MAX is undefined
388388
#define UPB_PRESERVE_NONE
389389
#endif
390390

391+
#if defined(__aarch64__) && (defined(__GNUC__) || defined(__clang__))
392+
#define UPB_ARM64_ASM 1
393+
#else
394+
#define UPB_ARM64_ASM 0
395+
#endif
396+
397+
/* When compiling with branch protection, we need to ensure that all branch
398+
* targets in assembly use the appropriate landing pad instruction. These
399+
* instructions are backwards compatible with processors that don't have
400+
* FEAT_BTI and are treated as nops.
401+
*/
402+
#if UPB_ARM64_ASM && defined(__ARM_FEATURE_BTI_DEFAULT)
403+
#if __ARM_FEATURE_BTI_DEFAULT == 1
404+
#define UPB_ARM64_BTI_DEFAULT 1
405+
#else
406+
#define UPB_ARM64_BTI_DEFAULT 0
407+
#endif
408+
#else
409+
#define UPB_ARM64_BTI_DEFAULT 0
410+
#endif
411+
391412
/* This check is not fully robust: it does not require that we have "musttail"
392413
* support available. We need tail calls to avoid consuming arbitrary amounts
393414
* of stack space.
@@ -16748,15 +16769,27 @@ static char* encode_fixed32(char* ptr, upb_encstate* e, uint32_t val) {
1674816769

1674916770
#define UPB_PB_VARINT_MAX_LEN 10
1675016771

16751-
// Need gnu extended inline asm; msan can't instrument stores in inline assembly
16752-
#if defined(__aarch64__) && (defined(__GNUC__) || defined(__clang__)) && \
16753-
!UPB_HAS_FEATURE(memory_sanitizer)
16754-
#define UPB_ARM64_ASM
16772+
#if UPB_ARM64_ASM
16773+
// Each arm64 instruction encodes to 4 bytes, and it takes two intructions
16774+
// to process each byte of output, so we branch ahead by (4 + 4) * skip to
16775+
// avoid the remaining bytes. When BTI is on, we need to use specific
16776+
// "landing pad" instructions, so we pad those with nop to make it a power
16777+
// of 2, skipping 16 bytes at each stage instead of 8. This carries some
16778+
// overhead especially on in-order cores so they're not included unless
16779+
// building with branch protection.
16780+
#if UPB_ARM64_BTI_DEFAULT
16781+
// BTI is used with jc targets here because we don't control which register will
16782+
// be used for addr; if it's x16 or x17 a `br` is treated like a call.
16783+
#define UPB_BTI_JC "bti jc\n"
16784+
#define UPB_BTI_NOP "nop\n"
16785+
#define UPB_BTI_SHIFT_IMM "4\n"
16786+
#else
16787+
#define UPB_BTI_JC
16788+
#define UPB_BTI_NOP
16789+
#define UPB_BTI_SHIFT_IMM "3\n"
1675516790
#endif
16756-
16757-
#ifdef UPB_ARM64_ASM
16758-
UPB_NOINLINE static char* encode_longvarint_arm64(char* ptr, upb_encstate* e,
16759-
uint64_t val) {
16791+
UPB_NOINLINE static char* encode_longvarint(char* ptr, upb_encstate* e,
16792+
uint64_t val) {
1676016793
ptr = encode_reserve(ptr, e, UPB_PB_VARINT_MAX_LEN);
1676116794
uint64_t clz;
1676216795
__asm__("clz %[cnt], %[val]\n" : [cnt] "=r"(clz) : [val] "r"(val));
@@ -16767,37 +16800,66 @@ UPB_NOINLINE static char* encode_longvarint_arm64(char* ptr, upb_encstate* e,
1676716800
ptr += skip;
1676816801
uint64_t addr, mask;
1676916802
__asm__ volatile(
16803+
// Formatter keeps merging short lines
16804+
// clang-format off
1677016805
"adr %[addr], 0f\n"
16771-
// Each arm64 instruction encodes to 4 bytes, and it takes two
16772-
// intructions to process each byte of output, so we branch ahead by
16773-
// (4 + 4) * skip to avoid the remaining bytes.
16774-
"add %[addr], %[addr], %[cnt], lsl #3\n"
16806+
"add %[addr], %[addr], %[cnt], lsl #" UPB_BTI_SHIFT_IMM
1677516807
"mov %w[mask], #0x80\n"
1677616808
"br %[addr]\n"
16809+
".p2align " UPB_BTI_SHIFT_IMM
1677716810
"0:\n"
1677816811
// We don't need addr any more, but we've got the register for our whole
1677916812
// assembly block so we'll use it as scratch to store the shift+masked
1678016813
// values before storing them.
1678116814
// The following stores are unsigned offset stores:
1678216815
// strb Wt, [Xn, #imm]
16816+
UPB_BTI_JC
1678316817
"orr %[addr], %[mask], %[val], lsr #56\n"
1678416818
"strb %w[addr], [%[ptr], #8]\n"
16819+
UPB_BTI_NOP
16820+
16821+
UPB_BTI_JC
1678516822
"orr %[addr], %[mask], %[val], lsr #49\n"
1678616823
"strb %w[addr], [%[ptr], #7]\n"
16824+
UPB_BTI_NOP
16825+
16826+
UPB_BTI_JC
1678716827
"orr %[addr], %[mask], %[val], lsr #42\n"
1678816828
"strb %w[addr], [%[ptr], #6]\n"
16829+
UPB_BTI_NOP
16830+
16831+
UPB_BTI_JC
1678916832
"orr %[addr], %[mask], %[val], lsr #35\n"
1679016833
"strb %w[addr], [%[ptr], #5]\n"
16834+
UPB_BTI_NOP
16835+
16836+
UPB_BTI_JC
1679116837
"orr %[addr], %[mask], %[val], lsr #28\n"
1679216838
"strb %w[addr], [%[ptr], #4]\n"
16839+
UPB_BTI_NOP
16840+
16841+
UPB_BTI_JC
1679316842
"orr %w[addr], %w[mask], %w[val], lsr #21\n"
1679416843
"strb %w[addr], [%[ptr], #3]\n"
16844+
UPB_BTI_NOP
16845+
16846+
UPB_BTI_JC
1679516847
"orr %w[addr], %w[mask], %w[val], lsr #14\n"
1679616848
"strb %w[addr], [%[ptr], #2]\n"
16849+
UPB_BTI_NOP
16850+
16851+
UPB_BTI_JC
1679716852
"orr %w[addr], %w[mask], %w[val], lsr #7\n"
1679816853
"strb %w[addr], [%[ptr], #1]\n"
16854+
UPB_BTI_NOP
16855+
16856+
UPB_BTI_JC
1679916857
"orr %w[addr], %w[val], #0x80\n"
1680016858
"strb %w[addr], [%[ptr]]\n"
16859+
UPB_BTI_NOP
16860+
16861+
UPB_BTI_JC
16862+
// clang-format on
1680116863
: [addr] "=&r"(addr), [mask] "=&r"(mask)
1680216864
: [val] "r"(val), [ptr] "r"(ptr), [cnt] "r"((uint64_t)skip)
1680316865
: "memory");
@@ -16806,6 +16868,9 @@ UPB_NOINLINE static char* encode_longvarint_arm64(char* ptr, upb_encstate* e,
1680616868
ptr[continuations] = val >> (7 * continuations);
1680716869
return ptr;
1680816870
}
16871+
#undef UPB_BTI_JC
16872+
#undef UPB_BTI_NOP
16873+
#undef UPB_BTI_SHIFT_IMM
1680916874
#else
1681016875
UPB_NOINLINE
1681116876
static char* encode_longvarint(char* ptr, upb_encstate* e, uint64_t val) {
@@ -16830,11 +16895,7 @@ char* encode_varint(char* ptr, upb_encstate* e, uint64_t val) {
1683016895
*ptr = val;
1683116896
return ptr;
1683216897
} else {
16833-
#ifdef UPB_ARM64_ASM
16834-
return encode_longvarint_arm64(ptr, e, val);
16835-
#else
1683616898
return encode_longvarint(ptr, e, val);
16837-
#endif
1683816899
}
1683916900
}
1684016901

@@ -17623,3 +17684,5 @@ const char* UPB_PRIVATE(_upb_WireReader_SkipGroup)(
1762317684
#undef UPB_XSAN
1762417685
#undef UPB_XSAN_STRUCT_SIZE
1762517686
#undef UPB_ENABLE_REF_CYCLE_CHECKS
17687+
#undef UPB_ARM64_ASM
17688+
#undef UPB_ARM64_BTI_DEFAULT

‎php/ext/google/protobuf/php-upb.h‎

Lines changed: 23 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -387,6 +387,27 @@ Error, UINTPTR_MAX is undefined
387387
#define UPB_PRESERVE_NONE
388388
#endif
389389

390+
#if defined(__aarch64__) && (defined(__GNUC__) || defined(__clang__))
391+
#define UPB_ARM64_ASM 1
392+
#else
393+
#define UPB_ARM64_ASM 0
394+
#endif
395+
396+
/* When compiling with branch protection, we need to ensure that all branch
397+
* targets in assembly use the appropriate landing pad instruction. These
398+
* instructions are backwards compatible with processors that don't have
399+
* FEAT_BTI and are treated as nops.
400+
*/
401+
#if UPB_ARM64_ASM && defined(__ARM_FEATURE_BTI_DEFAULT)
402+
#if __ARM_FEATURE_BTI_DEFAULT == 1
403+
#define UPB_ARM64_BTI_DEFAULT 1
404+
#else
405+
#define UPB_ARM64_BTI_DEFAULT 0
406+
#endif
407+
#else
408+
#define UPB_ARM64_BTI_DEFAULT 0
409+
#endif
410+
390411
/* This check is not fully robust: it does not require that we have "musttail"
391412
* support available. We need tail calls to avoid consuming arbitrary amounts
392413
* of stack space.
@@ -16869,3 +16890,5 @@ UPB_PRIVATE(upb_WireWriter_VarintUnusedSizeFromLeadingZeros64)(uint64_t clz) {
1686916890
#undef UPB_XSAN
1687016891
#undef UPB_XSAN_STRUCT_SIZE
1687116892
#undef UPB_ENABLE_REF_CYCLE_CHECKS
16893+
#undef UPB_ARM64_ASM
16894+
#undef UPB_ARM64_BTI_DEFAULT

‎ruby/ext/google/protobuf_c/ruby-upb.c‎

Lines changed: 79 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -388,6 +388,27 @@ Error, UINTPTR_MAX is undefined
388388
#define UPB_PRESERVE_NONE
389389
#endif
390390

391+
#if defined(__aarch64__) && (defined(__GNUC__) || defined(__clang__))
392+
#define UPB_ARM64_ASM 1
393+
#else
394+
#define UPB_ARM64_ASM 0
395+
#endif
396+
397+
/* When compiling with branch protection, we need to ensure that all branch
398+
* targets in assembly use the appropriate landing pad instruction. These
399+
* instructions are backwards compatible with processors that don't have
400+
* FEAT_BTI and are treated as nops.
401+
*/
402+
#if UPB_ARM64_ASM && defined(__ARM_FEATURE_BTI_DEFAULT)
403+
#if __ARM_FEATURE_BTI_DEFAULT == 1
404+
#define UPB_ARM64_BTI_DEFAULT 1
405+
#else
406+
#define UPB_ARM64_BTI_DEFAULT 0
407+
#endif
408+
#else
409+
#define UPB_ARM64_BTI_DEFAULT 0
410+
#endif
411+
391412
/* This check is not fully robust: it does not require that we have "musttail"
392413
* support available. We need tail calls to avoid consuming arbitrary amounts
393414
* of stack space.
@@ -16300,15 +16321,27 @@ static char* encode_fixed32(char* ptr, upb_encstate* e, uint32_t val) {
1630016321

1630116322
#define UPB_PB_VARINT_MAX_LEN 10
1630216323

16303-
// Need gnu extended inline asm; msan can't instrument stores in inline assembly
16304-
#if defined(__aarch64__) && (defined(__GNUC__) || defined(__clang__)) && \
16305-
!UPB_HAS_FEATURE(memory_sanitizer)
16306-
#define UPB_ARM64_ASM
16324+
#if UPB_ARM64_ASM
16325+
// Each arm64 instruction encodes to 4 bytes, and it takes two intructions
16326+
// to process each byte of output, so we branch ahead by (4 + 4) * skip to
16327+
// avoid the remaining bytes. When BTI is on, we need to use specific
16328+
// "landing pad" instructions, so we pad those with nop to make it a power
16329+
// of 2, skipping 16 bytes at each stage instead of 8. This carries some
16330+
// overhead especially on in-order cores so they're not included unless
16331+
// building with branch protection.
16332+
#if UPB_ARM64_BTI_DEFAULT
16333+
// BTI is used with jc targets here because we don't control which register will
16334+
// be used for addr; if it's x16 or x17 a `br` is treated like a call.
16335+
#define UPB_BTI_JC "bti jc\n"
16336+
#define UPB_BTI_NOP "nop\n"
16337+
#define UPB_BTI_SHIFT_IMM "4\n"
16338+
#else
16339+
#define UPB_BTI_JC
16340+
#define UPB_BTI_NOP
16341+
#define UPB_BTI_SHIFT_IMM "3\n"
1630716342
#endif
16308-
16309-
#ifdef UPB_ARM64_ASM
16310-
UPB_NOINLINE static char* encode_longvarint_arm64(char* ptr, upb_encstate* e,
16311-
uint64_t val) {
16343+
UPB_NOINLINE static char* encode_longvarint(char* ptr, upb_encstate* e,
16344+
uint64_t val) {
1631216345
ptr = encode_reserve(ptr, e, UPB_PB_VARINT_MAX_LEN);
1631316346
uint64_t clz;
1631416347
__asm__("clz %[cnt], %[val]\n" : [cnt] "=r"(clz) : [val] "r"(val));
@@ -16319,37 +16352,66 @@ UPB_NOINLINE static char* encode_longvarint_arm64(char* ptr, upb_encstate* e,
1631916352
ptr += skip;
1632016353
uint64_t addr, mask;
1632116354
__asm__ volatile(
16355+
// Formatter keeps merging short lines
16356+
// clang-format off
1632216357
"adr %[addr], 0f\n"
16323-
// Each arm64 instruction encodes to 4 bytes, and it takes two
16324-
// intructions to process each byte of output, so we branch ahead by
16325-
// (4 + 4) * skip to avoid the remaining bytes.
16326-
"add %[addr], %[addr], %[cnt], lsl #3\n"
16358+
"add %[addr], %[addr], %[cnt], lsl #" UPB_BTI_SHIFT_IMM
1632716359
"mov %w[mask], #0x80\n"
1632816360
"br %[addr]\n"
16361+
".p2align " UPB_BTI_SHIFT_IMM
1632916362
"0:\n"
1633016363
// We don't need addr any more, but we've got the register for our whole
1633116364
// assembly block so we'll use it as scratch to store the shift+masked
1633216365
// values before storing them.
1633316366
// The following stores are unsigned offset stores:
1633416367
// strb Wt, [Xn, #imm]
16368+
UPB_BTI_JC
1633516369
"orr %[addr], %[mask], %[val], lsr #56\n"
1633616370
"strb %w[addr], [%[ptr], #8]\n"
16371+
UPB_BTI_NOP
16372+
16373+
UPB_BTI_JC
1633716374
"orr %[addr], %[mask], %[val], lsr #49\n"
1633816375
"strb %w[addr], [%[ptr], #7]\n"
16376+
UPB_BTI_NOP
16377+
16378+
UPB_BTI_JC
1633916379
"orr %[addr], %[mask], %[val], lsr #42\n"
1634016380
"strb %w[addr], [%[ptr], #6]\n"
16381+
UPB_BTI_NOP
16382+
16383+
UPB_BTI_JC
1634116384
"orr %[addr], %[mask], %[val], lsr #35\n"
1634216385
"strb %w[addr], [%[ptr], #5]\n"
16386+
UPB_BTI_NOP
16387+
16388+
UPB_BTI_JC
1634316389
"orr %[addr], %[mask], %[val], lsr #28\n"
1634416390
"strb %w[addr], [%[ptr], #4]\n"
16391+
UPB_BTI_NOP
16392+
16393+
UPB_BTI_JC
1634516394
"orr %w[addr], %w[mask], %w[val], lsr #21\n"
1634616395
"strb %w[addr], [%[ptr], #3]\n"
16396+
UPB_BTI_NOP
16397+
16398+
UPB_BTI_JC
1634716399
"orr %w[addr], %w[mask], %w[val], lsr #14\n"
1634816400
"strb %w[addr], [%[ptr], #2]\n"
16401+
UPB_BTI_NOP
16402+
16403+
UPB_BTI_JC
1634916404
"orr %w[addr], %w[mask], %w[val], lsr #7\n"
1635016405
"strb %w[addr], [%[ptr], #1]\n"
16406+
UPB_BTI_NOP
16407+
16408+
UPB_BTI_JC
1635116409
"orr %w[addr], %w[val], #0x80\n"
1635216410
"strb %w[addr], [%[ptr]]\n"
16411+
UPB_BTI_NOP
16412+
16413+
UPB_BTI_JC
16414+
// clang-format on
1635316415
: [addr] "=&r"(addr), [mask] "=&r"(mask)
1635416416
: [val] "r"(val), [ptr] "r"(ptr), [cnt] "r"((uint64_t)skip)
1635516417
: "memory");
@@ -16358,6 +16420,9 @@ UPB_NOINLINE static char* encode_longvarint_arm64(char* ptr, upb_encstate* e,
1635816420
ptr[continuations] = val >> (7 * continuations);
1635916421
return ptr;
1636016422
}
16423+
#undef UPB_BTI_JC
16424+
#undef UPB_BTI_NOP
16425+
#undef UPB_BTI_SHIFT_IMM
1636116426
#else
1636216427
UPB_NOINLINE
1636316428
static char* encode_longvarint(char* ptr, upb_encstate* e, uint64_t val) {
@@ -16382,11 +16447,7 @@ char* encode_varint(char* ptr, upb_encstate* e, uint64_t val) {
1638216447
*ptr = val;
1638316448
return ptr;
1638416449
} else {
16385-
#ifdef UPB_ARM64_ASM
16386-
return encode_longvarint_arm64(ptr, e, val);
16387-
#else
1638816450
return encode_longvarint(ptr, e, val);
16389-
#endif
1639016451
}
1639116452
}
1639216453

@@ -17175,3 +17236,5 @@ const char* UPB_PRIVATE(_upb_WireReader_SkipGroup)(
1717517236
#undef UPB_XSAN
1717617237
#undef UPB_XSAN_STRUCT_SIZE
1717717238
#undef UPB_ENABLE_REF_CYCLE_CHECKS
17239+
#undef UPB_ARM64_ASM
17240+
#undef UPB_ARM64_BTI_DEFAULT

‎ruby/ext/google/protobuf_c/ruby-upb.h‎

Lines changed: 23 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -389,6 +389,27 @@ Error, UINTPTR_MAX is undefined
389389
#define UPB_PRESERVE_NONE
390390
#endif
391391

392+
#if defined(__aarch64__) && (defined(__GNUC__) || defined(__clang__))
393+
#define UPB_ARM64_ASM 1
394+
#else
395+
#define UPB_ARM64_ASM 0
396+
#endif
397+
398+
/* When compiling with branch protection, we need to ensure that all branch
399+
* targets in assembly use the appropriate landing pad instruction. These
400+
* instructions are backwards compatible with processors that don't have
401+
* FEAT_BTI and are treated as nops.
402+
*/
403+
#if UPB_ARM64_ASM && defined(__ARM_FEATURE_BTI_DEFAULT)
404+
#if __ARM_FEATURE_BTI_DEFAULT == 1
405+
#define UPB_ARM64_BTI_DEFAULT 1
406+
#else
407+
#define UPB_ARM64_BTI_DEFAULT 0
408+
#endif
409+
#else
410+
#define UPB_ARM64_BTI_DEFAULT 0
411+
#endif
412+
392413
/* This check is not fully robust: it does not require that we have "musttail"
393414
* support available. We need tail calls to avoid consuming arbitrary amounts
394415
* of stack space.
@@ -16708,3 +16729,5 @@ UPB_PRIVATE(upb_WireWriter_VarintUnusedSizeFromLeadingZeros64)(uint64_t clz) {
1670816729
#undef UPB_XSAN
1670916730
#undef UPB_XSAN_STRUCT_SIZE
1671016731
#undef UPB_ENABLE_REF_CYCLE_CHECKS
16732+
#undef UPB_ARM64_ASM
16733+
#undef UPB_ARM64_BTI_DEFAULT

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