diff --git a/ports/stm32/boards/DEV190806042/bdev.c b/ports/stm32/boards/DEV190806042/bdev.c
new file mode 100644
index 0000000000000..9305fb3551cc5
--- /dev/null
+++ b/ports/stm32/boards/DEV190806042/bdev.c
@@ -0,0 +1,46 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2018-2019 Damien P. George
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "storage.h"
+#include "qspi.h"
+
+#if MICROPY_HW_SPIFLASH_ENABLE_CACHE
+// Shared cache for first and second SPI block devices
+static mp_spiflash_cache_t spi_bdev_cache;
+#endif
+
+// First external SPI flash uses hardware QSPI interface
+
+const mp_spiflash_config_t spiflash_config = {
+    .bus_kind = MP_SPIFLASH_BUS_QSPI,
+    .bus.u_qspi.data = NULL,
+    .bus.u_qspi.proto = &qspi_proto,
+    #if MICROPY_HW_SPIFLASH_ENABLE_CACHE
+    .cache = &spi_bdev_cache,
+    #endif
+};
+
+spi_bdev_t spi_bdev;
diff --git a/ports/stm32/boards/DEV190806042/board.json b/ports/stm32/boards/DEV190806042/board.json
new file mode 100644
index 0000000000000..30943308086ad
--- /dev/null
+++ b/ports/stm32/boards/DEV190806042/board.json
@@ -0,0 +1,16 @@
+{
+    "deploy": [
+        "../deploy.md"
+    ],
+    "docs": "",
+    "features": [],
+    "images": [
+        "DEV190806042.jpg",
+        "DEV190806042_B.jpg"
+    ],
+    "mcu": "stm32h7",
+    "product": "DEV190806042",
+    "thumbnail": "",
+    "url": "",
+    "vendor": "Aliexpress"
+}
diff --git a/ports/stm32/boards/DEV190806042/manifest.py b/ports/stm32/boards/DEV190806042/manifest.py
new file mode 100644
index 0000000000000..832942f052606
--- /dev/null
+++ b/ports/stm32/boards/DEV190806042/manifest.py
@@ -0,0 +1 @@
+include("$(PORT_DIR)/boards/manifest.py")
diff --git a/ports/stm32/boards/DEV190806042/mpconfigboard.h b/ports/stm32/boards/DEV190806042/mpconfigboard.h
new file mode 100644
index 0000000000000..1ddd01a8cd44d
--- /dev/null
+++ b/ports/stm32/boards/DEV190806042/mpconfigboard.h
@@ -0,0 +1,196 @@
+#define MICROPY_HW_BOARD_NAME       "DEV190806042"
+#define MICROPY_HW_MCU_NAME         "STM32H743"
+
+#define MICROPY_HW_ENABLE_RTC       (1)
+#define MICROPY_HW_ENABLE_SERVO     (1)
+#define MICROPY_HW_ENABLE_RNG       (1)
+#define MICROPY_HW_ENABLE_HW_I2C    (1)
+#define MICROPY_HW_ENABLE_ADC       (1)
+#define MICROPY_HW_ENABLE_DAC       (1)
+#define MICROPY_HW_ENABLE_USB       (1)
+#define MICROPY_HW_USB_HID          (1)
+#define MICROPY_HW_ENABLE_SDCARD    (0)
+#define MICROPY_HW_HAS_FLASH        (1)
+#define MICROPY_HW_ENABLE_STORAGE   (1)
+
+#define MODULE_ST_LTDC_ENABLED      (1)
+#define MODULE_TOUCH_I2C_ENABLED    (1)
+
+// CAUTION: Do not enable! A bug here creates incorrect Option Bytes,
+// potentially bricking the device.
+#define MICROPY_HW_ENABLE_INTERNAL_FLASH_STORAGE (0)
+
+#define MICROPY_HW_ENTER_BOOTLOADER_VIA_RESET   (0)
+#define MICROPY_HW_SDCARD_MOUNT_AT_BOOT         (0)
+
+#if defined(MODULE_ST_LTDC_ENABLED) && MODULE_ST_LTDC_ENABLED
+extern void lv_deinit(void);
+#define MICROPY_BOARD_START_SOFT_RESET(state) do { boardctrl_start_soft_reset(state); lv_deinit(); } while(0)
+#endif
+
+// The board has an 25MHz HSE, the following gives 480MHz CPU speed
+#define MICROPY_HW_CLK_PLLM         (5)
+#define MICROPY_HW_CLK_PLLN         (192)
+#define MICROPY_HW_CLK_PLLP         (2)
+#define MICROPY_HW_CLK_PLLQ         (2)
+#define MICROPY_HW_CLK_PLLR         (2)
+#define MICROPY_HW_CLK_PLLVCI       (RCC_PLL1VCIRANGE_2)
+#define MICROPY_HW_CLK_PLLVCO       (RCC_PLL1VCOWIDE)
+#define MICROPY_HW_CLK_PLLFRAC      (0)
+
+// Bus clock divider values
+#define MICROPY_HW_CLK_AHB_DIV      (RCC_HCLK_DIV2)
+#define MICROPY_HW_CLK_APB1_DIV     (RCC_APB1_DIV2)
+#define MICROPY_HW_CLK_APB2_DIV     (RCC_APB2_DIV2)
+#define MICROPY_HW_CLK_APB3_DIV     (RCC_APB3_DIV2)
+#define MICROPY_HW_CLK_APB4_DIV     (RCC_APB4_DIV2)
+
+// 4 wait states
+#define MICROPY_HW_FLASH_LATENCY    FLASH_LATENCY_4
+
+// UART config
+#define MICROPY_HW_UART1_TX         (pin_A9)
+#define MICROPY_HW_UART1_RX         (pin_A10)
+#define MICROPY_HW_UART_REPL        PYB_UART_1
+#define MICROPY_HW_UART_REPL_BAUD   115200
+
+// FLASH QSPI config - W25Q256
+#define MICROPY_HW_QSPIFLASH_SIZE_BITS_LOG2  (28)
+#define MICROPY_HW_QSPIFLASH_CS              (pin_G6)
+#define MICROPY_HW_QSPIFLASH_SCK             (pin_F10)
+#define MICROPY_HW_QSPIFLASH_IO0             (pin_F8)
+#define MICROPY_HW_QSPIFLASH_IO1             (pin_F9)
+#define MICROPY_HW_QSPIFLASH_IO2             (pin_F7)
+#define MICROPY_HW_QSPIFLASH_IO3             (pin_F6)
+
+// Block device config for SPI flash
+extern const struct _mp_spiflash_config_t spiflash_config;
+extern struct _spi_bdev_t spi_bdev;
+#define MICROPY_HW_SPIFLASH_ENABLE_CACHE    (1)
+#define MICROPY_HW_BDEV_SPIFLASH            (&spi_bdev)
+#define MICROPY_HW_BDEV_SPIFLASH_CONFIG     (&spiflash_config)
+#define MICROPY_HW_SPIFLASH_SIZE_BITS       (256 * 1024 * 1024)
+#define MICROPY_HW_BDEV_SPIFLASH_SIZE_BYTES (MICROPY_HW_SPIFLASH_SIZE_BITS / 8)
+#define MICROPY_HW_QSPI_PRESCALER           (2)
+#define MICROPY_HW_BDEV_SPIFLASH_EXTENDED   (&spi_bdev)
+
+// USB config
+// Enable the HSI48 oscillator and route it to USB
+#define MICROPY_HW_RCC_HSI48_STATE      (RCC_HSI48_ON)
+#define MICROPY_HW_RCC_USB_CLKSOURCE    (RCC_USBCLKSOURCE_HSI48)
+
+#define MICROPY_HW_USB_FS           (1)
+#define MICROPY_HW_USB_HS           (0)
+#define MICROPY_HW_USB_HS_IN_FS     (0)
+#define MICROPY_HW_USB_MAIN_DEV     (USB_PHY_FS_ID)
+#define MICROPY_HW_USB_CDC_NUM      (2)
+#define MICROPY_HW_USB_MSC          (1)
+
+#define MICROPY_HW_USB_PRODUCT_FS_STRING          "STM32H7 Virtual Comm Port in FS Mode"
+#define MICROPY_HW_USB_INTERFACE_FS_STRING        "STM32H7 Interface"
+#define MICROPY_HW_USB_MSC_INQUIRY_PRODUCT_STRING "STM32H7 Flash   "
+
+#define MICROPY_HW_LED1             (pin_B0)
+#define MICROPY_HW_LED_ON(pin)      (mp_hal_pin_low(pin))
+#define MICROPY_HW_LED_OFF(pin)     (mp_hal_pin_high(pin))
+
+#define MICROPY_HW_USRSW_PIN        (pin_A0)
+#define MICROPY_HW_HAS_SWITCH       (1)
+// USRSW is pulled low. Pressing the button makes the input go high.
+#define MICROPY_HW_USRSW_PULL       (GPIO_NOPULL)
+#define MICROPY_HW_USRSW_EXTI_MODE  (GPIO_MODE_IT_RISING)
+#define MICROPY_HW_USRSW_PRESSED    (1)
+
+// I2C buses
+#define MICROPY_HW_I2C4_SCL         (pin_D12)
+#define MICROPY_HW_I2C4_SDA         (pin_D13)
+
+// SDRAM
+#define MICROPY_HW_SDRAM_SIZE               (32 * 1024 * 1024)
+#define MICROPY_HW_SDRAM_STARTUP_TEST       (1)
+#define MICROPY_HW_SDRAM_TEST_FAIL_ON_ERROR (1)
+#define MICROPY_HEAP_START  ((sdram_valid) ? sdram_start() : &_heap_start)
+#define MICROPY_HEAP_END    ((sdram_valid) ? sdram_end() : &_heap_end)
+
+// Timing configuration for SDRAM @120Mhz
+#define MICROPY_HW_SDRAM_TIMING_TMRD        (2)
+#define MICROPY_HW_SDRAM_TIMING_TXSR        (9)
+#define MICROPY_HW_SDRAM_TIMING_TRAS        (6)
+#define MICROPY_HW_SDRAM_TIMING_TRC         (8)
+#define MICROPY_HW_SDRAM_TIMING_TWR         (2)
+#define MICROPY_HW_SDRAM_TIMING_TRP         (3)
+#define MICROPY_HW_SDRAM_TIMING_TRCD        (3)
+#define MICROPY_HW_SDRAM_REFRESH_RATE       (64)
+// Required by upstream micropython SDRAM driver;
+// harmless on lv_micropython until sync.
+#define MICROPY_HW_SDRAM_FREQUENCY_KHZ      (120000) // 120 MHz
+#define MICROPY_HW_SDRAM_REFRESH_CYCLES     8192
+
+#define MICROPY_HW_SDRAM_BURST_LENGTH       8
+#define MICROPY_HW_SDRAM_CAS_LATENCY        2
+#define MICROPY_HW_SDRAM_COLUMN_BITS_NUM    9
+#define MICROPY_HW_SDRAM_ROW_BITS_NUM       12
+#define MICROPY_HW_SDRAM_MEM_BUS_WIDTH      32
+#define MICROPY_HW_SDRAM_INTERN_BANKS_NUM   4
+#define MICROPY_HW_SDRAM_CLOCK_PERIOD       2
+#define MICROPY_HW_SDRAM_RPIPE_DELAY        1
+#define MICROPY_HW_SDRAM_RBURST             (1)
+#define MICROPY_HW_SDRAM_WRITE_PROTECTION   (0)
+#define MICROPY_HW_SDRAM_AUTOREFRESH_NUM    (4)
+
+#define MICROPY_HW_FMC_SDNE0        (pin_C2)
+#define MICROPY_HW_FMC_SDCKE0       (pin_C3)
+#define MICROPY_HW_FMC_SDNWE        (pin_C0)
+#define MICROPY_HW_FMC_SDNRAS       (pin_F11)
+#define MICROPY_HW_FMC_SDNCAS       (pin_G15)
+#define MICROPY_HW_FMC_SDCLK        (pin_G8)
+#define MICROPY_HW_FMC_BA0          (pin_G4)
+#define MICROPY_HW_FMC_BA1          (pin_G5)
+#define MICROPY_HW_FMC_NBL0         (pin_E0)
+#define MICROPY_HW_FMC_NBL1         (pin_E1)
+#define MICROPY_HW_FMC_NBL2         (pin_I4)
+#define MICROPY_HW_FMC_NBL3         (pin_I5)
+#define MICROPY_HW_FMC_A0           (pin_F0)
+#define MICROPY_HW_FMC_A1           (pin_F1)
+#define MICROPY_HW_FMC_A2           (pin_F2)
+#define MICROPY_HW_FMC_A3           (pin_F3)
+#define MICROPY_HW_FMC_A4           (pin_F4)
+#define MICROPY_HW_FMC_A5           (pin_F5)
+#define MICROPY_HW_FMC_A6           (pin_F12)
+#define MICROPY_HW_FMC_A7           (pin_F13)
+#define MICROPY_HW_FMC_A8           (pin_F14)
+#define MICROPY_HW_FMC_A9           (pin_F15)
+#define MICROPY_HW_FMC_A10          (pin_G0)
+#define MICROPY_HW_FMC_A11          (pin_G1)
+#define MICROPY_HW_FMC_D0           (pin_D14)
+#define MICROPY_HW_FMC_D1           (pin_D15)
+#define MICROPY_HW_FMC_D2           (pin_D0)
+#define MICROPY_HW_FMC_D3           (pin_D1)
+#define MICROPY_HW_FMC_D4           (pin_E7)
+#define MICROPY_HW_FMC_D5           (pin_E8)
+#define MICROPY_HW_FMC_D6           (pin_E9)
+#define MICROPY_HW_FMC_D7           (pin_E10)
+#define MICROPY_HW_FMC_D8           (pin_E11)
+#define MICROPY_HW_FMC_D9           (pin_E12)
+#define MICROPY_HW_FMC_D10          (pin_E13)
+#define MICROPY_HW_FMC_D11          (pin_E14)
+#define MICROPY_HW_FMC_D12          (pin_E15)
+#define MICROPY_HW_FMC_D13          (pin_D8)
+#define MICROPY_HW_FMC_D14          (pin_D9)
+#define MICROPY_HW_FMC_D15          (pin_D10)
+#define MICROPY_HW_FMC_D16          (pin_H8)
+#define MICROPY_HW_FMC_D17          (pin_H9)
+#define MICROPY_HW_FMC_D18          (pin_H10)
+#define MICROPY_HW_FMC_D19          (pin_H11)
+#define MICROPY_HW_FMC_D20          (pin_H12)
+#define MICROPY_HW_FMC_D21          (pin_H13)
+#define MICROPY_HW_FMC_D22          (pin_H14)
+#define MICROPY_HW_FMC_D23          (pin_H15)
+#define MICROPY_HW_FMC_D24          (pin_I0)
+#define MICROPY_HW_FMC_D25          (pin_I1)
+#define MICROPY_HW_FMC_D26          (pin_I2)
+#define MICROPY_HW_FMC_D27          (pin_I3)
+#define MICROPY_HW_FMC_D28          (pin_I6)
+#define MICROPY_HW_FMC_D29          (pin_I7)
+#define MICROPY_HW_FMC_D30          (pin_I9)
+#define MICROPY_HW_FMC_D31          (pin_I10)
diff --git a/ports/stm32/boards/DEV190806042/mpconfigboard.mk b/ports/stm32/boards/DEV190806042/mpconfigboard.mk
new file mode 100644
index 0000000000000..cfccf8dab4816
--- /dev/null
+++ b/ports/stm32/boards/DEV190806042/mpconfigboard.mk
@@ -0,0 +1,39 @@
+
+# MCU settings
+MCU_SERIES = h7
+CMSIS_MCU = STM32H743xx
+MICROPY_FLOAT_IMPL = double
+AF_FILE = boards/stm32h743_af.csv
+TOP_DIR := $(abspath ../..)
+
+# Enable LVGL modules
+LV_CONF_PATH = ${TOP_DIR}/user_modules/lv_binding_micropython/driver/stm32/st_ltdc/lv_conf.h
+USER_C_MODULES = ${TOP_DIR}/user_modules/lv_binding_micropython/micropython.mk
+USER_C_MODULES += ${TOP_DIR}/user_modules/lv_binding_micropython/driver/stm32/st_ltdc
+
+ifeq ($(USE_MBOOT),1)
+# When using Mboot everything goes after the bootloader
+LD_FILES = boards/FK743M5-XIH6/stm32h743.ld
+TEXT0_ADDR = 0x08020000
+else
+# When not using Mboot everything goes at the start of flash
+LD_FILES = boards/FK743M5-XIH6/stm32h743.ld
+TEXT0_ADDR = 0x08000000
+endif
+
+# MicroPython settings
+MICROPY_PY_LWIP = 0
+MICROPY_PY_SSL = 0
+MICROPY_SSL_MBEDTLS = 0
+MICROPY_VFS_LFS2 = 1
+MICROPY_VFS_FAT = 1
+MICROPY_HW_ENABLE_ISR_UART_FLASH_FUNCS_IN_RAM = 1
+
+FROZEN_MANIFEST ?= $(BOARD_DIR)/manifest.py
+FROZEN_MANIFEST += ${TOP_DIR}/user_modules/lv_binding_micropython/driver/stm32/st_ltdc/manifest.py
+
+HAL_SRC_C += $(addprefix $(STM32LIB_HAL_BASE)/Src/stm32$(MCU_SERIES)xx_,\
+	hal_ltdc.c \
+	hal_ltdc_ex.c \
+	hal_dma2d.c \
+	)
diff --git a/ports/stm32/boards/DEV190806042/pins.csv b/ports/stm32/boards/DEV190806042/pins.csv
new file mode 100644
index 0000000000000..bbf8729bacee5
--- /dev/null
+++ b/ports/stm32/boards/DEV190806042/pins.csv
@@ -0,0 +1,141 @@
+A0,PA0
+A1,PA1
+A2,PA2
+A3,PA3
+A4,PA4
+A5,PA5
+A9,PA9
+A10,PA10
+A11,PA11
+A12,PA12
+A13,PA13
+A14,PA14
+A15,PA15
+B0,PB0
+B1,PB1
+B2,PB2
+B3,PB3
+B4,PB4
+B5,PB5
+B6,PB6
+B7,PB7
+B8,PB8
+B9,PB9
+B10,PB10
+B11,PB11
+B12,PB12
+B13,PB13
+B14,PB14
+B15,PB15
+C0,PC0
+C1,PC1
+C2,PC2
+C3,PC3
+C4,PC4
+C5,PC5
+C6,PC6
+C7,PC7
+C8,PC8
+C9,PC9
+C10,PC10
+C11,PC11
+C12,PC12
+C13,PC13
+C14,PC14
+C15,PC15
+D0,PD0
+D1,PD1
+D2,PD2
+D3,PD3
+D4,PD4
+D5,PD5
+D6,PD6
+D7,PD7
+D8,PD8
+D9,PD9
+D10,PD10
+D11,PD11
+D12,PD12
+D13,PD13
+D14,PD14
+D15,PD15
+E0,PE0
+E1,PE1
+E2,PE2
+E3,PE3
+E4,PE4
+E5,PE5
+E6,PE6
+E7,PE7
+E8,PE8
+E9,PE9
+E10,PE10
+E11,PE11
+E12,PE12
+E13,PE13
+E14,PE14
+E15,PE15
+F0,PF0
+F1,PF1
+F2,PF2
+F3,PF3
+F4,PF4
+F5,PF5
+F6,PF6
+F7,PF7
+F8,PF8
+F9,PF9
+F10,PF10
+F11,PF11
+F12,PF12
+F13,PF13
+F14,PF14
+F15,PF15
+G0,PG0
+G1,PG1
+G2,PG2
+G3,PG3
+G4,PG4
+G5,PG5
+G6,PG6
+G7,PG7
+G8,PG8
+G9,PG9
+G10,PG10
+G11,PG11
+G12,PG12
+G13,PG13
+G14,PG14
+G15,PG15
+H0,PH0
+H1,PH1
+H2,PH2
+H3,PH3
+H4,PH4
+H5,PH5
+H6,PH6
+H7,PH7
+H8,PH8
+H9,PH9
+H10,PH10
+H11,PH11
+H12,PH12
+H13,PH13
+H14,PH14
+H15,PH15
+I0,PI0
+I1,PI1
+I2,PI2
+I3,PI3
+I4,PI4
+I5,PI5
+I6,PI6
+I7,PI7
+I8,PI8
+I9,PI9
+I10,PI10
+I11,PI11
+I12,PI12
+I13,PI13
+I14,PI14
+I15,PI15
diff --git a/ports/stm32/boards/DEV190806042/stm32h743.ld b/ports/stm32/boards/DEV190806042/stm32h743.ld
new file mode 100644
index 0000000000000..4be8e549ed2ab
--- /dev/null
+++ b/ports/stm32/boards/DEV190806042/stm32h743.ld
@@ -0,0 +1,53 @@
+/*
+    GNU linker script for STM32H743
+*/
+
+/* Specify the memory areas */
+MEMORY
+{
+    FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 2M      /* sectors (0-15)  */
+    FLASH_APP  (rx) : ORIGIN = 0x08020000, LENGTH = 1920K   /* sectors (1-15)  */
+    DTCM (xrw)      : ORIGIN = 0x20000000, LENGTH = 128K    /* Used for storage cache */
+    RAM (xrw)       : ORIGIN = 0x24000000, LENGTH = 512K    /* AXI SRAM */
+    RAM_D2 (xrw)    : ORIGIN = 0x30000000, LENGTH = 288K
+    SDRAM (xrw)     : ORIGIN = 0xC0000000, LENGTH = 32M     /* external SDRAM */
+}
+
+/* produce a link error if there is not this amount of RAM for these sections */
+_minimum_stack_size = 2K;
+_minimum_heap_size = 16K;
+
+/* Define the stack.  The stack is full descending so begins just above last byte
+   of RAM.  Note that EABI requires the stack to be 8-byte aligned for a call. */
+_estack = ORIGIN(RAM) + LENGTH(RAM) - _estack_reserve;
+_sstack = _estack - 16K; /* tunable */
+
+/* RAM extents for the garbage collector */
+_ram_start = ORIGIN(RAM);
+_ram_end = ORIGIN(RAM) + LENGTH(RAM);
+_heap_start = _ebss; /* heap starts just after statically allocated memory */
+_heap_end = _sstack;
+
+/* Location of filesystem RAM cache */
+_micropy_hw_internal_flash_storage_ram_cache_start = ORIGIN(DTCM);
+_micropy_hw_internal_flash_storage_ram_cache_end = ORIGIN(DTCM) + LENGTH(DTCM);
+
+/* Define output sections */
+SECTIONS
+{
+    .sdram_pool (NOLOAD) :
+    {
+       . = ALIGN(32);
+       _sdram_pool_start = .;
+    } > SDRAM
+
+    /* Define the end of the SDRAM pool to prevent overflow */
+    _sdram_pool_end = ORIGIN(SDRAM) + LENGTH(SDRAM);
+
+    .eth_buffers (NOLOAD) : {
+        . = ABSOLUTE(0x30040000);
+        *eth.o*(.bss.eth_dma)
+    } >RAM_D2
+}
+
+INCLUDE common_basic.ld
diff --git a/ports/stm32/boards/DEV190806042/stm32h7xx_hal_conf.h b/ports/stm32/boards/DEV190806042/stm32h7xx_hal_conf.h
new file mode 100644
index 0000000000000..cdf8b3b0c54fa
--- /dev/null
+++ b/ports/stm32/boards/DEV190806042/stm32h7xx_hal_conf.h
@@ -0,0 +1,101 @@
+/* This file is part of the MicroPython project, http://micropython.org/
+ * The MIT License (MIT)
+ * Copyright (c) 2019 Damien P. George
+ */
+#ifndef MICROPY_INCLUDED_STM32H7XX_HAL_CONF_H
+#define MICROPY_INCLUDED_STM32H7XX_HAL_CONF_H
+
+// Oscillator values in Hz
+#define HSE_VALUE (25000000)
+#define LSE_VALUE (32768)
+#define EXTERNAL_CLOCK_VALUE (12288000)
+
+// Oscillator timeouts in ms
+#define HSE_STARTUP_TIMEOUT (5000)
+#define LSE_STARTUP_TIMEOUT (5000)
+
+// Enable various HAL modules
+#define HAL_ADC_MODULE_ENABLED
+#define HAL_DAC_MODULE_ENABLED
+#define HAL_LTDC_MODULE_ENABLED
+#define HAL_DMA2D_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_CRC_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_HASH_MODULE_ENABLED
+#define HAL_I2C_MODULE_ENABLED
+#define HAL_I2S_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_RTC_MODULE_ENABLED
+#define HAL_SD_MODULE_ENABLED
+#define HAL_SDRAM_MODULE_ENABLED
+#define HAL_SPI_MODULE_ENABLED
+#define HAL_TIM_MODULE_ENABLED
+#define HAL_UART_MODULE_ENABLED
+#define HAL_USART_MODULE_ENABLED
+#define HAL_PCD_MODULE_ENABLED
+
+// Oscillator values in Hz
+#define CSI_VALUE (4000000)
+#define HSI_VALUE (64000000)
+
+// SysTick has the highest priority
+#define TICK_INT_PRIORITY (0x00)
+
+// Miscellaneous HAL settings
+#define USE_RTOS            0
+#define USE_SD_TRANSCEIVER  0
+#define USE_SPI_CRC         1
+
+// Include various HAL modules for convenience
+#include "stm32h7xx_hal_dma.h"
+#include "stm32h7xx_hal_mdma.h"
+#include "stm32h7xx_hal_adc.h"
+#include "stm32h7xx_hal_cortex.h"
+#include "stm32h7xx_hal_crc.h"
+#include "stm32h7xx_hal_dac.h"
+#include "stm32h7xx_hal_dcmi.h"
+#include "stm32h7xx_hal_fdcan.h"
+#include "stm32h7xx_hal_flash.h"
+#include "stm32h7xx_hal_gpio.h"
+#include "stm32h7xx_hal_hash.h"
+#include "stm32h7xx_hal_hcd.h"
+#include "stm32h7xx_hal_i2c.h"
+#include "stm32h7xx_hal_i2c_ex.h"
+#include "stm32h7xx_hal_i2s.h"
+#include "stm32h7xx_hal_iwdg.h"
+#include "stm32h7xx_hal_pcd.h"
+#include "stm32h7xx_hal_pwr.h"
+#include "stm32h7xx_hal_rcc.h"
+#include "stm32h7xx_hal_rtc.h"
+#include "stm32h7xx_hal_sd.h"
+#include "stm32h7xx_hal_sdram.h"
+#include "stm32h7xx_hal_spi.h"
+#include "stm32h7xx_hal_tim.h"
+#include "stm32h7xx_hal_uart.h"
+#include "stm32h7xx_hal_usart.h"
+#include "stm32h7xx_hal_wwdg.h"
+#include "stm32h7xx_hal_ltdc.h"
+#include "stm32h7xx_hal_dma2d.h"
+#include "stm32h7xx_ll_adc.h"
+#include "stm32h7xx_ll_lpuart.h"
+#include "stm32h7xx_ll_pwr.h"
+#include "stm32h7xx_ll_rcc.h"
+#include "stm32h7xx_ll_rtc.h"
+#include "stm32h7xx_ll_usart.h"
+
+// HAL parameter assertions are disabled
+#define assert_param(expr) ((void)0)
+
+// The STM32H7xx HAL defines LPUART1 AF macros without numbers.
+#ifndef GPIO_AF3_LPUART1
+#define GPIO_AF3_LPUART1 GPIO_AF3_LPUART
+#define GPIO_AF8_LPUART1 GPIO_AF8_LPUART
+#endif
+
+extern LTDC_HandleTypeDef hltdc;
+
+#endif // MICROPY_INCLUDED_STM32H7XX_HAL_CONF_H
diff --git a/ports/stm32/boards/FK743M5-XIH6/bdev.c b/ports/stm32/boards/FK743M5-XIH6/bdev.c
new file mode 100644
index 0000000000000..9305fb3551cc5
--- /dev/null
+++ b/ports/stm32/boards/FK743M5-XIH6/bdev.c
@@ -0,0 +1,46 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2018-2019 Damien P. George
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "storage.h"
+#include "qspi.h"
+
+#if MICROPY_HW_SPIFLASH_ENABLE_CACHE
+// Shared cache for first and second SPI block devices
+static mp_spiflash_cache_t spi_bdev_cache;
+#endif
+
+// First external SPI flash uses hardware QSPI interface
+
+const mp_spiflash_config_t spiflash_config = {
+    .bus_kind = MP_SPIFLASH_BUS_QSPI,
+    .bus.u_qspi.data = NULL,
+    .bus.u_qspi.proto = &qspi_proto,
+    #if MICROPY_HW_SPIFLASH_ENABLE_CACHE
+    .cache = &spi_bdev_cache,
+    #endif
+};
+
+spi_bdev_t spi_bdev;
diff --git a/ports/stm32/boards/FK743M5-XIH6/board.json b/ports/stm32/boards/FK743M5-XIH6/board.json
new file mode 100644
index 0000000000000..17aba382e9831
--- /dev/null
+++ b/ports/stm32/boards/FK743M5-XIH6/board.json
@@ -0,0 +1,16 @@
+{
+    "deploy": [
+        "../deploy.md"
+    ],
+    "docs": "",
+    "features": [],
+    "images": [
+        "FK743M5-XIH6.jpg",
+        "FK743M5-XIH6_B.jpg"
+    ],
+    "mcu": "stm32h7",
+    "product": "FK743M5-XIH6",
+    "thumbnail": "",
+    "url": "",
+    "vendor": "Aliexpress"
+}
diff --git a/ports/stm32/boards/FK743M5-XIH6/manifest.py b/ports/stm32/boards/FK743M5-XIH6/manifest.py
new file mode 100644
index 0000000000000..832942f052606
--- /dev/null
+++ b/ports/stm32/boards/FK743M5-XIH6/manifest.py
@@ -0,0 +1 @@
+include("$(PORT_DIR)/boards/manifest.py")
diff --git a/ports/stm32/boards/FK743M5-XIH6/mpconfigboard.h b/ports/stm32/boards/FK743M5-XIH6/mpconfigboard.h
new file mode 100644
index 0000000000000..a30cceccbe842
--- /dev/null
+++ b/ports/stm32/boards/FK743M5-XIH6/mpconfigboard.h
@@ -0,0 +1,181 @@
+#define MICROPY_HW_BOARD_NAME       "FK743M5-XIH6"
+#define MICROPY_HW_MCU_NAME         "STM32H743"
+
+#define MICROPY_HW_ENABLE_RTC       (1)
+#define MICROPY_HW_ENABLE_SERVO     (1)
+#define MICROPY_HW_ENABLE_RNG       (1)
+#define MICROPY_HW_ENABLE_HW_I2C    (1)
+#define MICROPY_HW_ENABLE_ADC       (1)
+#define MICROPY_HW_ENABLE_DAC       (1)
+#define MICROPY_HW_ENABLE_USB       (1)
+#define MICROPY_HW_USB_HID          (1)
+#define MICROPY_HW_ENABLE_SDCARD    (1)
+#define MICROPY_HW_HAS_FLASH        (1)
+#define MICROPY_HW_ENABLE_STORAGE   (1)
+
+#define MODULE_ST_LTDC_ENABLED      (1)
+#define MODULE_TOUCH_I2C_ENABLED    (1)
+
+// CAUTION: Do not enable! A bug here creates incorrect Option Bytes,
+// potentially bricking the device.
+#define MICROPY_HW_ENABLE_INTERNAL_FLASH_STORAGE (0)
+
+#define MICROPY_HW_ENTER_BOOTLOADER_VIA_RESET   (0)
+#define MICROPY_HW_SDCARD_MOUNT_AT_BOOT         (1)
+
+#if defined(MODULE_ST_LTDC_ENABLED) && MODULE_ST_LTDC_ENABLED
+extern void lv_deinit(void);
+#define MICROPY_BOARD_START_SOFT_RESET(state) do { boardctrl_start_soft_reset(state); lv_deinit(); } while(0)
+#endif
+
+// The board has a 25MHz HSE, the following gives 480MHz CPU speed
+#define MICROPY_HW_CLK_PLLM         (5)
+#define MICROPY_HW_CLK_PLLN         (192)
+#define MICROPY_HW_CLK_PLLP         (2)
+#define MICROPY_HW_CLK_PLLQ         (2)
+#define MICROPY_HW_CLK_PLLR         (2)
+#define MICROPY_HW_CLK_PLLVCI       (RCC_PLL1VCIRANGE_2)
+#define MICROPY_HW_CLK_PLLVCO       (RCC_PLL1VCOWIDE)
+#define MICROPY_HW_CLK_PLLFRAC      (0)
+
+// Bus clock divider values
+#define MICROPY_HW_CLK_AHB_DIV      (RCC_HCLK_DIV2)
+#define MICROPY_HW_CLK_APB1_DIV     (RCC_APB1_DIV2)
+#define MICROPY_HW_CLK_APB2_DIV     (RCC_APB2_DIV2)
+#define MICROPY_HW_CLK_APB3_DIV     (RCC_APB3_DIV2)
+#define MICROPY_HW_CLK_APB4_DIV     (RCC_APB4_DIV2)
+
+// 4 wait states
+#define MICROPY_HW_FLASH_LATENCY    FLASH_LATENCY_4
+
+#define MICROPY_HW_SDCARD_CK           (pin_C12)
+#define MICROPY_HW_SDCARD_CMD          (pin_D2)
+#define MICROPY_HW_SDCARD_D0           (pin_C8)
+#define MICROPY_HW_SDCARD_D1           (pin_C9)
+#define MICROPY_HW_SDCARD_D2           (pin_C10)
+#define MICROPY_HW_SDCARD_D3           (pin_C11)
+
+// UART config
+#define MICROPY_HW_UART1_TX         (pin_A9)
+#define MICROPY_HW_UART1_RX         (pin_A10)
+
+#define MICROPY_HW_UART_REPL        PYB_UART_1
+#define MICROPY_HW_UART_REPL_BAUD   115200
+
+// FLASH QSPI config - W25Q64 8MB
+#define MICROPY_HW_QSPIFLASH_SIZE_BITS_LOG2  (26)   /* 64 Mbit */
+#define MICROPY_HW_QSPIFLASH_CS              (pin_G6)
+#define MICROPY_HW_QSPIFLASH_SCK             (pin_F10)
+#define MICROPY_HW_QSPIFLASH_IO0             (pin_F8)
+#define MICROPY_HW_QSPIFLASH_IO1             (pin_F9)
+#define MICROPY_HW_QSPIFLASH_IO2             (pin_F7)
+#define MICROPY_HW_QSPIFLASH_IO3             (pin_F6)
+
+// Block device config for SPI flash
+extern const struct _mp_spiflash_config_t spiflash_config;
+extern struct _spi_bdev_t spi_bdev;
+#define MICROPY_HW_SPIFLASH_ENABLE_CACHE    (1)
+#define MICROPY_HW_BDEV_SPIFLASH            (&spi_bdev)
+#define MICROPY_HW_BDEV_SPIFLASH_CONFIG     (&spiflash_config)
+#define MICROPY_HW_SPIFLASH_SIZE_BITS       (64 * 1024 * 1024)
+#define MICROPY_HW_BDEV_SPIFLASH_SIZE_BYTES (MICROPY_HW_SPIFLASH_SIZE_BITS / 8)
+#define MICROPY_HW_QSPI_PRESCALER           (2)
+#define MICROPY_HW_BDEV_SPIFLASH_EXTENDED   (&spi_bdev)
+
+// USB config
+// Enable the HSI48 oscillator and route it to USB
+#define MICROPY_HW_RCC_HSI48_STATE      (RCC_HSI48_ON)
+#define MICROPY_HW_RCC_USB_CLKSOURCE    (RCC_USBCLKSOURCE_HSI48)
+
+#define MICROPY_HW_USB_FS           (1)
+#define MICROPY_HW_USB_HS           (0)
+#define MICROPY_HW_USB_HS_IN_FS     (0)
+#define MICROPY_HW_USB_MAIN_DEV     (USB_PHY_FS_ID)
+#define MICROPY_HW_USB_CDC_NUM      (2)
+#define MICROPY_HW_USB_MSC          (1)
+
+#define MICROPY_HW_USB_PRODUCT_FS_STRING          "STM32H7 Virtual Comm Port in FS Mode"
+#define MICROPY_HW_USB_INTERFACE_FS_STRING        "STM32H7 Interface"
+#define MICROPY_HW_USB_MSC_INQUIRY_PRODUCT_STRING "STM32H7 Flash   "
+
+#define MICROPY_HW_LED1             (pin_C13)
+
+#define MICROPY_HW_LED_ON(pin)      (mp_hal_pin_low(pin))
+#define MICROPY_HW_LED_OFF(pin)     (mp_hal_pin_high(pin))
+
+// I2C buses
+#define MICROPY_HW_I2C4_SCL         (pin_D12)
+#define MICROPY_HW_I2C4_SDA         (pin_D13)
+
+// SDRAM
+#define MICROPY_HW_SDRAM_SIZE               (32 * 1024 * 1024)  // 32MB
+#define MICROPY_HW_SDRAM_STARTUP_TEST       (1)
+#define MICROPY_HW_SDRAM_TEST_FAIL_ON_ERROR (1)
+#define MICROPY_HEAP_START  ((sdram_valid) ? sdram_start() : &_heap_start)
+#define MICROPY_HEAP_END    ((sdram_valid) ? sdram_end() : &_heap_end)
+
+// Timing configuration for SDRAM @120Mhz
+#define MICROPY_HW_SDRAM_TIMING_TMRD        (2)
+#define MICROPY_HW_SDRAM_TIMING_TXSR        (9)
+#define MICROPY_HW_SDRAM_TIMING_TRAS        (5)
+#define MICROPY_HW_SDRAM_TIMING_TRC         (8)
+#define MICROPY_HW_SDRAM_TIMING_TWR         (2)
+#define MICROPY_HW_SDRAM_TIMING_TRP         (3)
+#define MICROPY_HW_SDRAM_TIMING_TRCD        (3)
+#define MICROPY_HW_SDRAM_REFRESH_RATE       (64)
+// Required by upstream micropython SDRAM driver;
+// harmless on lv_micropython until sync.
+#define MICROPY_HW_SDRAM_FREQUENCY_KHZ      (120000) // 120 MHz
+#define MICROPY_HW_SDRAM_REFRESH_CYCLES     8192
+
+#define MICROPY_HW_SDRAM_BURST_LENGTH       8
+#define MICROPY_HW_SDRAM_CAS_LATENCY        3
+#define MICROPY_HW_SDRAM_COLUMN_BITS_NUM    9
+#define MICROPY_HW_SDRAM_ROW_BITS_NUM       13
+#define MICROPY_HW_SDRAM_MEM_BUS_WIDTH      16
+#define MICROPY_HW_SDRAM_INTERN_BANKS_NUM   4
+#define MICROPY_HW_SDRAM_CLOCK_PERIOD       2
+#define MICROPY_HW_SDRAM_RPIPE_DELAY        1
+#define MICROPY_HW_SDRAM_RBURST             (1)
+#define MICROPY_HW_SDRAM_WRITE_PROTECTION   (0)
+#define MICROPY_HW_SDRAM_AUTOREFRESH_NUM    (4)
+
+#define MICROPY_HW_FMC_SDCKE0   (pin_H2)
+#define MICROPY_HW_FMC_SDNE0    (pin_H3)
+#define MICROPY_HW_FMC_SDCLK    (pin_G8)
+#define MICROPY_HW_FMC_SDNCAS   (pin_G15)
+#define MICROPY_HW_FMC_SDNRAS   (pin_F11)
+#define MICROPY_HW_FMC_SDNWE    (pin_C0)
+#define MICROPY_HW_FMC_BA0      (pin_G4)
+#define MICROPY_HW_FMC_BA1      (pin_G5)
+#define MICROPY_HW_FMC_NBL0     (pin_E0)
+#define MICROPY_HW_FMC_NBL1     (pin_E1)
+#define MICROPY_HW_FMC_A0       (pin_F0)
+#define MICROPY_HW_FMC_A1       (pin_F1)
+#define MICROPY_HW_FMC_A2       (pin_F2)
+#define MICROPY_HW_FMC_A3       (pin_F3)
+#define MICROPY_HW_FMC_A4       (pin_F4)
+#define MICROPY_HW_FMC_A5       (pin_F5)
+#define MICROPY_HW_FMC_A6       (pin_F12)
+#define MICROPY_HW_FMC_A7       (pin_F13)
+#define MICROPY_HW_FMC_A8       (pin_F14)
+#define MICROPY_HW_FMC_A9       (pin_F15)
+#define MICROPY_HW_FMC_A10      (pin_G0)
+#define MICROPY_HW_FMC_A11      (pin_G1)
+#define MICROPY_HW_FMC_A12      (pin_G2)
+#define MICROPY_HW_FMC_D0       (pin_D14)
+#define MICROPY_HW_FMC_D1       (pin_D15)
+#define MICROPY_HW_FMC_D2       (pin_D0)
+#define MICROPY_HW_FMC_D3       (pin_D1)
+#define MICROPY_HW_FMC_D4       (pin_E7)
+#define MICROPY_HW_FMC_D5       (pin_E8)
+#define MICROPY_HW_FMC_D6       (pin_E9)
+#define MICROPY_HW_FMC_D7       (pin_E10)
+#define MICROPY_HW_FMC_D8       (pin_E11)
+#define MICROPY_HW_FMC_D9       (pin_E12)
+#define MICROPY_HW_FMC_D10      (pin_E13)
+#define MICROPY_HW_FMC_D11      (pin_E14)
+#define MICROPY_HW_FMC_D12      (pin_E15)
+#define MICROPY_HW_FMC_D13      (pin_D8)
+#define MICROPY_HW_FMC_D14      (pin_D9)
+#define MICROPY_HW_FMC_D15      (pin_D10)
diff --git a/ports/stm32/boards/FK743M5-XIH6/mpconfigboard.mk b/ports/stm32/boards/FK743M5-XIH6/mpconfigboard.mk
new file mode 100644
index 0000000000000..cfccf8dab4816
--- /dev/null
+++ b/ports/stm32/boards/FK743M5-XIH6/mpconfigboard.mk
@@ -0,0 +1,39 @@
+
+# MCU settings
+MCU_SERIES = h7
+CMSIS_MCU = STM32H743xx
+MICROPY_FLOAT_IMPL = double
+AF_FILE = boards/stm32h743_af.csv
+TOP_DIR := $(abspath ../..)
+
+# Enable LVGL modules
+LV_CONF_PATH = ${TOP_DIR}/user_modules/lv_binding_micropython/driver/stm32/st_ltdc/lv_conf.h
+USER_C_MODULES = ${TOP_DIR}/user_modules/lv_binding_micropython/micropython.mk
+USER_C_MODULES += ${TOP_DIR}/user_modules/lv_binding_micropython/driver/stm32/st_ltdc
+
+ifeq ($(USE_MBOOT),1)
+# When using Mboot everything goes after the bootloader
+LD_FILES = boards/FK743M5-XIH6/stm32h743.ld
+TEXT0_ADDR = 0x08020000
+else
+# When not using Mboot everything goes at the start of flash
+LD_FILES = boards/FK743M5-XIH6/stm32h743.ld
+TEXT0_ADDR = 0x08000000
+endif
+
+# MicroPython settings
+MICROPY_PY_LWIP = 0
+MICROPY_PY_SSL = 0
+MICROPY_SSL_MBEDTLS = 0
+MICROPY_VFS_LFS2 = 1
+MICROPY_VFS_FAT = 1
+MICROPY_HW_ENABLE_ISR_UART_FLASH_FUNCS_IN_RAM = 1
+
+FROZEN_MANIFEST ?= $(BOARD_DIR)/manifest.py
+FROZEN_MANIFEST += ${TOP_DIR}/user_modules/lv_binding_micropython/driver/stm32/st_ltdc/manifest.py
+
+HAL_SRC_C += $(addprefix $(STM32LIB_HAL_BASE)/Src/stm32$(MCU_SERIES)xx_,\
+	hal_ltdc.c \
+	hal_ltdc_ex.c \
+	hal_dma2d.c \
+	)
diff --git a/ports/stm32/boards/FK743M5-XIH6/pins.csv b/ports/stm32/boards/FK743M5-XIH6/pins.csv
new file mode 100644
index 0000000000000..bbf8729bacee5
--- /dev/null
+++ b/ports/stm32/boards/FK743M5-XIH6/pins.csv
@@ -0,0 +1,141 @@
+A0,PA0
+A1,PA1
+A2,PA2
+A3,PA3
+A4,PA4
+A5,PA5
+A9,PA9
+A10,PA10
+A11,PA11
+A12,PA12
+A13,PA13
+A14,PA14
+A15,PA15
+B0,PB0
+B1,PB1
+B2,PB2
+B3,PB3
+B4,PB4
+B5,PB5
+B6,PB6
+B7,PB7
+B8,PB8
+B9,PB9
+B10,PB10
+B11,PB11
+B12,PB12
+B13,PB13
+B14,PB14
+B15,PB15
+C0,PC0
+C1,PC1
+C2,PC2
+C3,PC3
+C4,PC4
+C5,PC5
+C6,PC6
+C7,PC7
+C8,PC8
+C9,PC9
+C10,PC10
+C11,PC11
+C12,PC12
+C13,PC13
+C14,PC14
+C15,PC15
+D0,PD0
+D1,PD1
+D2,PD2
+D3,PD3
+D4,PD4
+D5,PD5
+D6,PD6
+D7,PD7
+D8,PD8
+D9,PD9
+D10,PD10
+D11,PD11
+D12,PD12
+D13,PD13
+D14,PD14
+D15,PD15
+E0,PE0
+E1,PE1
+E2,PE2
+E3,PE3
+E4,PE4
+E5,PE5
+E6,PE6
+E7,PE7
+E8,PE8
+E9,PE9
+E10,PE10
+E11,PE11
+E12,PE12
+E13,PE13
+E14,PE14
+E15,PE15
+F0,PF0
+F1,PF1
+F2,PF2
+F3,PF3
+F4,PF4
+F5,PF5
+F6,PF6
+F7,PF7
+F8,PF8
+F9,PF9
+F10,PF10
+F11,PF11
+F12,PF12
+F13,PF13
+F14,PF14
+F15,PF15
+G0,PG0
+G1,PG1
+G2,PG2
+G3,PG3
+G4,PG4
+G5,PG5
+G6,PG6
+G7,PG7
+G8,PG8
+G9,PG9
+G10,PG10
+G11,PG11
+G12,PG12
+G13,PG13
+G14,PG14
+G15,PG15
+H0,PH0
+H1,PH1
+H2,PH2
+H3,PH3
+H4,PH4
+H5,PH5
+H6,PH6
+H7,PH7
+H8,PH8
+H9,PH9
+H10,PH10
+H11,PH11
+H12,PH12
+H13,PH13
+H14,PH14
+H15,PH15
+I0,PI0
+I1,PI1
+I2,PI2
+I3,PI3
+I4,PI4
+I5,PI5
+I6,PI6
+I7,PI7
+I8,PI8
+I9,PI9
+I10,PI10
+I11,PI11
+I12,PI12
+I13,PI13
+I14,PI14
+I15,PI15
diff --git a/ports/stm32/boards/FK743M5-XIH6/stm32h743.ld b/ports/stm32/boards/FK743M5-XIH6/stm32h743.ld
new file mode 100644
index 0000000000000..4be8e549ed2ab
--- /dev/null
+++ b/ports/stm32/boards/FK743M5-XIH6/stm32h743.ld
@@ -0,0 +1,53 @@
+/*
+    GNU linker script for STM32H743
+*/
+
+/* Specify the memory areas */
+MEMORY
+{
+    FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 2M      /* sectors (0-15)  */
+    FLASH_APP  (rx) : ORIGIN = 0x08020000, LENGTH = 1920K   /* sectors (1-15)  */
+    DTCM (xrw)      : ORIGIN = 0x20000000, LENGTH = 128K    /* Used for storage cache */
+    RAM (xrw)       : ORIGIN = 0x24000000, LENGTH = 512K    /* AXI SRAM */
+    RAM_D2 (xrw)    : ORIGIN = 0x30000000, LENGTH = 288K
+    SDRAM (xrw)     : ORIGIN = 0xC0000000, LENGTH = 32M     /* external SDRAM */
+}
+
+/* produce a link error if there is not this amount of RAM for these sections */
+_minimum_stack_size = 2K;
+_minimum_heap_size = 16K;
+
+/* Define the stack.  The stack is full descending so begins just above last byte
+   of RAM.  Note that EABI requires the stack to be 8-byte aligned for a call. */
+_estack = ORIGIN(RAM) + LENGTH(RAM) - _estack_reserve;
+_sstack = _estack - 16K; /* tunable */
+
+/* RAM extents for the garbage collector */
+_ram_start = ORIGIN(RAM);
+_ram_end = ORIGIN(RAM) + LENGTH(RAM);
+_heap_start = _ebss; /* heap starts just after statically allocated memory */
+_heap_end = _sstack;
+
+/* Location of filesystem RAM cache */
+_micropy_hw_internal_flash_storage_ram_cache_start = ORIGIN(DTCM);
+_micropy_hw_internal_flash_storage_ram_cache_end = ORIGIN(DTCM) + LENGTH(DTCM);
+
+/* Define output sections */
+SECTIONS
+{
+    .sdram_pool (NOLOAD) :
+    {
+       . = ALIGN(32);
+       _sdram_pool_start = .;
+    } > SDRAM
+
+    /* Define the end of the SDRAM pool to prevent overflow */
+    _sdram_pool_end = ORIGIN(SDRAM) + LENGTH(SDRAM);
+
+    .eth_buffers (NOLOAD) : {
+        . = ABSOLUTE(0x30040000);
+        *eth.o*(.bss.eth_dma)
+    } >RAM_D2
+}
+
+INCLUDE common_basic.ld
diff --git a/ports/stm32/boards/FK743M5-XIH6/stm32h7xx_hal_conf.h b/ports/stm32/boards/FK743M5-XIH6/stm32h7xx_hal_conf.h
new file mode 100644
index 0000000000000..cdf8b3b0c54fa
--- /dev/null
+++ b/ports/stm32/boards/FK743M5-XIH6/stm32h7xx_hal_conf.h
@@ -0,0 +1,101 @@
+/* This file is part of the MicroPython project, http://micropython.org/
+ * The MIT License (MIT)
+ * Copyright (c) 2019 Damien P. George
+ */
+#ifndef MICROPY_INCLUDED_STM32H7XX_HAL_CONF_H
+#define MICROPY_INCLUDED_STM32H7XX_HAL_CONF_H
+
+// Oscillator values in Hz
+#define HSE_VALUE (25000000)
+#define LSE_VALUE (32768)
+#define EXTERNAL_CLOCK_VALUE (12288000)
+
+// Oscillator timeouts in ms
+#define HSE_STARTUP_TIMEOUT (5000)
+#define LSE_STARTUP_TIMEOUT (5000)
+
+// Enable various HAL modules
+#define HAL_ADC_MODULE_ENABLED
+#define HAL_DAC_MODULE_ENABLED
+#define HAL_LTDC_MODULE_ENABLED
+#define HAL_DMA2D_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_CRC_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_HASH_MODULE_ENABLED
+#define HAL_I2C_MODULE_ENABLED
+#define HAL_I2S_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_RTC_MODULE_ENABLED
+#define HAL_SD_MODULE_ENABLED
+#define HAL_SDRAM_MODULE_ENABLED
+#define HAL_SPI_MODULE_ENABLED
+#define HAL_TIM_MODULE_ENABLED
+#define HAL_UART_MODULE_ENABLED
+#define HAL_USART_MODULE_ENABLED
+#define HAL_PCD_MODULE_ENABLED
+
+// Oscillator values in Hz
+#define CSI_VALUE (4000000)
+#define HSI_VALUE (64000000)
+
+// SysTick has the highest priority
+#define TICK_INT_PRIORITY (0x00)
+
+// Miscellaneous HAL settings
+#define USE_RTOS            0
+#define USE_SD_TRANSCEIVER  0
+#define USE_SPI_CRC         1
+
+// Include various HAL modules for convenience
+#include "stm32h7xx_hal_dma.h"
+#include "stm32h7xx_hal_mdma.h"
+#include "stm32h7xx_hal_adc.h"
+#include "stm32h7xx_hal_cortex.h"
+#include "stm32h7xx_hal_crc.h"
+#include "stm32h7xx_hal_dac.h"
+#include "stm32h7xx_hal_dcmi.h"
+#include "stm32h7xx_hal_fdcan.h"
+#include "stm32h7xx_hal_flash.h"
+#include "stm32h7xx_hal_gpio.h"
+#include "stm32h7xx_hal_hash.h"
+#include "stm32h7xx_hal_hcd.h"
+#include "stm32h7xx_hal_i2c.h"
+#include "stm32h7xx_hal_i2c_ex.h"
+#include "stm32h7xx_hal_i2s.h"
+#include "stm32h7xx_hal_iwdg.h"
+#include "stm32h7xx_hal_pcd.h"
+#include "stm32h7xx_hal_pwr.h"
+#include "stm32h7xx_hal_rcc.h"
+#include "stm32h7xx_hal_rtc.h"
+#include "stm32h7xx_hal_sd.h"
+#include "stm32h7xx_hal_sdram.h"
+#include "stm32h7xx_hal_spi.h"
+#include "stm32h7xx_hal_tim.h"
+#include "stm32h7xx_hal_uart.h"
+#include "stm32h7xx_hal_usart.h"
+#include "stm32h7xx_hal_wwdg.h"
+#include "stm32h7xx_hal_ltdc.h"
+#include "stm32h7xx_hal_dma2d.h"
+#include "stm32h7xx_ll_adc.h"
+#include "stm32h7xx_ll_lpuart.h"
+#include "stm32h7xx_ll_pwr.h"
+#include "stm32h7xx_ll_rcc.h"
+#include "stm32h7xx_ll_rtc.h"
+#include "stm32h7xx_ll_usart.h"
+
+// HAL parameter assertions are disabled
+#define assert_param(expr) ((void)0)
+
+// The STM32H7xx HAL defines LPUART1 AF macros without numbers.
+#ifndef GPIO_AF3_LPUART1
+#define GPIO_AF3_LPUART1 GPIO_AF3_LPUART
+#define GPIO_AF8_LPUART1 GPIO_AF8_LPUART
+#endif
+
+extern LTDC_HandleTypeDef hltdc;
+
+#endif // MICROPY_INCLUDED_STM32H7XX_HAL_CONF_H
diff --git a/ports/stm32/boards/STM32H7_CORE/bdev.c b/ports/stm32/boards/STM32H7_CORE/bdev.c
new file mode 100644
index 0000000000000..9305fb3551cc5
--- /dev/null
+++ b/ports/stm32/boards/STM32H7_CORE/bdev.c
@@ -0,0 +1,46 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2018-2019 Damien P. George
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "storage.h"
+#include "qspi.h"
+
+#if MICROPY_HW_SPIFLASH_ENABLE_CACHE
+// Shared cache for first and second SPI block devices
+static mp_spiflash_cache_t spi_bdev_cache;
+#endif
+
+// First external SPI flash uses hardware QSPI interface
+
+const mp_spiflash_config_t spiflash_config = {
+    .bus_kind = MP_SPIFLASH_BUS_QSPI,
+    .bus.u_qspi.data = NULL,
+    .bus.u_qspi.proto = &qspi_proto,
+    #if MICROPY_HW_SPIFLASH_ENABLE_CACHE
+    .cache = &spi_bdev_cache,
+    #endif
+};
+
+spi_bdev_t spi_bdev;
diff --git a/ports/stm32/boards/STM32H7_CORE/board.json b/ports/stm32/boards/STM32H7_CORE/board.json
new file mode 100644
index 0000000000000..54fbcd231d239
--- /dev/null
+++ b/ports/stm32/boards/STM32H7_CORE/board.json
@@ -0,0 +1,22 @@
+{
+    "deploy": [
+        "../deploy.md"
+    ],
+    "docs": "",
+    "features": [],
+    "images": [
+        "STM32H743_CORE_V10.jpg",
+        "STM32H743_CORE_V10_B.jpg",
+        "STM32H743_CORE_V13.jpg",
+        "STM32H743_CORE_V13_B.jpg"
+    ],
+    "mcu": "stm32h7",
+    "product": "STM32H743 CORE",
+    "thumbnail": "",
+    "url": "",
+    "variants": {
+        "V10": "CORE BOARD V1.0",
+        "V13": "CORE BOARD V1.3"
+    },
+    "vendor": "Aliexpress"
+}
diff --git a/ports/stm32/boards/STM32H7_CORE/manifest.py b/ports/stm32/boards/STM32H7_CORE/manifest.py
new file mode 100644
index 0000000000000..832942f052606
--- /dev/null
+++ b/ports/stm32/boards/STM32H7_CORE/manifest.py
@@ -0,0 +1 @@
+include("$(PORT_DIR)/boards/manifest.py")
diff --git a/ports/stm32/boards/STM32H7_CORE/mpconfigboard.h b/ports/stm32/boards/STM32H7_CORE/mpconfigboard.h
new file mode 100644
index 0000000000000..430fc4bc63285
--- /dev/null
+++ b/ports/stm32/boards/STM32H7_CORE/mpconfigboard.h
@@ -0,0 +1,220 @@
+#define MICROPY_HW_BOARD_NAME       "STM32H7_CORE"
+#define MICROPY_HW_MCU_NAME         "STM32H743"
+
+#define MICROPY_HW_ENABLE_RTC       (1)
+#define MICROPY_HW_ENABLE_SERVO     (1)
+#define MICROPY_HW_ENABLE_RNG       (1)
+#define MICROPY_HW_ENABLE_HW_I2C    (1)
+#define MICROPY_HW_ENABLE_ADC       (1)
+#define MICROPY_HW_ENABLE_DAC       (1)
+#define MICROPY_HW_ENABLE_USB       (1)
+#define MICROPY_HW_USB_HID          (1)
+#define MICROPY_HW_ENABLE_SDCARD    (1)
+#define MICROPY_HW_HAS_FLASH        (1)
+#define MICROPY_HW_ENABLE_STORAGE   (1)
+
+#define MODULE_ST_LTDC_ENABLED      (1)
+#define MODULE_TOUCH_I2C_ENABLED    (1)
+
+// CAUTION: Do not enable! A bug here creates incorrect Option Bytes,
+// potentially bricking the device.
+#define MICROPY_HW_ENABLE_INTERNAL_FLASH_STORAGE (0)
+
+#define MICROPY_HW_ENTER_BOOTLOADER_VIA_RESET   (0)
+#define MICROPY_HW_SDCARD_MOUNT_AT_BOOT         (1)
+
+#if defined(MODULE_ST_LTDC_ENABLED) && MODULE_ST_LTDC_ENABLED
+extern void lv_deinit(void);
+#define MICROPY_BOARD_START_SOFT_RESET(state) do { boardctrl_start_soft_reset(state); lv_deinit(); } while(0)
+#endif
+
+// The board has a 25MHz HSE, the following gives 480MHz CPU speed
+#define MICROPY_HW_CLK_PLLM         (5)
+#define MICROPY_HW_CLK_PLLN         (192)
+#define MICROPY_HW_CLK_PLLP         (2)
+#define MICROPY_HW_CLK_PLLQ         (2)
+#define MICROPY_HW_CLK_PLLR         (2)
+#define MICROPY_HW_CLK_PLLVCI       (RCC_PLL1VCIRANGE_2)
+#define MICROPY_HW_CLK_PLLVCO       (RCC_PLL1VCOWIDE)
+#define MICROPY_HW_CLK_PLLFRAC      (0)
+
+// Bus clock divider values
+#define MICROPY_HW_CLK_AHB_DIV      (RCC_HCLK_DIV2)
+#define MICROPY_HW_CLK_APB1_DIV     (RCC_APB1_DIV2)
+#define MICROPY_HW_CLK_APB2_DIV     (RCC_APB2_DIV2)
+#define MICROPY_HW_CLK_APB3_DIV     (RCC_APB3_DIV2)
+#define MICROPY_HW_CLK_APB4_DIV     (RCC_APB4_DIV2)
+
+// 4 wait states
+#define MICROPY_HW_FLASH_LATENCY    FLASH_LATENCY_4
+
+#if !defined(BOARD_V10) && !defined(BOARD_V13)
+#error "Unsupported STM32H7_CORE Board!"
+#endif
+
+#if defined(BOARD_V10)
+// GPIO SDCARD (SDMMC2)
+#define MICROPY_HW_SDCARD_SDMMC (2)
+#define MICROPY_HW_SDCARD_D0    (pin_B14)
+#define MICROPY_HW_SDCARD_D1    (pin_B15)
+#define MICROPY_HW_SDCARD_D2    (pin_B3)
+#define MICROPY_HW_SDCARD_D3    (pin_B4)
+#define MICROPY_HW_SDCARD_CK    (pin_D6)
+#define MICROPY_HW_SDCARD_CMD   (pin_D7)
+#elif defined(BOARD_V13)
+// GPIO SDCARD
+#define MICROPY_HW_SDCARD_D0    (pin_C8)
+#define MICROPY_HW_SDCARD_D1    (pin_C9)
+#define MICROPY_HW_SDCARD_D2    (pin_C10)
+#define MICROPY_HW_SDCARD_D3    (pin_C11)
+#define MICROPY_HW_SDCARD_CK    (pin_C12)
+#define MICROPY_HW_SDCARD_CMD   (pin_D2)
+#endif
+
+// Be careful, if you connect the serial the BOOT
+// will be held high by the DTR
+// UART config
+#define MICROPY_HW_UART1_TX         (pin_A9)
+#define MICROPY_HW_UART1_RX         (pin_A10)
+
+#define MICROPY_HW_UART_REPL        PYB_UART_1
+#define MICROPY_HW_UART_REPL_BAUD   115200
+
+// FLASH QSPI config - W25Q128 16MB
+#define MICROPY_HW_QSPIFLASH_SIZE_BITS_LOG2 (27) // W25Q128 128Mbit = 16MB
+#define MICROPY_HW_QSPIFLASH_CS     (pin_B6)
+#define MICROPY_HW_QSPIFLASH_SCK    (pin_B2)
+#define MICROPY_HW_QSPIFLASH_IO0    (pin_F8)
+#define MICROPY_HW_QSPIFLASH_IO1    (pin_F9)
+#define MICROPY_HW_QSPIFLASH_IO2    (pin_F7)
+#define MICROPY_HW_QSPIFLASH_IO3    (pin_F6)
+
+// Block device config for SPI flash
+extern const struct _mp_spiflash_config_t spiflash_config;
+extern struct _spi_bdev_t spi_bdev;
+#define MICROPY_HW_SPIFLASH_ENABLE_CACHE    (1)
+#define MICROPY_HW_BDEV_SPIFLASH            (&spi_bdev)
+#define MICROPY_HW_BDEV_SPIFLASH_CONFIG     (&spiflash_config)
+#define MICROPY_HW_SPIFLASH_SIZE_BITS       (128 * 1024 * 1024)
+#define MICROPY_HW_BDEV_SPIFLASH_SIZE_BYTES (MICROPY_HW_SPIFLASH_SIZE_BITS / 8)
+#define MICROPY_HW_QSPI_PRESCALER           (2)
+#define MICROPY_HW_BDEV_SPIFLASH_EXTENDED   (&spi_bdev)
+
+// USB config
+// Enable the HSI48 oscillator and route it to USB
+#define MICROPY_HW_RCC_HSI48_STATE      (RCC_HSI48_ON)
+#define MICROPY_HW_RCC_USB_CLKSOURCE    (RCC_USBCLKSOURCE_HSI48)
+
+#define MICROPY_HW_USB_FS           (1)
+#define MICROPY_HW_USB_HS           (0)
+#define MICROPY_HW_USB_HS_IN_FS     (0)
+#define MICROPY_HW_USB_MAIN_DEV     (USB_PHY_FS_ID)
+#define MICROPY_HW_USB_CDC_NUM      (2)
+#define MICROPY_HW_USB_MSC          (1)
+
+#define MICROPY_HW_USB_PRODUCT_FS_STRING          "STM32H7 Virtual Comm Port in FS Mode"
+#define MICROPY_HW_USB_INTERFACE_FS_STRING        "STM32H7 Interface"
+#define MICROPY_HW_USB_MSC_INQUIRY_PRODUCT_STRING "STM32H7 Flash   "
+
+#if defined(BOARD_V10)
+#define MICROPY_HW_LED1             (pin_C13)
+#define MICROPY_HW_HAS_SWITCH       (0)
+#elif defined(BOARD_V13)
+#define MICROPY_HW_LED1             (pin_B0)    // red
+#define MICROPY_HW_LED2             (pin_B1)    // green
+#define MICROPY_HW_USRSW_PIN        (pin_A1)
+#define MICROPY_HW_HAS_SWITCH       (1)
+// USRSW is pulled low. Pressing the button makes the input go high.
+#define MICROPY_HW_USRSW_PULL       (GPIO_NOPULL)
+#define MICROPY_HW_USRSW_EXTI_MODE  (GPIO_MODE_IT_RISING)
+#define MICROPY_HW_USRSW_PRESSED    (1)
+#endif
+
+#define MICROPY_HW_LED_ON(pin)      (mp_hal_pin_low(pin))
+#define MICROPY_HW_LED_OFF(pin)     (mp_hal_pin_high(pin))
+
+// I2C buses
+#if defined(BOARD_V10)
+#define MICROPY_HW_I2C4_SCL         (pin_D12)
+#define MICROPY_HW_I2C4_SDA         (pin_D13)
+#elif defined(BOARD_V13)
+#define MICROPY_HW_I2C2_SCL         (pin_H4)
+#define MICROPY_HW_I2C2_SDA         (pin_H5)
+#endif
+
+// SDRAM
+#define MICROPY_HW_SDRAM_SIZE               (32 * 1024 * 1024)  // 32MB
+#define MICROPY_HW_SDRAM_STARTUP_TEST       (1)
+#define MICROPY_HW_SDRAM_TEST_FAIL_ON_ERROR (1)
+#define MICROPY_HEAP_START  ((sdram_valid) ? sdram_start() : &_heap_start)
+#define MICROPY_HEAP_END    ((sdram_valid) ? sdram_end() : &_heap_end)
+
+// Timing configuration for SDRAM @120Mhz
+#define MICROPY_HW_SDRAM_TIMING_TMRD        (2)
+#define MICROPY_HW_SDRAM_TIMING_TXSR        (9)
+#define MICROPY_HW_SDRAM_TIMING_TRAS        (5)
+#define MICROPY_HW_SDRAM_TIMING_TRC         (8)
+#define MICROPY_HW_SDRAM_TIMING_TWR         (2)
+#define MICROPY_HW_SDRAM_TIMING_TRP         (3)
+#define MICROPY_HW_SDRAM_TIMING_TRCD        (3)
+#define MICROPY_HW_SDRAM_REFRESH_RATE       (64)
+// Required by upstream micropython SDRAM driver;
+// harmless on lv_micropython until sync.
+#define MICROPY_HW_SDRAM_FREQUENCY_KHZ      (120000) // 120 MHz
+#define MICROPY_HW_SDRAM_REFRESH_CYCLES     8192
+
+#define MICROPY_HW_SDRAM_BURST_LENGTH       8
+#define MICROPY_HW_SDRAM_CAS_LATENCY        3
+#define MICROPY_HW_SDRAM_COLUMN_BITS_NUM    9
+#define MICROPY_HW_SDRAM_ROW_BITS_NUM       13
+#define MICROPY_HW_SDRAM_MEM_BUS_WIDTH      16
+#define MICROPY_HW_SDRAM_INTERN_BANKS_NUM   4
+#define MICROPY_HW_SDRAM_CLOCK_PERIOD       2
+#define MICROPY_HW_SDRAM_RPIPE_DELAY        1
+#define MICROPY_HW_SDRAM_RBURST             (1)
+#define MICROPY_HW_SDRAM_WRITE_PROTECTION   (0)
+#define MICROPY_HW_SDRAM_AUTOREFRESH_NUM    (4)
+
+#define MICROPY_HW_FMC_SDCKE0   (pin_H2)
+#define MICROPY_HW_FMC_SDNE0    (pin_H3)
+#define MICROPY_HW_FMC_SDCLK    (pin_G8)
+#define MICROPY_HW_FMC_SDNCAS   (pin_G15)
+#define MICROPY_HW_FMC_SDNRAS   (pin_F11)
+#if defined(BOARD_V10)
+#define MICROPY_HW_FMC_SDNWE    (pin_H5)
+#elif defined(BOARD_V13)
+#define MICROPY_HW_FMC_SDNWE    (pin_C0)
+#endif
+#define MICROPY_HW_FMC_BA0      (pin_G4)
+#define MICROPY_HW_FMC_BA1      (pin_G5)
+#define MICROPY_HW_FMC_NBL0     (pin_E0)
+#define MICROPY_HW_FMC_NBL1     (pin_E1)
+#define MICROPY_HW_FMC_A0       (pin_F0)
+#define MICROPY_HW_FMC_A1       (pin_F1)
+#define MICROPY_HW_FMC_A2       (pin_F2)
+#define MICROPY_HW_FMC_A3       (pin_F3)
+#define MICROPY_HW_FMC_A4       (pin_F4)
+#define MICROPY_HW_FMC_A5       (pin_F5)
+#define MICROPY_HW_FMC_A6       (pin_F12)
+#define MICROPY_HW_FMC_A7       (pin_F13)
+#define MICROPY_HW_FMC_A8       (pin_F14)
+#define MICROPY_HW_FMC_A9       (pin_F15)
+#define MICROPY_HW_FMC_A10      (pin_G0)
+#define MICROPY_HW_FMC_A11      (pin_G1)
+#define MICROPY_HW_FMC_A12      (pin_G2)
+#define MICROPY_HW_FMC_D0       (pin_D14)
+#define MICROPY_HW_FMC_D1       (pin_D15)
+#define MICROPY_HW_FMC_D2       (pin_D0)
+#define MICROPY_HW_FMC_D3       (pin_D1)
+#define MICROPY_HW_FMC_D4       (pin_E7)
+#define MICROPY_HW_FMC_D5       (pin_E8)
+#define MICROPY_HW_FMC_D6       (pin_E9)
+#define MICROPY_HW_FMC_D7       (pin_E10)
+#define MICROPY_HW_FMC_D8       (pin_E11)
+#define MICROPY_HW_FMC_D9       (pin_E12)
+#define MICROPY_HW_FMC_D10      (pin_E13)
+#define MICROPY_HW_FMC_D11      (pin_E14)
+#define MICROPY_HW_FMC_D12      (pin_E15)
+#define MICROPY_HW_FMC_D13      (pin_D8)
+#define MICROPY_HW_FMC_D14      (pin_D9)
+#define MICROPY_HW_FMC_D15      (pin_D10)
diff --git a/ports/stm32/boards/STM32H7_CORE/mpconfigboard.mk b/ports/stm32/boards/STM32H7_CORE/mpconfigboard.mk
new file mode 100644
index 0000000000000..11fd94c4c4d0c
--- /dev/null
+++ b/ports/stm32/boards/STM32H7_CORE/mpconfigboard.mk
@@ -0,0 +1,38 @@
+# MCU settings
+MCU_SERIES = h7
+CMSIS_MCU = STM32H743xx
+MICROPY_FLOAT_IMPL = double
+AF_FILE = boards/stm32h743_af.csv
+TOP_DIR := $(abspath ../..)
+
+# Enable LVGL modules
+LV_CONF_PATH = ${TOP_DIR}/user_modules/lv_binding_micropython/driver/stm32/st_ltdc/lv_conf.h
+USER_C_MODULES = ${TOP_DIR}/user_modules/lv_binding_micropython/micropython.mk
+USER_C_MODULES += ${TOP_DIR}/user_modules/lv_binding_micropython/driver/stm32/st_ltdc
+
+ifeq ($(USE_MBOOT),1)
+# When using Mboot everything goes after the bootloader
+LD_FILES = boards/STM32H7_CORE/stm32h743.ld
+TEXT0_ADDR = 0x08020000
+else
+# When not using Mboot everything goes at the start of flash
+LD_FILES = boards/STM32H7_CORE/stm32h743.ld
+TEXT0_ADDR = 0x08000000
+endif
+
+# MicroPython settings
+MICROPY_PY_LWIP = 0
+MICROPY_PY_SSL = 0
+MICROPY_SSL_MBEDTLS = 0
+MICROPY_VFS_LFS2 = 1
+MICROPY_VFS_FAT = 1
+MICROPY_HW_ENABLE_ISR_UART_FLASH_FUNCS_IN_RAM = 1
+
+FROZEN_MANIFEST ?= $(BOARD_DIR)/manifest.py
+FROZEN_MANIFEST += ${TOP_DIR}/user_modules/lv_binding_micropython/driver/stm32/st_ltdc/manifest.py
+
+HAL_SRC_C += $(addprefix $(STM32LIB_HAL_BASE)/Src/stm32$(MCU_SERIES)xx_,\
+	hal_ltdc.c \
+	hal_ltdc_ex.c \
+	hal_dma2d.c \
+	)
diff --git a/ports/stm32/boards/STM32H7_CORE/mpconfigvariant_V10.mk b/ports/stm32/boards/STM32H7_CORE/mpconfigvariant_V10.mk
new file mode 100644
index 0000000000000..53ad015ad2ff7
--- /dev/null
+++ b/ports/stm32/boards/STM32H7_CORE/mpconfigvariant_V10.mk
@@ -0,0 +1 @@
+CFLAGS += -DBOARD_V10
diff --git a/ports/stm32/boards/STM32H7_CORE/mpconfigvariant_V13.mk b/ports/stm32/boards/STM32H7_CORE/mpconfigvariant_V13.mk
new file mode 100644
index 0000000000000..ff38f51ff07d3
--- /dev/null
+++ b/ports/stm32/boards/STM32H7_CORE/mpconfigvariant_V13.mk
@@ -0,0 +1 @@
+CFLAGS += -DBOARD_V13
diff --git a/ports/stm32/boards/STM32H7_CORE/pins.csv b/ports/stm32/boards/STM32H7_CORE/pins.csv
new file mode 100644
index 0000000000000..bbf8729bacee5
--- /dev/null
+++ b/ports/stm32/boards/STM32H7_CORE/pins.csv
@@ -0,0 +1,141 @@
+A0,PA0
+A1,PA1
+A2,PA2
+A3,PA3
+A4,PA4
+A5,PA5
+A9,PA9
+A10,PA10
+A11,PA11
+A12,PA12
+A13,PA13
+A14,PA14
+A15,PA15
+B0,PB0
+B1,PB1
+B2,PB2
+B3,PB3
+B4,PB4
+B5,PB5
+B6,PB6
+B7,PB7
+B8,PB8
+B9,PB9
+B10,PB10
+B11,PB11
+B12,PB12
+B13,PB13
+B14,PB14
+B15,PB15
+C0,PC0
+C1,PC1
+C2,PC2
+C3,PC3
+C4,PC4
+C5,PC5
+C6,PC6
+C7,PC7
+C8,PC8
+C9,PC9
+C10,PC10
+C11,PC11
+C12,PC12
+C13,PC13
+C14,PC14
+C15,PC15
+D0,PD0
+D1,PD1
+D2,PD2
+D3,PD3
+D4,PD4
+D5,PD5
+D6,PD6
+D7,PD7
+D8,PD8
+D9,PD9
+D10,PD10
+D11,PD11
+D12,PD12
+D13,PD13
+D14,PD14
+D15,PD15
+E0,PE0
+E1,PE1
+E2,PE2
+E3,PE3
+E4,PE4
+E5,PE5
+E6,PE6
+E7,PE7
+E8,PE8
+E9,PE9
+E10,PE10
+E11,PE11
+E12,PE12
+E13,PE13
+E14,PE14
+E15,PE15
+F0,PF0
+F1,PF1
+F2,PF2
+F3,PF3
+F4,PF4
+F5,PF5
+F6,PF6
+F7,PF7
+F8,PF8
+F9,PF9
+F10,PF10
+F11,PF11
+F12,PF12
+F13,PF13
+F14,PF14
+F15,PF15
+G0,PG0
+G1,PG1
+G2,PG2
+G3,PG3
+G4,PG4
+G5,PG5
+G6,PG6
+G7,PG7
+G8,PG8
+G9,PG9
+G10,PG10
+G11,PG11
+G12,PG12
+G13,PG13
+G14,PG14
+G15,PG15
+H0,PH0
+H1,PH1
+H2,PH2
+H3,PH3
+H4,PH4
+H5,PH5
+H6,PH6
+H7,PH7
+H8,PH8
+H9,PH9
+H10,PH10
+H11,PH11
+H12,PH12
+H13,PH13
+H14,PH14
+H15,PH15
+I0,PI0
+I1,PI1
+I2,PI2
+I3,PI3
+I4,PI4
+I5,PI5
+I6,PI6
+I7,PI7
+I8,PI8
+I9,PI9
+I10,PI10
+I11,PI11
+I12,PI12
+I13,PI13
+I14,PI14
+I15,PI15
diff --git a/ports/stm32/boards/STM32H7_CORE/stm32h743.ld b/ports/stm32/boards/STM32H7_CORE/stm32h743.ld
new file mode 100644
index 0000000000000..4be8e549ed2ab
--- /dev/null
+++ b/ports/stm32/boards/STM32H7_CORE/stm32h743.ld
@@ -0,0 +1,53 @@
+/*
+    GNU linker script for STM32H743
+*/
+
+/* Specify the memory areas */
+MEMORY
+{
+    FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 2M      /* sectors (0-15)  */
+    FLASH_APP  (rx) : ORIGIN = 0x08020000, LENGTH = 1920K   /* sectors (1-15)  */
+    DTCM (xrw)      : ORIGIN = 0x20000000, LENGTH = 128K    /* Used for storage cache */
+    RAM (xrw)       : ORIGIN = 0x24000000, LENGTH = 512K    /* AXI SRAM */
+    RAM_D2 (xrw)    : ORIGIN = 0x30000000, LENGTH = 288K
+    SDRAM (xrw)     : ORIGIN = 0xC0000000, LENGTH = 32M     /* external SDRAM */
+}
+
+/* produce a link error if there is not this amount of RAM for these sections */
+_minimum_stack_size = 2K;
+_minimum_heap_size = 16K;
+
+/* Define the stack.  The stack is full descending so begins just above last byte
+   of RAM.  Note that EABI requires the stack to be 8-byte aligned for a call. */
+_estack = ORIGIN(RAM) + LENGTH(RAM) - _estack_reserve;
+_sstack = _estack - 16K; /* tunable */
+
+/* RAM extents for the garbage collector */
+_ram_start = ORIGIN(RAM);
+_ram_end = ORIGIN(RAM) + LENGTH(RAM);
+_heap_start = _ebss; /* heap starts just after statically allocated memory */
+_heap_end = _sstack;
+
+/* Location of filesystem RAM cache */
+_micropy_hw_internal_flash_storage_ram_cache_start = ORIGIN(DTCM);
+_micropy_hw_internal_flash_storage_ram_cache_end = ORIGIN(DTCM) + LENGTH(DTCM);
+
+/* Define output sections */
+SECTIONS
+{
+    .sdram_pool (NOLOAD) :
+    {
+       . = ALIGN(32);
+       _sdram_pool_start = .;
+    } > SDRAM
+
+    /* Define the end of the SDRAM pool to prevent overflow */
+    _sdram_pool_end = ORIGIN(SDRAM) + LENGTH(SDRAM);
+
+    .eth_buffers (NOLOAD) : {
+        . = ABSOLUTE(0x30040000);
+        *eth.o*(.bss.eth_dma)
+    } >RAM_D2
+}
+
+INCLUDE common_basic.ld
diff --git a/ports/stm32/boards/STM32H7_CORE/stm32h7xx_hal_conf.h b/ports/stm32/boards/STM32H7_CORE/stm32h7xx_hal_conf.h
new file mode 100644
index 0000000000000..cdf8b3b0c54fa
--- /dev/null
+++ b/ports/stm32/boards/STM32H7_CORE/stm32h7xx_hal_conf.h
@@ -0,0 +1,101 @@
+/* This file is part of the MicroPython project, http://micropython.org/
+ * The MIT License (MIT)
+ * Copyright (c) 2019 Damien P. George
+ */
+#ifndef MICROPY_INCLUDED_STM32H7XX_HAL_CONF_H
+#define MICROPY_INCLUDED_STM32H7XX_HAL_CONF_H
+
+// Oscillator values in Hz
+#define HSE_VALUE (25000000)
+#define LSE_VALUE (32768)
+#define EXTERNAL_CLOCK_VALUE (12288000)
+
+// Oscillator timeouts in ms
+#define HSE_STARTUP_TIMEOUT (5000)
+#define LSE_STARTUP_TIMEOUT (5000)
+
+// Enable various HAL modules
+#define HAL_ADC_MODULE_ENABLED
+#define HAL_DAC_MODULE_ENABLED
+#define HAL_LTDC_MODULE_ENABLED
+#define HAL_DMA2D_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_CRC_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_HASH_MODULE_ENABLED
+#define HAL_I2C_MODULE_ENABLED
+#define HAL_I2S_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_RTC_MODULE_ENABLED
+#define HAL_SD_MODULE_ENABLED
+#define HAL_SDRAM_MODULE_ENABLED
+#define HAL_SPI_MODULE_ENABLED
+#define HAL_TIM_MODULE_ENABLED
+#define HAL_UART_MODULE_ENABLED
+#define HAL_USART_MODULE_ENABLED
+#define HAL_PCD_MODULE_ENABLED
+
+// Oscillator values in Hz
+#define CSI_VALUE (4000000)
+#define HSI_VALUE (64000000)
+
+// SysTick has the highest priority
+#define TICK_INT_PRIORITY (0x00)
+
+// Miscellaneous HAL settings
+#define USE_RTOS            0
+#define USE_SD_TRANSCEIVER  0
+#define USE_SPI_CRC         1
+
+// Include various HAL modules for convenience
+#include "stm32h7xx_hal_dma.h"
+#include "stm32h7xx_hal_mdma.h"
+#include "stm32h7xx_hal_adc.h"
+#include "stm32h7xx_hal_cortex.h"
+#include "stm32h7xx_hal_crc.h"
+#include "stm32h7xx_hal_dac.h"
+#include "stm32h7xx_hal_dcmi.h"
+#include "stm32h7xx_hal_fdcan.h"
+#include "stm32h7xx_hal_flash.h"
+#include "stm32h7xx_hal_gpio.h"
+#include "stm32h7xx_hal_hash.h"
+#include "stm32h7xx_hal_hcd.h"
+#include "stm32h7xx_hal_i2c.h"
+#include "stm32h7xx_hal_i2c_ex.h"
+#include "stm32h7xx_hal_i2s.h"
+#include "stm32h7xx_hal_iwdg.h"
+#include "stm32h7xx_hal_pcd.h"
+#include "stm32h7xx_hal_pwr.h"
+#include "stm32h7xx_hal_rcc.h"
+#include "stm32h7xx_hal_rtc.h"
+#include "stm32h7xx_hal_sd.h"
+#include "stm32h7xx_hal_sdram.h"
+#include "stm32h7xx_hal_spi.h"
+#include "stm32h7xx_hal_tim.h"
+#include "stm32h7xx_hal_uart.h"
+#include "stm32h7xx_hal_usart.h"
+#include "stm32h7xx_hal_wwdg.h"
+#include "stm32h7xx_hal_ltdc.h"
+#include "stm32h7xx_hal_dma2d.h"
+#include "stm32h7xx_ll_adc.h"
+#include "stm32h7xx_ll_lpuart.h"
+#include "stm32h7xx_ll_pwr.h"
+#include "stm32h7xx_ll_rcc.h"
+#include "stm32h7xx_ll_rtc.h"
+#include "stm32h7xx_ll_usart.h"
+
+// HAL parameter assertions are disabled
+#define assert_param(expr) ((void)0)
+
+// The STM32H7xx HAL defines LPUART1 AF macros without numbers.
+#ifndef GPIO_AF3_LPUART1
+#define GPIO_AF3_LPUART1 GPIO_AF3_LPUART
+#define GPIO_AF8_LPUART1 GPIO_AF8_LPUART
+#endif
+
+extern LTDC_HandleTypeDef hltdc;
+
+#endif // MICROPY_INCLUDED_STM32H7XX_HAL_CONF_H