From dd644984c58da046ea17a8164ca5ae15350d32c9 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Tue, 30 Apr 2024 17:25:06 +0200 Subject: [PATCH] SystemZ: Use REG_SEQUENCE for PAIR128 PAIR128 should probably just be removed entirely --- .../Target/SystemZ/SystemZISelLowering.cpp | 20 ++++++------------- .../CodeGen/SystemZ/atomicrmw-ops-i128.ll | 14 ++++++------- 2 files changed, 13 insertions(+), 21 deletions(-) diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp index 2920c1f02a314..5cb67ebf4e4b4 100644 --- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp +++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp @@ -8868,23 +8868,15 @@ SystemZTargetLowering::emitAtomicCmpSwapW(MachineInstr &MI, MachineBasicBlock * SystemZTargetLowering::emitPair128(MachineInstr &MI, MachineBasicBlock *MBB) const { - MachineFunction &MF = *MBB->getParent(); const SystemZInstrInfo *TII = Subtarget.getInstrInfo(); - MachineRegisterInfo &MRI = MF.getRegInfo(); - DebugLoc DL = MI.getDebugLoc(); + const DebugLoc &DL = MI.getDebugLoc(); Register Dest = MI.getOperand(0).getReg(); - Register Hi = MI.getOperand(1).getReg(); - Register Lo = MI.getOperand(2).getReg(); - Register Tmp1 = MRI.createVirtualRegister(&SystemZ::GR128BitRegClass); - Register Tmp2 = MRI.createVirtualRegister(&SystemZ::GR128BitRegClass); - - BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::IMPLICIT_DEF), Tmp1); - BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::INSERT_SUBREG), Tmp2) - .addReg(Tmp1).addReg(Hi).addImm(SystemZ::subreg_h64); - BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::INSERT_SUBREG), Dest) - .addReg(Tmp2).addReg(Lo).addImm(SystemZ::subreg_l64); - + BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::REG_SEQUENCE), Dest) + .add(MI.getOperand(1)) + .addImm(SystemZ::subreg_h64) + .add(MI.getOperand(2)) + .addImm(SystemZ::subreg_l64); MI.eraseFromParent(); return MBB; } diff --git a/llvm/test/CodeGen/SystemZ/atomicrmw-ops-i128.ll b/llvm/test/CodeGen/SystemZ/atomicrmw-ops-i128.ll index 604fd50baadeb..c088f6d862e7c 100644 --- a/llvm/test/CodeGen/SystemZ/atomicrmw-ops-i128.ll +++ b/llvm/test/CodeGen/SystemZ/atomicrmw-ops-i128.ll @@ -372,8 +372,8 @@ define i128 @atomicrmw_udec_wrap(ptr %src, i128 %b) { ; CHECK-NEXT: # in Loop: Header=BB12_2 Depth=1 ; CHECK-NEXT: vlgvg %r1, %v3, 1 ; CHECK-NEXT: vlgvg %r0, %v3, 0 -; CHECK-NEXT: vlgvg %r5, %v4, 1 -; CHECK-NEXT: vlgvg %r4, %v4, 0 +; CHECK-NEXT: vlgvg %r5, %v5, 1 +; CHECK-NEXT: vlgvg %r4, %v5, 0 ; CHECK-NEXT: cdsg %r0, %r4, 0(%r3) ; CHECK-NEXT: vlvgp %v3, %r0, %r1 ; CHECK-NEXT: je .LBB12_8 @@ -386,19 +386,19 @@ define i128 @atomicrmw_udec_wrap(ptr %src, i128 %b) { ; CHECK-NEXT: vchlgs %v4, %v3, %v0 ; CHECK-NEXT: .LBB12_4: # %atomicrmw.start ; CHECK-NEXT: # in Loop: Header=BB12_2 Depth=1 -; CHECK-NEXT: vlr %v5, %v0 +; CHECK-NEXT: vlr %v4, %v0 ; CHECK-NEXT: jl .LBB12_6 ; CHECK-NEXT: # %bb.5: # %atomicrmw.start ; CHECK-NEXT: # in Loop: Header=BB12_2 Depth=1 -; CHECK-NEXT: vaq %v5, %v3, %v1 +; CHECK-NEXT: vaq %v4, %v3, %v1 ; CHECK-NEXT: .LBB12_6: # %atomicrmw.start ; CHECK-NEXT: # in Loop: Header=BB12_2 Depth=1 -; CHECK-NEXT: vceqgs %v4, %v3, %v2 -; CHECK-NEXT: vlr %v4, %v0 +; CHECK-NEXT: vceqgs %v5, %v3, %v2 +; CHECK-NEXT: vlr %v5, %v0 ; CHECK-NEXT: je .LBB12_1 ; CHECK-NEXT: # %bb.7: # %atomicrmw.start ; CHECK-NEXT: # in Loop: Header=BB12_2 Depth=1 -; CHECK-NEXT: vlr %v4, %v5 +; CHECK-NEXT: vlr %v5, %v4 ; CHECK-NEXT: j .LBB12_1 ; CHECK-NEXT: .LBB12_8: # %atomicrmw.end ; CHECK-NEXT: vst %v3, 0(%r2), 3