From f414207cec9703d14e3ff4cb46198db16fbc5001 Mon Sep 17 00:00:00 2001 From: Venkata Ramanaiah Nalamothu Date: Wed, 18 Dec 2024 17:30:49 +0530 Subject: [PATCH] [llvm] Pass MachineInstr flags to storeRegToStackSlot/loadRegFromStackSlot (NFC) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch is in preparation to enable setting the MachineInstr::MIFlag flags, i.e. FrameSetup/FrameDestroy, on callee saved register spill/reload instructions in prologue/epilogue. This eventually helps in setting the prologue_end and epilogue_begin markers more accurately. The DWARF Spec in "6.4 Call Frame Information" says: The code that allocates space on the call frame stack and performs the save operation is called the subroutine’s prologue, and the code that performs the restore operation and deallocates the frame is called its epilogue. which means the callee saved register spills and reloads are part of prologue (a.k.a frame setup) and epilogue (a.k.a frame destruction), respectively. And, IIUC, LLVM backend uses FrameSetup/FrameDestroy flags to identify instructions that are part of call frame setup and destruction. In the trunk, while most targets consistently set FrameSetup/FrameDestroy on save/restore call frame information (CFI) instructions of callee saved registers, they do not consistently set those flags on the actual callee saved register spill/reload instructions. I believe this patch provides a clean mechanism to set FrameSetup/FrameDestroy flags on the actual callee saved register spill/reload instructions as needed. And, by having default argument of MachineInstr::NoFlags for Flags, this patch is a NFC. With this patch, the targets have to just pass FrameSetup/FrameDestroy flag to the storeRegToStackSlot/loadRegFromStackSlot calls from the target derived spillCalleeSavedRegisters and restoreCalleeSavedRegisters to set those flags on callee saved register spill/reload instructions. Also, this patch makes it very easy to set the source line information on callee saved register spill/reload instructions which is needed by the DwarfDebug.cpp implementation to set prologue_end and epilogue_begin markers more accurately. As per DwarfDebug.cpp implementation: prologue_end is the first known non-DBG_VALUE and non-FrameSetup location that marks the beginning of the function body epilogue_begin is the first FrameDestroy location that has been seen in the epilogue basic block With this patch, the targets have to just do the following to set the source line information on callee saved register spill/reload instructions, without hampering the LLVM's efforts to avoid adding source line information on the artificial code generated by the compiler. InstrInfo::storeRegToStackSlot() { ... DebugLoc DL = Flags & MachineInstr::FrameSetup ? DebugLoc() : MBB.findDebugLoc(I); ... } InstrInfo::loadRegFromStackSlot() { ... DebugLoc DL = Flags & MachineInstr::FrameDestroy ? MBB.findDebugLoc(I) : DebugLoc(); ... } While I understand this patch would break out-of-tree backend builds, I think it is in the right direction. One immediate use case that can benefit from this patch is fixing #120553 becomes simpler. --- llvm/include/llvm/CodeGen/TargetInstrInfo.h | 30 +++++------ llvm/lib/Target/AArch64/AArch64InstrInfo.cpp | 13 +++-- llvm/lib/Target/AArch64/AArch64InstrInfo.h | 23 ++++----- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 6 ++- llvm/lib/Target/AMDGPU/SIInstrInfo.h | 23 ++++----- llvm/lib/Target/ARC/ARCInstrInfo.cpp | 6 ++- llvm/lib/Target/ARC/ARCInstrInfo.h | 23 ++++----- llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 13 +++-- llvm/lib/Target/ARM/ARMBaseInstrInfo.h | 23 ++++----- llvm/lib/Target/ARM/Thumb1InstrInfo.cpp | 13 +++-- llvm/lib/Target/ARM/Thumb1InstrInfo.h | 23 ++++----- llvm/lib/Target/ARM/Thumb2InstrInfo.cpp | 13 +++-- llvm/lib/Target/ARM/Thumb2InstrInfo.h | 23 ++++----- llvm/lib/Target/AVR/AVRInstrInfo.cpp | 6 ++- llvm/lib/Target/AVR/AVRInstrInfo.h | 21 ++++---- llvm/lib/Target/BPF/BPFInstrInfo.cpp | 13 +++-- llvm/lib/Target/BPF/BPFInstrInfo.h | 21 ++++---- llvm/lib/Target/CSKY/CSKYInstrInfo.cpp | 13 +++-- llvm/lib/Target/CSKY/CSKYInstrInfo.h | 23 ++++----- llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp | 13 +++-- llvm/lib/Target/Hexagon/HexagonInstrInfo.h | 21 ++++---- llvm/lib/Target/Lanai/LanaiInstrInfo.cpp | 6 ++- llvm/lib/Target/Lanai/LanaiInstrInfo.h | 26 +++++----- .../Target/LoongArch/LoongArchInstrInfo.cpp | 13 +++-- .../lib/Target/LoongArch/LoongArchInstrInfo.h | 21 ++++---- llvm/lib/Target/M68k/M68kInstrInfo.cpp | 6 ++- llvm/lib/Target/M68k/M68kInstrInfo.h | 23 ++++----- llvm/lib/Target/MSP430/MSP430InstrInfo.cpp | 13 +++-- llvm/lib/Target/MSP430/MSP430InstrInfo.h | 21 ++++---- llvm/lib/Target/Mips/Mips16InstrInfo.cpp | 13 +++-- llvm/lib/Target/Mips/Mips16InstrInfo.h | 24 ++++----- llvm/lib/Target/Mips/MipsInstrInfo.h | 50 +++++++++---------- llvm/lib/Target/Mips/MipsSEInstrInfo.cpp | 20 ++++---- llvm/lib/Target/Mips/MipsSEInstrInfo.h | 24 ++++----- llvm/lib/Target/NVPTX/NVPTXInstrInfo.h | 21 ++++---- llvm/lib/Target/PowerPC/PPCInstrInfo.cpp | 13 +++-- llvm/lib/Target/PowerPC/PPCInstrInfo.h | 21 ++++---- llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 13 +++-- llvm/lib/Target/RISCV/RISCVInstrInfo.h | 23 ++++----- llvm/lib/Target/Sparc/SparcInstrInfo.cpp | 13 +++-- llvm/lib/Target/Sparc/SparcInstrInfo.h | 23 ++++----- llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp | 13 +++-- llvm/lib/Target/SystemZ/SystemZInstrInfo.h | 21 ++++---- llvm/lib/Target/VE/VEInstrInfo.cpp | 13 +++-- llvm/lib/Target/VE/VEInstrInfo.h | 23 ++++----- llvm/lib/Target/X86/X86InstrInfo.cpp | 13 +++-- llvm/lib/Target/X86/X86InstrInfo.h | 23 ++++----- llvm/lib/Target/XCore/XCoreInstrInfo.cpp | 6 ++- llvm/lib/Target/XCore/XCoreInstrInfo.h | 23 ++++----- llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp | 13 +++-- llvm/lib/Target/Xtensa/XtensaInstrInfo.h | 23 ++++----- 51 files changed, 446 insertions(+), 475 deletions(-) diff --git a/llvm/include/llvm/CodeGen/TargetInstrInfo.h b/llvm/include/llvm/CodeGen/TargetInstrInfo.h index 165af902e42d0..bc90364875b68 100644 --- a/llvm/include/llvm/CodeGen/TargetInstrInfo.h +++ b/llvm/include/llvm/CodeGen/TargetInstrInfo.h @@ -1142,13 +1142,14 @@ class TargetInstrInfo : public MCInstrInfo { /// register, \p VReg is the register being assigned. This additional register /// argument is needed for certain targets when invoked from RegAllocFast to /// map the spilled physical register to its virtual register. A null register - /// can be passed elsewhere. - virtual void storeRegToStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - Register SrcReg, bool isKill, int FrameIndex, - const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, - Register VReg) const { + /// can be passed elsewhere. The \p Flags is used to set appropriate machine + /// flags on the spill instruction e.g. FrameSetup flag on a callee saved + /// register spill instruction, part of prologue, during the frame lowering. + virtual void storeRegToStackSlot( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, + bool isKill, int FrameIndex, const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI, Register VReg, + MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const { llvm_unreachable("Target didn't implement " "TargetInstrInfo::storeRegToStackSlot!"); } @@ -1160,13 +1161,14 @@ class TargetInstrInfo : public MCInstrInfo { /// register, \p VReg is the register being assigned. This additional register /// argument is needed for certain targets when invoked from RegAllocFast to /// map the loaded physical register to its virtual register. A null register - /// can be passed elsewhere. - virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - Register DestReg, int FrameIndex, - const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, - Register VReg) const { + /// can be passed elsewhere. The \p Flags is used to set appropriate machine + /// flags on the spill instruction e.g. FrameDestroy flag on a callee saved + /// register reload instruction, part of epilogue, during the frame lowering. + virtual void loadRegFromStackSlot( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, + int FrameIndex, const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI, Register VReg, + MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const { llvm_unreachable("Target didn't implement " "TargetInstrInfo::loadRegFromStackSlot!"); } diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp index 6b8a7e9559e00..7ccd65b105220 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp @@ -5278,7 +5278,8 @@ void AArch64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, Register SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, - Register VReg) const { + Register VReg, + MachineInstr::MIFlag Flags) const { MachineFunction &MF = *MBB.getParent(); MachineFrameInfo &MFI = MF.getFrameInfo(); @@ -5445,12 +5446,10 @@ static void loadRegPairFromStackSlot(const TargetRegisterInfo &TRI, .addMemOperand(MMO); } -void AArch64InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MBBI, - Register DestReg, int FI, - const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, - Register VReg) const { +void AArch64InstrInfo::loadRegFromStackSlot( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, + int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, + Register VReg, MachineInstr::MIFlag Flags) const { MachineFunction &MF = *MBB.getParent(); MachineFrameInfo &MFI = MF.getFrameInfo(); MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(MF, FI); diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.h b/llvm/lib/Target/AArch64/AArch64InstrInfo.h index e37f70f7d985d..9a0034223ab9b 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.h +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.h @@ -347,18 +347,17 @@ class AArch64InstrInfo final : public AArch64GenInstrInfo { bool KillSrc, bool RenamableDest = false, bool RenamableSrc = false) const override; - void storeRegToStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MBBI, Register SrcReg, - bool isKill, int FrameIndex, - const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, - Register VReg) const override; - - void loadRegFromStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MBBI, Register DestReg, - int FrameIndex, const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, - Register VReg) const override; + void storeRegToStackSlot( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, + bool isKill, int FrameIndex, const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI, Register VReg, + MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override; + + void loadRegFromStackSlot( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, + Register DestReg, int FrameIndex, const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI, Register VReg, + MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override; // This tells target independent code that it is okay to pass instructions // with subreg operands to foldMemoryOperandImpl. diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp index 8fc32d9e60bf2..2f7e06d424249 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -1724,7 +1724,8 @@ static unsigned getVectorRegSpillSaveOpcode(Register Reg, void SIInstrInfo::storeRegToStackSlot( MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, Register VReg) const { + const TargetRegisterInfo *TRI, Register VReg, + MachineInstr::MIFlag Flags) const { MachineFunction *MF = MBB.getParent(); SIMachineFunctionInfo *MFI = MF->getInfo(); MachineFrameInfo &FrameInfo = MF->getFrameInfo(); @@ -1951,7 +1952,8 @@ void SIInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, - Register VReg) const { + Register VReg, + MachineInstr::MIFlag Flags) const { MachineFunction *MF = MBB.getParent(); SIMachineFunctionInfo *MFI = MF->getInfo(); MachineFrameInfo &FrameInfo = MF->getFrameInfo(); diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h index d49939bf81b10..6390fbc489726 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h @@ -280,18 +280,17 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo { MachineBasicBlock::iterator I, const DebugLoc &DL, Register SrcReg, int Value) const; - void storeRegToStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, Register SrcReg, - bool isKill, int FrameIndex, - const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, - Register VReg) const override; - - void loadRegFromStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, Register DestReg, - int FrameIndex, const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, - Register VReg) const override; + void storeRegToStackSlot( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, + bool isKill, int FrameIndex, const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI, Register VReg, + MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override; + + void loadRegFromStackSlot( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, + int FrameIndex, const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI, Register VReg, + MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override; bool expandPostRAPseudo(MachineInstr &MI) const override; diff --git a/llvm/lib/Target/ARC/ARCInstrInfo.cpp b/llvm/lib/Target/ARC/ARCInstrInfo.cpp index 78db68fca3050..aa30c8a2a96da 100644 --- a/llvm/lib/Target/ARC/ARCInstrInfo.cpp +++ b/llvm/lib/Target/ARC/ARCInstrInfo.cpp @@ -294,7 +294,8 @@ void ARCInstrInfo::copyPhysReg(MachineBasicBlock &MBB, void ARCInstrInfo::storeRegToStackSlot( MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register SrcReg, bool IsKill, int FrameIndex, const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, Register VReg) const { + const TargetRegisterInfo *TRI, Register VReg, + MachineInstr::MIFlag Flags) const { DebugLoc DL = MBB.findDebugLoc(I); MachineFunction &MF = *MBB.getParent(); MachineFrameInfo &MFI = MF.getFrameInfo(); @@ -323,7 +324,8 @@ void ARCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, - Register VReg) const { + Register VReg, + MachineInstr::MIFlag Flags) const { DebugLoc DL = MBB.findDebugLoc(I); MachineFunction &MF = *MBB.getParent(); MachineFrameInfo &MFI = MF.getFrameInfo(); diff --git a/llvm/lib/Target/ARC/ARCInstrInfo.h b/llvm/lib/Target/ARC/ARCInstrInfo.h index e25f990252260..8861b4689925f 100644 --- a/llvm/lib/Target/ARC/ARCInstrInfo.h +++ b/llvm/lib/Target/ARC/ARCInstrInfo.h @@ -68,18 +68,17 @@ class ARCInstrInfo : public ARCGenInstrInfo { bool KillSrc, bool RenamableDest = false, bool RenamableSrc = false) const override; - void storeRegToStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, Register SrcReg, - bool IsKill, int FrameIndex, - const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, - Register VReg) const override; - - void loadRegFromStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, Register DestReg, - int FrameIndex, const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, - Register VReg) const override; + void storeRegToStackSlot( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, + bool IsKill, int FrameIndex, const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI, Register VReg, + MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override; + + void loadRegFromStackSlot( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, + int FrameIndex, const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI, Register VReg, + MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override; bool reverseBranchCondition(SmallVectorImpl &Cond) const override; diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp index 2bca2c08c3454..c167c1897bc91 100644 --- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -1118,7 +1118,8 @@ void ARMBaseInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, Register SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, - Register VReg) const { + Register VReg, + MachineInstr::MIFlag Flags) const { MachineFunction &MF = *MBB.getParent(); MachineFrameInfo &MFI = MF.getFrameInfo(); Align Alignment = MFI.getObjectAlign(FI); @@ -1379,12 +1380,10 @@ Register ARMBaseInstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI, return false; } -void ARMBaseInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator I, - Register DestReg, int FI, - const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, - Register VReg) const { +void ARMBaseInstrInfo::loadRegFromStackSlot( + MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register DestReg, + int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, + Register VReg, MachineInstr::MIFlag Flags) const { DebugLoc DL; if (I != MBB.end()) DL = I->getDebugLoc(); MachineFunction &MF = *MBB.getParent(); diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h index 9422e12c5dfc5..ae760e881e7fa 100644 --- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h +++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h @@ -212,18 +212,17 @@ class ARMBaseInstrInfo : public ARMGenInstrInfo { bool KillSrc, bool RenamableDest = false, bool RenamableSrc = false) const override; - void storeRegToStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MBBI, Register SrcReg, - bool isKill, int FrameIndex, - const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, - Register VReg) const override; - - void loadRegFromStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MBBI, Register DestReg, - int FrameIndex, const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, - Register VReg) const override; + void storeRegToStackSlot( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, + bool isKill, int FrameIndex, const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI, Register VReg, + MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override; + + void loadRegFromStackSlot( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, + Register DestReg, int FrameIndex, const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI, Register VReg, + MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override; bool expandPostRAPseudo(MachineInstr &MI) const override; diff --git a/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp b/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp index a38aa3de40d90..cf151e1f8458f 100644 --- a/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp +++ b/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp @@ -117,7 +117,8 @@ void Thumb1InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, Register SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, - Register VReg) const { + Register VReg, + MachineInstr::MIFlag Flags) const { assert((RC == &ARM::tGPRRegClass || (SrcReg.isPhysical() && isARMLowRegister(SrcReg))) && "Unknown regclass!"); @@ -141,12 +142,10 @@ void Thumb1InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, } } -void Thumb1InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator I, - Register DestReg, int FI, - const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, - Register VReg) const { +void Thumb1InstrInfo::loadRegFromStackSlot( + MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register DestReg, + int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, + Register VReg, MachineInstr::MIFlag Flags) const { assert((RC->hasSuperClassEq(&ARM::tGPRRegClass) || (DestReg.isPhysical() && isARMLowRegister(DestReg))) && "Unknown regclass!"); diff --git a/llvm/lib/Target/ARM/Thumb1InstrInfo.h b/llvm/lib/Target/ARM/Thumb1InstrInfo.h index 84241fb8a9a66..b9eb58692bab0 100644 --- a/llvm/lib/Target/ARM/Thumb1InstrInfo.h +++ b/llvm/lib/Target/ARM/Thumb1InstrInfo.h @@ -41,18 +41,17 @@ class Thumb1InstrInfo : public ARMBaseInstrInfo { const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc, bool RenamableDest = false, bool RenamableSrc = false) const override; - void storeRegToStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MBBI, Register SrcReg, - bool isKill, int FrameIndex, - const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, - Register VReg) const override; - - void loadRegFromStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MBBI, Register DestReg, - int FrameIndex, const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, - Register VReg) const override; + void storeRegToStackSlot( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, + bool isKill, int FrameIndex, const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI, Register VReg, + MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override; + + void loadRegFromStackSlot( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, + Register DestReg, int FrameIndex, const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI, Register VReg, + MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override; bool canCopyGluedNodeDuringSchedule(SDNode *N) const override; private: diff --git a/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp b/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp index 4d759d3bd5a3c..3e7bd05b1d9d1 100644 --- a/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp +++ b/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp @@ -166,7 +166,8 @@ void Thumb2InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, Register SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, - Register VReg) const { + Register VReg, + MachineInstr::MIFlag Flags) const { DebugLoc DL; if (I != MBB.end()) DL = I->getDebugLoc(); @@ -206,12 +207,10 @@ void Thumb2InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, Register()); } -void Thumb2InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator I, - Register DestReg, int FI, - const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, - Register VReg) const { +void Thumb2InstrInfo::loadRegFromStackSlot( + MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register DestReg, + int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, + Register VReg, MachineInstr::MIFlag Flags) const { MachineFunction &MF = *MBB.getParent(); MachineFrameInfo &MFI = MF.getFrameInfo(); MachineMemOperand *MMO = MF.getMachineMemOperand( diff --git a/llvm/lib/Target/ARM/Thumb2InstrInfo.h b/llvm/lib/Target/ARM/Thumb2InstrInfo.h index 70ee3270e64ac..7e751c5b6bb9e 100644 --- a/llvm/lib/Target/ARM/Thumb2InstrInfo.h +++ b/llvm/lib/Target/ARM/Thumb2InstrInfo.h @@ -42,18 +42,17 @@ class Thumb2InstrInfo : public ARMBaseInstrInfo { bool KillSrc, bool RenamableDest = false, bool RenamableSrc = false) const override; - void storeRegToStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MBBI, Register SrcReg, - bool isKill, int FrameIndex, - const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, - Register VReg) const override; - - void loadRegFromStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MBBI, Register DestReg, - int FrameIndex, const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, - Register VReg) const override; + void storeRegToStackSlot( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, + bool isKill, int FrameIndex, const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI, Register VReg, + MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override; + + void loadRegFromStackSlot( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, + Register DestReg, int FrameIndex, const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI, Register VReg, + MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override; /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As /// such, whenever a client has an instance of instruction info, it should diff --git a/llvm/lib/Target/AVR/AVRInstrInfo.cpp b/llvm/lib/Target/AVR/AVRInstrInfo.cpp index 7d58ece95c869..5ba83b616db37 100644 --- a/llvm/lib/Target/AVR/AVRInstrInfo.cpp +++ b/llvm/lib/Target/AVR/AVRInstrInfo.cpp @@ -127,7 +127,8 @@ Register AVRInstrInfo::isStoreToStackSlot(const MachineInstr &MI, void AVRInstrInfo::storeRegToStackSlot( MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, Register VReg) const { + const TargetRegisterInfo *TRI, Register VReg, + MachineInstr::MIFlag Flags) const { MachineFunction &MF = *MBB.getParent(); AVRMachineFunctionInfo *AFI = MF.getInfo(); @@ -161,7 +162,8 @@ void AVRInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, - Register VReg) const { + Register VReg, + MachineInstr::MIFlag Flags) const { MachineFunction &MF = *MBB.getParent(); const MachineFrameInfo &MFI = MF.getFrameInfo(); diff --git a/llvm/lib/Target/AVR/AVRInstrInfo.h b/llvm/lib/Target/AVR/AVRInstrInfo.h index 8eb4292f2422d..452160a06663d 100644 --- a/llvm/lib/Target/AVR/AVRInstrInfo.h +++ b/llvm/lib/Target/AVR/AVRInstrInfo.h @@ -77,17 +77,16 @@ class AVRInstrInfo : public AVRGenInstrInfo { const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc, bool RenamableDest = false, bool RenamableSrc = false) const override; - void storeRegToStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, Register SrcReg, - bool isKill, int FrameIndex, - const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, - Register VReg) const override; - void loadRegFromStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, Register DestReg, - int FrameIndex, const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, - Register VReg) const override; + void storeRegToStackSlot( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, + bool isKill, int FrameIndex, const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI, Register VReg, + MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override; + void loadRegFromStackSlot( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, + int FrameIndex, const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI, Register VReg, + MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override; Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override; Register isStoreToStackSlot(const MachineInstr &MI, diff --git a/llvm/lib/Target/BPF/BPFInstrInfo.cpp b/llvm/lib/Target/BPF/BPFInstrInfo.cpp index 1b07e7ffc0d31..c79fb99ba5cf4 100644 --- a/llvm/lib/Target/BPF/BPFInstrInfo.cpp +++ b/llvm/lib/Target/BPF/BPFInstrInfo.cpp @@ -127,7 +127,8 @@ void BPFInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, Register SrcReg, bool IsKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, - Register VReg) const { + Register VReg, + MachineInstr::MIFlag Flags) const { DebugLoc DL; if (I != MBB.end()) DL = I->getDebugLoc(); @@ -146,12 +147,10 @@ void BPFInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, llvm_unreachable("Can't store this register to stack slot"); } -void BPFInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator I, - Register DestReg, int FI, - const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, - Register VReg) const { +void BPFInstrInfo::loadRegFromStackSlot( + MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register DestReg, + int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, + Register VReg, MachineInstr::MIFlag Flags) const { DebugLoc DL; if (I != MBB.end()) DL = I->getDebugLoc(); diff --git a/llvm/lib/Target/BPF/BPFInstrInfo.h b/llvm/lib/Target/BPF/BPFInstrInfo.h index a6b6fd7dc4d96..904d94d47e476 100644 --- a/llvm/lib/Target/BPF/BPFInstrInfo.h +++ b/llvm/lib/Target/BPF/BPFInstrInfo.h @@ -36,18 +36,17 @@ class BPFInstrInfo : public BPFGenInstrInfo { bool expandPostRAPseudo(MachineInstr &MI) const override; - void storeRegToStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MBBI, Register SrcReg, - bool isKill, int FrameIndex, - const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, - Register VReg) const override; + void storeRegToStackSlot( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, + bool isKill, int FrameIndex, const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI, Register VReg, + MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override; - void loadRegFromStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MBBI, Register DestReg, - int FrameIndex, const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, - Register VReg) const override; + void loadRegFromStackSlot( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, + Register DestReg, int FrameIndex, const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI, Register VReg, + MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override; bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl &Cond, diff --git a/llvm/lib/Target/CSKY/CSKYInstrInfo.cpp b/llvm/lib/Target/CSKY/CSKYInstrInfo.cpp index a2bb87bcaaf94..75d581382fe5f 100644 --- a/llvm/lib/Target/CSKY/CSKYInstrInfo.cpp +++ b/llvm/lib/Target/CSKY/CSKYInstrInfo.cpp @@ -393,7 +393,8 @@ void CSKYInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, Register SrcReg, bool IsKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, - Register VReg) const { + Register VReg, + MachineInstr::MIFlag Flags) const { DebugLoc DL; if (I != MBB.end()) DL = I->getDebugLoc(); @@ -432,12 +433,10 @@ void CSKYInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, .addMemOperand(MMO); } -void CSKYInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator I, - Register DestReg, int FI, - const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, - Register VReg) const { +void CSKYInstrInfo::loadRegFromStackSlot( + MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register DestReg, + int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, + Register VReg, MachineInstr::MIFlag Flags) const { DebugLoc DL; if (I != MBB.end()) DL = I->getDebugLoc(); diff --git a/llvm/lib/Target/CSKY/CSKYInstrInfo.h b/llvm/lib/Target/CSKY/CSKYInstrInfo.h index 54c1106310d85..3e0166ecf8e0a 100644 --- a/llvm/lib/Target/CSKY/CSKYInstrInfo.h +++ b/llvm/lib/Target/CSKY/CSKYInstrInfo.h @@ -40,18 +40,17 @@ class CSKYInstrInfo : public CSKYGenInstrInfo { Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override; - void storeRegToStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, Register SrcReg, - bool IsKill, int FrameIndex, - const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, - Register VReg) const override; - - void loadRegFromStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, Register DestReg, - int FrameIndex, const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, - Register VReg) const override; + void storeRegToStackSlot( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, + bool IsKill, int FrameIndex, const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI, Register VReg, + MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override; + + void loadRegFromStackSlot( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, + int FrameIndex, const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI, Register VReg, + MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override; void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp index 366ccb0e00fa8..f30c45e820612 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -959,7 +959,8 @@ void HexagonInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, Register SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, - Register VReg) const { + Register VReg, + MachineInstr::MIFlag Flags) const { DebugLoc DL = MBB.findDebugLoc(I); MachineFunction &MF = *MBB.getParent(); MachineFrameInfo &MFI = MF.getFrameInfo(); @@ -1002,12 +1003,10 @@ void HexagonInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, } } -void HexagonInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator I, - Register DestReg, int FI, - const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, - Register VReg) const { +void HexagonInstrInfo::loadRegFromStackSlot( + MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register DestReg, + int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, + Register VReg, MachineInstr::MIFlag Flags) const { DebugLoc DL = MBB.findDebugLoc(I); MachineFunction &MF = *MBB.getParent(); MachineFrameInfo &MFI = MF.getFrameInfo(); diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.h b/llvm/lib/Target/Hexagon/HexagonInstrInfo.h index 854c3694ceba7..6bfb6d42095ba 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.h +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.h @@ -181,21 +181,20 @@ class HexagonInstrInfo : public HexagonGenInstrInfo { /// stack frame index. The store instruction is to be added to the given /// machine basic block before the specified machine instruction. If isKill /// is true, the register operand is the last use and must be marked kill. - void storeRegToStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MBBI, Register SrcReg, - bool isKill, int FrameIndex, - const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, - Register VReg) const override; + void storeRegToStackSlot( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, + bool isKill, int FrameIndex, const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI, Register VReg, + MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override; /// Load the specified register of the given register class from the specified /// stack frame index. The load instruction is to be added to the given /// machine basic block before the specified machine instruction. - void loadRegFromStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MBBI, Register DestReg, - int FrameIndex, const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, - Register VReg) const override; + void loadRegFromStackSlot( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, + Register DestReg, int FrameIndex, const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI, Register VReg, + MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override; /// This function is called for all pseudo instructions /// that remain after register allocation. Many pseudo instructions are diff --git a/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp b/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp index cd304d1a0a189..bd13c79ca79d6 100644 --- a/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp +++ b/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp @@ -48,7 +48,8 @@ void LanaiInstrInfo::storeRegToStackSlot( MachineBasicBlock &MBB, MachineBasicBlock::iterator Position, Register SourceRegister, bool IsKill, int FrameIndex, const TargetRegisterClass *RegisterClass, - const TargetRegisterInfo * /*RegisterInfo*/, Register /*VReg*/) const { + const TargetRegisterInfo * /*RegisterInfo*/, Register /*VReg*/, + MachineInstr::MIFlag /*Flags*/) const { DebugLoc DL; if (Position != MBB.end()) { DL = Position->getDebugLoc(); @@ -68,7 +69,8 @@ void LanaiInstrInfo::loadRegFromStackSlot( MachineBasicBlock &MBB, MachineBasicBlock::iterator Position, Register DestinationRegister, int FrameIndex, const TargetRegisterClass *RegisterClass, - const TargetRegisterInfo * /*RegisterInfo*/, Register /*VReg*/) const { + const TargetRegisterInfo * /*RegisterInfo*/, Register /*VReg*/, + MachineInstr::MIFlag /*Flags*/) const { DebugLoc DL; if (Position != MBB.end()) { DL = Position->getDebugLoc(); diff --git a/llvm/lib/Target/Lanai/LanaiInstrInfo.h b/llvm/lib/Target/Lanai/LanaiInstrInfo.h index 2630464f0a76f..13cf2b3571039 100644 --- a/llvm/lib/Target/Lanai/LanaiInstrInfo.h +++ b/llvm/lib/Target/Lanai/LanaiInstrInfo.h @@ -53,19 +53,19 @@ class LanaiInstrInfo : public LanaiGenInstrInfo { bool RenamableDest = false, bool RenamableSrc = false) const override; - void storeRegToStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator Position, - Register SourceRegister, bool IsKill, int FrameIndex, - const TargetRegisterClass *RegisterClass, - const TargetRegisterInfo *RegisterInfo, - Register VReg) const override; - - void loadRegFromStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator Position, - Register DestinationRegister, int FrameIndex, - const TargetRegisterClass *RegisterClass, - const TargetRegisterInfo *RegisterInfo, - Register VReg) const override; + void storeRegToStackSlot( + MachineBasicBlock &MBB, MachineBasicBlock::iterator Position, + Register SourceRegister, bool IsKill, int FrameIndex, + const TargetRegisterClass *RegisterClass, + const TargetRegisterInfo *RegisterInfo, Register VReg, + MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override; + + void loadRegFromStackSlot( + MachineBasicBlock &MBB, MachineBasicBlock::iterator Position, + Register DestinationRegister, int FrameIndex, + const TargetRegisterClass *RegisterClass, + const TargetRegisterInfo *RegisterInfo, Register VReg, + MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override; bool expandPostRAPseudo(MachineInstr &MI) const override; diff --git a/llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp b/llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp index 4e49ba6e339a6..903ee76fbc8d5 100644 --- a/llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp +++ b/llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp @@ -113,7 +113,8 @@ void LoongArchInstrInfo::copyPhysReg(MachineBasicBlock &MBB, void LoongArchInstrInfo::storeRegToStackSlot( MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register SrcReg, bool IsKill, int FI, const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, Register VReg) const { + const TargetRegisterInfo *TRI, Register VReg, + MachineInstr::MIFlag Flags) const { MachineFunction *MF = MBB.getParent(); MachineFrameInfo &MFI = MF->getFrameInfo(); @@ -146,12 +147,10 @@ void LoongArchInstrInfo::storeRegToStackSlot( .addMemOperand(MMO); } -void LoongArchInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator I, - Register DstReg, int FI, - const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, - Register VReg) const { +void LoongArchInstrInfo::loadRegFromStackSlot( + MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register DstReg, + int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, + Register VReg, MachineInstr::MIFlag Flags) const { MachineFunction *MF = MBB.getParent(); MachineFrameInfo &MFI = MF->getFrameInfo(); DebugLoc DL; diff --git a/llvm/lib/Target/LoongArch/LoongArchInstrInfo.h b/llvm/lib/Target/LoongArch/LoongArchInstrInfo.h index a5b31878bfa1c..08dc54dbfe98d 100644 --- a/llvm/lib/Target/LoongArch/LoongArchInstrInfo.h +++ b/llvm/lib/Target/LoongArch/LoongArchInstrInfo.h @@ -34,17 +34,16 @@ class LoongArchInstrInfo : public LoongArchGenInstrInfo { bool KillSrc, bool RenamableDest = false, bool RenamableSrc = false) const override; - void storeRegToStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MBBI, Register SrcReg, - bool IsKill, int FrameIndex, - const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, - Register VReg) const override; - void loadRegFromStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MBBI, Register DstReg, - int FrameIndex, const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, - Register VReg) const override; + void storeRegToStackSlot( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, + bool IsKill, int FrameIndex, const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI, Register VReg, + MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override; + void loadRegFromStackSlot( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DstReg, + int FrameIndex, const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI, Register VReg, + MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override; // Materializes the given integer Val into DstReg. void movImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, diff --git a/llvm/lib/Target/M68k/M68kInstrInfo.cpp b/llvm/lib/Target/M68k/M68kInstrInfo.cpp index 6340464520950..182582642c50e 100644 --- a/llvm/lib/Target/M68k/M68kInstrInfo.cpp +++ b/llvm/lib/Target/M68k/M68kInstrInfo.cpp @@ -844,7 +844,8 @@ bool M68kInstrInfo::getStackSlotRange(const TargetRegisterClass *RC, void M68kInstrInfo::storeRegToStackSlot( MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool IsKill, int FrameIndex, const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, Register VReg) const { + const TargetRegisterInfo *TRI, Register VReg, + MachineInstr::MIFlag Flags) const { const MachineFrameInfo &MFI = MBB.getParent()->getFrameInfo(); assert(MFI.getObjectSize(FrameIndex) >= TRI->getSpillSize(*RC) && "Stack slot is too small to store"); @@ -862,7 +863,8 @@ void M68kInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, Register DstReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, - Register VReg) const { + Register VReg, + MachineInstr::MIFlag Flags) const { const MachineFrameInfo &MFI = MBB.getParent()->getFrameInfo(); assert(MFI.getObjectSize(FrameIndex) >= TRI->getSpillSize(*RC) && "Stack slot is too small to load"); diff --git a/llvm/lib/Target/M68k/M68kInstrInfo.h b/llvm/lib/Target/M68k/M68kInstrInfo.h index 5d81956d89fdf..b72fd7a53b93d 100644 --- a/llvm/lib/Target/M68k/M68kInstrInfo.h +++ b/llvm/lib/Target/M68k/M68kInstrInfo.h @@ -278,18 +278,17 @@ class M68kInstrInfo : public M68kGenInstrInfo { unsigned &Size, unsigned &Offset, const MachineFunction &MF) const override; - void storeRegToStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, Register SrcReg, - bool IsKill, int FrameIndex, - const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, - Register VReg) const override; - - void loadRegFromStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, Register DestReg, - int FrameIndex, const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, - Register VReg) const override; + void storeRegToStackSlot( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, + bool IsKill, int FrameIndex, const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI, Register VReg, + MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override; + + void loadRegFromStackSlot( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, + int FrameIndex, const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI, Register VReg, + MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override; bool expandPostRAPseudo(MachineInstr &MI) const override; diff --git a/llvm/lib/Target/MSP430/MSP430InstrInfo.cpp b/llvm/lib/Target/MSP430/MSP430InstrInfo.cpp index 503939a880b83..3018d97f66b86 100644 --- a/llvm/lib/Target/MSP430/MSP430InstrInfo.cpp +++ b/llvm/lib/Target/MSP430/MSP430InstrInfo.cpp @@ -31,7 +31,8 @@ MSP430InstrInfo::MSP430InstrInfo(MSP430Subtarget &STI) void MSP430InstrInfo::storeRegToStackSlot( MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, Register VReg) const { + const TargetRegisterInfo *TRI, Register VReg, + MachineInstr::MIFlag Flags) const { DebugLoc DL; if (MI != MBB.end()) DL = MI->getDebugLoc(); MachineFunction &MF = *MBB.getParent(); @@ -54,12 +55,10 @@ void MSP430InstrInfo::storeRegToStackSlot( llvm_unreachable("Cannot store this register to stack slot!"); } -void MSP430InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - Register DestReg, int FrameIdx, - const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, - Register VReg) const { +void MSP430InstrInfo::loadRegFromStackSlot( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, + int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, + Register VReg, MachineInstr::MIFlag Flags) const { DebugLoc DL; if (MI != MBB.end()) DL = MI->getDebugLoc(); MachineFunction &MF = *MBB.getParent(); diff --git a/llvm/lib/Target/MSP430/MSP430InstrInfo.h b/llvm/lib/Target/MSP430/MSP430InstrInfo.h index 113a22318bec5..71395557454e8 100644 --- a/llvm/lib/Target/MSP430/MSP430InstrInfo.h +++ b/llvm/lib/Target/MSP430/MSP430InstrInfo.h @@ -40,17 +40,16 @@ class MSP430InstrInfo : public MSP430GenInstrInfo { bool KillSrc, bool RenamableDest = false, bool RenamableSrc = false) const override; - void storeRegToStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, Register SrcReg, - bool isKill, int FrameIndex, - const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, - Register VReg) const override; - void loadRegFromStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, Register DestReg, - int FrameIdx, const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, - Register VReg) const override; + void storeRegToStackSlot( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, + bool isKill, int FrameIndex, const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI, Register VReg, + MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override; + void loadRegFromStackSlot( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, + int FrameIdx, const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI, Register VReg, + MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override; unsigned getInstSizeInBytes(const MachineInstr &MI) const override; diff --git a/llvm/lib/Target/Mips/Mips16InstrInfo.cpp b/llvm/lib/Target/Mips/Mips16InstrInfo.cpp index c1f5c2fb84e8b..351caf55062e3 100644 --- a/llvm/lib/Target/Mips/Mips16InstrInfo.cpp +++ b/llvm/lib/Target/Mips/Mips16InstrInfo.cpp @@ -106,7 +106,8 @@ void Mips16InstrInfo::storeRegToStack(MachineBasicBlock &MBB, Register SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, - int64_t Offset) const { + int64_t Offset, + MachineInstr::MIFlag Flags) const { DebugLoc DL; if (I != MBB.end()) DL = I->getDebugLoc(); MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore); @@ -119,12 +120,10 @@ void Mips16InstrInfo::storeRegToStack(MachineBasicBlock &MBB, .addMemOperand(MMO); } -void Mips16InstrInfo::loadRegFromStack(MachineBasicBlock &MBB, - MachineBasicBlock::iterator I, - Register DestReg, int FI, - const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, - int64_t Offset) const { +void Mips16InstrInfo::loadRegFromStack( + MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register DestReg, + int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, + int64_t Offset, MachineInstr::MIFlag Flags) const { DebugLoc DL; if (I != MBB.end()) DL = I->getDebugLoc(); MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad); diff --git a/llvm/lib/Target/Mips/Mips16InstrInfo.h b/llvm/lib/Target/Mips/Mips16InstrInfo.h index 8e73c8079b0f8..095a1b2239a36 100644 --- a/llvm/lib/Target/Mips/Mips16InstrInfo.h +++ b/llvm/lib/Target/Mips/Mips16InstrInfo.h @@ -53,19 +53,17 @@ class Mips16InstrInfo : public MipsInstrInfo { bool KillSrc, bool RenamableDest = false, bool RenamableSrc = false) const override; - void storeRegToStack(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MBBI, - Register SrcReg, bool isKill, int FrameIndex, - const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, - int64_t Offset) const override; - - void loadRegFromStack(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MBBI, - Register DestReg, int FrameIndex, - const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, - int64_t Offset) const override; + void storeRegToStack( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, + bool isKill, int FrameIndex, const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI, int64_t Offset, + MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override; + + void loadRegFromStack( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, + Register DestReg, int FrameIndex, const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI, int64_t Offset, + MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override; bool expandPostRAPseudo(MachineInstr &MI) const override; diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.h b/llvm/lib/Target/Mips/MipsInstrInfo.h index 2ff12f80b1714..0fa8257089bc5 100644 --- a/llvm/lib/Target/Mips/MipsInstrInfo.h +++ b/llvm/lib/Target/Mips/MipsInstrInfo.h @@ -137,36 +137,34 @@ class MipsInstrInfo : public MipsGenInstrInfo { /// Return the number of bytes of code the specified instruction may be. unsigned getInstSizeInBytes(const MachineInstr &MI) const override; - void storeRegToStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MBBI, Register SrcReg, - bool isKill, int FrameIndex, - const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, - Register VReg) const override { - storeRegToStack(MBB, MBBI, SrcReg, isKill, FrameIndex, RC, TRI, 0); + void storeRegToStackSlot( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, + bool isKill, int FrameIndex, const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI, Register VReg, + MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override { + storeRegToStack(MBB, MBBI, SrcReg, isKill, FrameIndex, RC, TRI, 0, Flags); } - void loadRegFromStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MBBI, Register DestReg, - int FrameIndex, const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, - Register VReg) const override { - loadRegFromStack(MBB, MBBI, DestReg, FrameIndex, RC, TRI, 0); + void loadRegFromStackSlot( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, + Register DestReg, int FrameIndex, const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI, Register VReg, + MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override { + loadRegFromStack(MBB, MBBI, DestReg, FrameIndex, RC, TRI, 0, Flags); } - virtual void storeRegToStack(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - Register SrcReg, bool isKill, int FrameIndex, - const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, - int64_t Offset) const = 0; - - virtual void loadRegFromStack(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - Register DestReg, int FrameIndex, - const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, - int64_t Offset) const = 0; + virtual void + storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, + Register SrcReg, bool isKill, int FrameIndex, + const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, + int64_t Offset, + MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const = 0; + + virtual void loadRegFromStack( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, + int FrameIndex, const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI, int64_t Offset, + MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const = 0; virtual void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB, diff --git a/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp b/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp index 851fd2f3ead7d..c245a18ae0bef 100644 --- a/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp +++ b/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp @@ -209,11 +209,13 @@ MipsSEInstrInfo::isCopyInstrImpl(const MachineInstr &MI) const { return std::nullopt; } -void MipsSEInstrInfo:: -storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, - Register SrcReg, bool isKill, int FI, - const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, - int64_t Offset) const { +void MipsSEInstrInfo::storeRegToStack(MachineBasicBlock &MBB, + MachineBasicBlock::iterator I, + Register SrcReg, bool isKill, int FI, + const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI, + int64_t Offset, + MachineInstr::MIFlag Flags) const { DebugLoc DL; MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore); @@ -283,10 +285,10 @@ storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, .addFrameIndex(FI).addImm(Offset).addMemOperand(MMO); } -void MipsSEInstrInfo:: -loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, - Register DestReg, int FI, const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, int64_t Offset) const { +void MipsSEInstrInfo::loadRegFromStack( + MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register DestReg, + int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, + int64_t Offset, MachineInstr::MIFlag Flags) const { DebugLoc DL; if (I != MBB.end()) DL = I->getDebugLoc(); MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad); diff --git a/llvm/lib/Target/Mips/MipsSEInstrInfo.h b/llvm/lib/Target/Mips/MipsSEInstrInfo.h index 36bddba10410c..9004254857f32 100644 --- a/llvm/lib/Target/Mips/MipsSEInstrInfo.h +++ b/llvm/lib/Target/Mips/MipsSEInstrInfo.h @@ -47,19 +47,17 @@ class MipsSEInstrInfo : public MipsInstrInfo { bool KillSrc, bool RenamableDest = false, bool RenamableSrc = false) const override; - void storeRegToStack(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - Register SrcReg, bool isKill, int FrameIndex, - const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, - int64_t Offset) const override; - - void loadRegFromStack(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - Register DestReg, int FrameIndex, - const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, - int64_t Offset) const override; + void storeRegToStack( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, + bool isKill, int FrameIndex, const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI, int64_t Offset, + MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override; + + void loadRegFromStack( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, + int FrameIndex, const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI, int64_t Offset, + MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override; bool expandPostRAPseudo(MachineInstr &MI) const override; diff --git a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.h b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.h index a1d9f01712018..06b111c69fb74 100644 --- a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.h +++ b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.h @@ -38,17 +38,16 @@ class NVPTXInstrInfo : public NVPTXGenInstrInfo { * int &FrameIndex) const; * virtual Register isStoreToStackSlot(const MachineInstr *MI, * int &FrameIndex) const; - * virtual void storeRegToStackSlot(MachineBasicBlock &MBB, - * MachineBasicBlock::iterator MBBI, - * unsigned SrcReg, bool isKill, int FrameIndex, - * const TargetRegisterClass *RC, - * Register VReg) const; - * virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, - * MachineBasicBlock::iterator MBBI, - * unsigned DestReg, int FrameIndex, - * const TargetRegisterClass *RC, - * const TargetRegisterInfo *TRI, - * Register VReg) const; + * virtual void storeRegToStackSlot( + * MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, + * unsigned SrcReg, bool isKill, int FrameIndex, + * const TargetRegisterClass *RC, Register VReg, + * MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const; + * virtual void loadRegFromStackSlot( + * MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, + * unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, + * const TargetRegisterInfo *TRI, Register VReg, + * MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const; */ void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp index fa45a7fb7fabe..04b58bba7251e 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -1967,7 +1967,8 @@ void PPCInstrInfo::storeRegToStackSlotNoUpd( void PPCInstrInfo::storeRegToStackSlot( MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, Register VReg) const { + const TargetRegisterInfo *TRI, Register VReg, + MachineInstr::MIFlag Flags) const { // We need to avoid a situation in which the value from a VRRC register is // spilled using an Altivec instruction and reloaded into a VSRC register // using a VSX instruction. The issue with this is that the VSX @@ -2011,12 +2012,10 @@ void PPCInstrInfo::loadRegFromStackSlotNoUpd( NewMIs.back()->addMemOperand(MF, MMO); } -void PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - Register DestReg, int FrameIdx, - const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, - Register VReg) const { +void PPCInstrInfo::loadRegFromStackSlot( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, + int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, + Register VReg, MachineInstr::MIFlag Flags) const { // We need to avoid a situation in which the value from a VRRC register is // spilled using an Altivec instruction and reloaded into a VSRC register // using a VSX instruction. The issue with this is that the VSX diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.h b/llvm/lib/Target/PowerPC/PPCInstrInfo.h index cd8ecc2dcfac8..69279efe5c151 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.h +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.h @@ -461,12 +461,11 @@ class PPCInstrInfo : public PPCGenInstrInfo { bool KillSrc, bool RenamableDest = false, bool RenamableSrc = false) const override; - void storeRegToStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MBBI, Register SrcReg, - bool isKill, int FrameIndex, - const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, - Register VReg) const override; + void storeRegToStackSlot( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, + bool isKill, int FrameIndex, const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI, Register VReg, + MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override; // Emits a register spill without updating the register class for vector // registers. This ensures that when we spill a vector register the @@ -477,11 +476,11 @@ class PPCInstrInfo : public PPCGenInstrInfo { const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const; - void loadRegFromStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MBBI, Register DestReg, - int FrameIndex, const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, - Register VReg) const override; + void loadRegFromStackSlot( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, + Register DestReg, int FrameIndex, const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI, Register VReg, + MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override; // Emits a register reload without updating the register class for vector // registers. This ensures that when we reload a vector register the diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp index 1f7e8d87a11b0..471cd15ee9c87 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp @@ -579,7 +579,8 @@ void RISCVInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, Register SrcReg, bool IsKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, - Register VReg) const { + Register VReg, + MachineInstr::MIFlag Flags) const { MachineFunction *MF = MBB.getParent(); MachineFrameInfo &MFI = MF->getFrameInfo(); @@ -663,12 +664,10 @@ void RISCVInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, } } -void RISCVInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator I, - Register DstReg, int FI, - const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, - Register VReg) const { +void RISCVInstrInfo::loadRegFromStackSlot( + MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register DstReg, + int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, + Register VReg, MachineInstr::MIFlag Flags) const { MachineFunction *MF = MBB.getParent(); MachineFrameInfo &MFI = MF->getFrameInfo(); diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.h b/llvm/lib/Target/RISCV/RISCVInstrInfo.h index 7e8bcd451a8ef..1c81719c767ec 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.h +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.h @@ -92,18 +92,17 @@ class RISCVInstrInfo : public RISCVGenInstrInfo { bool KillSrc, bool RenamableDest = false, bool RenamableSrc = false) const override; - void storeRegToStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MBBI, Register SrcReg, - bool IsKill, int FrameIndex, - const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, - Register VReg) const override; - - void loadRegFromStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MBBI, Register DstReg, - int FrameIndex, const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, - Register VReg) const override; + void storeRegToStackSlot( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, + bool IsKill, int FrameIndex, const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI, Register VReg, + MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override; + + void loadRegFromStackSlot( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DstReg, + int FrameIndex, const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI, Register VReg, + MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override; using TargetInstrInfo::foldMemoryOperandImpl; MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.cpp b/llvm/lib/Target/Sparc/SparcInstrInfo.cpp index bc57a556c9ef6..225d6cd80f908 100644 --- a/llvm/lib/Target/Sparc/SparcInstrInfo.cpp +++ b/llvm/lib/Target/Sparc/SparcInstrInfo.cpp @@ -528,7 +528,8 @@ void SparcInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, Register SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, - Register VReg) const { + Register VReg, + MachineInstr::MIFlag Flags) const { DebugLoc DL; if (I != MBB.end()) DL = I->getDebugLoc(); @@ -563,12 +564,10 @@ void SparcInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, llvm_unreachable("Can't store this register to stack slot"); } -void SparcInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator I, - Register DestReg, int FI, - const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, - Register VReg) const { +void SparcInstrInfo::loadRegFromStackSlot( + MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register DestReg, + int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, + Register VReg, MachineInstr::MIFlag Flags) const { DebugLoc DL; if (I != MBB.end()) DL = I->getDebugLoc(); diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.h b/llvm/lib/Target/Sparc/SparcInstrInfo.h index fc04542c819d4..552e7c52be262 100644 --- a/llvm/lib/Target/Sparc/SparcInstrInfo.h +++ b/llvm/lib/Target/Sparc/SparcInstrInfo.h @@ -90,18 +90,17 @@ class SparcInstrInfo : public SparcGenInstrInfo { bool KillSrc, bool RenamableDest = false, bool RenamableSrc = false) const override; - void storeRegToStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MBBI, Register SrcReg, - bool isKill, int FrameIndex, - const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, - Register VReg) const override; - - void loadRegFromStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MBBI, Register DestReg, - int FrameIndex, const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, - Register VReg) const override; + void storeRegToStackSlot( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, + bool isKill, int FrameIndex, const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI, Register VReg, + MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override; + + void loadRegFromStackSlot( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, + Register DestReg, int FrameIndex, const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI, Register VReg, + MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override; Register getGlobalBaseReg(MachineFunction *MF) const; diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp index d553c72589f59..a6fb5ab0ee9e1 100644 --- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp +++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp @@ -993,7 +993,8 @@ void SystemZInstrInfo::copyPhysReg(MachineBasicBlock &MBB, void SystemZInstrInfo::storeRegToStackSlot( MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, Register VReg) const { + const TargetRegisterInfo *TRI, Register VReg, + MachineInstr::MIFlag Flags) const { DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); // Callers may expect a single instruction, so keep 128-bit moves @@ -1005,12 +1006,10 @@ void SystemZInstrInfo::storeRegToStackSlot( FrameIdx); } -void SystemZInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MBBI, - Register DestReg, int FrameIdx, - const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, - Register VReg) const { +void SystemZInstrInfo::loadRegFromStackSlot( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, + int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, + Register VReg, MachineInstr::MIFlag Flags) const { DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); // Callers may expect a single instruction, so keep 128-bit moves diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.h b/llvm/lib/Target/SystemZ/SystemZInstrInfo.h index cc8a4ccd234cd..3d709a24db36c 100644 --- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.h +++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.h @@ -278,17 +278,16 @@ class SystemZInstrInfo : public SystemZGenInstrInfo { const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc, bool RenamableDest = false, bool RenamableSrc = false) const override; - void storeRegToStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MBBI, Register SrcReg, - bool isKill, int FrameIndex, - const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, - Register VReg) const override; - void loadRegFromStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MBBI, Register DestReg, - int FrameIdx, const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, - Register VReg) const override; + void storeRegToStackSlot( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, + bool isKill, int FrameIndex, const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI, Register VReg, + MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override; + void loadRegFromStackSlot( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, + Register DestReg, int FrameIdx, const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI, Register VReg, + MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override; MachineInstr *convertToThreeAddress(MachineInstr &MI, LiveVariables *LV, LiveIntervals *LIS) const override; diff --git a/llvm/lib/Target/VE/VEInstrInfo.cpp b/llvm/lib/Target/VE/VEInstrInfo.cpp index 9295ae51b5d2e..3ace8e7eae927 100644 --- a/llvm/lib/Target/VE/VEInstrInfo.cpp +++ b/llvm/lib/Target/VE/VEInstrInfo.cpp @@ -461,7 +461,8 @@ void VEInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, Register SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, - Register VReg) const { + Register VReg, + MachineInstr::MIFlag Flags) const { DebugLoc DL; if (I != MBB.end()) DL = I->getDebugLoc(); @@ -519,12 +520,10 @@ void VEInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, report_fatal_error("Can't store this register to stack slot"); } -void VEInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator I, - Register DestReg, int FI, - const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, - Register VReg) const { +void VEInstrInfo::loadRegFromStackSlot( + MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register DestReg, + int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, + Register VReg, MachineInstr::MIFlag Flags) const { DebugLoc DL; if (I != MBB.end()) DL = I->getDebugLoc(); diff --git a/llvm/lib/Target/VE/VEInstrInfo.h b/llvm/lib/Target/VE/VEInstrInfo.h index 3a9718f2f2603..210ce1a8a2662 100644 --- a/llvm/lib/Target/VE/VEInstrInfo.h +++ b/llvm/lib/Target/VE/VEInstrInfo.h @@ -89,18 +89,17 @@ class VEInstrInfo : public VEGenInstrInfo { int &FrameIndex) const override; Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override; - void storeRegToStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MBBI, Register SrcReg, - bool isKill, int FrameIndex, - const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, - Register VReg) const override; - - void loadRegFromStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MBBI, Register DestReg, - int FrameIndex, const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, - Register VReg) const override; + void storeRegToStackSlot( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, + bool isKill, int FrameIndex, const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI, Register VReg, + MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override; + + void loadRegFromStackSlot( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, + Register DestReg, int FrameIndex, const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI, Register VReg, + MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override; /// } Stack Spill & Reload /// Optimization { diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp index 30a5161bbcc50..1baac05827c47 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.cpp +++ b/llvm/lib/Target/X86/X86InstrInfo.cpp @@ -4784,7 +4784,8 @@ void X86InstrInfo::loadStoreTileReg(MachineBasicBlock &MBB, void X86InstrInfo::storeRegToStackSlot( MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, Register VReg) const { + const TargetRegisterInfo *TRI, Register VReg, + MachineInstr::MIFlag Flags) const { const MachineFunction &MF = *MBB.getParent(); const MachineFrameInfo &MFI = MF.getFrameInfo(); assert(MFI.getObjectSize(FrameIdx) >= TRI->getSpillSize(*RC) && @@ -4803,12 +4804,10 @@ void X86InstrInfo::storeRegToStackSlot( .addReg(SrcReg, getKillRegState(isKill)); } -void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - Register DestReg, int FrameIdx, - const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, - Register VReg) const { +void X86InstrInfo::loadRegFromStackSlot( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, + int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, + Register VReg, MachineInstr::MIFlag Flags) const { const MachineFunction &MF = *MBB.getParent(); const MachineFrameInfo &MFI = MF.getFrameInfo(); assert(MFI.getObjectSize(FrameIdx) >= TRI->getSpillSize(*RC) && diff --git a/llvm/lib/Target/X86/X86InstrInfo.h b/llvm/lib/Target/X86/X86InstrInfo.h index b006bc3971984..5f87e02fe67c4 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.h +++ b/llvm/lib/Target/X86/X86InstrInfo.h @@ -420,18 +420,17 @@ class X86InstrInfo final : public X86GenInstrInfo { const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc, bool RenamableDest = false, bool RenamableSrc = false) const override; - void storeRegToStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, Register SrcReg, - bool isKill, int FrameIndex, - const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, - Register VReg) const override; - - void loadRegFromStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, Register DestReg, - int FrameIndex, const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, - Register VReg) const override; + void storeRegToStackSlot( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, + bool isKill, int FrameIndex, const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI, Register VReg, + MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override; + + void loadRegFromStackSlot( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, + int FrameIndex, const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI, Register VReg, + MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override; void loadStoreTileReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned Opc, Register Reg, int FrameIdx, diff --git a/llvm/lib/Target/XCore/XCoreInstrInfo.cpp b/llvm/lib/Target/XCore/XCoreInstrInfo.cpp index 5371f1f8db48d..a15681afa28d4 100644 --- a/llvm/lib/Target/XCore/XCoreInstrInfo.cpp +++ b/llvm/lib/Target/XCore/XCoreInstrInfo.cpp @@ -355,7 +355,8 @@ void XCoreInstrInfo::copyPhysReg(MachineBasicBlock &MBB, void XCoreInstrInfo::storeRegToStackSlot( MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, Register VReg) const { + const TargetRegisterInfo *TRI, Register VReg, + MachineInstr::MIFlag Flags) const { DebugLoc DL; if (I != MBB.end() && !I->isDebugInstr()) DL = I->getDebugLoc(); @@ -377,7 +378,8 @@ void XCoreInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, - Register VReg) const { + Register VReg, + MachineInstr::MIFlag Flags) const { DebugLoc DL; if (I != MBB.end() && !I->isDebugInstr()) DL = I->getDebugLoc(); diff --git a/llvm/lib/Target/XCore/XCoreInstrInfo.h b/llvm/lib/Target/XCore/XCoreInstrInfo.h index 7f330539dd76a..036321b573e35 100644 --- a/llvm/lib/Target/XCore/XCoreInstrInfo.h +++ b/llvm/lib/Target/XCore/XCoreInstrInfo.h @@ -67,18 +67,17 @@ class XCoreInstrInfo : public XCoreGenInstrInfo { bool KillSrc, bool RenamableDest = false, bool RenamableSrc = false) const override; - void storeRegToStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, Register SrcReg, - bool isKill, int FrameIndex, - const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, - Register VReg) const override; - - void loadRegFromStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, Register DestReg, - int FrameIndex, const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, - Register VReg) const override; + void storeRegToStackSlot( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, + bool isKill, int FrameIndex, const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI, Register VReg, + MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override; + + void loadRegFromStackSlot( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, + int FrameIndex, const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI, Register VReg, + MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override; bool reverseBranchCondition( SmallVectorImpl &Cond) const override; diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp b/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp index 7e00215ef3b97..c38c78b54ec21 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp @@ -123,7 +123,8 @@ void XtensaInstrInfo::copyPhysReg(MachineBasicBlock &MBB, void XtensaInstrInfo::storeRegToStackSlot( MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, Register VReg) const { + const TargetRegisterInfo *TRI, Register VReg, + MachineInstr::MIFlag Flags) const { DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); unsigned LoadOpcode, StoreOpcode; getLoadStoreOpcodes(RC, LoadOpcode, StoreOpcode, FrameIdx); @@ -132,12 +133,10 @@ void XtensaInstrInfo::storeRegToStackSlot( addFrameReference(MIB, FrameIdx); } -void XtensaInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MBBI, - Register DestReg, int FrameIdx, - const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, - Register VReg) const { +void XtensaInstrInfo::loadRegFromStackSlot( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, + int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, + Register VReg, MachineInstr::MIFlag Flags) const { DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); unsigned LoadOpcode, StoreOpcode; getLoadStoreOpcodes(RC, LoadOpcode, StoreOpcode, FrameIdx); diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.h b/llvm/lib/Target/Xtensa/XtensaInstrInfo.h index 31da4d481d309..5d1206b918089 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.h +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.h @@ -54,18 +54,17 @@ class XtensaInstrInfo : public XtensaGenInstrInfo { bool KillSrc, bool RenamableDest = false, bool RenamableSrc = false) const override; - void storeRegToStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MBBI, Register SrcReg, - bool isKill, int FrameIndex, - const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, - Register VReg) const override; - - void loadRegFromStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MBBI, Register DestReg, - int FrameIdx, const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, - Register VReg) const override; + void storeRegToStackSlot( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, + bool isKill, int FrameIndex, const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI, Register VReg, + MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override; + + void loadRegFromStackSlot( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, + Register DestReg, int FrameIdx, const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI, Register VReg, + MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override; // Get the load and store opcodes for a given register class and offset. void getLoadStoreOpcodes(const TargetRegisterClass *RC, unsigned &LoadOpcode,