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[LLVM][AArch64] Add assembly/disassembly for SME2p2 ftmopa and bftmopa
This patch adds assembly/disassembly for the following SME2p2 instructions (part of the 2024 AArch64 ISA update) - BFTMOPA (widening) - FEAT_SME2p2 - BFTMOPA (non-widening) - FEAT_SME2p2 & FEAT_SME_B16B16 - FTMOPA (4-way) - FEAT_SME2p2 & FEAT_SME_F8F32 - FTMOPA (2-way, 8-to-16) - FEAT_SME2p2 & FEAT_SME_F8F16 - FTMOPA (2-way, 16-to-32) - FEAT_SME2p2 - FTMOPA (non-widening, f16) - FEAT_SME2p2 & FEAT_SME_F16F16 - FTMOPA (non-widening, f32) - FEAT_SME2p2 - It also introduces .arch assembler tests for the new sme2p2 feature In accordance with: https://developer.arm.com/documentation/ddi0602/latest/ Co-authored-by: Marian Lukac [email protected]
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‎llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td

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@@ -1000,3 +1000,24 @@ defm FMOPA_MPPZZ_BtoS : sme_outer_product_fp32<0b0, 0b01, ZPR8, "fmopa", null_fr
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} //[HasSMEF8F32]
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let Predicates = [HasSME2p2] in {
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def FTMOPA_M2ZZZI_HtoS : sme_tmopa_32b<0b11000, ZZ_h_mul_r, ZPR16, "ftmopa">;
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def FTMOPA_M2ZZZI_StoS : sme_tmopa_32b<0b00000, ZZ_s_mul_r, ZPR32, "ftmopa">;
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def BFTMOPA_M2ZZZI_HtoS : sme_tmopa_32b<0b10000, ZZ_h_mul_r, ZPR16, "bftmopa">;
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} // [HasSME2p2]
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let Predicates = [HasSME2p2, HasSMEB16B16] in {
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def BFTMOPA_M2ZZZI_HtoH : sme_tmopa_16b<0b11001, ZZ_h_mul_r, ZPR16, "bftmopa">;
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} // [HasSME2p2, HasSMEB16B16]
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let Predicates = [HasSME2p2, HasSMEF8F32], Uses = [FPMR, FPCR] in {
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def FTMOPA_M2ZZZI_BtoS : sme_tmopa_32b<0b01000, ZZ_b_mul_r, ZPR8, "ftmopa">;
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} // [HasSME2p2, HasSMEF8F32], Uses = [FPMR, FPCR]
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let Predicates = [HasSME2p2, HasSMEF8F16], Uses = [FPMR, FPCR] in {
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def FTMOPA_M2ZZZI_BtoH : sme_tmopa_16b<0b01001, ZZ_b_mul_r, ZPR8, "ftmopa">;
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} // [HasSME2p2, HasSMEF8F16], Uses = [FPMR, FPCR]
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let Predicates = [HasSME2p2, HasSMEF16F16] in {
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def FTMOPA_M2ZZZI_HtoH : sme_tmopa_16b<0b10001, ZZ_h_mul_r, ZPR16, "ftmopa">;
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} // [HasSME2p2, HasSMEF16F16]

‎llvm/lib/Target/AArch64/SMEInstrFormats.td

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@@ -3192,6 +3192,68 @@ multiclass sme2_int_bmopx_tile<string mnemonic, bits<3> op, SDPatternOperator i
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def : SME_ZA_Tile_TwoPred_TwoVec_Pat<NAME, intrinsic, timm32_0_3, nxv4i1, nxv4i32>;
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}
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//===----------------------------------------------------------------------===//
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// SME2 Sparse Outer Product and Accumulate
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class sme_tmopa_16b<bits<5> opc, RegisterOperand zn_ty, RegisterOperand zm_ty, string mnemonic>
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: I<(outs TileOp16:$ZAda),
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(ins TileOp16:$_ZAda, zn_ty:$Zn, zm_ty:$Zm, ZK:$Zk, VectorIndexS32b:$imm),
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mnemonic, "\t$ZAda, $Zn, $Zm, $Zk$imm",
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"", []>,
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Sched<[]> {
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bit ZAda;
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bits<4> Zn;
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bits<5> Zm;
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bits<3> Zk;
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bits<2> imm;
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let Inst{31-25} = 0b1000000;
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let Inst{24} = opc{4};
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let Inst{23-22} = 0b01;
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let Inst{21} = opc{3};
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let Inst{20-16} = Zm;
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let Inst{15} = opc{2};
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let Inst{14} = 0b0;
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let Inst{13} = opc{1};
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let Inst{12-10} = Zk;
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let Inst{9-6} = Zn;
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let Inst{5-4} = imm;
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let Inst{3} = opc{0};
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let Inst{2-1} = 0b00;
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let Inst{0} = ZAda;
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let Constraints = "$ZAda = $_ZAda";
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}
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class sme_tmopa_32b<bits<5> opc, RegisterOperand zn_ty, RegisterOperand zm_ty, string mnemonic>
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: I<(outs TileOp32:$ZAda),
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(ins TileOp32:$_ZAda, zn_ty:$Zn, zm_ty:$Zm, ZK:$Zk, VectorIndexS32b:$imm),
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mnemonic, "\t$ZAda, $Zn, $Zm, $Zk$imm",
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"", []>,
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Sched<[]> {
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bits<2> ZAda;
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bits<4> Zn;
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bits<5> Zm;
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bits<3> Zk;
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bits<2> imm;
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let Inst{31-25} = 0b1000000;
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let Inst{24} = opc{4};
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let Inst{23-22} = 0b01;
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let Inst{21} = opc{3};
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let Inst{20-16} = Zm;
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let Inst{15} = opc{2};
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let Inst{14} = 0b0;
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let Inst{13} = opc{1};
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let Inst{12-10} = Zk;
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let Inst{9-6} = Zn;
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let Inst{5-4} = imm;
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let Inst{3} = opc{0};
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let Inst{2} = 0b0;
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let Inst{1-0} = ZAda;
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let Constraints = "$ZAda = $_ZAda";
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}
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//===----------------------------------------------------------------------===///
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// SME2 Zero Lookup Table.
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class sme2_zero_zt<string mnemonic, bits<4> opc>

‎llvm/test/MC/AArch64/SME2p2/bftmopa-diagnostics.s

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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2,+sme-b16b16 2>&1 < %s| FileCheck %s
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// --------------------------------------------------------------------------//
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// Invalid ZA register (range)
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bftmopa za2.h, {z30.h-z31.h}, z31.h, z31[3]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: bftmopa za2.h, {z30.h-z31.h}, z31.h, z31[3]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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bftmopa za4.s, {z30.h-z31.h}, z31.h, z31[3]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: bftmopa za4.s, {z30.h-z31.h}, z31.h, z31[3]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid ZA register (type-suffix)
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bftmopa za3.d, {z28.h-z29.h}, z31.h, z20[3]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-3].s
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// CHECK-NEXT: bftmopa za3.d, {z28.h-z29.h}, z31.h, z20[3]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid vector list operand
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bftmopa za0.h, {z28.h-z31.h}, z31.h, z31[3]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: bftmopa za0.h, {z28.h-z31.h}, z31.h, z31[3]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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bftmopa za0.h, {z29.h-z30.h}, z31.h, z31[3]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
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// CHECK-NEXT: bftmopa za0.h, {z29.h-z30.h}, z31.h, z31[3]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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bftmopa za0.s, {z28.h-z31.h}, z31.h, z31[3]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: bftmopa za0.s, {z28.h-z31.h}, z31.h, z31[3]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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bftmopa za3.s, {z29.h-z30.h}, z31.h, z31[3]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
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// CHECK-NEXT: bftmopa za3.s, {z29.h-z30.h}, z31.h, z31[3]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid ZK register
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bftmopa za0.h, {z28.h-z29.h}, z31.h, z19[3]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted vector register, expected register in z20..z23 or z28..z31
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// CHECK-NEXT: bftmopa za0.h, {z28.h-z29.h}, z31.h, z19[3]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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bftmopa za0.h, {z28.h-z29.h}, z31.h, z24[3]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted vector register, expected register in z20..z23 or z28..z31
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// CHECK-NEXT: bftmopa za0.h, {z28.h-z29.h}, z31.h, z24[3]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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bftmopa za3.s, {z28.h-z29.h}, z31.h, z19[3]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted vector register, expected register in z20..z23 or z28..z31
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// CHECK-NEXT: bftmopa za3.s, {z28.h-z29.h}, z31.h, z19[3]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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bftmopa za3.s, {z28.h-z29.h}, z31.h, z27[3]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted vector register, expected register in z20..z23 or z28..z31
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// CHECK-NEXT: bftmopa za3.s, {z28.h-z29.h}, z31.h, z27[3]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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bftmopa za0.h, {z28.h-z29.h}, z31.h, z21.h[3]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted vector register, expected register in z20..z23 or z28..z31
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// CHECK-NEXT: bftmopa za0.h, {z28.h-z29.h}, z31.h, z21.h[3]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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bftmopa za0.s, {z28.h-z29.h}, z31.h, z30.h[3]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted vector register, expected register in z20..z23 or z28..z31
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// CHECK-NEXT: bftmopa za0.s, {z28.h-z29.h}, z31.h, z30.h[3]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid immediate
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bftmopa za0.h, {z28.h-z29.h}, z31.h, z20[4]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]
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// CHECK-NEXT: bftmopa za0.h, {z28.h-z29.h}, z31.h, z20[4]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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bftmopa za3.s, {z28.h-z29.h}, z31.h, z20[4]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]
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// CHECK-NEXT: bftmopa za3.s, {z28.h-z29.h}, z31.h, z20[4]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid ZPR type suffix
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bftmopa za0.h, {z28.h-z29.h}, z31.s, z20[3]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: bftmopa za0.h, {z28.h-z29.h}, z31.s, z20[3]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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bftmopa za0.h, {z28.b-z29.b}, z31.b, z20[3]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: bftmopa za0.h, {z28.b-z29.b}, z31.b, z20[3]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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bftmopa za3.s, {z28.h-z29.h}, z31.s, z20[3]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: bftmopa za3.s, {z28.h-z29.h}, z31.s, z20[3]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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bftmopa za3.s, {z28.s-z29.s}, z31.s, z20[3]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: bftmopa za3.s, {z28.s-z29.s}, z31.s, z20[3]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

‎llvm/test/MC/AArch64/SME2p2/bftmopa.s

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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2,+sme-b16b16 < %s \
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// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
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// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2,+sme-b16b16 < %s \
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// RUN: | llvm-objdump -d --mattr=+sme2p2,+sme-b16b16 --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2,+sme-b16b16 < %s \
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// RUN: | llvm-objdump -d --mattr=-sme2p2 --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-UNKNOWN
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// Disassemble encoding and check the re-encoding (-show-encoding) matches.
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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2,+sme-b16b16 < %s \
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// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
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// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p2,+sme-b16b16 -disassemble -show-encoding \
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// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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// non-widening
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bftmopa za0.h, {z0.h-z1.h}, z0.h, z20[0] // 10000001-01100000-00000000-00001000
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// CHECK-INST: bftmopa za0.h, { z0.h, z1.h }, z0.h, z20[0]
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// CHECK-ENCODING: [0x08,0x00,0x60,0x81]
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// CHECK-ERROR: instruction requires: sme2p2 sme-b16b16
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// CHECK-UNKNOWN: 81600008 <unknown>
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bftmopa za1.h, {z12.h-z13.h}, z8.h, z23[3] // 10000001-01101000-00001101-10111001
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// CHECK-INST: bftmopa za1.h, { z12.h, z13.h }, z8.h, z23[3]
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// CHECK-ENCODING: [0xb9,0x0d,0x68,0x81]
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// CHECK-ERROR: instruction requires: sme2p2 sme-b16b16
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// CHECK-UNKNOWN: 81680db9 <unknown>
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bftmopa za1.h, {z30.h-z31.h}, z31.h, z31[3] // 10000001-01111111-00011111-11111001
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// CHECK-INST: bftmopa za1.h, { z30.h, z31.h }, z31.h, z31[3]
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// CHECK-ENCODING: [0xf9,0x1f,0x7f,0x81]
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// CHECK-ERROR: instruction requires: sme2p2 sme-b16b16
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// CHECK-UNKNOWN: 817f1ff9 <unknown>
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// widening
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bftmopa za0.s, {z0.h-z1.h}, z0.h, z20[0] // 10000001-01000000-00000000-00000000
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// CHECK-INST: bftmopa za0.s, { z0.h, z1.h }, z0.h, z20[0]
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// CHECK-ENCODING: [0x00,0x00,0x40,0x81]
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// CHECK-ERROR: instruction requires: sme2p2
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// CHECK-UNKNOWN: 81400000 <unknown>
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bftmopa za3.s, {z12.h-z13.h}, z8.h, z23[3] // 10000001-01001000-00001101-10110011
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// CHECK-INST: bftmopa za3.s, { z12.h, z13.h }, z8.h, z23[3]
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// CHECK-ENCODING: [0xb3,0x0d,0x48,0x81]
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// CHECK-ERROR: instruction requires: sme2p2
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// CHECK-UNKNOWN: 81480db3 <unknown>
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bftmopa za3.s, {z30.h-z31.h}, z31.h, z31[3] // 10000001-01011111-00011111-11110011
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// CHECK-INST: bftmopa za3.s, { z30.h, z31.h }, z31.h, z31[3]
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// CHECK-ENCODING: [0xf3,0x1f,0x5f,0x81]
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// CHECK-ERROR: instruction requires: sme2p2
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// CHECK-UNKNOWN: 815f1ff3 <unknown>

‎llvm/test/MC/AArch64/SME2p2/directive-arch-negative.s

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// RUN: not llvm-mc -triple aarch64 -filetype asm -o - %s 2>&1 | FileCheck %s
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.arch armv9-a+sme2p2
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.arch armv9-a+nosme2p2
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ftmopa za0.s, {z0.s-z1.s}, z0.s, z20[0]
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// CHECK: error: instruction requires: sme2p2
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// CHECK: ftmopa za0.s, {z0.s-z1.s}, z0.s, z20[0]

‎llvm/test/MC/AArch64/SME2p2/directive-arch.s

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// RUN: llvm-mc -triple aarch64 -o - %s 2>&1 | FileCheck %s
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.arch armv9-a+sme2p2
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ftmopa za0.s, {z0.s-z1.s}, z0.s, z20[0]
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// CHECK: ftmopa za0.s, { z0.s, z1.s }, z0.s, z20[0]

‎llvm/test/MC/AArch64/SME2p2/directive-arch_extension-negative.s

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// RUN: not llvm-mc -triple aarch64 -filetype asm -o - %s 2>&1 | FileCheck %s
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.arch_extension sme2p2
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.arch_extension nosme2p2
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ftmopa za0.s, {z0.s-z1.s}, z0.s, z20[0]
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// CHECK: error: instruction requires: sme2p2
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// CHECK: ftmopa za0.s, {z0.s-z1.s}, z0.s, z20[0]

‎llvm/test/MC/AArch64/SME2p2/directive-arch_extension.s

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// RUN: llvm-mc -triple aarch64 -filetype asm -o - %s 2>&1 | FileCheck %s
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.arch_extension sme2p2
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ftmopa za0.s, {z0.s-z1.s}, z0.s, z20[0]
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// CHECK: ftmopa za0.s, { z0.s, z1.s }, z0.s, z20[0]

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