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phoebewangphoebewang
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[X86] Use vXi1 for k constraint in inline asm (#77733)
Fixes #77172
1 parent 84bdee2 commit 8d6e82d

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5 files changed

+45
-21
lines changed

5 files changed

+45
-21
lines changed

‎clang/lib/CodeGen/CGStmt.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2399,9 +2399,9 @@ EmitAsmStores(CodeGenFunction &CGF, const AsmStmt &S,
23992399
Tmp = Builder.CreatePtrToInt(
24002400
Tmp, llvm::IntegerType::get(CTX, (unsigned)TmpSize));
24012401
Tmp = Builder.CreateTrunc(Tmp, TruncTy);
2402-
} else if (TruncTy->isIntegerTy()) {
2402+
} else if (Tmp->getType()->isIntegerTy() && TruncTy->isIntegerTy()) {
24032403
Tmp = Builder.CreateZExtOrTrunc(Tmp, TruncTy);
2404-
} else if (TruncTy->isVectorTy()) {
2404+
} else if (Tmp->getType()->isVectorTy() || TruncTy->isVectorTy()) {
24052405
Tmp = Builder.CreateBitCast(Tmp, TruncTy);
24062406
}
24072407
}

‎clang/lib/CodeGen/Targets/X86.cpp

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -40,6 +40,11 @@ static llvm::Type* X86AdjustInlineAsmType(CodeGen::CodeGenFunction &CGF,
4040
return llvm::Type::getX86_MMXTy(CGF.getLLVMContext());
4141
}
4242

43+
if (Constraint == "k") {
44+
llvm::Type *Int1Ty = llvm::Type::getInt1Ty(CGF.getLLVMContext());
45+
return llvm::FixedVectorType::get(Int1Ty, Ty->getScalarSizeInBits());
46+
}
47+
4348
// No operation needed
4449
return Ty;
4550
}

‎clang/test/CodeGen/X86/avx512-kconstraints-att_inline_asm.c

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -41,7 +41,7 @@ __m512i mask_Yk_i64(long long msk, __m512i x, __m512i y){
4141
}
4242

4343
char k_wise_op_i8(char msk_src1,char msk_src2){
44-
//CHECK: i8 asm "kandb\09$2, $1, $0", "=k,k,k,~{dirflag},~{fpsr},~{flags}"(i8 %{{.*}}, i8 %{{.*}})
44+
//CHECK: <8 x i1> asm "kandb\09$2, $1, $0", "=k,k,k,~{dirflag},~{fpsr},~{flags}"(<8 x i1> %{{.*}}, <8 x i1> %{{.*}})
4545
char msk_dst;
4646
asm ("kandb\t%2, %1, %0"
4747
: "=k" (msk_dst)
@@ -50,7 +50,7 @@ char k_wise_op_i8(char msk_src1,char msk_src2){
5050
}
5151

5252
short k_wise_op_i16(short msk_src1, short msk_src2){
53-
//CHECK: i16 asm "kandw\09$2, $1, $0", "=k,k,k,~{dirflag},~{fpsr},~{flags}"(i16 %{{.*}}, i16 %{{.*}})
53+
//CHECK: <16 x i1> asm "kandw\09$2, $1, $0", "=k,k,k,~{dirflag},~{fpsr},~{flags}"(<16 x i1> %{{.*}}, <16 x i1> %{{.*}})
5454
short msk_dst;
5555
asm ("kandw\t%2, %1, %0"
5656
: "=k" (msk_dst)
@@ -59,7 +59,7 @@ short k_wise_op_i16(short msk_src1, short msk_src2){
5959
}
6060

6161
int k_wise_op_i32(int msk_src1, int msk_src2){
62-
//CHECK: i32 asm "kandd\09$2, $1, $0", "=k,k,k,~{dirflag},~{fpsr},~{flags}"(i32 %{{.*}}, i32 %{{.*}})
62+
//CHECK: <32 x i1> asm "kandd\09$2, $1, $0", "=k,k,k,~{dirflag},~{fpsr},~{flags}"(<32 x i1> %{{.*}}, <32 x i1> %{{.*}})
6363
int msk_dst;
6464
asm ("kandd\t%2, %1, %0"
6565
: "=k" (msk_dst)
@@ -68,7 +68,7 @@ int k_wise_op_i32(int msk_src1, int msk_src2){
6868
}
6969

7070
long long k_wise_op_i64(long long msk_src1, long long msk_src2){
71-
//CHECK: i64 asm "kandq\09$2, $1, $0", "=k,k,k,~{dirflag},~{fpsr},~{flags}"(i64 %{{.*}}, i64 %{{.*}})
71+
//CHECK: <64 x i1> asm "kandq\09$2, $1, $0", "=k,k,k,~{dirflag},~{fpsr},~{flags}"(<64 x i1> %{{.*}}, <64 x i1> %{{.*}})
7272
long long msk_dst;
7373
asm ("kandq\t%2, %1, %0"
7474
: "=k" (msk_dst)

‎llvm/lib/Target/X86/X86ISelLowering.cpp

Lines changed: 15 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -57085,17 +57085,17 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
5708557085
// in the normal allocation?
5708657086
case 'k':
5708757087
if (Subtarget.hasAVX512()) {
57088-
if (VT == MVT::i1)
57088+
if (VT == MVT::v1i1 || VT == MVT::i1)
5708957089
return std::make_pair(0U, &X86::VK1RegClass);
57090-
if (VT == MVT::i8)
57090+
if (VT == MVT::v8i1 || VT == MVT::i8)
5709157091
return std::make_pair(0U, &X86::VK8RegClass);
57092-
if (VT == MVT::i16)
57092+
if (VT == MVT::v16i1 || VT == MVT::i16)
5709357093
return std::make_pair(0U, &X86::VK16RegClass);
5709457094
}
5709557095
if (Subtarget.hasBWI()) {
57096-
if (VT == MVT::i32)
57096+
if (VT == MVT::v32i1 || VT == MVT::i32)
5709757097
return std::make_pair(0U, &X86::VK32RegClass);
57098-
if (VT == MVT::i64)
57098+
if (VT == MVT::v64i1 || VT == MVT::i64)
5709957099
return std::make_pair(0U, &X86::VK64RegClass);
5710057100
}
5710157101
break;
@@ -57343,17 +57343,17 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
5734357343
case 'k':
5734457344
// This register class doesn't allocate k0 for masked vector operation.
5734557345
if (Subtarget.hasAVX512()) {
57346-
if (VT == MVT::i1)
57346+
if (VT == MVT::v1i1 || VT == MVT::i1)
5734757347
return std::make_pair(0U, &X86::VK1WMRegClass);
57348-
if (VT == MVT::i8)
57348+
if (VT == MVT::v8i1 || VT == MVT::i8)
5734957349
return std::make_pair(0U, &X86::VK8WMRegClass);
57350-
if (VT == MVT::i16)
57350+
if (VT == MVT::v16i1 || VT == MVT::i16)
5735157351
return std::make_pair(0U, &X86::VK16WMRegClass);
5735257352
}
5735357353
if (Subtarget.hasBWI()) {
57354-
if (VT == MVT::i32)
57354+
if (VT == MVT::v32i1 || VT == MVT::i32)
5735557355
return std::make_pair(0U, &X86::VK32WMRegClass);
57356-
if (VT == MVT::i64)
57356+
if (VT == MVT::v64i1 || VT == MVT::i64)
5735757357
return std::make_pair(0U, &X86::VK64WMRegClass);
5735857358
}
5735957359
break;
@@ -57506,15 +57506,15 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
5750657506
Res.second = nullptr;
5750757507
}
5750857508
} else if (isVKClass(*Class)) {
57509-
if (VT == MVT::i1)
57509+
if (VT == MVT::v1i1 || VT == MVT::i1)
5751057510
Res.second = &X86::VK1RegClass;
57511-
else if (VT == MVT::i8)
57511+
else if (VT == MVT::v8i1 || VT == MVT::i8)
5751257512
Res.second = &X86::VK8RegClass;
57513-
else if (VT == MVT::i16)
57513+
else if (VT == MVT::v16i1 || VT == MVT::i16)
5751457514
Res.second = &X86::VK16RegClass;
57515-
else if (VT == MVT::i32)
57515+
else if (VT == MVT::v32i1 || VT == MVT::i32)
5751657516
Res.second = &X86::VK32RegClass;
57517-
else if (VT == MVT::i64)
57517+
else if (VT == MVT::v64i1 || VT == MVT::i64)
5751857518
Res.second = &X86::VK64RegClass;
5751957519
else {
5752057520
// Type mismatch and not a clobber: Return an error;

‎llvm/test/CodeGen/X86/pr41678.ll

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -20,3 +20,22 @@ entry:
2020
store i16 %0, ptr %b, align 2
2121
ret void
2222
}
23+
24+
define void @b() {
25+
; CHECK-LABEL: b:
26+
; CHECK: # %bb.0: # %entry
27+
; CHECK-NEXT: subl $2, %esp
28+
; CHECK-NEXT: .cfi_def_cfa_offset 6
29+
; CHECK-NEXT: #APP
30+
; CHECK-NEXT: #NO_APP
31+
; CHECK-NEXT: # kill: def $k0 killed $k6
32+
; CHECK-NEXT: kmovw %k6, (%esp)
33+
; CHECK-NEXT: addl $2, %esp
34+
; CHECK-NEXT: .cfi_def_cfa_offset 4
35+
; CHECK-NEXT: retl
36+
entry:
37+
%b = alloca <16 x i1>, align 2
38+
%0 = call <16 x i1> asm "", "={k6},~{dirflag},~{fpsr},~{flags}"() #1
39+
store <16 x i1> %0, ptr %b, align 2
40+
ret void
41+
}

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