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MDevereauMDevereau
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Rebase and use uint8_t for second operand
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8 files changed

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‎clang/include/clang/Basic/arm_sme.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -342,6 +342,6 @@ let TargetGuard = "sme2" in {
342342
// lookup table expand two contiguous registers
343343
//
344344
let TargetGuard = "sme2" in {
345-
def SVLUTI2_LANE_ZT_X2 : Inst<"svluti2_lane_zt_{d}_x2", "2.dmdm", "cUcsUsiUibhf", MergeNone, "aarch64_sme_luti2_lane_zt_x2", [IsStreaming, IsSharedZA, IsPreservesZA], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_7>]>;
346-
def SVLUTI4_LANE_ZT_X2 : Inst<"svluti4_lane_zt_{d}_x2", "2.dmdm", "cUcsUsiUibhf", MergeNone, "aarch64_sme_luti4_lane_zt_x2", [IsStreaming, IsSharedZA, IsPreservesZA], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_3>]>;
345+
def SVLUTI2_LANE_ZT_X2 : Inst<"svluti2_lane_zt_{d}_x2", "2.di[i", "cUcsUsiUibhf", MergeNone, "aarch64_sme_luti2_lane_zt_x2", [IsStreaming, IsSharedZA, IsPreservesZA], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_7>]>;
346+
def SVLUTI4_LANE_ZT_X2 : Inst<"svluti4_lane_zt_{d}_x2", "2.di[i", "cUcsUsiUibhf", MergeNone, "aarch64_sme_luti4_lane_zt_x2", [IsStreaming, IsSharedZA, IsPreservesZA], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_3>]>;
347347
}

‎clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c

Lines changed: 36 additions & 36 deletions
Large diffs are not rendered by default.

‎clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c

Lines changed: 54 additions & 54 deletions
Large diffs are not rendered by default.

‎clang/test/Sema/aarch64-sme2-intrinsics/acle_sme2_imm.cpp

Lines changed: 22 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -78,56 +78,56 @@ void test_svluti4_lane_zt_x4(svuint8_t zn) __arm_streaming __arm_shared_za __arm
7878
svluti4_lane_zt_f32_x4(0, zn, 2); // expected-error {{argument value 2 is outside the valid range [0, 1]}}
7979
}
8080

81-
void test_svluti2_lane_zt_x2(svuint8_t zn_u8, svuint16_t zn_u16, svuint32_t zn_u32, svfloat16_t zn_f16, svbfloat16_t zn_bf16, svfloat32_t zn_f32) __arm_streaming __arm_shared_za __arm_preserves_za {
81+
void test_svluti2_lane_zt_x2(svuint8_t zn_u8) __arm_streaming __arm_shared_za __arm_preserves_za {
8282
// Test Reg Offset
8383
svluti2_lane_zt_u8_x2(1, zn_u8, 2); // expected-error {{argument value 1 is outside the valid range [0, 0]}}
8484
// Test index value range
8585
svluti2_lane_zt_u8_x2(0, zn_u8, 8); // expected-error {{argument value 8 is outside the valid range [0, 7]}}
8686
// Test Reg Offset
87-
svluti2_lane_zt_u16_x2(1, zn_u16, 2); // expected-error {{argument value 1 is outside the valid range [0, 0]}}
87+
svluti2_lane_zt_u16_x2(1, zn_u8, 2); // expected-error {{argument value 1 is outside the valid range [0, 0]}}
8888
// Test index value range
89-
svluti2_lane_zt_u16_x2(0, zn_u16, 8); // expected-error {{argument value 8 is outside the valid range [0, 7]}}
89+
svluti2_lane_zt_u16_x2(0, zn_u8, 8); // expected-error {{argument value 8 is outside the valid range [0, 7]}}
9090
// Test Reg Offset
91-
svluti2_lane_zt_u32_x2(1, zn_u32, 2); // expected-error {{argument value 1 is outside the valid range [0, 0]}}
91+
svluti2_lane_zt_u32_x2(1, zn_u8, 2); // expected-error {{argument value 1 is outside the valid range [0, 0]}}
9292
// Test index value range
93-
svluti2_lane_zt_u32_x2(0, zn_u32, 8); // expected-error {{argument value 8 is outside the valid range [0, 7]}}
93+
svluti2_lane_zt_u32_x2(0, zn_u8, 8); // expected-error {{argument value 8 is outside the valid range [0, 7]}}
9494
// Test Reg Offset
95-
svluti2_lane_zt_f16_x2(1, zn_f16, 2); // expected-error {{argument value 1 is outside the valid range [0, 0]}}
95+
svluti2_lane_zt_f16_x2(1, zn_u8, 2); // expected-error {{argument value 1 is outside the valid range [0, 0]}}
9696
// Test index value range
97-
svluti2_lane_zt_f16_x2(0, zn_f16, 8); // expected-error {{argument value 8 is outside the valid range [0, 7]}}
97+
svluti2_lane_zt_f16_x2(0, zn_u8, 8); // expected-error {{argument value 8 is outside the valid range [0, 7]}}
9898
// Test Reg Offset
99-
svluti2_lane_zt_bf16_x2(1, zn_bf16, 2); // expected-error {{argument value 1 is outside the valid range [0, 0]}}
99+
svluti2_lane_zt_bf16_x2(1, zn_u8, 2); // expected-error {{argument value 1 is outside the valid range [0, 0]}}
100100
// Test index value range
101-
svluti2_lane_zt_bf16_x2(0, zn_bf16, 8); // expected-error {{argument value 8 is outside the valid range [0, 7]}}
101+
svluti2_lane_zt_bf16_x2(0, zn_u8, 8); // expected-error {{argument value 8 is outside the valid range [0, 7]}}
102102
// Test Reg Offset
103-
svluti2_lane_zt_f32_x2(1, zn_f32, 2); // expected-error {{argument value 1 is outside the valid range [0, 0]}}
103+
svluti2_lane_zt_f32_x2(1, zn_u8, 2); // expected-error {{argument value 1 is outside the valid range [0, 0]}}
104104
// Test index value range
105-
svluti2_lane_zt_f32_x2(0, zn_f32, 8); // expected-error {{argument value 8 is outside the valid range [0, 7]}}
105+
svluti2_lane_zt_f32_x2(0, zn_u8, 8); // expected-error {{argument value 8 is outside the valid range [0, 7]}}
106106
}
107107

108-
void test_svluti4_lane_zt_x2(svuint8_t zn_u8, svuint16_t zn_u16, svuint32_t zn_u32, svfloat16_t zn_f16, svbfloat16_t zn_bf16, svfloat32_t zn_f32) __arm_streaming __arm_shared_za __arm_preserves_za {
108+
void test_svluti4_lane_zt_x2(svuint8_t zn_u8) __arm_streaming __arm_shared_za __arm_preserves_za {
109109
// Test Reg Offset
110110
svluti4_lane_zt_u8_x2(1, zn_u8, 2); // expected-error {{argument value 1 is outside the valid range [0, 0]}}
111111
// Test index value range
112112
svluti4_lane_zt_u8_x2(0, zn_u8, 4); // expected-error {{argument value 4 is outside the valid range [0, 3]}}
113113
// Test Reg Offset
114-
svluti4_lane_zt_u16_x2(1, zn_u16, 2); // expected-error {{argument value 1 is outside the valid range [0, 0]}}
114+
svluti4_lane_zt_u16_x2(1, zn_u8, 2); // expected-error {{argument value 1 is outside the valid range [0, 0]}}
115115
// Test index value range
116-
svluti4_lane_zt_u16_x2(0, zn_u16, 4); // expected-error {{argument value 4 is outside the valid range [0, 3]}}
116+
svluti4_lane_zt_u16_x2(0, zn_u8, 4); // expected-error {{argument value 4 is outside the valid range [0, 3]}}
117117
// Test Reg Offset
118-
svluti4_lane_zt_u32_x2(1, zn_u32, 2); // expected-error {{argument value 1 is outside the valid range [0, 0]}}
118+
svluti4_lane_zt_u32_x2(1, zn_u8, 2); // expected-error {{argument value 1 is outside the valid range [0, 0]}}
119119
// Test index value range
120-
svluti4_lane_zt_u32_x2(0, zn_u32, 4); // expected-error {{argument value 4 is outside the valid range [0, 3]}}
120+
svluti4_lane_zt_u32_x2(0, zn_u8, 4); // expected-error {{argument value 4 is outside the valid range [0, 3]}}
121121
// Test Reg Offset
122-
svluti4_lane_zt_f16_x2(1, zn_f16, 2); // expected-error {{argument value 1 is outside the valid range [0, 0]}}
122+
svluti4_lane_zt_f16_x2(1, zn_u8, 2); // expected-error {{argument value 1 is outside the valid range [0, 0]}}
123123
// Test index value range
124-
svluti4_lane_zt_f16_x2(0, zn_f16, 4); // expected-error {{argument value 4 is outside the valid range [0, 3]}}
124+
svluti4_lane_zt_f16_x2(0, zn_u8, 4); // expected-error {{argument value 4 is outside the valid range [0, 3]}}
125125
// Test Reg Offset
126-
svluti4_lane_zt_bf16_x2(1, zn_bf16, 2); // expected-error {{argument value 1 is outside the valid range [0, 0]}}
126+
svluti4_lane_zt_bf16_x2(1, zn_u8, 2); // expected-error {{argument value 1 is outside the valid range [0, 0]}}
127127
// Test index value range
128-
svluti4_lane_zt_bf16_x2(0, zn_bf16, 4); // expected-error {{argument value 4 is outside the valid range [0, 3]}}
128+
svluti4_lane_zt_bf16_x2(0, zn_u8, 4); // expected-error {{argument value 4 is outside the valid range [0, 3]}}
129129
// Test Reg Offset
130-
svluti4_lane_zt_f32_x2(1, zn_f32, 2); // expected-error {{argument value 1 is outside the valid range [0, 0]}}
130+
svluti4_lane_zt_f32_x2(1, zn_u8, 2); // expected-error {{argument value 1 is outside the valid range [0, 0]}}
131131
// Test index value range
132-
svluti4_lane_zt_f32_x2(0, zn_f32, 4); // expected-error {{argument value 4 is outside the valid range [0, 3]}}
132+
svluti4_lane_zt_f32_x2(0, zn_u8, 4); // expected-error {{argument value 4 is outside the valid range [0, 3]}}
133133
}

‎llvm/include/llvm/IR/IntrinsicsAArch64.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3565,10 +3565,10 @@ let TargetPrefix = "aarch64" in {
35653565
// Lookup table expand two registers
35663566
//
35673567
def int_aarch64_sme_luti2_lane_zt_x2
3568-
: DefaultAttrsIntrinsic<[llvm_anyvector_ty, LLVMMatchType<0>], [llvm_i32_ty, LLVMMatchType<0>, llvm_i32_ty],
3568+
: DefaultAttrsIntrinsic<[llvm_anyvector_ty, LLVMMatchType<0>], [llvm_i32_ty, llvm_nxv16i8_ty, llvm_i32_ty],
35693569
[ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>, IntrReadMem]>;
35703570
def int_aarch64_sme_luti4_lane_zt_x2
3571-
: DefaultAttrsIntrinsic<[llvm_anyvector_ty, LLVMMatchType<0>], [llvm_i32_ty, LLVMMatchType<0>, llvm_i32_ty],
3571+
: DefaultAttrsIntrinsic<[llvm_anyvector_ty, LLVMMatchType<0>], [llvm_i32_ty, llvm_nxv16i8_ty, llvm_i32_ty],
35723572
[ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>, IntrReadMem]>;
35733573

35743574
}

‎llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5134,7 +5134,7 @@ void AArch64DAGToDAGISel::Select(SDNode *Node) {
51345134
Node->getValueType(0),
51355135
{AArch64::LUTI4_2ZTZI_B, AArch64::LUTI4_2ZTZI_H,
51365136
AArch64::LUTI4_2ZTZI_S}))
5137-
// Second Immediate must be <= 3:
5137+
// Second Immediate must be <= 3:
51385138
SelectMultiVectorLuti(Node, 2, Opc, 3);
51395139
return;
51405140
}

‎llvm/test/CodeGen/AArch64/sme2-intrinsics-luti2-lane-x2.ll

Lines changed: 17 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -6,60 +6,60 @@
66
define {<vscale x 16 x i8>, <vscale x 16 x i8>} @luti2_i8(<vscale x 16 x i8> %x) {
77
; CHECK-LABEL: luti2_i8:
88
; CHECK: // %bb.0:
9-
; CHECK-NEXT: luti2 { z0.b, z1.b }, zt0, z0[0]
9+
; CHECK-NEXT: luti2 { z0.b, z1.b }, zt0, z0[7]
1010
; CHECK-NEXT: ret
11-
%res = call {<vscale x 16 x i8>, <vscale x 16 x i8>} @llvm.aarch64.sme.luti2.lane.zt.x2.nxv16i8(i32 0, <vscale x 16 x i8> %x, i32 0)
11+
%res = call {<vscale x 16 x i8>, <vscale x 16 x i8>} @llvm.aarch64.sme.luti2.lane.zt.x2.nxv16i8(i32 0, <vscale x 16 x i8> %x, i32 7)
1212
ret {<vscale x 16 x i8>, <vscale x 16 x i8>} %res
1313
}
1414

15-
define {<vscale x 8 x i16>, <vscale x 8 x i16>} @luti2_i16(<vscale x 8 x i16> %x) {
15+
define {<vscale x 8 x i16>, <vscale x 8 x i16>} @luti2_i16(<vscale x 16 x i8> %x) {
1616
; CHECK-LABEL: luti2_i16:
1717
; CHECK: // %bb.0:
1818
; CHECK-NEXT: luti2 { z0.h, z1.h }, zt0, z0[7]
1919
; CHECK-NEXT: ret
20-
%res = call {<vscale x 8 x i16>, <vscale x 8 x i16>} @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8i16(i32 0, <vscale x 8 x i16> %x, i32 7)
20+
%res = call {<vscale x 8 x i16>, <vscale x 8 x i16>} @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8i16(i32 0, <vscale x 16 x i8> %x, i32 7)
2121
ret {<vscale x 8 x i16>, <vscale x 8 x i16>} %res
2222
}
2323

24-
define {<vscale x 4 x i32>, <vscale x 4 x i32>} @luti2_i32(<vscale x 4 x i32> %x) {
24+
define {<vscale x 4 x i32>, <vscale x 4 x i32>} @luti2_i32(<vscale x 16 x i8> %x) {
2525
; CHECK-LABEL: luti2_i32:
2626
; CHECK: // %bb.0:
2727
; CHECK-NEXT: luti2 { z0.s, z1.s }, zt0, z0[7]
2828
; CHECK-NEXT: ret
29-
%res = call {<vscale x 4 x i32>, <vscale x 4 x i32>} @llvm.aarch64.sme.luti2.lane.zt.x2.nxv4i32(i32 0, <vscale x 4 x i32> %x, i32 7)
29+
%res = call {<vscale x 4 x i32>, <vscale x 4 x i32>} @llvm.aarch64.sme.luti2.lane.zt.x2.nxv4i32(i32 0, <vscale x 16 x i8> %x, i32 7)
3030
ret {<vscale x 4 x i32>, <vscale x 4 x i32>} %res
3131
}
3232

33-
define {<vscale x 8 x half>, <vscale x 8 x half>} @luti2_f16(<vscale x 8 x half> %x) {
33+
define {<vscale x 8 x half>, <vscale x 8 x half>} @luti2_f16(<vscale x 16 x i8> %x) {
3434
; CHECK-LABEL: luti2_f16:
3535
; CHECK: // %bb.0:
3636
; CHECK-NEXT: luti2 { z0.h, z1.h }, zt0, z0[7]
3737
; CHECK-NEXT: ret
38-
%res = call {<vscale x 8 x half>, <vscale x 8 x half>} @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8f16(i32 0, <vscale x 8 x half> %x, i32 7)
38+
%res = call {<vscale x 8 x half>, <vscale x 8 x half>} @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8f16(i32 0, <vscale x 16 x i8> %x, i32 7)
3939
ret {<vscale x 8 x half>, <vscale x 8 x half>} %res
4040
}
4141

42-
define {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>} @luti2_bf16(<vscale x 8 x bfloat> %x) {
42+
define {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>} @luti2_bf16(<vscale x 16 x i8> %x) {
4343
; CHECK-LABEL: luti2_bf16:
4444
; CHECK: // %bb.0:
4545
; CHECK-NEXT: luti2 { z0.h, z1.h }, zt0, z0[7]
4646
; CHECK-NEXT: ret
47-
%res = call {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>} @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8bf16(i32 0, <vscale x 8 x bfloat> %x, i32 7)
47+
%res = call {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>} @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8bf16(i32 0, <vscale x 16 x i8> %x, i32 7)
4848
ret {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>} %res
4949
}
5050

51-
define {<vscale x 4 x float>, <vscale x 4 x float>} @luti2_f32(<vscale x 4 x float> %x) {
51+
define {<vscale x 4 x float>, <vscale x 4 x float>} @luti2_f32(<vscale x 16 x i8> %x) {
5252
; CHECK-LABEL: luti2_f32:
5353
; CHECK: // %bb.0:
5454
; CHECK-NEXT: luti2 { z0.s, z1.s }, zt0, z0[7]
5555
; CHECK-NEXT: ret
56-
%res = call {<vscale x 4 x float>, <vscale x 4 x float>} @llvm.aarch64.sme.luti2.lane.zt.x2.nxv4f32(i32 0, <vscale x 4 x float> %x, i32 7)
56+
%res = call {<vscale x 4 x float>, <vscale x 4 x float>} @llvm.aarch64.sme.luti2.lane.zt.x2.nxv4f32(i32 0, <vscale x 16 x i8> %x, i32 7)
5757
ret {<vscale x 4 x float>, <vscale x 4 x float>} %res
5858
}
5959

6060
declare {<vscale x 16 x i8>, <vscale x 16 x i8>} @llvm.aarch64.sme.luti2.lane.zt.x2.nxv16i8(i32, <vscale x 16 x i8>, i32)
61-
declare {<vscale x 8 x i16>, <vscale x 8 x i16>} @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8i16(i32, <vscale x 8 x i16>, i32)
62-
declare {<vscale x 4 x i32>, <vscale x 4 x i32>} @llvm.aarch64.sme.luti2.lane.zt.x2.nxv4i32(i32, <vscale x 4 x i32>, i32)
63-
declare {<vscale x 8 x half>, <vscale x 8 x half>} @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8f16(i32, <vscale x 8 x half>, i32)
64-
declare {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>} @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8bf16(i32, <vscale x 8 x bfloat>, i32)
65-
declare {<vscale x 4 x float>, <vscale x 4 x float>} @llvm.aarch64.sme.luti2.lane.zt.x2.nxv4f32(i32, <vscale x 4 x float>, i32)
61+
declare {<vscale x 8 x i16>, <vscale x 8 x i16>} @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8i16(i32, <vscale x 16 x i8>, i32)
62+
declare {<vscale x 4 x i32>, <vscale x 4 x i32>} @llvm.aarch64.sme.luti2.lane.zt.x2.nxv4i32(i32, <vscale x 16 x i8>, i32)
63+
declare {<vscale x 8 x half>, <vscale x 8 x half>} @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8f16(i32, <vscale x 16 x i8>, i32)
64+
declare {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>} @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8bf16(i32, <vscale x 16 x i8>, i32)
65+
declare {<vscale x 4 x float>, <vscale x 4 x float>} @llvm.aarch64.sme.luti2.lane.zt.x2.nxv4f32(i32, <vscale x 16 x i8>, i32)

‎llvm/test/CodeGen/AArch64/sme2-intrinsics-luti4-lane-x2.ll

Lines changed: 17 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -6,60 +6,60 @@
66
define {<vscale x 16 x i8>, <vscale x 16 x i8>} @luti4_i8(<vscale x 16 x i8> %x) {
77
; CHECK-LABEL: luti4_i8:
88
; CHECK: // %bb.0:
9-
; CHECK-NEXT: luti4 { z0.b, z1.b }, zt0, z0[0]
9+
; CHECK-NEXT: luti4 { z0.b, z1.b }, zt0, z0[3]
1010
; CHECK-NEXT: ret
11-
%res = call {<vscale x 16 x i8>, <vscale x 16 x i8>} @llvm.aarch64.sme.luti4.lane.zt.x2.nxv16i8(i32 0, <vscale x 16 x i8> %x, i32 0)
11+
%res = call {<vscale x 16 x i8>, <vscale x 16 x i8>} @llvm.aarch64.sme.luti4.lane.zt.x2.nxv16i8(i32 0, <vscale x 16 x i8> %x, i32 3)
1212
ret {<vscale x 16 x i8>, <vscale x 16 x i8>} %res
1313
}
1414

15-
define {<vscale x 8 x i16>, <vscale x 8 x i16>} @luti4_i16(<vscale x 8 x i16> %x) {
15+
define {<vscale x 8 x i16>, <vscale x 8 x i16>} @luti4_i16(<vscale x 16 x i8> %x) {
1616
; CHECK-LABEL: luti4_i16:
1717
; CHECK: // %bb.0:
1818
; CHECK-NEXT: luti4 { z0.h, z1.h }, zt0, z0[3]
1919
; CHECK-NEXT: ret
20-
%res = call {<vscale x 8 x i16>, <vscale x 8 x i16>} @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8i16(i32 0, <vscale x 8 x i16> %x, i32 3)
20+
%res = call {<vscale x 8 x i16>, <vscale x 8 x i16>} @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8i16(i32 0, <vscale x 16 x i8> %x, i32 3)
2121
ret {<vscale x 8 x i16>, <vscale x 8 x i16>} %res
2222
}
2323

24-
define {<vscale x 4 x i32>, <vscale x 4 x i32>} @luti4_i32(<vscale x 4 x i32> %x) {
24+
define {<vscale x 4 x i32>, <vscale x 4 x i32>} @luti4_i32(<vscale x 16 x i8> %x) {
2525
; CHECK-LABEL: luti4_i32:
2626
; CHECK: // %bb.0:
2727
; CHECK-NEXT: luti4 { z0.s, z1.s }, zt0, z0[3]
2828
; CHECK-NEXT: ret
29-
%res = call {<vscale x 4 x i32>, <vscale x 4 x i32>} @llvm.aarch64.sme.luti4.lane.zt.x2.nxv4i32(i32 0, <vscale x 4 x i32> %x, i32 3)
29+
%res = call {<vscale x 4 x i32>, <vscale x 4 x i32>} @llvm.aarch64.sme.luti4.lane.zt.x2.nxv4i32(i32 0, <vscale x 16 x i8> %x, i32 3)
3030
ret {<vscale x 4 x i32>, <vscale x 4 x i32>} %res
3131
}
3232

33-
define {<vscale x 8 x half>, <vscale x 8 x half>} @luti4_f16(<vscale x 8 x half> %x) {
33+
define {<vscale x 8 x half>, <vscale x 8 x half>} @luti4_f16(<vscale x 16 x i8> %x) {
3434
; CHECK-LABEL: luti4_f16:
3535
; CHECK: // %bb.0:
3636
; CHECK-NEXT: luti4 { z0.h, z1.h }, zt0, z0[3]
3737
; CHECK-NEXT: ret
38-
%res = call {<vscale x 8 x half>, <vscale x 8 x half>} @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8f16(i32 0, <vscale x 8 x half> %x, i32 3)
38+
%res = call {<vscale x 8 x half>, <vscale x 8 x half>} @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8f16(i32 0, <vscale x 16 x i8> %x, i32 3)
3939
ret {<vscale x 8 x half>, <vscale x 8 x half>} %res
4040
}
4141

42-
define {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>} @luti4_bf16(<vscale x 8 x bfloat> %x) {
42+
define {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>} @luti4_bf16(<vscale x 16 x i8> %x) {
4343
; CHECK-LABEL: luti4_bf16:
4444
; CHECK: // %bb.0:
4545
; CHECK-NEXT: luti4 { z0.h, z1.h }, zt0, z0[3]
4646
; CHECK-NEXT: ret
47-
%res = call {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>} @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8bf16(i32 0, <vscale x 8 x bfloat> %x, i32 3)
47+
%res = call {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>} @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8bf16(i32 0, <vscale x 16 x i8> %x, i32 3)
4848
ret {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>} %res
4949
}
5050

51-
define {<vscale x 4 x float>, <vscale x 4 x float>} @luti4_f32(<vscale x 4 x float> %x) {
51+
define {<vscale x 4 x float>, <vscale x 4 x float>} @luti4_f32(<vscale x 16 x i8> %x) {
5252
; CHECK-LABEL: luti4_f32:
5353
; CHECK: // %bb.0:
5454
; CHECK-NEXT: luti4 { z0.s, z1.s }, zt0, z0[3]
5555
; CHECK-NEXT: ret
56-
%res = call {<vscale x 4 x float>, <vscale x 4 x float>} @llvm.aarch64.sme.luti4.lane.zt.x2.nxv4f32(i32 0, <vscale x 4 x float> %x, i32 3)
56+
%res = call {<vscale x 4 x float>, <vscale x 4 x float>} @llvm.aarch64.sme.luti4.lane.zt.x2.nxv4f32(i32 0, <vscale x 16 x i8> %x, i32 3)
5757
ret {<vscale x 4 x float>, <vscale x 4 x float>} %res
5858
}
5959

6060
declare {<vscale x 16 x i8>, <vscale x 16 x i8>} @llvm.aarch64.sme.luti4.lane.zt.x2.nxv16i8(i32, <vscale x 16 x i8>, i32)
61-
declare {<vscale x 8 x i16>, <vscale x 8 x i16>} @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8i16(i32, <vscale x 8 x i16>, i32)
62-
declare {<vscale x 4 x i32>, <vscale x 4 x i32>} @llvm.aarch64.sme.luti4.lane.zt.x2.nxv4i32(i32, <vscale x 4 x i32>, i32)
63-
declare {<vscale x 8 x half>, <vscale x 8 x half>} @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8f16(i32, <vscale x 8 x half>, i32)
64-
declare {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>} @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8bf16(i32, <vscale x 8 x bfloat>, i32)
65-
declare {<vscale x 4 x float>, <vscale x 4 x float>} @llvm.aarch64.sme.luti4.lane.zt.x2.nxv4f32(i32, <vscale x 4 x float>, i32)
61+
declare {<vscale x 8 x i16>, <vscale x 8 x i16>} @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8i16(i32, <vscale x 16 x i8>, i32)
62+
declare {<vscale x 4 x i32>, <vscale x 4 x i32>} @llvm.aarch64.sme.luti4.lane.zt.x2.nxv4i32(i32, <vscale x 16 x i8>, i32)
63+
declare {<vscale x 8 x half>, <vscale x 8 x half>} @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8f16(i32, <vscale x 16 x i8>, i32)
64+
declare {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>} @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8bf16(i32, <vscale x 16 x i8>, i32)
65+
declare {<vscale x 4 x float>, <vscale x 4 x float>} @llvm.aarch64.sme.luti4.lane.zt.x2.nxv4f32(i32, <vscale x 16 x i8>, i32)

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