do not clamp && merge main

Author: Shoreshen

llvm/lib/Target/AMDGPU/SIInstructions.td

@@ -3306,14 +3306,14 @@ multiclass V_SAT_PK_Pat<Instruction inst> {
     (i16 (conc_lo_u8_i16 (clamp_s16_u8 i16:$lo), (clamp_s16_u8 i16:$hi))),
     (inst
       (V_LSHL_OR_B32_e64 VRegSrc_32:$hi, (S_MOV_B32 (i32 16)),
-      (V_AND_B32_e64 VRegSrc_32:$lo, (S_MOV_B32 (i32 0xFFFF)))))
+      VRegSrc_32:$lo))
   >;
 
   def: GCNPatIgnoreCopies<
     (i16 (conc_lo_u8_i16 (clamp_s16_u8 i16:$lo), (smax i16:$hi, (i16 0)))),
     (inst
       (V_LSHL_OR_B32_e64 VRegSrc_32:$hi, (S_MOV_B32 (i32 16)),
-      (V_AND_B32_e64 VRegSrc_32:$lo, (S_MOV_B32 (i32 0xFFFF)))))
+      VRegSrc_32:$lo))
   >;
 
   def: GCNPatIgnoreCopies<

llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll

@@ -846,9 +846,8 @@ define i16 @basic_smax_smin_bit_or(i16 %src0, i16 %src1) {
 ; SDAG-GFX12-NEXT:    s_wait_samplecnt 0x0
 ; SDAG-GFX12-NEXT:    s_wait_bvhcnt 0x0
 ; SDAG-GFX12-NEXT:    s_wait_kmcnt 0x0
-; SDAG-GFX12-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; SDAG-GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
 ; SDAG-GFX12-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
+; SDAG-GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
 ; SDAG-GFX12-NEXT:    v_sat_pk_u8_i16_e32 v0, v0
 ; SDAG-GFX12-NEXT:    s_setpc_b64 s[30:31]
 ;
@@ -1019,9 +1018,8 @@ define i16 @basic_smax_smin_vec_cast(i16 %src0, i16 %src1) {
 ; SDAG-GFX11-LABEL: basic_smax_smin_vec_cast:
 ; SDAG-GFX11:       ; %bb.0:
 ; SDAG-GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; SDAG-GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
 ; SDAG-GFX11-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
+; SDAG-GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
 ; SDAG-GFX11-NEXT:    v_sat_pk_u8_i16_e32 v0, v0
 ; SDAG-GFX11-NEXT:    s_setpc_b64 s[30:31]
 ;
@@ -1065,9 +1063,8 @@ define i16 @basic_smax_smin_vec_cast(i16 %src0, i16 %src1) {
 ; GISEL-GFX11-LABEL: basic_smax_smin_vec_cast:
 ; GISEL-GFX11:       ; %bb.0:
 ; GISEL-GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GISEL-GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
 ; GISEL-GFX11-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
+; GISEL-GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
 ; GISEL-GFX11-NEXT:    v_sat_pk_u8_i16_e32 v0, v0
 ; GISEL-GFX11-NEXT:    s_setpc_b64 s[30:31]
 ;
@@ -1147,9 +1144,8 @@ define i16 @basic_smax_smin_bit_shl(i16 %src0, i16 %src1) {
 ; SDAG-GFX12-NEXT:    s_wait_samplecnt 0x0
 ; SDAG-GFX12-NEXT:    s_wait_bvhcnt 0x0
 ; SDAG-GFX12-NEXT:    s_wait_kmcnt 0x0
-; SDAG-GFX12-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; SDAG-GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
 ; SDAG-GFX12-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
+; SDAG-GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
 ; SDAG-GFX12-NEXT:    v_sat_pk_u8_i16_e32 v0, v0
 ; SDAG-GFX12-NEXT:    s_setpc_b64 s[30:31]
 ;