[SimplifyCFG] Start redesigning FoldTwoEntryPHINode().

The current `FoldTwoEntryPHINode()` is not quite designed correctly.
It starts from the merge point, and then tries to detect
the 'divergence' point.

Because of that, it is limited to the simple two-predecessor case,
where the PHI completely goes away. but that is rather pessimistic,
and it doesn't make much sense from the costmodel side of things.

For example if there is some other unrelated predecessor of
the merge point,  we could split the merge point so that
the then/else blocks first branch to an empty block
and then to the merge point, and then we'd be able to speculate
the then/else code.

But if we'd instead simply start at the divergence point,
and look for the merge point, then we'll just natively support this case.

There's also the fact that `SpeculativelyExecuteBB()` already does
just that, but only if there is a single block to speculate,
and with a much more restrictive cost model.
But that also means we have code duplication.

Now, sadly, while this is as much NFCI as possible,
there is just no way to cleanly migrate to
the proper implementation. The results *are* going to be different
somewhat because of various phase ordering effects and SimplifyCFG
block iteration strategy.

Author: LebedevRI

llvm/lib/Transforms/Utils/SimplifyCFG.cpp

@@ -2960,6 +2960,81 @@ static bool FoldTwoEntryPHINode(PHINode *PN, const TargetTransformInfo &TTI,
   return true;
 }
 
+static bool SpeculativelyExecuteThenElseCode(BranchInst *BI,
+                                             const TargetTransformInfo &TTI,
+                                             DomTreeUpdater *DTU,
+                                             const DataLayout &DL) {
+  assert(BI->isConditional() && !isa<ConstantInt>(BI->getCondition()) &&
+         BI->getSuccessor(0) != BI->getSuccessor(1) &&
+         "Only for truly conditional branches.");
+  BasicBlock *BB = BI->getParent();
+
+  // Which ones of our successors end up with an unconditional branch?
+  SmallVector<BasicBlock *, 2> UncondSuccessors;
+  SmallVector<BasicBlock *, 2> OtherSuccessors;
+  for (BasicBlock *Succ : successors(BI)) {
+    auto *SuccBI = dyn_cast<BranchInst>(Succ->getTerminator());
+    if (SuccBI && SuccBI->isUnconditional())
+      UncondSuccessors.emplace_back(Succ);
+    else
+      OtherSuccessors.emplace_back(Succ);
+  }
+  assert(UncondSuccessors.size() + OtherSuccessors.size() == 2 &&
+         "Can not have more than two successors!");
+
+  // If none do, then we can't do anything.
+  if (UncondSuccessors.empty())
+    return false;
+
+  // We want to hoist code from the unconditional block[s] and eliminate them,
+  // but if they have their address taken, then we essentially can't do this.
+  for (BasicBlock *UncondSucc : UncondSuccessors)
+    if (UncondSucc->hasAddressTaken())
+      return false;
+
+  // All unconditional successors must have a single (and the same) predecessor.
+  // FIXME: lift this restriction.
+  for (BasicBlock *UncondSucc : UncondSuccessors)
+    if (!UncondSucc->getSinglePredecessor())
+      return false;
+
+  // Now, what is the merge point?
+  BasicBlock *MergeBB = nullptr;
+  // If there was only a single unconditional successor,
+  // then the other successor *must* be the merge point.
+  if (UncondSuccessors.size() == 1)
+    MergeBB = OtherSuccessors.front();
+
+  // All unconditional successors must have the same successor themselves.
+  for (BasicBlock *UncondSucc : UncondSuccessors) {
+    auto *SuccBI = cast<BranchInst>(UncondSucc->getTerminator());
+    assert(SuccBI->isUnconditional() && "Should be an unconditional branch.");
+    BasicBlock *SuccOfSucc = SuccBI->getSuccessor(0);
+    if (!MergeBB) // First unconditional successor, record it's successor.
+      MergeBB = SuccOfSucc;
+    else if (SuccOfSucc != MergeBB) // Do all succs have the same successor?
+      return false;
+  }
+
+  assert(MergeBB && "Should have found the merge point.");
+  assert(all_of(UncondSuccessors,
+                [MergeBB](BasicBlock *UncondSucc) {
+                  return is_contained(predecessors(MergeBB), UncondSucc);
+                }) &&
+         "All unconditional successors must be predecessors of merge block.");
+  assert((UncondSuccessors.size() != 1 ||
+          is_contained(predecessors(MergeBB), BB)) &&
+         "If there is only a single unconditional successor, then the dispatch "
+         "block must also be merge block's predecessor.");
+
+  if (auto *PN = dyn_cast<PHINode>(MergeBB->begin()))
+    // FIXME: lift this restriction.
+    if (PN->getNumIncomingValues() == 2)
+      return FoldTwoEntryPHINode(PN, TTI, DTU, DL);
+
+  return false;
+}
+
 static Value *createLogicalOp(IRBuilderBase &Builder,
                               Instruction::BinaryOps Opc, Value *LHS,
                               Value *RHS, const Twine &Name = "") {
@@ -6521,6 +6596,11 @@ bool SimplifyCFGOpt::simplifyCondBranch(BranchInst *BI, IRBuilder<> &Builder) {
         return requestResimplify();
   }
 
+  if (Options.FoldTwoEntryPHINode) {
+    if (SpeculativelyExecuteThenElseCode(BI, TTI, DTU, DL))
+      return true;
+  }
+
   // If this is a branch on a phi node in the current block, thread control
   // through this block if any PHI node entries are constants.
   if (PHINode *PN = dyn_cast<PHINode>(BI->getCondition()))
@@ -6736,15 +6816,6 @@ bool SimplifyCFGOpt::simplifyOnce(BasicBlock *BB) {
 
   IRBuilder<> Builder(BB);
 
-  if (Options.FoldTwoEntryPHINode) {
-    // If there is a trivial two-entry PHI node in this basic block, and we can
-    // eliminate it, do so now.
-    if (auto *PN = dyn_cast<PHINode>(BB->begin()))
-      if (PN->getNumIncomingValues() == 2)
-        if (FoldTwoEntryPHINode(PN, TTI, DTU, DL))
-          return true;
-  }
-
   Instruction *Terminator = BB->getTerminator();
   Builder.SetInsertPoint(Terminator);
   switch (Terminator->getOpcode()) {

llvm/test/CodeGen/AArch64/check-sign-bit-before-extension.ll

@@ -13,10 +13,12 @@
 define i32 @f_i8_sign_extend_inreg(i8 %in, i32 %a, i32 %b) nounwind {
 ; CHECK-LABEL: f_i8_sign_extend_inreg:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    sxtb w8, w0
-; CHECK-NEXT:    cmp w8, #0
-; CHECK-NEXT:    csel w8, w1, w2, ge
-; CHECK-NEXT:    add w0, w8, w0, uxtb
+; CHECK-NEXT:    and w8, w0, #0xff
+; CHECK-NEXT:    sxtb w9, w0
+; CHECK-NEXT:    add w10, w8, w1
+; CHECK-NEXT:    add w8, w8, w2
+; CHECK-NEXT:    cmp w9, #0
+; CHECK-NEXT:    csel w0, w10, w8, ge
 ; CHECK-NEXT:    ret
 entry:
   %cmp = icmp sgt i8 %in, -1
@@ -35,10 +37,12 @@ B:
 define i32 @f_i16_sign_extend_inreg(i16 %in, i32 %a, i32 %b) nounwind {
 ; CHECK-LABEL: f_i16_sign_extend_inreg:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    sxth w8, w0
-; CHECK-NEXT:    cmp w8, #0
-; CHECK-NEXT:    csel w8, w1, w2, ge
-; CHECK-NEXT:    add w0, w8, w0, uxth
+; CHECK-NEXT:    and w8, w0, #0xffff
+; CHECK-NEXT:    sxth w9, w0
+; CHECK-NEXT:    add w10, w8, w1
+; CHECK-NEXT:    add w8, w8, w2
+; CHECK-NEXT:    cmp w9, #0
+; CHECK-NEXT:    csel w0, w10, w8, ge
 ; CHECK-NEXT:    ret
 entry:
   %cmp = icmp sgt i16 %in, -1
@@ -57,9 +61,11 @@ B:
 define i64 @f_i32_sign_extend_inreg(i32 %in, i64 %a, i64 %b) nounwind {
 ; CHECK-LABEL: f_i32_sign_extend_inreg:
 ; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    mov w8, w0
 ; CHECK-NEXT:    cmp w0, #0
-; CHECK-NEXT:    csel x8, x1, x2, ge
-; CHECK-NEXT:    add x0, x8, w0, uxtw
+; CHECK-NEXT:    add x9, x8, x1
+; CHECK-NEXT:    add x8, x8, x2
+; CHECK-NEXT:    csel x0, x9, x8, ge
 ; CHECK-NEXT:    ret
 entry:
   %cmp = icmp sgt i32 %in, -1
@@ -78,10 +84,12 @@ B:
 define i32 @g_i8_sign_extend_inreg(i8 %in, i32 %a, i32 %b) nounwind {
 ; CHECK-LABEL: g_i8_sign_extend_inreg:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    sxtb w8, w0
-; CHECK-NEXT:    cmp w8, #0
-; CHECK-NEXT:    csel w8, w1, w2, lt
-; CHECK-NEXT:    add w0, w8, w0, uxtb
+; CHECK-NEXT:    and w8, w0, #0xff
+; CHECK-NEXT:    sxtb w9, w0
+; CHECK-NEXT:    add w10, w8, w1
+; CHECK-NEXT:    add w8, w8, w2
+; CHECK-NEXT:    cmp w9, #0
+; CHECK-NEXT:    csel w0, w10, w8, lt
 ; CHECK-NEXT:    ret
 entry:
   %cmp = icmp slt i8 %in, 0
@@ -100,10 +108,12 @@ B:
 define i32 @g_i16_sign_extend_inreg(i16 %in, i32 %a, i32 %b) nounwind {
 ; CHECK-LABEL: g_i16_sign_extend_inreg:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    sxth w8, w0
-; CHECK-NEXT:    cmp w8, #0
-; CHECK-NEXT:    csel w8, w1, w2, lt
-; CHECK-NEXT:    add w0, w8, w0, uxth
+; CHECK-NEXT:    and w8, w0, #0xffff
+; CHECK-NEXT:    sxth w9, w0
+; CHECK-NEXT:    add w10, w8, w1
+; CHECK-NEXT:    add w8, w8, w2
+; CHECK-NEXT:    cmp w9, #0
+; CHECK-NEXT:    csel w0, w10, w8, lt
 ; CHECK-NEXT:    ret
 entry:
   %cmp = icmp slt i16 %in, 0
@@ -122,9 +132,11 @@ B:
 define i64 @g_i32_sign_extend_inreg(i32 %in, i64 %a, i64 %b) nounwind {
 ; CHECK-LABEL: g_i32_sign_extend_inreg:
 ; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    mov w8, w0
 ; CHECK-NEXT:    cmp w0, #0
-; CHECK-NEXT:    csel x8, x1, x2, lt
-; CHECK-NEXT:    add x0, x8, w0, uxtw
+; CHECK-NEXT:    add x9, x8, x1
+; CHECK-NEXT:    add x8, x8, x2
+; CHECK-NEXT:    csel x0, x9, x8, lt
 ; CHECK-NEXT:    ret
 entry:
   %cmp = icmp slt i32 %in, 0
@@ -144,10 +156,12 @@ define i64 @f_i32_sign_extend_i64(i32 %in, i64 %a, i64 %b) nounwind {
 ; CHECK-LABEL: f_i32_sign_extend_i64:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    // kill: def $w0 killed $w0 def $x0
-; CHECK-NEXT:    sxtw x8, w0
-; CHECK-NEXT:    cmp x8, #0
-; CHECK-NEXT:    csel x8, x1, x2, ge
-; CHECK-NEXT:    add x0, x8, w0, uxtw
+; CHECK-NEXT:    mov w8, w0
+; CHECK-NEXT:    sxtw x9, w0
+; CHECK-NEXT:    add x10, x8, x1
+; CHECK-NEXT:    add x8, x8, x2
+; CHECK-NEXT:    cmp x9, #0
+; CHECK-NEXT:    csel x0, x10, x8, ge
 ; CHECK-NEXT:    ret
 entry:
   %inext = sext i32 %in to i64
@@ -168,10 +182,12 @@ define i64 @g_i32_sign_extend_i64(i32 %in, i64 %a, i64 %b) nounwind {
 ; CHECK-LABEL: g_i32_sign_extend_i64:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    // kill: def $w0 killed $w0 def $x0
-; CHECK-NEXT:    sxtw x8, w0
-; CHECK-NEXT:    cmp x8, #0
-; CHECK-NEXT:    csel x8, x1, x2, lt
-; CHECK-NEXT:    add x0, x8, w0, uxtw
+; CHECK-NEXT:    mov w8, w0
+; CHECK-NEXT:    sxtw x9, w0
+; CHECK-NEXT:    add x10, x8, x1
+; CHECK-NEXT:    add x8, x8, x2
+; CHECK-NEXT:    cmp x9, #0
+; CHECK-NEXT:    csel x0, x10, x8, lt
 ; CHECK-NEXT:    ret
 entry:
   %inext = sext i32 %in to i64

llvm/test/CodeGen/AArch64/combine-comparisons-by-cse.ll

@@ -654,7 +654,7 @@ define i32 @fcmpri(i32 %argc, i8** nocapture readonly %argv) {
 ; CHECK-NEXT:    cbz x8, .LBB9_3
 ; CHECK-NEXT:  // %bb.2:
 ; CHECK-NEXT:    mov w0, #3
-; CHECK-NEXT:    b .LBB9_4
+; CHECK-NEXT:    b .LBB9_6
 ; CHECK-NEXT:  .LBB9_3: // %if.end
 ; CHECK-NEXT:    mov w0, #1
 ; CHECK-NEXT:    bl zoo
@@ -666,14 +666,17 @@ define i32 @fcmpri(i32 %argc, i8** nocapture readonly %argv) {
 ; CHECK-NEXT:    cinc w0, w19, gt
 ; CHECK-NEXT:    fmov d8, d0
 ; CHECK-NEXT:    bl xoo
-; CHECK-NEXT:    fmov d0, #-1.00000000
 ; CHECK-NEXT:    fcmp d8, #0.0
+; CHECK-NEXT:    b.gt .LBB9_5
+; CHECK-NEXT:  // %bb.4: // %cond.false12
+; CHECK-NEXT:    fmov d0, #-1.00000000
+; CHECK-NEXT:    fadd d8, d8, d0
+; CHECK-NEXT:  .LBB9_5: // %cond.end14
+; CHECK-NEXT:    fmov d0, d8
 ; CHECK-NEXT:    fmov d1, #-2.00000000
-; CHECK-NEXT:    fadd d0, d8, d0
-; CHECK-NEXT:    fcsel d0, d8, d0, gt
 ; CHECK-NEXT:    bl woo
 ; CHECK-NEXT:    mov w0, #4
-; CHECK-NEXT:  .LBB9_4: // %return
+; CHECK-NEXT:  .LBB9_6: // %return
 ; CHECK-NEXT:    ldp x30, x19, [sp, #16] // 16-byte Folded Reload
 ; CHECK-NEXT:    ldr d8, [sp], #32 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret

llvm/test/CodeGen/AArch64/typepromotion-phisret.ll

@@ -103,12 +103,11 @@ define void @phi_i16() {
 ; CHECK-LABEL: phi_i16:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    mov w8, wzr
-; CHECK-NEXT:    mov w9, #1
 ; CHECK-NEXT:  .LBB2_1: // %loop
 ; CHECK-NEXT:    // =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    add w9, w8, #2
 ; CHECK-NEXT:    cmp w8, #128
-; CHECK-NEXT:    cinc w10, w9, lo
-; CHECK-NEXT:    add w8, w8, w10
+; CHECK-NEXT:    csinc w8, w9, w8, lo
 ; CHECK-NEXT:    cmp w8, #253
 ; CHECK-NEXT:    b.lo .LBB2_1
 ; CHECK-NEXT:  // %bb.2: // %exit
@@ -142,12 +141,11 @@ define i8 @ret_i8() {
 ; CHECK-LABEL: ret_i8:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    mov w0, wzr
-; CHECK-NEXT:    mov w8, #1
 ; CHECK-NEXT:  .LBB3_1: // %loop
 ; CHECK-NEXT:    // =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    add w8, w0, #2
 ; CHECK-NEXT:    cmp w0, #128
-; CHECK-NEXT:    cinc w9, w8, lo
-; CHECK-NEXT:    add w0, w0, w9
+; CHECK-NEXT:    csinc w0, w8, w0, lo
 ; CHECK-NEXT:    cmp w0, #252
 ; CHECK-NEXT:    b.hi .LBB3_1
 ; CHECK-NEXT:  // %bb.2: // %exit
@@ -180,14 +178,13 @@ exit:                                             ; preds = %if.end
 define i16 @phi_multiple_undefs(i16 zeroext %arg) {
 ; CHECK-LABEL: phi_multiple_undefs:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    mov w8, #1
-; CHECK-NEXT:    // implicit-def: $w9
+; CHECK-NEXT:    // implicit-def: $w8
 ; CHECK-NEXT:  .LBB4_1: // %loop
 ; CHECK-NEXT:    // =>This Inner Loop Header: Depth=1
-; CHECK-NEXT:    cmp w9, #128
-; CHECK-NEXT:    cinc w10, w8, lo
-; CHECK-NEXT:    add w9, w9, w10
-; CHECK-NEXT:    cmp w9, #253
+; CHECK-NEXT:    add w9, w8, #2
+; CHECK-NEXT:    cmp w8, #128
+; CHECK-NEXT:    csinc w8, w9, w8, lo
+; CHECK-NEXT:    cmp w8, #253
 ; CHECK-NEXT:    b.lo .LBB4_1
 ; CHECK-NEXT:  // %bb.2: // %exit
 ; CHECK-NEXT:    ret

llvm/test/CodeGen/ARM/ifcvt-callback.ll

@@ -8,11 +8,11 @@
 define i32 @test_ifcvt(i32 %a, i32 %b) #0 {
 ; CHECK-LABEL: test_ifcvt:
 ; CHECK:       @ %bb.0: @ %common.ret
-; CHECK-NEXT:    movs r2, #1
+; CHECK-NEXT:    adds r2, r1, #1
 ; CHECK-NEXT:    cmp r0, #0
 ; CHECK-NEXT:    it eq
-; CHECK-NEXT:    moveq.w r2, #-1
-; CHECK-NEXT:    adds r0, r1, r2
+; CHECK-NEXT:    subeq r2, r1, #1
+; CHECK-NEXT:    mov r0, r2
 ; CHECK-NEXT:    bx lr
   %tmp2 = icmp eq i32 %a, 0
   br i1 %tmp2, label %cond_false, label %cond_true

llvm/test/CodeGen/ARM/ifcvt1.ll

@@ -5,18 +5,18 @@
 define i32 @t1(i32 %a, i32 %b) {
 ; A8-LABEL: t1:
 ; A8:       @ %bb.0: @ %common.ret
-; A8-NEXT:    mov r2, #1
+; A8-NEXT:    add r2, r1, #1
 ; A8-NEXT:    cmp r0, #0
-; A8-NEXT:    mvneq r2, #0
-; A8-NEXT:    add r0, r1, r2
+; A8-NEXT:    subeq r2, r1, #1
+; A8-NEXT:    mov r0, r2
 ; A8-NEXT:    bx lr
 ;
 ; SWIFT-LABEL: t1:
 ; SWIFT:       @ %bb.0: @ %common.ret
-; SWIFT-NEXT:    mov r2, #1
+; SWIFT-NEXT:    add r2, r1, #1
 ; SWIFT-NEXT:    cmp r0, #0
-; SWIFT-NEXT:    mvneq r2, #0
-; SWIFT-NEXT:    add r0, r1, r2
+; SWIFT-NEXT:    subeq r2, r1, #1
+; SWIFT-NEXT:    mov r0, r2
 ; SWIFT-NEXT:    bx lr
 	%tmp2 = icmp eq i32 %a, 0
 	br i1 %tmp2, label %cond_false, label %cond_true