Skip to content

Commit 06a8d18

Browse files
committed
Fix code to make generated CIR consistent on different OS
1 parent b911c20 commit 06a8d18

File tree

2 files changed

+5
-5
lines changed

2 files changed

+5
-5
lines changed

clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2274,9 +2274,9 @@ static void vecExtendIntValue(CIRGenFunction &cgf, cir::VectorType argVTy,
22742274
// The constant argument to an _n_ intrinsic always has Int32Ty, so truncate
22752275
// it before inserting.
22762276
arg = builder.createIntCast(arg, eltTy);
2277+
mlir::Value zero = builder.getConstInt(loc, cgf.SizeTy, 0);
22772278
arg = builder.create<cir::VecInsertOp>(
2278-
loc, builder.create<cir::PoisonOp>(loc, argVTy), arg,
2279-
builder.getConstInt(loc, cgf.SizeTy, 0));
2279+
loc, builder.create<cir::PoisonOp>(loc, argVTy), arg, zero);
22802280
}
22812281

22822282
/// Reduce vector type value to scalar, usually for result of a

clang/test/CIR/CodeGen/AArch64/neon.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -14616,9 +14616,9 @@ int16_t test_vqmovns_s32(int32_t a) {
1461614616

1461714617
// CIR-LABEL: vqmovns_s32
1461814618
// CIR: [[A:%.*]] = cir.load {{.*}} : !cir.ptr<!s32i>, !s32i
14619-
// CIR-NEXT: [[POISON:%.*]] = cir.poison : !cir.vector<!s32i x 4>
14620-
// CIR-NEXT: [[VQMOVNS_S32_ZERO1:%.*]] = cir.const #cir.int<0> : !u64i
14621-
// CIR-NEXT: [[TMP0:%.*]] = cir.vec.insert [[A]], [[POISON]][[[VQMOVNS_S32_ZERO1]] : !u64i] : !cir.vector<!s32i x 4>
14619+
// CIR: [[VQMOVNS_S32_ZERO1:%.*]] = cir.const #cir.int<0> : !u64i
14620+
// CIR: [[POISON:%.*]] = cir.poison : !cir.vector<!s32i x 4>
14621+
// CIR: [[TMP0:%.*]] = cir.vec.insert [[A]], [[POISON]][[[VQMOVNS_S32_ZERO1]] : !u64i] : !cir.vector<!s32i x 4>
1462214622
// CIR: [[VQMOVNS_S32_I:%.*]] = cir.llvm.intrinsic "aarch64.neon.sqxtn" [[TMP0]] : (!cir.vector<!s32i x 4>) -> !cir.vector<!s16i x 4>
1462314623
// CIR: [[VQMOVNS_S32_ZERO2:%.*]] = cir.const #cir.int<0> : !u64i
1462414624
// CIR: [[TMP1:%.*]] = cir.vec.extract [[VQMOVNS_S32_I]][[[VQMOVNS_S32_ZERO2]] : !u64i] : !cir.vector<!s16i x 4> loc(#loc4503)

0 commit comments

Comments
 (0)