chore: restore tests

Author: luisacicolini

test/Conversion/ImportVerilog/basic.sv

@@ -3254,10 +3254,10 @@ function void StructCreateConversion (logic [7:0][7:0] array, logic [63:0] immed
    } testStruct;
 
     // CHECK: [[TS:%.+]] = moore.struct_create [[IMM]] : !moore.l64 -> struct<{structField: l64}>
-   testStruct ts = '{structField: immediate};
+   automatic testStruct ts = '{structField: immediate};
     // CHECK: [[CAST:%.+]] = moore.packed_to_sbv [[ARRAY]] : array<8 x l8>
     // CHECK-NEXT: [[TS2:%.+]] = moore.struct_create [[CAST]] : !moore.l64 -> struct<{structField: l64}>
-   testStruct ts2 = '{structField: array};
+   automatic testStruct ts2 = '{structField: array};
 
 endfunction
 
@@ -3845,3 +3845,7 @@ module implicitCastsFunctionArguments;
     fn(q, r);
   end
 endmodule
+
+// CHECK-LABEL: moore.module @ProgramsAreMostlyModules
+program ProgramsAreMostlyModules;
+endprogram

test/Conversion/MooreToCore/basic.mlir

@@ -1412,4 +1412,12 @@ func.func @RealToIntLowering(%arg0: !moore.f32, %arg1: !moore.f64) {
   %0 = moore.real_to_int %arg0 : f32 -> i42
   %1 = moore.real_to_int %arg1 : f64 -> i42
   return
-}
+}
+
+// CHECK-LABEL: func.func @CurrentTime
+func.func @CurrentTime() -> !moore.time {
+  // CHECK-NEXT: [[TMP:%.+]] = llhd.current_time
+  %0 = moore.builtin.time
+  // CHECK-NEXT: return [[TMP]] : !llhd.time
+  return %0 : !moore.time
+}

test/Dialect/FIRRTL/errors.mlir

@@ -3043,6 +3043,17 @@ firrtl.circuit "DomainInfoNotArray" {
 
 // -----
 
+firrtl.circuit "DomainInfoWrongSize" {
+  firrtl.domain @ClockDomain
+  // expected-error @below {{requires 2 port domains, but has 1}}
+  firrtl.module @WrongDomainPortInfo(
+    in %A: !firrtl.domain of @ClockDomain,
+    in %a: !firrtl.uint<1>
+  ) attributes {domainInfo = [@ClockDomain]} {}
+}
+
+// -----
+
 firrtl.circuit "WrongDomainPortInfo" {
   firrtl.domain @ClockDomain
   // expected-error @below {{domain information for domain port 'A' must be a 'FlatSymbolRefAttr'}}
@@ -3053,16 +3064,46 @@ firrtl.circuit "WrongDomainPortInfo" {
 
 // -----
 
-firrtl.circuit "WrongNonDomainPortInfo" {
+firrtl.circuit "WrongNonDomainPortInfoType" {
+  firrtl.domain @ClockDomain
+  // expected-error @below {{domain information for non-domain port 'a' must be an 'ArrayAttr'}}
+  firrtl.module @WrongNonDomainPortInfoType(
+    in %a: !firrtl.uint<1>
+  ) attributes {domainInfo = ["hello"]} {}
+}
+
+// -----
+
+firrtl.circuit "WrongNonDomainPortInfoElementType" {
   firrtl.domain @ClockDomain
   // expected-error @below {{domain information for non-domain port 'a' must be an 'ArrayAttr<IntegerAttr>'}}
-  firrtl.module @WrongNonDomainPortInfo(
+  firrtl.module @WrongNonDomainPortInfoElementType(
     in %a: !firrtl.uint<1>
   ) attributes {domainInfo = [["hello"]]} {}
 }
 
 // -----
 
+firrtl.circuit "DomainAssociationOOB" {
+  firrtl.domain @ClockDomain
+  // expected-error @below {{has domain association 1 for port 'a', but the module only has 1 ports}}
+  firrtl.module @DomainAssociationOOB(
+    in %a: !firrtl.uint<1>
+  ) attributes {domainInfo = [[1 : i32]]} {}
+}
+
+// -----
+
+firrtl.circuit "DomainAssociationOOB" {
+  firrtl.domain @ClockDomain
+  // expected-error @below {{has port 'a' which has a domain association with non-domain port 'a'}}
+  firrtl.module @DomainAssociationOOB(
+    in %a: !firrtl.uint<1>
+  ) attributes {domainInfo = [[0 : i32]]} {}
+}
+
+// -----
+
 // Output domain ports on modules can only be driven once.
 
 firrtl.circuit "Top" {

test/Dialect/FIRRTL/infer-widths.mlir

@@ -435,8 +435,15 @@ firrtl.circuit "Foo" {
     firrtl.connect %ui, %c0_ui5 : !firrtl.uint, !firrtl.uint<5>
   }
 
+  firrtl.domain @ClockDomain
+
   // CHECK-LABEL: @TransparentOps
-  firrtl.module @TransparentOps(in %clk: !firrtl.clock, in %a: !firrtl.uint<1>) {
+  firrtl.module @TransparentOps(
+    in %clk: !firrtl.clock,
+    in %a: !firrtl.uint<1>,
+    in %A: !firrtl.domain of @ClockDomain,
+    out %B: !firrtl.domain of @ClockDomain
+  ) {
     %false = firrtl.constant 0 : !firrtl.uint<1>
     %true = firrtl.constant 1 : !firrtl.uint<1>
     %c0_ui4 = firrtl.constant 0 : !firrtl.uint<4>
@@ -457,6 +464,7 @@ firrtl.circuit "Foo" {
     firrtl.assume %clk, %true, %true, "foo" : !firrtl.clock, !firrtl.uint<1>, !firrtl.uint<1>
     firrtl.int.unclocked_assume %true, %true, "foo" : !firrtl.uint<1>, !firrtl.uint<1>
     firrtl.cover %clk, %true, %true, "foo" : !firrtl.clock, !firrtl.uint<1>, !firrtl.uint<1>
+    firrtl.domain.define %B, %A
   }
 
   // Issue #1088
@@ -859,7 +867,7 @@ firrtl.circuit "Foo" {
 
     %c0_ui2 = firrtl.constant 0 : !firrtl.uint<2>
     firrtl.connect %w, %c0_ui2 : !firrtl.uint, !firrtl.uint<2>
-    
+
     %bov_a = firrtl.subfield %bov[a] : !firrtl.bundle<a: vector<uint, 2>, b flip: uint>
     %bov_a_1 = firrtl.subindex %bov_a[1] : !firrtl.vector<uint, 2>
     %bov_b = firrtl.subfield %bov[b] : !firrtl.bundle<a: vector<uint, 2>, b flip: uint>
@@ -914,7 +922,7 @@ firrtl.circuit "Foo" {
     %0 = firrtl.subfield %invalid[a] : !firrtl.bundle<a: vector<uint, 2>>
     %1 = firrtl.subindex %0[0] : !firrtl.vector<uint, 2>
   }
-  
+
   // CHECK-LABEL: @InferConst
   // CHECK-SAME: out %out: !firrtl.const.bundle<a: uint<1>, b: sint<2>, c: analog<3>, d: vector<uint<4>, 2>>
   firrtl.module @InferConst(in %a: !firrtl.const.uint<1>, in %b: !firrtl.const.sint<2>, in %c: !firrtl.const.analog<3>, in %d: !firrtl.const.vector<uint<4>, 2>,
@@ -929,7 +937,7 @@ firrtl.circuit "Foo" {
     firrtl.attach %2, %c : !firrtl.const.analog, !firrtl.const.analog<3>
     firrtl.connect %3, %d : !firrtl.const.vector<uint, 2>, !firrtl.const.vector<uint<4>, 2>
   }
-  
+
   // Should not crash when encountering property types.
   // CHECK: firrtl.module @Property(in %a: !firrtl.string)
   firrtl.module @Property(in %a: !firrtl.string) { }

test/Dialect/LLHD/IR/basic.mlir

@@ -197,3 +197,10 @@ hw.module @CombinationalProcess(in %arg0: i1, in %arg1: i42, in %arg2: i9001, in
     llhd.yield %1, %2 : i42, i9001
   }
 }
+
+// CHECK-LABEL: @CurrentTime
+func.func @CurrentTime() -> !llhd.time {
+  // CHECK: llhd.current_time
+  %0 = llhd.current_time
+  return %0 : !llhd.time
+}