[FIRRTL] Copy domain info in LowerOpenAggs

Fix an oversight in the `LowerOpenAggs` pass where it was not copying
domain information to lowered bundles.

Signed-off-by: Schuyler Eldridge <[email protected]>

Author: seldridge

lib/Dialect/FIRRTL/Transforms/LowerOpenAggs.cpp

@@ -306,7 +306,7 @@ LogicalResult Visitor::visit(FModuleLike mod) {
           auto orientation =
               (Direction)((unsigned)port.direction ^ field.isFlip);
           PortInfo pi(name, field.type, orientation, /*symName=*/StringAttr{},
-                      port.loc, std::nullopt);
+                      port.loc, std::nullopt, port.domains);
           newPorts.emplace_back(idxOfInsertPoint, pi);
         }
         return success();

test/Dialect/FIRRTL/lower-open-aggs.mlir

@@ -324,3 +324,19 @@ firrtl.circuit "NonHWWiresHaveDroppableNames" {
     %w = firrtl.wire interesting_name : !firrtl.openbundle<a: uint<1>, b: probe<uint<1>>>
   }
 }
+
+// -----
+
+// CHECK-LABEL: circuit "DomainInfo"
+firrtl.circuit "DomainInfo" {
+  firrtl.domain @ClockDomain
+  // CHECK:      firrtl.module @DomainInfo
+  // CHECK-SAME:   out %a: !firrtl.bundle<b: uint<1>> domains [%A]
+  // CHECK-SAME:   out %a_c: !firrtl.probe<uint<1>> domains [%A]
+  // CHECK-SAME:   in %A: !firrtl.domain of @ClockDomain
+  firrtl.module @DomainInfo(
+    out %a: !firrtl.openbundle<b: uint<1>, c: probe<uint<1>>> domains [%A],
+    in %A: !firrtl.domain of @ClockDomain
+  ) {
+  }
+}