enabled best effort lowering in circt verilog

Author: Kavya Chopra

lib/Conversion/ImportVerilog/ImportVerilog.cpp

@@ -484,7 +484,7 @@ void circt::populateLlhdToCorePipeline(
 
   // Convert `arith.select` generated by some of the control flow canonicalizers
   // to `comb.mux`.
-  modulePM.addPass(createMapArithToCombPass());
+  modulePM.addPass(createMapArithToCombPass(true));
 
   // Simplify module-level signals.
   modulePM.addPass(llhd::createCombineDrivesPass());