@@ -95,14 +95,6 @@ CHECK(sha2, {
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: : : "v0"
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);
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})
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- CHECK (sha1 , {
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- asm volatile (
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- "fmov s0, #0" "\n"
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- // FIXME: sha1h is under +sha2 in clang, and +sha1 doesn't exist yet.
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- ".inst 0x5e280800" "\n" // sha1h s0, s0
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- : : : "v0"
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- );
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- })
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CHECK (aes , {
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asm volatile (
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"fmov d0, #0" "\n"
@@ -111,13 +103,6 @@ CHECK(aes, {
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: : : "v0"
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);
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})
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- CHECK (pmull , {
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- asm volatile (
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- "fmov d0, #0" "\n"
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- "pmull v0.1q, v0.1d, v0.1d" "\n"
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- : : : "v0"
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- );
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- })
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CHECK (rcpc , {
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int x ;
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asm volatile (
@@ -174,46 +159,12 @@ CHECK(i8mm, {
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: : : "v0"
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);
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})
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- CHECK (dit , {
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- asm volatile (
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- "msr DIT, x0"
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- : : : "x0"
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- );
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- })
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CHECK (fp16 , {
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asm volatile (
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"fmov h0, #0"
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: : : "v0"
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);
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})
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- CHECK (ssbs2 , {
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- asm volatile (
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- "mrs x0, SSBS" "\n"
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- "msr SSBS, x0" "\n"
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- : : : "x0"
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- );
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- })
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- CHECK (bti , {
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- // The only test for this requires reading a register that is only
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- // accessible to EL1.
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- #ifdef __linux__
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- // On linux, the kernel intercepts the trap, and emulates it for EL0 processes.
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- int val = 0 ;
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- asm volatile ("mrs %0, ID_AA64PFR1_EL1" : "=r" (val ));
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- // ID_AA64PFR1_EL1.BT, bits [3:0] = 0b0001 if Branch Target Identification
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- // mechanism implemented.
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- if ((val & 0xF ) != 0x1 )
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- return false;
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- #elif defined(__APPLE__ )
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- // On Apple platforms, we need to check a sysctl.
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- int32_t val = 0 ;
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- size_t size = sizeof (val );
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- if (sysctlbyname ("hw.optional.arm.FEAT_BTI" , & val , & size , NULL , 0 ) || val != 1 )
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- return false;
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- #else
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- // TODO: implement me on your platform to fix this test!
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- #endif
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- })
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CHECK (simd , {
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asm volatile (
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"mov v0.B[0], w0"
@@ -263,9 +214,7 @@ int main(int, const char **) {
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check_rdm ();
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check_lse ();
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check_sha2 ();
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- check_sha1 ();
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check_aes ();
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- check_pmull ();
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check_rcpc ();
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check_rcpc2 ();
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check_fcma ();
@@ -274,10 +223,7 @@ int main(int, const char **) {
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check_dpb2 ();
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check_bf16 ();
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check_i8mm ();
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- check_dit ();
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check_fp16 ();
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- check_ssbs2 ();
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- check_bti ();
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check_simd ();
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check_fp ();
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check_crc ();
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