spi: spi-cadence-quadspi: Remove dependency on SRAM Fill Register during indirect non-dma read

After reading the SRAM, the SRAM fill level of the SRAM Indirect Read
partition should decrement. However, in indirect non-DMA reads, after the
driver reads the SRAM, the SRAM fill level of the SRAM Indirect Read
partition is not updating. Consequently, the driver performs an extra SRAM
read when there is no data in SRAM, leading to a kernel crash.

Call trace:
Kernel panic - not syncing: Asynchronous SError Interrupt
CPU: 1 PID: 366 Comm: insmod Not tainted 6.6.0-g90a952a27096-dirty torvalds#111
Hardware name: Xilinx Versal vmk180 Eval board revA (OSPI) (DT)
dump_backtrace+0x94/0xec
show_stack+0x18/0x24
dump_stack_lvl+0x48/0x60
dump_stack+0x18/0x24
panic+0x30c/0x36c
nmi_panic+0x8c/0x90
arm64_serror_panic+0x6c/0x78
do_serror+0x28/0x70
el1h_64_error_handler+0x30/0x48
el1h_64_error+0x64/0x68
cqspi_indirect_read_execute+0x68/0x434
cqspi_versal_indirect_read_dma+0xa0/0x420
cqspi_exec_mem_op+0xcd4/0xf88
spi_mem_exec_op+0x3c8/0x41c
spi_mem_no_dirmap_read+0x98/0xb0
spi_mem_dirmap_read+0xd4/0x13c
spi_nor_read_data+0x10c/0x178
spi_nor_read+0x1a0/0x5f8
mtd_read_oob_std+0x7c/0x88
mtd_read_oob+0x8c/0x14c
mtd_read+0x64/0xa0
mtdtest_read+0x3c/0xac [mtd_stresstest]
mtd_stresstest_init+0x2a8/0x1000 [mtd_stresstest]

The SRAM Fill Register is not updating as expected it shows a non-zero
value when there is no more data in the SRAM to be read. Occurrence of
these failure scenarios are random in nature. it appears to be an IP issue
that requires discussion with the IP team for a proper fix. As a software
workaround updated the indirect non-DMA read to not depend on the SRAM fill
register value and fifo_depth when decrementing the bytes_to_read variable
after reading the SRAM, used the bytes_read variable instead.

Fixes: 1406234 ("mtd: spi-nor: Add driver for Cadence Quad SPI Flash Controller")
Signed-off-by: Amit Kumar Mahapatra <[email protected]>
Reviewed-by: Radhey Shyam Pandey <[email protected]>
State: not-upstreamable

Author: Amit Kumar Mahapatra

drivers/spi/spi-cadence-quadspi.c

@@ -349,14 +349,6 @@ static bool cqspi_is_idle(struct cqspi_st *cqspi)
 	return reg & (1UL << CQSPI_REG_CONFIG_IDLE_LSB);
 }
 
-static u32 cqspi_get_rd_sram_level(struct cqspi_st *cqspi)
-{
-	u32 reg = readl(cqspi->iobase + CQSPI_REG_SDRAMLEVEL);
-
-	reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB;
-	return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK;
-}
-
 static u32 cqspi_get_versal_dma_status(struct cqspi_st *cqspi)
 {
 	u32 dma_status;
@@ -1131,8 +1123,7 @@ static int cqspi_indirect_read_execute(struct cqspi_flash_pdata *f_pdata,
 			rxbuf += bytes_read;
 			remaining -= bytes_read;
 			req_bytes -= bytes_read;
-			bytes_to_read = cqspi_get_rd_sram_level(cqspi);
-			bytes_to_read *= cqspi->fifo_width;
+			bytes_to_read -= bytes_read;
 		}
 
 		if (remaining > 0) {