diff --git a/ChangeLog b/ChangeLog index 6ef875812c635..3dd1ce544af2b 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,3 +1,76 @@ +2015-06-23 Release Manager + + * GCC 4.8.5 released. + +2015-05-03 Matthias Klose + + * configure.ac: Match $host configured with triplets. + * configure: Regenerate. + +2014-12-19 Release Manager + + * GCC 4.8.4 released. + +2014-12-08 Richard Biener + + Backport from 4.9 branch + 2014-12-04 Tobias Burnus + + * configure.ac: Permit also ISL 0.14 with CLooG. + * Makefile.def: Make more dependent on mpfr, mpc, isl, and cloog. + * Makefile.in: Regenerate. + * configure: Regenerate. + +2014-07-26 Uros Bizjak + + PR target/47230 + * configure.ac (alpha*-*-linux*): Use mh-alpha-linux. + * configure: Regenerate. + +2014-05-22 Release Manager + + * GCC 4.8.3 released. + +2014-04-04 Bill Schmidt + + Backport from mainline + 2013-11-15 Ulrich Weigand + + * libtool.m4: Update to mainline version. + * configure: Regenerate. + +2014-04-04 Bill Schmidt + + Backport from mainline r203071: + + 2013-10-01 Joern Rennecke + + Import from savannah.gnu.org: + * config.guess: Update to 2013-06-10 version. + * config.sub: Update to 2013-10-01 version. + +2013-10-16 Release Manager + + * GCC 4.8.2 released. + +2013-09-03 Richard Biener + + * configure.ac: Also allow ISL 0.12. + * configure: Regenerated. + +2013-05-31 Release Manager + + * GCC 4.8.1 released. + +2013-03-30 Matthias Klose + + * Makefile.def (target_modules): Don't install libffi. + * Makefile.in: Regenerate. + +2013-03-22 Release Manager + + * GCC 4.8.0 released. + 2013-02-20 Andrew Sutton * MAINTAINERS (Write After Approval): Add myself. diff --git a/Makefile.def b/Makefile.def index 1af7460d242c0..b1e35e325e843 100644 --- a/Makefile.def +++ b/Makefile.def @@ -138,7 +138,7 @@ target_modules = { module= libtermcap; no_check=true; missing=maintainer-clean; }; target_modules = { module= winsup; }; target_modules = { module= libgloss; no_check=true; }; -target_modules = { module= libffi; }; +target_modules = { module= libffi; no_install=true; }; target_modules = { module= libjava; raw_cxx=true; extra_configure_flags="$(EXTRA_CONFIGARGS_LIBJAVA)"; }; target_modules = { module= zlib; }; @@ -292,6 +292,10 @@ dependencies = { module=all-build-fixincludes; on=all-build-libiberty; }; // Host modules specific to gcc. dependencies = { module=configure-gcc; on=configure-intl; }; dependencies = { module=configure-gcc; on=all-gmp; }; +dependencies = { module=configure-gcc; on=all-mpfr; }; +dependencies = { module=configure-gcc; on=all-mpc; }; +dependencies = { module=configure-gcc; on=all-isl; }; +dependencies = { module=configure-gcc; on=all-cloog; }; dependencies = { module=configure-gcc; on=all-lto-plugin; }; dependencies = { module=configure-gcc; on=all-binutils; }; dependencies = { module=configure-gcc; on=all-gas; }; diff --git a/Makefile.in b/Makefile.in index 08049deb96d0c..30a15efca14e5 100644 --- a/Makefile.in +++ b/Makefile.in @@ -38710,13 +38710,8 @@ maybe-install-target-libffi: @if target-libffi maybe-install-target-libffi: install-target-libffi -install-target-libffi: installdirs - @: $(MAKE); $(unstage) - @r=`${PWD_COMMAND}`; export r; \ - s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \ - $(NORMAL_TARGET_EXPORTS) \ - (cd $(TARGET_SUBDIR)/libffi && \ - $(MAKE) $(TARGET_FLAGS_TO_PASS) install) +# Dummy target for uninstallable. +install-target-libffi: @endif target-libffi @@ -38725,13 +38720,8 @@ maybe-install-strip-target-libffi: @if target-libffi maybe-install-strip-target-libffi: install-strip-target-libffi -install-strip-target-libffi: installdirs - @: $(MAKE); $(unstage) - @r=`${PWD_COMMAND}`; export r; \ - s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \ - $(NORMAL_TARGET_EXPORTS) \ - (cd $(TARGET_SUBDIR)/libffi && \ - $(MAKE) $(TARGET_FLAGS_TO_PASS) install-strip) +# Dummy target for uninstallable. +install-strip-target-libffi: @endif target-libffi @@ -45493,6 +45483,38 @@ configure-stage3-gcc: maybe-all-stage3-gmp configure-stage4-gcc: maybe-all-stage4-gmp configure-stageprofile-gcc: maybe-all-stageprofile-gmp configure-stagefeedback-gcc: maybe-all-stagefeedback-gmp +configure-gcc: maybe-all-mpfr + +configure-stage1-gcc: maybe-all-stage1-mpfr +configure-stage2-gcc: maybe-all-stage2-mpfr +configure-stage3-gcc: maybe-all-stage3-mpfr +configure-stage4-gcc: maybe-all-stage4-mpfr +configure-stageprofile-gcc: maybe-all-stageprofile-mpfr +configure-stagefeedback-gcc: maybe-all-stagefeedback-mpfr +configure-gcc: maybe-all-mpc + +configure-stage1-gcc: maybe-all-stage1-mpc +configure-stage2-gcc: maybe-all-stage2-mpc +configure-stage3-gcc: maybe-all-stage3-mpc +configure-stage4-gcc: maybe-all-stage4-mpc +configure-stageprofile-gcc: maybe-all-stageprofile-mpc +configure-stagefeedback-gcc: maybe-all-stagefeedback-mpc +configure-gcc: maybe-all-isl + +configure-stage1-gcc: maybe-all-stage1-isl +configure-stage2-gcc: maybe-all-stage2-isl +configure-stage3-gcc: maybe-all-stage3-isl +configure-stage4-gcc: maybe-all-stage4-isl +configure-stageprofile-gcc: maybe-all-stageprofile-isl +configure-stagefeedback-gcc: maybe-all-stagefeedback-isl +configure-gcc: maybe-all-cloog + +configure-stage1-gcc: maybe-all-stage1-cloog +configure-stage2-gcc: maybe-all-stage2-cloog +configure-stage3-gcc: maybe-all-stage3-cloog +configure-stage4-gcc: maybe-all-stage4-cloog +configure-stageprofile-gcc: maybe-all-stageprofile-cloog +configure-stagefeedback-gcc: maybe-all-stagefeedback-cloog configure-gcc: maybe-all-lto-plugin configure-stage1-gcc: maybe-all-stage1-lto-plugin diff --git a/boehm-gc/ChangeLog b/boehm-gc/ChangeLog index be2a484249d04..475c3990ac25f 100644 --- a/boehm-gc/ChangeLog +++ b/boehm-gc/ChangeLog @@ -1,3 +1,54 @@ +2015-06-23 Release Manager + + * GCC 4.8.5 released. + +2014-12-19 Release Manager + + * GCC 4.8.4 released. + +2014-05-22 Release Manager + + * GCC 4.8.3 released. + +2014-04-04 Bill Schmidt + + Backport from mainline + 2013-11-15 Ulrich Weigand + + * configure: Regenerate. + +2013-12-29 Andreas Tobler + + Merge from trunk: + * include/private/gcconfig.h: Add FreeBSD powerpc64 defines. + +2013-10-16 Release Manager + + * GCC 4.8.2 released. + +2013-09-04 Matthias Klose + + * Makefile.am (libgcjgc_la_LIBADD): Add EXTRA_TEST_LIBS. + * Makefile.in: Regenerate. + +2013-05-31 Release Manager + + * GCC 4.8.1 released. + +2013-03-22 Jakub Jelinek + + PR other/43620 + * Makefile.am (AUTOMAKE_OPTIONS): Add no-dist. + * include/Makefile.am (AUTOMAKE_OPTIONS): Add no-dist. + * testsuite/Makefile.am (AUTOMAKE_OPTIONS): Add no-dist. + * Makefile.in: Regenerated. + * include/Makefile.in: Regenerated. + * testsuite/Makefile.in: Regenerated. + +2013-03-22 Release Manager + + * GCC 4.8.0 released. + 2013-03-06 Rainer Orth * os_dep.c [SOLARIS_STACKBOTTOM] (GC_solaris_stack_base): New diff --git a/boehm-gc/Makefile.am b/boehm-gc/Makefile.am index 2b68938e18d38..fa187ef31ee24 100644 --- a/boehm-gc/Makefile.am +++ b/boehm-gc/Makefile.am @@ -4,7 +4,7 @@ ## files that should be in the distribution are not mentioned in this ## Makefile.am. -AUTOMAKE_OPTIONS = foreign subdir-objects +AUTOMAKE_OPTIONS = foreign subdir-objects no-dist ACLOCAL_AMFLAGS = -I .. -I ../config SUBDIRS = include testsuite @@ -35,7 +35,7 @@ sparc_sunos4_mach_dep.s ia64_save_regs_in_stack.s # Include THREADLIBS here to ensure that the correct versions of # linuxthread semaphore functions get linked: -libgcjgc_la_LIBADD = $(addobjs) $(THREADLIBS) +libgcjgc_la_LIBADD = $(addobjs) $(THREADLIBS) $(EXTRA_TEST_LIBS) libgcjgc_la_DEPENDENCIES = $(addobjs) libgcjgc_la_LDFLAGS = $(extra_ldflags_libgc) -version-info 1:2:0 -rpath $(toolexeclibdir) libgcjgc_la_LINK = $(LINK) $(libgcjgc_la_LDFLAGS) diff --git a/boehm-gc/Makefile.in b/boehm-gc/Makefile.in index e1a3b70ca347f..5fc84910128ff 100644 --- a/boehm-gc/Makefile.in +++ b/boehm-gc/Makefile.in @@ -36,13 +36,10 @@ build_triplet = @build@ host_triplet = @host@ target_triplet = @target@ subdir = . -DIST_COMMON = $(am__configure_deps) $(srcdir)/../compile \ - $(srcdir)/../config.guess $(srcdir)/../config.sub \ - $(srcdir)/../depcomp $(srcdir)/../install-sh \ - $(srcdir)/../ltmain.sh $(srcdir)/../missing \ - $(srcdir)/../mkinstalldirs $(srcdir)/Makefile.am \ - $(srcdir)/Makefile.in $(srcdir)/threads.mk.in \ - $(top_srcdir)/configure ChangeLog depcomp +DIST_COMMON = ChangeLog $(srcdir)/Makefile.in $(srcdir)/Makefile.am \ + $(top_srcdir)/configure $(am__configure_deps) \ + $(srcdir)/../mkinstalldirs $(srcdir)/threads.mk.in \ + $(srcdir)/../depcomp ACLOCAL_M4 = $(top_srcdir)/aclocal.m4 am__aclocal_m4_deps = $(top_srcdir)/../config/acx.m4 \ $(top_srcdir)/../config/depstand.m4 \ @@ -63,14 +60,6 @@ CONFIG_CLEAN_FILES = threads.mk CONFIG_CLEAN_VPATH_FILES = LTLIBRARIES = $(noinst_LTLIBRARIES) am__DEPENDENCIES_1 = -am__libgcjgc_la_SOURCES_DIST = allchblk.c alloc.c blacklst.c \ - checksums.c dbg_mlc.c dyn_load.c finalize.c gc_dlopen.c \ - gcj_mlc.c headers.c malloc.c mallocx.c mark.c mark_rts.c \ - misc.c new_hblk.c obj_map.c os_dep.c pcr_interface.c \ - ptr_chck.c real_malloc.c reclaim.c specific.c stubborn.c \ - typd_mlc.c backgraph.c win32_threads.c pthread_support.c \ - pthread_stop_world.c darwin_stop_world.c \ - powerpc_darwin_mach_dep.s @POWERPC_DARWIN_TRUE@am__objects_1 = powerpc_darwin_mach_dep.lo am_libgcjgc_la_OBJECTS = allchblk.lo alloc.lo blacklst.lo checksums.lo \ dbg_mlc.lo dyn_load.lo finalize.lo gc_dlopen.lo gcj_mlc.lo \ @@ -80,14 +69,6 @@ am_libgcjgc_la_OBJECTS = allchblk.lo alloc.lo blacklst.lo checksums.lo \ backgraph.lo win32_threads.lo pthread_support.lo \ pthread_stop_world.lo darwin_stop_world.lo $(am__objects_1) libgcjgc_la_OBJECTS = $(am_libgcjgc_la_OBJECTS) -am__libgcjgc_convenience_la_SOURCES_DIST = allchblk.c alloc.c \ - blacklst.c checksums.c dbg_mlc.c dyn_load.c finalize.c \ - gc_dlopen.c gcj_mlc.c headers.c malloc.c mallocx.c mark.c \ - mark_rts.c misc.c new_hblk.c obj_map.c os_dep.c \ - pcr_interface.c ptr_chck.c real_malloc.c reclaim.c specific.c \ - stubborn.c typd_mlc.c backgraph.c win32_threads.c \ - pthread_support.c pthread_stop_world.c darwin_stop_world.c \ - powerpc_darwin_mach_dep.s am__objects_2 = allchblk.lo alloc.lo blacklst.lo checksums.lo \ dbg_mlc.lo dyn_load.lo finalize.lo gc_dlopen.lo gcj_mlc.lo \ headers.lo malloc.lo mallocx.lo mark.lo mark_rts.lo misc.lo \ @@ -115,8 +96,6 @@ CCASCOMPILE = $(CCAS) $(AM_CCASFLAGS) $(CCASFLAGS) LTCCASCOMPILE = $(LIBTOOL) $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) \ --mode=compile $(CCAS) $(AM_CCASFLAGS) $(CCASFLAGS) SOURCES = $(libgcjgc_la_SOURCES) $(libgcjgc_convenience_la_SOURCES) -DIST_SOURCES = $(am__libgcjgc_la_SOURCES_DIST) \ - $(am__libgcjgc_convenience_la_SOURCES_DIST) MULTISRCTOP = MULTIBUILDTOP = MULTIDIRS = @@ -133,47 +112,10 @@ RECURSIVE_TARGETS = all-recursive check-recursive dvi-recursive \ RECURSIVE_CLEAN_TARGETS = mostlyclean-recursive clean-recursive \ distclean-recursive maintainer-clean-recursive AM_RECURSIVE_TARGETS = $(RECURSIVE_TARGETS:-recursive=) \ - $(RECURSIVE_CLEAN_TARGETS:-recursive=) tags TAGS ctags CTAGS \ - distdir dist dist-all distcheck + $(RECURSIVE_CLEAN_TARGETS:-recursive=) tags TAGS ctags CTAGS ETAGS = etags CTAGS = ctags DIST_SUBDIRS = $(SUBDIRS) -DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST) -distdir = $(PACKAGE)-$(VERSION) -top_distdir = $(distdir) -am__remove_distdir = \ - { test ! -d "$(distdir)" \ - || { find "$(distdir)" -type d ! -perm -200 -exec chmod u+w {} ';' \ - && rm -fr "$(distdir)"; }; } -am__relativize = \ - dir0=`pwd`; \ - sed_first='s,^\([^/]*\)/.*$$,\1,'; \ - sed_rest='s,^[^/]*/*,,'; \ - sed_last='s,^.*/\([^/]*\)$$,\1,'; \ - sed_butlast='s,/*[^/]*$$,,'; \ - while test -n "$$dir1"; do \ - first=`echo "$$dir1" | sed -e "$$sed_first"`; \ - if test "$$first" != "."; then \ - if test "$$first" = ".."; then \ - dir2=`echo "$$dir0" | sed -e "$$sed_last"`/"$$dir2"; \ - dir0=`echo "$$dir0" | sed -e "$$sed_butlast"`; \ - else \ - first2=`echo "$$dir2" | sed -e "$$sed_first"`; \ - if test "$$first2" = "$$first"; then \ - dir2=`echo "$$dir2" | sed -e "$$sed_rest"`; \ - else \ - dir2="../$$dir2"; \ - fi; \ - dir0="$$dir0"/"$$first"; \ - fi; \ - fi; \ - dir1=`echo "$$dir1" | sed -e "$$sed_rest"`; \ - done; \ - reldir="$$dir2" -DIST_ARCHIVES = $(distdir).tar.gz -GZIP_ENV = --best -distuninstallcheck_listfiles = find . -type f -print -distcleancheck_listfiles = find . -type f -print ACLOCAL = @ACLOCAL@ AMTAR = @AMTAR@ AM_CPPFLAGS = @AM_CPPFLAGS@ @@ -314,7 +256,7 @@ toolexeclibdir = @toolexeclibdir@ top_build_prefix = @top_build_prefix@ top_builddir = @top_builddir@ top_srcdir = @top_srcdir@ -AUTOMAKE_OPTIONS = foreign subdir-objects +AUTOMAKE_OPTIONS = foreign subdir-objects no-dist ACLOCAL_AMFLAGS = -I .. -I ../config SUBDIRS = include testsuite noinst_LTLIBRARIES = libgcjgc.la libgcjgc_convenience.la @@ -338,7 +280,7 @@ sparc_sunos4_mach_dep.s ia64_save_regs_in_stack.s # Include THREADLIBS here to ensure that the correct versions of # linuxthread semaphore functions get linked: -libgcjgc_la_LIBADD = $(addobjs) $(THREADLIBS) +libgcjgc_la_LIBADD = $(addobjs) $(THREADLIBS) $(EXTRA_TEST_LIBS) libgcjgc_la_DEPENDENCIES = $(addobjs) libgcjgc_la_LDFLAGS = $(extra_ldflags_libgc) -version-info 1:2:0 -rpath $(toolexeclibdir) libgcjgc_la_LINK = $(LINK) $(libgcjgc_la_LDFLAGS) @@ -672,182 +614,6 @@ GTAGS: distclean-tags: -rm -f TAGS ID GTAGS GRTAGS GSYMS GPATH tags - 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Then -# it guarantees that the distribution is self-contained by making another -# tarfile. -distcheck: dist - case '$(DIST_ARCHIVES)' in \ - *.tar.gz*) \ - GZIP=$(GZIP_ENV) gzip -dc $(distdir).tar.gz | $(am__untar) ;;\ - *.tar.bz2*) \ - bzip2 -dc $(distdir).tar.bz2 | $(am__untar) ;;\ - *.tar.lzma*) \ - lzma -dc $(distdir).tar.lzma | $(am__untar) ;;\ - *.tar.xz*) \ - xz -dc $(distdir).tar.xz | $(am__untar) ;;\ - *.tar.Z*) \ - uncompress -c $(distdir).tar.Z | $(am__untar) ;;\ - *.shar.gz*) \ - GZIP=$(GZIP_ENV) gzip -dc $(distdir).shar.gz | unshar ;;\ - *.zip*) \ - unzip $(distdir).zip ;;\ - esac - chmod -R a-w $(distdir); chmod a+w $(distdir) - mkdir $(distdir)/_build - mkdir $(distdir)/_inst - chmod a-w $(distdir) - test -d $(distdir)/_build || exit 0; \ - dc_install_base=`$(am__cd) $(distdir)/_inst && pwd | sed -e 's,^[^:\\/]:[\\/],/,'` \ - && dc_destdir="$${TMPDIR-/tmp}/am-dc-$$$$/" \ - && am__cwd=`pwd` \ - && $(am__cd) $(distdir)/_build \ - && ../configure --srcdir=.. --prefix="$$dc_install_base" \ - $(DISTCHECK_CONFIGURE_FLAGS) \ - && $(MAKE) $(AM_MAKEFLAGS) \ - && $(MAKE) $(AM_MAKEFLAGS) dvi \ - && $(MAKE) $(AM_MAKEFLAGS) check \ - && $(MAKE) $(AM_MAKEFLAGS) install \ - && $(MAKE) $(AM_MAKEFLAGS) installcheck \ - && $(MAKE) $(AM_MAKEFLAGS) uninstall \ - && $(MAKE) $(AM_MAKEFLAGS) distuninstallcheck_dir="$$dc_install_base" \ - distuninstallcheck \ - && chmod -R a-w "$$dc_install_base" \ - && ({ \ - (cd ../.. && umask 077 && mkdir "$$dc_destdir") \ - && $(MAKE) $(AM_MAKEFLAGS) DESTDIR="$$dc_destdir" install \ - && $(MAKE) $(AM_MAKEFLAGS) DESTDIR="$$dc_destdir" uninstall \ - && $(MAKE) $(AM_MAKEFLAGS) DESTDIR="$$dc_destdir" \ - distuninstallcheck_dir="$$dc_destdir" distuninstallcheck; \ - } || { rm -rf "$$dc_destdir"; exit 1; }) \ - && rm -rf "$$dc_destdir" \ - && $(MAKE) $(AM_MAKEFLAGS) dist \ - && rm -rf $(DIST_ARCHIVES) \ - && $(MAKE) $(AM_MAKEFLAGS) distcleancheck \ - && cd "$$am__cwd" \ - || exit 1 - $(am__remove_distdir) - @(echo "$(distdir) archives ready for distribution: "; \ - list='$(DIST_ARCHIVES)'; for i in $$list; do echo $$i; done) | \ - sed -e 1h -e 1s/./=/g -e 1p -e 1x -e '$$p' -e '$$x' -distuninstallcheck: - @$(am__cd) '$(distuninstallcheck_dir)' \ - && test `$(distuninstallcheck_listfiles) | wc -l` -le 1 \ - || { echo "ERROR: files left after uninstall:" ; \ - if test -n "$(DESTDIR)"; then \ - echo " (check DESTDIR support)"; \ - fi ; \ - $(distuninstallcheck_listfiles) ; \ - exit 1; } >&2 -distcleancheck: distclean - @if test '$(srcdir)' = . ; then \ - echo "ERROR: distcleancheck can only run from a VPATH build" ; \ - exit 1 ; \ - fi - @test `$(distcleancheck_listfiles) | wc -l` -eq 0 \ - || { echo "ERROR: files left in build directory after distclean:" ; \ - $(distcleancheck_listfiles) ; \ - exit 1; } >&2 check-am: all-am check: check-recursive all-am: Makefile $(LTLIBRARIES) all-multi @@ -960,21 +726,19 @@ uninstall-am: .PHONY: $(RECURSIVE_CLEAN_TARGETS) $(RECURSIVE_TARGETS) CTAGS GTAGS \ all all-am all-multi am--refresh check check-am clean \ clean-generic clean-libtool clean-multi \ - clean-noinstLTLIBRARIES ctags ctags-recursive dist dist-all \ - dist-bzip2 dist-gzip dist-lzma dist-shar dist-tarZ dist-xz \ - dist-zip distcheck distclean distclean-compile \ - distclean-generic distclean-libtool distclean-multi \ - distclean-tags distcleancheck distdir distuninstallcheck dvi \ - dvi-am html html-am info info-am install install-am \ - install-data install-data-am install-dvi install-dvi-am \ - install-exec install-exec-am install-html install-html-am \ - install-info install-info-am install-man install-multi \ - install-pdf install-pdf-am install-ps install-ps-am \ - install-strip installcheck installcheck-am installdirs \ - installdirs-am maintainer-clean maintainer-clean-generic \ - maintainer-clean-multi mostlyclean mostlyclean-compile \ - mostlyclean-generic mostlyclean-libtool mostlyclean-multi pdf \ - pdf-am ps ps-am tags tags-recursive uninstall uninstall-am + clean-noinstLTLIBRARIES ctags ctags-recursive distclean \ + distclean-compile distclean-generic distclean-libtool \ + distclean-multi distclean-tags dvi dvi-am html html-am info \ + info-am install install-am install-data install-data-am \ + install-dvi install-dvi-am install-exec install-exec-am \ + install-html install-html-am install-info install-info-am \ + install-man install-multi install-pdf install-pdf-am \ + install-ps install-ps-am install-strip installcheck \ + installcheck-am installdirs installdirs-am maintainer-clean \ + maintainer-clean-generic maintainer-clean-multi mostlyclean \ + mostlyclean-compile mostlyclean-generic mostlyclean-libtool \ + mostlyclean-multi pdf pdf-am ps ps-am tags tags-recursive \ + uninstall uninstall-am override CFLAGS := $(filter-out $(O0_CFLAGS), $(CFLAGS)) $(O0_CFLAGS) diff --git a/boehm-gc/configure b/boehm-gc/configure index 6020e9884eb98..025003cac1356 100755 --- a/boehm-gc/configure +++ b/boehm-gc/configure @@ -6770,7 +6770,7 @@ ia64-*-hpux*) rm -rf conftest* ;; -x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \ +x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \ s390*-*linux*|s390*-*tpf*|sparc*-*linux*) # Find out which ABI we are using. echo 'int i;' > conftest.$ac_ext @@ -6795,7 +6795,10 @@ s390*-*linux*|s390*-*tpf*|sparc*-*linux*) ;; esac ;; - ppc64-*linux*|powerpc64-*linux*) + powerpc64le-*linux*) + LD="${LD-ld} -m elf32lppclinux" + ;; + powerpc64-*linux*) LD="${LD-ld} -m elf32ppclinux" ;; s390x-*linux*) @@ -6814,7 +6817,10 @@ s390*-*linux*|s390*-*tpf*|sparc*-*linux*) x86_64-*linux*) LD="${LD-ld} -m elf_x86_64" ;; - ppc*-*linux*|powerpc*-*linux*) + powerpcle-*linux*) + LD="${LD-ld} -m elf64lppc" + ;; + powerpc-*linux*) LD="${LD-ld} -m elf64ppc" ;; s390*-*linux*|s390*-*tpf*) @@ -11312,7 +11318,7 @@ else lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 lt_status=$lt_dlunknown cat > conftest.$ac_ext <<_LT_EOF -#line 11315 "configure" +#line 11321 "configure" #include "confdefs.h" #if HAVE_DLFCN_H @@ -11418,7 +11424,7 @@ else lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 lt_status=$lt_dlunknown cat > conftest.$ac_ext <<_LT_EOF -#line 11421 "configure" +#line 11427 "configure" #include "confdefs.h" #if HAVE_DLFCN_H diff --git a/boehm-gc/include/Makefile.am b/boehm-gc/include/Makefile.am index 381ae76b8fee0..63aec07605605 100644 --- a/boehm-gc/include/Makefile.am +++ b/boehm-gc/include/Makefile.am @@ -1,4 +1,4 @@ -AUTOMAKE_OPTIONS = foreign +AUTOMAKE_OPTIONS = foreign no-dist noinst_HEADERS = gc.h gc_backptr.h gc_local_alloc.h \ gc_pthread_redirects.h gc_cpp.h diff --git a/boehm-gc/include/Makefile.in b/boehm-gc/include/Makefile.in index db67a999adf01..8287ef6b1d952 100644 --- a/boehm-gc/include/Makefile.in +++ b/boehm-gc/include/Makefile.in @@ -36,9 +36,9 @@ build_triplet = @build@ host_triplet = @host@ target_triplet = @target@ subdir = include -DIST_COMMON = $(noinst_HEADERS) $(srcdir)/Makefile.am \ - $(srcdir)/Makefile.in $(srcdir)/gc_config.h.in \ - $(srcdir)/gc_ext_config.h.in +DIST_COMMON = $(srcdir)/Makefile.in $(srcdir)/Makefile.am \ + $(srcdir)/gc_config.h.in $(srcdir)/gc_ext_config.h.in \ + $(noinst_HEADERS) ACLOCAL_M4 = $(top_srcdir)/aclocal.m4 am__aclocal_m4_deps = $(top_srcdir)/../config/acx.m4 \ $(top_srcdir)/../config/depstand.m4 \ @@ -55,11 +55,9 @@ CONFIG_HEADER = gc_config.h gc_ext_config.h CONFIG_CLEAN_FILES = CONFIG_CLEAN_VPATH_FILES = SOURCES = -DIST_SOURCES = HEADERS = $(noinst_HEADERS) ETAGS = etags CTAGS = ctags -DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST) ACLOCAL = @ACLOCAL@ AMTAR = @AMTAR@ AM_CPPFLAGS = @AM_CPPFLAGS@ @@ -200,7 +198,7 @@ toolexeclibdir = @toolexeclibdir@ top_build_prefix = @top_build_prefix@ top_builddir = @top_builddir@ top_srcdir = @top_srcdir@ -AUTOMAKE_OPTIONS = foreign +AUTOMAKE_OPTIONS = foreign no-dist noinst_HEADERS = gc.h gc_backptr.h gc_local_alloc.h \ gc_pthread_redirects.h gc_cpp.h @@ -323,37 +321,6 @@ GTAGS: distclean-tags: -rm -f TAGS ID GTAGS GRTAGS GSYMS GPATH tags - -distdir: $(DISTFILES) - @srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \ - topsrcdirstrip=`echo "$(top_srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \ - list='$(DISTFILES)'; \ - dist_files=`for file in $$list; do echo $$file; done | \ - sed -e "s|^$$srcdirstrip/||;t" \ - -e "s|^$$topsrcdirstrip/|$(top_builddir)/|;t"`; \ - case $$dist_files in \ - */*) $(MKDIR_P) `echo "$$dist_files" | \ - sed '/\//!d;s|^|$(distdir)/|;s,/[^/]*$$,,' | \ - sort -u` ;; \ - esac; \ - for file in $$dist_files; do \ - if test -f $$file || test -d $$file; then d=.; else d=$(srcdir); fi; \ - if test -d $$d/$$file; then \ - dir=`echo "/$$file" | sed -e 's,/[^/]*$$,,'`; \ - if test -d "$(distdir)/$$file"; then \ - find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \ - fi; \ - if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \ - cp -fpR $(srcdir)/$$file "$(distdir)$$dir" || exit 1; \ - find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \ - fi; \ - cp -fpR $$d/$$file "$(distdir)$$dir" || exit 1; \ - else \ - test -f "$(distdir)/$$file" \ - || cp -p $$d/$$file "$(distdir)/$$file" \ - || exit 1; \ - fi; \ - done check-am: all-am check: check-am all-am: Makefile $(HEADERS) gc_config.h gc_ext_config.h @@ -453,16 +420,15 @@ uninstall-am: .PHONY: CTAGS GTAGS all all-am check check-am clean clean-generic \ clean-libtool ctags distclean distclean-generic distclean-hdr \ - distclean-libtool distclean-tags distdir dvi dvi-am html \ - html-am info info-am install install-am install-data \ - install-data-am install-dvi install-dvi-am install-exec \ - install-exec-am install-html install-html-am install-info \ - install-info-am install-man install-pdf install-pdf-am \ - install-ps install-ps-am install-strip installcheck \ - installcheck-am installdirs maintainer-clean \ - maintainer-clean-generic mostlyclean mostlyclean-generic \ - mostlyclean-libtool pdf pdf-am ps ps-am tags uninstall \ - uninstall-am + distclean-libtool distclean-tags dvi dvi-am html html-am info \ + info-am install install-am install-data install-data-am \ + install-dvi install-dvi-am install-exec install-exec-am \ + install-html install-html-am install-info install-info-am \ + install-man install-pdf install-pdf-am install-ps \ + install-ps-am install-strip installcheck installcheck-am \ + installdirs maintainer-clean maintainer-clean-generic \ + mostlyclean mostlyclean-generic mostlyclean-libtool pdf pdf-am \ + ps ps-am tags uninstall uninstall-am # Tell versions [3.59,3.63) of GNU make to not export all variables. diff --git a/boehm-gc/include/private/gcconfig.h b/boehm-gc/include/private/gcconfig.h index 9420c7caf8f4d..79f5fb71efbde 100644 --- a/boehm-gc/include/private/gcconfig.h +++ b/boehm-gc/include/private/gcconfig.h @@ -837,7 +837,15 @@ # define NO_PTHREAD_TRYLOCK # endif # ifdef FREEBSD +# if defined(__powerpc64__) +# define ALIGNMENT 8 +# define CPP_WORDSZ 64 +# ifndef HBLKSIZE +# define HBLKSIZE 4096 +# endif +# else # define ALIGNMENT 4 +# endif # define OS_TYPE "FREEBSD" # ifndef GC_FREEBSD_THREADS # define MPROTECT_VDB diff --git a/boehm-gc/testsuite/Makefile.am b/boehm-gc/testsuite/Makefile.am index 98010bd1f69df..f1eac3b16663f 100644 --- a/boehm-gc/testsuite/Makefile.am +++ b/boehm-gc/testsuite/Makefile.am @@ -1,6 +1,6 @@ ## Process this file with automake to produce Makefile.in. -AUTOMAKE_OPTIONS = foreign dejagnu +AUTOMAKE_OPTIONS = foreign dejagnu no-dist EXPECT = expect diff --git a/boehm-gc/testsuite/Makefile.in b/boehm-gc/testsuite/Makefile.in index b12a5c51558e2..dbb2ff604e02f 100644 --- a/boehm-gc/testsuite/Makefile.in +++ b/boehm-gc/testsuite/Makefile.in @@ -35,7 +35,7 @@ build_triplet = @build@ host_triplet = @host@ target_triplet = @target@ subdir = testsuite -DIST_COMMON = $(srcdir)/Makefile.am $(srcdir)/Makefile.in +DIST_COMMON = $(srcdir)/Makefile.in $(srcdir)/Makefile.am ACLOCAL_M4 = $(top_srcdir)/aclocal.m4 am__aclocal_m4_deps = $(top_srcdir)/../config/acx.m4 \ $(top_srcdir)/../config/depstand.m4 \ @@ -53,10 +53,8 @@ CONFIG_HEADER = $(top_builddir)/include/gc_config.h \ CONFIG_CLEAN_FILES = CONFIG_CLEAN_VPATH_FILES = SOURCES = -DIST_SOURCES = RUNTESTDEFAULTFLAGS = --tool $$tool --srcdir $$srcdir RUNTEST = runtest -DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST) ACLOCAL = @ACLOCAL@ AMTAR = @AMTAR@ AM_CPPFLAGS = @AM_CPPFLAGS@ @@ -197,7 +195,7 @@ toolexeclibdir = @toolexeclibdir@ top_build_prefix = @top_build_prefix@ top_builddir = @top_builddir@ top_srcdir = @top_srcdir@ -AUTOMAKE_OPTIONS = foreign dejagnu +AUTOMAKE_OPTIONS = foreign dejagnu no-dist EXPECT = expect # Override default. @@ -267,37 +265,6 @@ distclean-DEJAGNU: -l='$(DEJATOOL)'; for tool in $$l; do \ rm -f $$tool.sum $$tool.log; \ done - -distdir: $(DISTFILES) - @srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \ - topsrcdirstrip=`echo "$(top_srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \ - list='$(DISTFILES)'; \ - dist_files=`for file in $$list; do echo $$file; done | \ - sed -e "s|^$$srcdirstrip/||;t" \ - -e "s|^$$topsrcdirstrip/|$(top_builddir)/|;t"`; \ - case $$dist_files in \ - */*) $(MKDIR_P) `echo "$$dist_files" | \ - sed '/\//!d;s|^|$(distdir)/|;s,/[^/]*$$,,' | \ - sort -u` ;; \ - esac; \ - for file in $$dist_files; do \ - if test -f $$file || test -d $$file; then d=.; else d=$(srcdir); fi; \ - if test -d $$d/$$file; then \ - dir=`echo "/$$file" | sed -e 's,/[^/]*$$,,'`; \ - if test -d "$(distdir)/$$file"; then \ - find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \ - fi; \ - if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \ - cp -fpR $(srcdir)/$$file "$(distdir)$$dir" || exit 1; \ - find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \ - fi; \ - cp -fpR $$d/$$file "$(distdir)$$dir" || exit 1; \ - else \ - test -f "$(distdir)/$$file" \ - || cp -p $$d/$$file "$(distdir)/$$file" \ - || exit 1; \ - fi; \ - done check-am: all-am $(MAKE) $(AM_MAKEFLAGS) check-DEJAGNU check: check-am @@ -399,8 +366,8 @@ uninstall-am: .PHONY: all all-am check check-DEJAGNU check-am clean clean-generic \ clean-libtool distclean distclean-DEJAGNU distclean-generic \ - distclean-libtool distdir dvi dvi-am html html-am info info-am \ - install install-am install-data install-data-am install-dvi \ + distclean-libtool dvi dvi-am html html-am info info-am install \ + install-am install-data install-data-am install-dvi \ install-dvi-am install-exec install-exec-am install-html \ install-html-am install-info install-info-am install-man \ install-pdf install-pdf-am install-ps install-ps-am \ diff --git a/config.guess b/config.guess index 0aee6044d303a..b79252d6b1034 100755 --- a/config.guess +++ b/config.guess @@ -1,10 +1,8 @@ #! /bin/sh # Attempt to guess a canonical system name. -# Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, -# 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, -# 2011, 2012, 2013 Free Software Foundation, Inc. +# Copyright 1992-2013 Free Software Foundation, Inc. -timestamp='2012-12-30' +timestamp='2013-06-10' # This file is free software; you can redistribute it and/or modify it # under the terms of the GNU General Public License as published by @@ -52,9 +50,7 @@ version="\ GNU config.guess ($timestamp) Originally written by Per Bothner. -Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, -2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, -2012, 2013 Free Software Foundation, Inc. +Copyright 1992-2013 Free Software Foundation, Inc. This is free software; see the source for copying conditions. There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE." @@ -136,6 +132,27 @@ UNAME_RELEASE=`(uname -r) 2>/dev/null` || UNAME_RELEASE=unknown UNAME_SYSTEM=`(uname -s) 2>/dev/null` || UNAME_SYSTEM=unknown UNAME_VERSION=`(uname -v) 2>/dev/null` || UNAME_VERSION=unknown +case "${UNAME_SYSTEM}" in +Linux|GNU|GNU/*) + # If the system lacks a compiler, then just pick glibc. + # We could probably try harder. + LIBC=gnu + + eval $set_cc_for_build + cat <<-EOF > $dummy.c + #include + #if defined(__UCLIBC__) + LIBC=uclibc + #elif defined(__dietlibc__) + LIBC=dietlibc + #else + LIBC=gnu + #endif + EOF + eval `$CC_FOR_BUILD -E $dummy.c 2>/dev/null | grep '^LIBC'` + ;; +esac + # Note: order is significant - the case branches are not exclusive. case "${UNAME_MACHINE}:${UNAME_SYSTEM}:${UNAME_RELEASE}:${UNAME_VERSION}" in @@ -857,21 +874,21 @@ EOF exit ;; *:GNU:*:*) # the GNU system - echo `echo ${UNAME_MACHINE}|sed -e 's,[-/].*$,,'`-unknown-gnu`echo ${UNAME_RELEASE}|sed -e 's,/.*$,,'` + echo `echo ${UNAME_MACHINE}|sed -e 's,[-/].*$,,'`-unknown-${LIBC}`echo ${UNAME_RELEASE}|sed -e 's,/.*$,,'` exit ;; *:GNU/*:*:*) # other systems with GNU libc and userland - echo ${UNAME_MACHINE}-unknown-`echo ${UNAME_SYSTEM} | sed 's,^[^/]*/,,' | tr '[A-Z]' '[a-z]'``echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'`-gnu + echo ${UNAME_MACHINE}-unknown-`echo ${UNAME_SYSTEM} | sed 's,^[^/]*/,,' | tr '[A-Z]' '[a-z]'``echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'`-${LIBC} exit ;; i*86:Minix:*:*) echo ${UNAME_MACHINE}-pc-minix exit ;; aarch64:Linux:*:*) - echo ${UNAME_MACHINE}-unknown-linux-gnu + echo ${UNAME_MACHINE}-unknown-linux-${LIBC} exit ;; aarch64_be:Linux:*:*) UNAME_MACHINE=aarch64_be - echo ${UNAME_MACHINE}-unknown-linux-gnu + echo ${UNAME_MACHINE}-unknown-linux-${LIBC} exit ;; alpha:Linux:*:*) case `sed -n '/^cpu model/s/^.*: \(.*\)/\1/p' < /proc/cpuinfo` in @@ -884,59 +901,54 @@ EOF EV68*) UNAME_MACHINE=alphaev68 ;; esac objdump --private-headers /bin/sh | grep -q ld.so.1 - if test "$?" = 0 ; then LIBC="libc1" ; else LIBC="" ; fi - echo ${UNAME_MACHINE}-unknown-linux-gnu${LIBC} + if test "$?" = 0 ; then LIBC="gnulibc1" ; fi + echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; + arc:Linux:*:* | arceb:Linux:*:*) + echo ${UNAME_MACHINE}-unknown-linux-${LIBC} exit ;; arm*:Linux:*:*) eval $set_cc_for_build if echo __ARM_EABI__ | $CC_FOR_BUILD -E - 2>/dev/null \ | grep -q __ARM_EABI__ then - echo ${UNAME_MACHINE}-unknown-linux-gnu + echo ${UNAME_MACHINE}-unknown-linux-${LIBC} else if echo __ARM_PCS_VFP | $CC_FOR_BUILD -E - 2>/dev/null \ | grep -q __ARM_PCS_VFP then - echo ${UNAME_MACHINE}-unknown-linux-gnueabi + echo ${UNAME_MACHINE}-unknown-linux-${LIBC}eabi else - echo ${UNAME_MACHINE}-unknown-linux-gnueabihf + echo ${UNAME_MACHINE}-unknown-linux-${LIBC}eabihf fi fi exit ;; avr32*:Linux:*:*) - echo ${UNAME_MACHINE}-unknown-linux-gnu + echo ${UNAME_MACHINE}-unknown-linux-${LIBC} exit ;; cris:Linux:*:*) - echo ${UNAME_MACHINE}-axis-linux-gnu + echo ${UNAME_MACHINE}-axis-linux-${LIBC} exit ;; crisv32:Linux:*:*) - echo ${UNAME_MACHINE}-axis-linux-gnu + echo ${UNAME_MACHINE}-axis-linux-${LIBC} exit ;; frv:Linux:*:*) - echo ${UNAME_MACHINE}-unknown-linux-gnu + echo ${UNAME_MACHINE}-unknown-linux-${LIBC} exit ;; hexagon:Linux:*:*) - echo ${UNAME_MACHINE}-unknown-linux-gnu + echo ${UNAME_MACHINE}-unknown-linux-${LIBC} exit ;; i*86:Linux:*:*) - LIBC=gnu - eval $set_cc_for_build - sed 's/^ //' << EOF >$dummy.c - #ifdef __dietlibc__ - LIBC=dietlibc - #endif -EOF - eval `$CC_FOR_BUILD -E $dummy.c 2>/dev/null | grep '^LIBC'` - echo "${UNAME_MACHINE}-pc-linux-${LIBC}" + echo ${UNAME_MACHINE}-pc-linux-${LIBC} exit ;; ia64:Linux:*:*) - echo ${UNAME_MACHINE}-unknown-linux-gnu + echo ${UNAME_MACHINE}-unknown-linux-${LIBC} exit ;; m32r*:Linux:*:*) - echo ${UNAME_MACHINE}-unknown-linux-gnu + echo ${UNAME_MACHINE}-unknown-linux-${LIBC} exit ;; m68*:Linux:*:*) - echo ${UNAME_MACHINE}-unknown-linux-gnu + echo ${UNAME_MACHINE}-unknown-linux-${LIBC} exit ;; mips:Linux:*:* | mips64:Linux:*:*) eval $set_cc_for_build @@ -955,54 +967,63 @@ EOF #endif EOF eval `$CC_FOR_BUILD -E $dummy.c 2>/dev/null | grep '^CPU'` - test x"${CPU}" != x && { echo "${CPU}-unknown-linux-gnu"; exit; } + test x"${CPU}" != x && { echo "${CPU}-unknown-linux-${LIBC}"; exit; } ;; + or1k:Linux:*:*) + echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; or32:Linux:*:*) - echo ${UNAME_MACHINE}-unknown-linux-gnu + echo ${UNAME_MACHINE}-unknown-linux-${LIBC} exit ;; padre:Linux:*:*) - echo sparc-unknown-linux-gnu + echo sparc-unknown-linux-${LIBC} exit ;; parisc64:Linux:*:* | hppa64:Linux:*:*) - echo hppa64-unknown-linux-gnu + echo hppa64-unknown-linux-${LIBC} exit ;; parisc:Linux:*:* | hppa:Linux:*:*) # Look for CPU level case `grep '^cpu[^a-z]*:' /proc/cpuinfo 2>/dev/null | cut -d' ' -f2` in - PA7*) echo hppa1.1-unknown-linux-gnu ;; - PA8*) echo hppa2.0-unknown-linux-gnu ;; - *) echo hppa-unknown-linux-gnu ;; + PA7*) echo hppa1.1-unknown-linux-${LIBC} ;; + PA8*) echo hppa2.0-unknown-linux-${LIBC} ;; + *) echo hppa-unknown-linux-${LIBC} ;; esac exit ;; ppc64:Linux:*:*) - echo powerpc64-unknown-linux-gnu + echo powerpc64-unknown-linux-${LIBC} exit ;; ppc:Linux:*:*) - echo powerpc-unknown-linux-gnu + echo powerpc-unknown-linux-${LIBC} + exit ;; + ppc64le:Linux:*:*) + echo powerpc64le-unknown-linux-${LIBC} + exit ;; + ppcle:Linux:*:*) + echo powerpcle-unknown-linux-${LIBC} exit ;; s390:Linux:*:* | s390x:Linux:*:*) - echo ${UNAME_MACHINE}-ibm-linux + echo ${UNAME_MACHINE}-ibm-linux-${LIBC} exit ;; sh64*:Linux:*:*) - echo ${UNAME_MACHINE}-unknown-linux-gnu + echo ${UNAME_MACHINE}-unknown-linux-${LIBC} exit ;; sh*:Linux:*:*) - echo ${UNAME_MACHINE}-unknown-linux-gnu + echo ${UNAME_MACHINE}-unknown-linux-${LIBC} exit ;; sparc:Linux:*:* | sparc64:Linux:*:*) - echo ${UNAME_MACHINE}-unknown-linux-gnu + echo ${UNAME_MACHINE}-unknown-linux-${LIBC} exit ;; tile*:Linux:*:*) - echo ${UNAME_MACHINE}-unknown-linux-gnu + echo ${UNAME_MACHINE}-unknown-linux-${LIBC} exit ;; vax:Linux:*:*) - echo ${UNAME_MACHINE}-dec-linux-gnu + echo ${UNAME_MACHINE}-dec-linux-${LIBC} exit ;; x86_64:Linux:*:*) - echo ${UNAME_MACHINE}-unknown-linux-gnu + echo ${UNAME_MACHINE}-unknown-linux-${LIBC} exit ;; xtensa*:Linux:*:*) - echo ${UNAME_MACHINE}-unknown-linux-gnu + echo ${UNAME_MACHINE}-unknown-linux-${LIBC} exit ;; i*86:DYNIX/ptx:4*:*) # ptx 4.0 does uname -s correctly, with DYNIX/ptx in there. @@ -1235,19 +1256,21 @@ EOF exit ;; *:Darwin:*:*) UNAME_PROCESSOR=`uname -p` || UNAME_PROCESSOR=unknown - case $UNAME_PROCESSOR in - i386) - eval $set_cc_for_build - if [ "$CC_FOR_BUILD" != 'no_compiler_found' ]; then - if (echo '#ifdef __LP64__'; echo IS_64BIT_ARCH; echo '#endif') | \ - (CCOPTS= $CC_FOR_BUILD -E - 2>/dev/null) | \ - grep IS_64BIT_ARCH >/dev/null - then - UNAME_PROCESSOR="x86_64" - fi - fi ;; - unknown) UNAME_PROCESSOR=powerpc ;; - esac + eval $set_cc_for_build + if test "$UNAME_PROCESSOR" = unknown ; then + UNAME_PROCESSOR=powerpc + fi + if [ "$CC_FOR_BUILD" != 'no_compiler_found' ]; then + if (echo '#ifdef __LP64__'; echo IS_64BIT_ARCH; echo '#endif') | \ + (CCOPTS= $CC_FOR_BUILD -E - 2>/dev/null) | \ + grep IS_64BIT_ARCH >/dev/null + then + case $UNAME_PROCESSOR in + i386) UNAME_PROCESSOR=x86_64 ;; + powerpc) UNAME_PROCESSOR=powerpc64 ;; + esac + fi + fi echo ${UNAME_PROCESSOR}-apple-darwin${UNAME_RELEASE} exit ;; *:procnto*:*:* | *:QNX:[0123456789]*:*) diff --git a/config.sub b/config.sub index 707e9e2efe8d4..61cb4bc22db8e 100755 --- a/config.sub +++ b/config.sub @@ -1,10 +1,8 @@ #! /bin/sh # Configuration validation subroutine script. -# Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, -# 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, -# 2011, 2012, 2013 Free Software Foundation, Inc. +# Copyright 1992-2013 Free Software Foundation, Inc. -timestamp='2013-01-11' +timestamp='2013-10-01' # This file is free software; you can redistribute it and/or modify it # under the terms of the GNU General Public License as published by @@ -70,9 +68,7 @@ Report bugs and patches to ." version="\ GNU config.sub ($timestamp) -Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, -2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, -2012, 2013 Free Software Foundation, Inc. +Copyright 1992-2013 Free Software Foundation, Inc. This is free software; see the source for copying conditions. There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE." @@ -256,12 +252,12 @@ case $basic_machine in | alpha | alphaev[4-8] | alphaev56 | alphaev6[78] | alphapca5[67] \ | alpha64 | alpha64ev[4-8] | alpha64ev56 | alpha64ev6[78] | alpha64pca5[67] \ | am33_2.0 \ - | arc \ + | arc | arceb \ | arm | arm[bl]e | arme[lb] | armv[2-8] | armv[3-8][lb] | armv7[arm] \ | avr | avr32 \ | be32 | be64 \ | bfin \ - | c4x | clipper \ + | c4x | c8051 | clipper \ | d10v | d30v | dlx | dsp16xx \ | epiphany \ | fido | fr30 | frv \ @@ -269,6 +265,7 @@ case $basic_machine in | hexagon \ | i370 | i860 | i960 | ia64 \ | ip2k | iq2000 \ + | k1om \ | le32 | le64 \ | lm32 \ | m32c | m32r | m32rle | m68000 | m68k | m88k \ @@ -297,10 +294,10 @@ case $basic_machine in | mt \ | msp430 \ | nds32 | nds32le | nds32be \ - | nios | nios2 \ + | nios | nios2 | nios2eb | nios2el \ | ns16k | ns32k \ | open8 \ - | or32 \ + | or1k | or32 \ | pdp10 | pdp11 | pj | pjl \ | powerpc | powerpc64 | powerpc64le | powerpcle \ | pyramid \ @@ -328,7 +325,7 @@ case $basic_machine in c6x) basic_machine=tic6x-unknown ;; - m6811 | m68hc11 | m6812 | m68hc12 | m68hcs12x | picochip) + m6811 | m68hc11 | m6812 | m68hc12 | m68hcs12x | nvptx | picochip) basic_machine=$basic_machine-unknown os=-none ;; @@ -370,13 +367,13 @@ case $basic_machine in | aarch64-* | aarch64_be-* \ | alpha-* | alphaev[4-8]-* | alphaev56-* | alphaev6[78]-* \ | alpha64-* | alpha64ev[4-8]-* | alpha64ev56-* | alpha64ev6[78]-* \ - | alphapca5[67]-* | alpha64pca5[67]-* | arc-* \ + | alphapca5[67]-* | alpha64pca5[67]-* | arc-* | arceb-* \ | arm-* | armbe-* | armle-* | armeb-* | armv*-* \ | avr-* | avr32-* \ | be32-* | be64-* \ | bfin-* | bs2000-* \ | c[123]* | c30-* | [cjt]90-* | c4x-* \ - | clipper-* | craynv-* | cydra-* \ + | c8051-* | clipper-* | craynv-* | cydra-* \ | d10v-* | d30v-* | dlx-* \ | elxsi-* \ | f30[01]-* | f700-* | fido-* | fr30-* | frv-* | fx80-* \ @@ -385,6 +382,7 @@ case $basic_machine in | hexagon-* \ | i*86-* | i860-* | i960-* | ia64-* \ | ip2k-* | iq2000-* \ + | k1om-* \ | le32-* | le64-* \ | lm32-* \ | m32c-* | m32r-* | m32rle-* \ @@ -414,7 +412,7 @@ case $basic_machine in | mt-* \ | msp430-* \ | nds32-* | nds32le-* | nds32be-* \ - | nios-* | nios2-* \ + | nios-* | nios2-* | nios2eb-* | nios2el-* \ | none-* | np1-* | ns16k-* | ns32k-* \ | open8-* \ | orion-* \ @@ -798,7 +796,7 @@ case $basic_machine in os=-mingw64 ;; mingw32) - basic_machine=i386-pc + basic_machine=i686-pc os=-mingw32 ;; mingw32ce) @@ -834,7 +832,7 @@ case $basic_machine in basic_machine=`echo $basic_machine | sed -e 's/ms1-/mt-/'` ;; msys) - basic_machine=i386-pc + basic_machine=i686-pc os=-msys ;; mvs) @@ -1550,6 +1548,9 @@ case $basic_machine in c4x-* | tic4x-*) os=-coff ;; + c8051-*) + os=-elf + ;; hexagon-*) os=-elf ;; @@ -1593,6 +1594,9 @@ case $basic_machine in mips*-*) os=-elf ;; + or1k-*) + os=-elf + ;; or32-*) os=-coff ;; diff --git a/config/ChangeLog b/config/ChangeLog index 68b911932a283..b82548b4f92be 100644 --- a/config/ChangeLog +++ b/config/ChangeLog @@ -1,3 +1,32 @@ +2015-06-23 Release Manager + + * GCC 4.8.5 released. + +2014-12-19 Release Manager + + * GCC 4.8.4 released. + +2014-07-26 Uros Bizjak + + PR target/47230 + * mh-alpha-linux: New file. + +2014-05-22 Release Manager + + * GCC 4.8.3 released. + +2013-10-16 Release Manager + + * GCC 4.8.2 released. + +2013-05-31 Release Manager + + * GCC 4.8.1 released. + +2013-03-22 Release Manager + + * GCC 4.8.0 released. + 2013-02-25 H.J. Lu * bootstrap-asan.mk (POSTSTAGE1_LDFLAGS): Add diff --git a/config/mh-alpha-linux b/config/mh-alpha-linux new file mode 100644 index 0000000000000..9a9244baaa364 --- /dev/null +++ b/config/mh-alpha-linux @@ -0,0 +1,3 @@ +# Prevent GPREL16 relocation truncation +LDFLAGS += -Wl,--no-relax +BOOT_LDFLAGS += -Wl,--no-relax diff --git a/configure b/configure index d809535ed0aaf..80cf60626b9b0 100755 --- a/configure +++ b/configure @@ -3834,6 +3834,9 @@ fi *-mingw*) host_makefile_frag="config/mh-mingw" ;; + alpha*-linux*) + host_makefile_frag="config/mh-alpha-linux" + ;; hppa*-hp-hpux10*) host_makefile_frag="config/mh-pa-hpux10" ;; @@ -5939,6 +5942,104 @@ $as_echo "$gcc_cv_isl" >&6; } fi + if test "${gcc_cv_isl}" = no ; then + + if test "${ENABLE_ISL_CHECK}" = yes ; then + _isl_saved_CFLAGS=$CFLAGS + _isl_saved_LDFLAGS=$LDFLAGS + _isl_saved_LIBS=$LIBS + + CFLAGS="${_isl_saved_CFLAGS} ${islinc} ${gmpinc}" + LDFLAGS="${_isl_saved_LDFLAGS} ${isllibs}" + LIBS="${_isl_saved_LIBS} -lisl" + + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for version 0.12 of ISL" >&5 +$as_echo_n "checking for version 0.12 of ISL... " >&6; } + if test "$cross_compiling" = yes; then : + gcc_cv_isl=yes +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include + #include +int +main () +{ +if (strncmp (isl_version (), "isl-0.12", strlen ("isl-0.12")) != 0) + return 1; + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_run "$LINENO"; then : + gcc_cv_isl=yes +else + gcc_cv_isl=no +fi +rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext \ + conftest.$ac_objext conftest.beam conftest.$ac_ext +fi + + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $gcc_cv_isl" >&5 +$as_echo "$gcc_cv_isl" >&6; } + + CFLAGS=$_isl_saved_CFLAGS + LDFLAGS=$_isl_saved_LDFLAGS + LIBS=$_isl_saved_LIBS + fi + + + if test "${gcc_cv_isl}" = no ; then + + if test "${ENABLE_ISL_CHECK}" = yes ; then + _isl_saved_CFLAGS=$CFLAGS + _isl_saved_LDFLAGS=$LDFLAGS + _isl_saved_LIBS=$LIBS + + CFLAGS="${_isl_saved_CFLAGS} ${islinc} ${gmpinc}" + LDFLAGS="${_isl_saved_LDFLAGS} ${isllibs}" + LIBS="${_isl_saved_LIBS} -lisl" + + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for version 0.14 of ISL" >&5 +$as_echo_n "checking for version 0.14 of ISL... " >&6; } + if test "$cross_compiling" = yes; then : + gcc_cv_isl=yes +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include + #include +int +main () +{ +if (strncmp (isl_version (), "isl-0.14", strlen ("isl-0.14")) != 0) + return 1; + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_run "$LINENO"; then : + gcc_cv_isl=yes +else + gcc_cv_isl=no +fi +rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext \ + conftest.$ac_objext conftest.beam conftest.$ac_ext +fi + + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $gcc_cv_isl" >&5 +$as_echo "$gcc_cv_isl" >&6; } + + CFLAGS=$_isl_saved_CFLAGS + LDFLAGS=$_isl_saved_LDFLAGS + LIBS=$_isl_saved_LIBS + fi + + + fi + fi fi diff --git a/configure.ac b/configure.ac index 48ec1aae6b409..90221a706ec13 100644 --- a/configure.ac +++ b/configure.ac @@ -1154,6 +1154,9 @@ case "${host}" in *-mingw*) host_makefile_frag="config/mh-mingw" ;; + alpha*-linux*) + host_makefile_frag="config/mh-alpha-linux" + ;; hppa*-hp-hpux10*) host_makefile_frag="config/mh-pa-hpux10" ;; @@ -1630,6 +1633,12 @@ if test "x$with_isl" != "xno" && ISL_CHECK_VERSION(0,10) if test "${gcc_cv_isl}" = no ; then ISL_CHECK_VERSION(0,11) + if test "${gcc_cv_isl}" = no ; then + ISL_CHECK_VERSION(0,12) + if test "${gcc_cv_isl}" = no ; then + ISL_CHECK_VERSION(0,14) + fi + fi fi dnl Only execute fail-action, if ISL has been requested. ISL_IF_FAILED([ diff --git a/contrib/ChangeLog b/contrib/ChangeLog index 4339d3c2dddd4..b8cea11addc4a 100644 --- a/contrib/ChangeLog +++ b/contrib/ChangeLog @@ -1,3 +1,39 @@ +2015-06-23 Release Manager + + * GCC 4.8.5 released. + +2014-12-19 Release Manager + + * GCC 4.8.4 released. + +2014-07-07 Richard Biener + + * gennews: Use gcc-3.0/index.html. + +2014-05-22 Release Manager + + * GCC 4.8.3 released. + +2013-10-21 Mike Stump + + * gcc_update (configure): Update to handle svn 1.8.1. + +2013-10-16 Release Manager + + * GCC 4.8.2 released. + +2013-05-31 Release Manager + + * GCC 4.8.1 released. + +2013-03-22 Release Manager + + * GCC 4.8.0 released. + +2013-03-22 Jakub Jelinek + + * gennews (files): Add files for GCC 4.8. + 2013-03-06 Tobias Burnus * make-obstacks-texi.pl: New. @@ -33,7 +69,7 @@ * update-copyright.py: New file. -2013-01-15 David Blaikie +2013-01-15 David Blaikie * dg-extract-results.sh: Handle KPASSes. @@ -289,8 +325,8 @@ * repro_fail: Add --debug and --debug-tui flags. -2012-02-02 Sumanth G - Jayant R Sonar +2012-02-02 Sumanth G + Jayant R Sonar * config-list.mk (LIST): Add cr16-elf. @@ -708,7 +744,7 @@ * compare-debug: New. 2007-08-16 H.J. Lu - Andreas Schwab + Andreas Schwab * gcc_update: Use "svn info" for revision number. Create gcc/REVISION with branch name and revision number. @@ -849,7 +885,7 @@ * gcc_build: Remove -d from the call to gcc_update. 2005-10-28 Daniel Berlin - Ben Elliston + Ben Elliston * gcc_update: Update for svn. * newcvsroot: Ditto. @@ -951,7 +987,7 @@ * gcc_update: libjava/configure.in -> configure.ac. -2004-08-03 Richard Earnshaw +2004-08-03 Richard Earnshaw * gcc_update: gcc/config/arm/arm-tune.md -> arm-cores.def gentune.sh. @@ -1118,7 +1154,7 @@ gcc/testsuite/gcc.dg/cpp/_Pragma3.c depends on gcc/testsuite/gcc.dg/cpp/mi1c.h. -2003-05-23 Nathanael Nerode +2003-05-23 Nathanael Nerode * paranoia.cc: Fix spelling error. @@ -1133,7 +1169,7 @@ * test_summary: Add -h, print existing comments as help. -2003-03-03 H.J. Lu +2003-03-03 H.J. Lu * gcc_build: Use $GCC_CVS/$CVS instead of cvs. * gcc_update: Likewise. @@ -1216,7 +1252,7 @@ * enquire.c: Move from gcc. -2002-07-16 H.J. Lu +2002-07-16 H.J. Lu * gcc_update (touch_files): Pass -s to ${MAKE}. @@ -1289,7 +1325,7 @@ and @center. Allow [a-z] after @enumerate. Handle 0 and numbers greater than 9 in enumerations. -2001-11-07 Laurent Guerby +2001-11-07 Laurent Guerby * gcc_update (files_and_dependencies): Add Ada dependencies. @@ -1304,7 +1340,7 @@ gcc/java/parse-scan.c and gcc/java/keyword.h to list of files to touch. -2001-09-04 David.Billinghurst +2001-09-04 David.Billinghurst * gcc_update: (files_and_dependencies) Add gcc/java/parse.c gcc/java/parse-scan.c and gcc/java/keyword.h to list of files to @@ -1331,7 +1367,7 @@ Fri Jul 27 18:01:21 CEST 2001 Jan Hubicka * gcc_update: Dump timestamp in LAST_UPDATED. 2001-07-26 Andreas Jaeger , - Hans-Peter Nilsson + Hans-Peter Nilsson * analyze_brprob: Fix documentation. @@ -1355,7 +1391,7 @@ Mon Jul 23 15:47:19 CEST 2001 Jan Hubicka * gcc_update: Remove entries for gcc.1, cpp.1, gcov.1. -2001-07-01 Zoltan Felleg +2001-07-01 Zoltan Felleg * warn_summary: Fix typo in a comment. @@ -1630,7 +1666,7 @@ Sun Jul 16 12:04:33 2000 Mark P Mitchell * index-prop: Use a single pattern. Also support *** cdiffs. -2000-04-28 Pavel Roskin +2000-04-28 Pavel Roskin * index-prop: Don't change /dev/null. @@ -1656,7 +1692,7 @@ Sun Nov 28 00:41:44 1999 William Bader (william@nscs.fast.net) * gcc_update: Allow patches compressed by bzip2. -1999-10-11 Martin v. Löwis +1999-10-11 Martin v. Löwis * newcvsroot: New file. @@ -1693,7 +1729,7 @@ Sun Nov 28 00:41:44 1999 William Bader (william@nscs.fast.net) * test_summary: Replace egcs with gcc. Update e-mail address. 1999-07-05 Gerald Pfeifer - Jerry Quinn + Jerry Quinn * egcs_update (touch_files, apply_patch): New functions. Use them. New command-line option --patch. Split test of local @@ -1789,7 +1825,7 @@ Fri Oct 30 00:39:27 1998 Jeffrey A Law (law@cygnus.com) * egcs_update: Do touch java/parse.c and java/parse-scan.c. They're in the repo again. -Fri Oct 16 07:35:00 1998 Bruce Korb +Fri Oct 16 07:35:00 1998 Bruce Korb * egcs_update: Added gcc/fixinc/* generated files to touch list. @@ -1812,7 +1848,7 @@ Mon Oct 5 14:19:48 1998 Kaveh R. Ghazi keywords that are preserved in the "warning type" summary and tighten up the "arg ???" regexp. -Tue Sep 22 07:30 Bruce Korb +Tue Sep 22 07:30 Bruce Korb * fixinc/inclhack.def: Not all C++ comments in C headers were treated alike. They are now. Also fixed syntax @@ -1826,7 +1862,7 @@ Wed Sep 16 16:06:51 1998 Kaveh R. Ghazi * egcs_update: Additionally touch gcc/java/parse.[ch]. -Thu Sep 9 16:48 Bruce Korb +Thu Sep 9 16:48 Bruce Korb * fixinc/inclhack.def: Added two files required by SCO's Open Server 5's avoid_bool fix. @@ -1857,7 +1893,7 @@ Tue Aug 11 17:33:19 1998 Gerald Pfeifer * egcs_update: New script. -1998-08-05 Bruce Korb +1998-08-05 Bruce Korb * fixinc/Makefile Added define for target machine so machine-specific tests @@ -1890,7 +1926,7 @@ Mon Jul 27 20:33:02 1998 Gerald Pfeifer * test_summary: Corrected script name in comments providing documentation. Added linebreaks for lines with > 80 characters. -Fri Jun 19 02:36:59 1998 Alexandre Oliva +Fri Jun 19 02:36:59 1998 Alexandre Oliva * test_summary: New switch, -i, and environment variable, append_logs, for including files in the report. @@ -1900,7 +1936,7 @@ Fri Jun 19 02:36:59 1998 Alexandre Oliva * warn_summary: Update to Kaveh's latest version allowing to specify the last stage built. -1998-05-29 Bruce Korb +1998-05-29 Bruce Korb * fixinc/mkfixinc.sh Changes to make it easier to invoke on platforms that @@ -1910,7 +1946,7 @@ Fri Jun 19 02:36:59 1998 Alexandre Oliva Applied fixes from egcs/gcc/fixincludes from the past several months. -1998-05-28 Bruce Korb +1998-05-28 Bruce Korb * fixinc/*: Updated most everything for a first real try at getting "fast_fixincludes" working. diff --git a/contrib/gcc_update b/contrib/gcc_update index 10a5970f6214e..212a99fc7d9fc 100755 --- a/contrib/gcc_update +++ b/contrib/gcc_update @@ -382,7 +382,7 @@ case $vcs_type in fi revision=`$GCC_SVN info | awk '/Revision:/ { print $2 }'` - branch=`$GCC_SVN info | sed -ne "/URL:/ { + branch=`$GCC_SVN info | sed -ne "/^URL:/ { s,.*/trunk,trunk, s,.*/branches/,, s,.*/tags/,, diff --git a/contrib/gennews b/contrib/gennews index 524415a686975..294e660cff805 100755 --- a/contrib/gennews +++ b/contrib/gennews @@ -24,6 +24,7 @@ website=http://gcc.gnu.org/ files=" + gcc-4.8/index.html gcc-4.8/changes.html gcc-4.7/index.html gcc-4.7/changes.html gcc-4.6/index.html gcc-4.6/changes.html gcc-4.5/index.html gcc-4.5/changes.html @@ -36,7 +37,7 @@ files=" gcc-3.3/index.html gcc-3.3/changes.html gcc-3.2/index.html gcc-3.2/changes.html gcc-3.1/index.html gcc-3.1/changes.html - gcc-3.0/gcc-3.0.html gcc-3.0/features.html gcc-3.0/caveats.html + gcc-3.0/index.html gcc-3.0/features.html gcc-3.0/caveats.html gcc-2.95/index.html gcc-2.95/features.html gcc-2.95/caveats.html egcs-1.1/index.html egcs-1.1/features.html egcs-1.1/caveats.html egcs-1.0/index.html egcs-1.0/features.html egcs-1.0/caveats.html" diff --git a/contrib/reghunt/ChangeLog b/contrib/reghunt/ChangeLog index af27b8f97c4c9..5e63e57785673 100644 --- a/contrib/reghunt/ChangeLog +++ b/contrib/reghunt/ChangeLog @@ -1,3 +1,27 @@ +2015-06-23 Release Manager + + * GCC 4.8.5 released. + +2014-12-19 Release Manager + + * GCC 4.8.4 released. + +2014-05-22 Release Manager + + * GCC 4.8.3 released. + +2013-10-16 Release Manager + + * GCC 4.8.2 released. + +2013-05-31 Release Manager + + * GCC 4.8.1 released. + +2013-03-22 Release Manager + + * GCC 4.8.0 released. + 2010-06-27 Ralf Wildenhues * bin/gcc-svn-ids: Fix unportable shell quoting. diff --git a/contrib/regression/ChangeLog b/contrib/regression/ChangeLog index a4194276aa329..04c19794c26c3 100644 --- a/contrib/regression/ChangeLog +++ b/contrib/regression/ChangeLog @@ -1,3 +1,27 @@ +2015-06-23 Release Manager + + * GCC 4.8.5 released. + +2014-12-19 Release Manager + + * GCC 4.8.4 released. + +2014-05-22 Release Manager + + * GCC 4.8.3 released. + +2013-10-16 Release Manager + + * GCC 4.8.2 released. + +2013-05-31 Release Manager + + * GCC 4.8.1 released. + +2013-03-22 Release Manager + + * GCC 4.8.0 released. + 2012-08-26 Hans-Peter Nilsson * btest-gcc.sh (TESTLOGS): Make gfortran.sum optional. diff --git a/fixincludes/ChangeLog b/fixincludes/ChangeLog index 88aa56368a9d3..b361618ef95fd 100644 --- a/fixincludes/ChangeLog +++ b/fixincludes/ChangeLog @@ -1,3 +1,47 @@ +2015-06-23 Release Manager + + * GCC 4.8.5 released. + +2014-12-19 Release Manager + + * GCC 4.8.4 released. + +2014-12-13 David Edelsohn + + Backport from mainline: + 2013-09-02 David Edelsohn + + * inclhack.def (aix_assert): New fix. + * fixincl.x: Regenerate. + * tests/base/assert.h [AIX_ASSERT_CHECK]: New check. + +2014-05-22 Release Manager + + * GCC 4.8.3 released. + +2013-10-16 Release Manager + + * GCC 4.8.2 released. + +2013-05-31 Rainer Orth + + Backport from mainline: + 2013-05-17 Rainer Orth + + * inclhack.def (solaris_pow_int_overload): Update comment. + Change guard to match . + * fixincl.x: Regenerate. + * tests/base/iso/math_iso.h [SOLARIS_POW_INT_OVERLOAD_CHECK]: + Matching change. + +2013-05-31 Release Manager + + * GCC 4.8.1 released. + +2013-03-22 Release Manager + + * GCC 4.8.0 released. + 2013-01-16 Alexandre Oliva * inclhack.def (feraiseexcept_nosse_invalid): New. diff --git a/fixincludes/fixincl.x b/fixincludes/fixincl.x index 29fc52abf4578..ad324a386062e 100644 --- a/fixincludes/fixincl.x +++ b/fixincludes/fixincl.x @@ -2,11 +2,11 @@ * * DO NOT EDIT THIS FILE (fixincl.x) * - * It has been AutoGen-ed Saturday December 29, 2012 at 09:17:09 AM BRST + * It has been AutoGen-ed December 13, 2014 at 05:31:32 AM by AutoGen 5.12 * From the definitions inclhack.def * and the template file fixincl */ -/* DO NOT SVN-MERGE THIS FILE, EITHER Sat Dec 29 09:17:10 BRST 2012 +/* DO NOT SVN-MERGE THIS FILE, EITHER Sat Dec 13 05:31:32 PST 2014 * * You must regenerate it. Use the ./genfixes script. * @@ -15,7 +15,7 @@ * certain ANSI-incompatible system header files which are fixed to work * correctly with ANSI C and placed in a directory that GNU C will search. * - * This file contains 226 fixup descriptions. + * This file contains 227 fixup descriptions. * * See README for more information. * @@ -734,6 +734,45 @@ static const char* apzAab_Vxworks_UnistdPatch[] = { #endif /* _UNISTD_H */", (char*)NULL }; +/* * * * * * * * * * * * * * * * * * * * * * * * * * + * + * Description of Aix_Assert fix + */ +tSCC zAix_AssertName[] = + "aix_assert"; + +/* + * File name selection pattern + */ +tSCC zAix_AssertList[] = + "assert.h\0"; +/* + * Machine/OS name selection pattern + */ +tSCC* apzAix_AssertMachs[] = { + "*-*-aix*", + (const char*)NULL }; + +/* + * content selection pattern - do fix if pattern found + */ +tSCC zAix_AssertSelect0[] = + "#define[ \t]static_assert[ \t]_Static_assert"; + +#define AIX_ASSERT_TEST_CT 1 +static tTestDesc aAix_AssertTests[] = { + { TT_EGREP, zAix_AssertSelect0, (regex_t*)NULL }, }; + +/* + * Fix Command Arguments for Aix_Assert + */ +static const char* apzAix_AssertPatch[] = { + "format", + "#ifndef __cplusplus\n\ +%0\n\ +#endif", + (char*)NULL }; + /* * * * * * * * * * * * * * * * * * * * * * * * * * * * Description of Aix_Complex fix @@ -6663,7 +6702,7 @@ static tTestDesc aSolaris_Pow_Int_OverloadTests[] = { */ static const char* apzSolaris_Pow_Int_OverloadPatch[] = { "format", - "#ifndef __GXX_EXPERIMENTAL_CXX0X__\n\ + "#if __cplusplus < 201103L\n\ %0\n\ #endif", (char*)NULL }; @@ -9265,9 +9304,9 @@ static const char* apzFeraiseexcept_Nosse_DivbyzeroPatch[] = { * * List of all fixes */ -#define REGEX_COUNT 264 +#define REGEX_COUNT 265 #define MACH_LIST_SIZE_LIMIT 187 -#define FIX_COUNT 226 +#define FIX_COUNT 227 /* * Enumerate the fixes @@ -9285,6 +9324,7 @@ typedef enum { AAB_VXWORKS_REGS_VXTYPES_FIXIDX, AAB_VXWORKS_STDINT_FIXIDX, AAB_VXWORKS_UNISTD_FIXIDX, + AIX_ASSERT_FIXIDX, AIX_COMPLEX_FIXIDX, AIX_MALLOC_FIXIDX, AIX_NET_IF_ARP_FIXIDX, @@ -9562,6 +9602,11 @@ tFixDesc fixDescList[ FIX_COUNT ] = { AAB_VXWORKS_UNISTD_TEST_CT, FD_MACH_ONLY | FD_REPLACEMENT, aAab_Vxworks_UnistdTests, apzAab_Vxworks_UnistdPatch, 0 }, + { zAix_AssertName, zAix_AssertList, + apzAix_AssertMachs, + AIX_ASSERT_TEST_CT, FD_MACH_ONLY | FD_SUBROUTINE, + aAix_AssertTests, apzAix_AssertPatch, 0 }, + { zAix_ComplexName, zAix_ComplexList, apzAix_ComplexMachs, AIX_COMPLEX_TEST_CT, FD_MACH_ONLY | FD_SUBROUTINE, diff --git a/fixincludes/inclhack.def b/fixincludes/inclhack.def index 24069201d1220..66d4f2b731536 100644 --- a/fixincludes/inclhack.def +++ b/fixincludes/inclhack.def @@ -574,6 +574,19 @@ fix = { _EndOfHeader_; }; +/* + * assert.h on AIX 7 redefines static_assert as _Static_assert without + * protecting C++. + */ +fix = { + hackname = aix_assert; + mach = "*-*-aix*"; + files = assert.h; + select = "#define[ \t]static_assert[ \t]_Static_assert"; + c_fix = format; + c_fix_arg = "#ifndef __cplusplus\n%0\n#endif"; + test_text = "#define static_assert _Static_assert"; +}; /* * complex.h on AIX 5 and AIX 6 define _Complex_I and I in terms of __I, @@ -3447,7 +3460,7 @@ fix = { /* - * The pow overloads with int were removed in C++ 2011. + * The pow overloads with int were removed in C++ 2011 DR 550. */ fix = { hackname = solaris_pow_int_overload; @@ -3456,7 +3469,7 @@ fix = { select = "^[ \t]*inline [a-z ]* pow\\([^()]*, int [^()]*\\)" " *\\{[^{}]*\n[^{}]*\\}"; c_fix = format; - c_fix_arg = "#ifndef __GXX_EXPERIMENTAL_CXX0X__\n%0\n#endif"; + c_fix_arg = "#if __cplusplus < 201103L\n%0\n#endif"; test_text = " inline long double pow(long double __X, int __Y) { return\n" diff --git a/fixincludes/tests/base/assert.h b/fixincludes/tests/base/assert.h index 2642cbe49c4bf..19dc52575ee15 100644 --- a/fixincludes/tests/base/assert.h +++ b/fixincludes/tests/base/assert.h @@ -19,6 +19,13 @@ #include +#if defined( AIX_ASSERT_CHECK ) +#ifndef __cplusplus +#define static_assert _Static_assert +#endif +#endif /* AIX_ASSERT_CHECK */ + + #if defined( ALPHA___ASSERT_CHECK ) extern void __assert(const char *, const char *, int); #endif /* ALPHA___ASSERT_CHECK */ diff --git a/fixincludes/tests/base/iso/math_iso.h b/fixincludes/tests/base/iso/math_iso.h index 6c08a94bb54d2..a1313a7f493b7 100644 --- a/fixincludes/tests/base/iso/math_iso.h +++ b/fixincludes/tests/base/iso/math_iso.h @@ -10,7 +10,7 @@ #if defined( SOLARIS_POW_INT_OVERLOAD_CHECK ) -#ifndef __GXX_EXPERIMENTAL_CXX0X__ +#if __cplusplus < 201103L inline long double pow(long double __X, int __Y) { return __powl(__X, (long double) (__Y)); } #endif diff --git a/gcc/BASE-VER b/gcc/BASE-VER index 88f181192c438..bb6ebd31d520c 100644 --- a/gcc/BASE-VER +++ b/gcc/BASE-VER @@ -1 +1 @@ -4.8.0 +4.8.5 diff --git a/gcc/ChangeLog b/gcc/ChangeLog index e94d20db947cb..1c8d1ebf1a6ff 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9889 @@ +2015-06-23 Ludovic Courtès + + PR 65711 + * config/arm/linux-elf.h (LINUX_TARGET_LINK_SPEC): Move + '-dynamic-linker' within %{!shared: ...}. + +2015-06-23 Release Manager + + * GCC 4.8.5 released. + +2015-06-23 Richard Biener + + * cpp.texi: Update displayed copyright years. + * cppinternals.texi: Likewise. + * gcc.texi: Likewise. + * gccint.texi: Likewise. + * gcov.texi: Likewise. + * install.texi: Likewise. + * invoke.texi: Likewise. + * gcc.c: Likewise. + * gcov-dump.c: Likewise. + * gcov.c: Likewise. + +2015-06-18 Richard Biener + + Backport from mainline + 2014-12-04 Marek Polacek + + PR middle-end/56917 + * fold-const.c (fold_unary_loc): Perform the negation in A's type + when transforming ~ (A - 1) or ~ (A + -1) to -A. + +2015-06-18 Jakub Jelinek + + PR tree-optimization/66233 + * fold-const.c (fold_unary_loc): Don't handle vector types. + Simplify. + * tree-ssa-forwprop.c (combine_conversions): Likewise. + +2015-06-16 Richard Biener + + Revert + 2015-06-01 Richard Biener + + Backport from mainline + 2015-05-26 Michael Matz + + PR middle-end/66251 + * tree-vect-stmts.c (vect_create_vectorized_demotion_stmts): Always set + STMT_VINFO_VEC_STMT, also with SLP. + + 2015-05-22 Richard Biener + + PR tree-optimization/66251 + * tree-vect-stmts.c (vectorizable_conversion): Properly + set STMT_VINFO_VEC_STMT even for the SLP case. + +2015-06-16 Christophe Lyon + + Backported from mainline r217076. + 2014-11-04 Michael Collison + + * config/aarch64/iterators.md (lconst_atomic): New mode attribute + to support constraints for CONST_INT in atomic operations. + * config/aarch64/atomics.md + (atomic_): Use lconst_atomic constraint. + (atomic_nand): Likewise. + (atomic_fetch_): Likewise. + (atomic_fetch_nand): Likewise. + (atomic__fetch): Likewise. + (atomic_nand_fetch): Likewise. + +2015-06-12 Michael Matz + + Backported from mainline + 2014-10-23 Jakub Jelinek + + PR debug/63623 + * var-tracking.c (stack_adjust_offset_pre_post_cb): New function. + (stack_adjust_offset_pre_post): Use it through for_each_inc_dec, + instead of only handling autoinc in dest if it is a MEM. + +2015-06-12 Jakub Jelinek + + Backported from mainline + 2014-12-15 Vladimir Makarov + + PR target/62642 + * ira.c (rtx_moveable_p): Prevent UNSPEC_VOLATILE moves. + +2015-06-12 Jakub Jelinek + + PR middle-end/63608 + Backported from mainline + 2014-05-16 Eric Botcazou + + * fold-const (fold_unary_loc) : New case. + : Pass arg0 instead of op0 to fold_convert_const. + +2015-06-11 John David Anglin + + * config/pa/pa.c (pa_output_global_address): Handle LABEL_REF plus + CONST_INT for goto. + +2015-06-11 Richard Biener + + Backport from mainline, guarded with in_lto_p + 2015-06-02 Richard Biener + + PR debug/65549 + * dwarf2out.c (lookup_context_die): New function. + (resolve_addr): Avoid forcing a full DIE for the + target of a DW_TAG_GNU_call_site during late compilation. + Instead create a stub DIE without a type if we have a + context DIE present. + + Backport from mainline + 2014-04-04 Jan Hubicka + + PR ipa/59626 + * ipa.c (process_references, symtab_remove_unreachable_nodes): + Drop bodies of always inline after early inlining. + (symtab_remove_unreachable_nodes): Remove always_inline attribute. + +2015-06-10 Michael Meissner + + Backport from mainline: + 2015-06-10 Michael Meissner + + PR target/66474 + * doc/md.texi (Machine Constraints): Document that on the PowerPC + if you use a constraint that targets a VSX register, you must use + %x in the template. + +2015-06-10 Richard Biener + + Backport from mainline + 2014-04-04 Cong Hou + + PR tree-optimization/60656 + * tree-vect-stmts.c (supportable_widening_operation): + Fix a bug that elements in a vector with vect_used_by_reduction + property are incorrectly reordered when the operation on it is not + consistant with the one in reduction operation. + + 2014-01-31 Richard Biener + + PR middle-end/59990 + * builtins.c (fold_builtin_memory_op): Make sure to not + use a floating-point mode or a boolean or enumeral type for + the copy operation. + +2015-06-10 Jakub Jelinek + + PR target/66470 + * config/i386/i386.c (ix86_split_long_move): For collisions + involving direct tls segment refs, move the UNSPEC_TP possibly + wrapped in ZERO_EXTEND out of the address for lea, to each of + the memory loads. + +2015-06-08 Uros Bizjak + + Backport from mainline: + 2015-06-03 Uros Bizjak + + PR target/66275 + * config/i386/i386.c (ix86_function_arg_regno): Use ix86_cfun_abi + to determine current function ABI. + (ix86_function_value_regno_p): Ditto. + +2015-06-05 Venkataramanan Kumar + + * config/i386/sse.md (sse3_mwait): Swap the operand constriants. + +2015-06-03 Jakub Jelinek + + Backported from mainline + 2015-05-13 Jakub Jelinek + + PR middle-end/66133 + * omp-low.c (expand_omp_taskreg): For GIMPLE_OMP_TASK expansion, + make sure it is never noreturn, even when the task body does not + return. + (lower_omp_taskreg): For GIMPLE_OMP_TASK, emit GIMPLE_OMP_CONTINUE + right before GIMPLE_OMP_RETURN. + * tree-cfg.c (make_edges): Accept GIMPLE_OMP_CONTINUE as ->cont + for GIMPLE_OMP_TASK. For GIMPLE_OMP_RETURN corresponding to + GIMPLE_OMP_TASK add an EDGE_ABNORMAL edge from entry to exit. + + 2015-04-07 Jakub Jelinek + + PR middle-end/65680 + * expr.c (get_inner_reference): Handle bit_offset that doesn't fit + into signed HOST_WIDE_INT the same as negative bit_offset. + + 2015-03-10 Jakub Jelinek + + PR target/65368 + * config/i386/i386.md (bmi2_bzhi_3): Removed define_insn, + new define_expand. + (*bmi2_bzhi_3, *bmi2_bzhi_3_1): New define_insns. + + 2015-02-18 Jakub Jelinek + + PR gcov-profile/64634 + * tree-eh.c (frob_into_branch_around): Fix up typos + in function comment. + (lower_catch): Put eh_seq resulting from EH lowering of + the cleanup sequence after the cleanup rather than before + it. + +2015-06-03 Richard Biener + + Backport from mainline + 2015-05-26 Michael Matz + + PR middle-end/66251 + * tree-vect-stmts.c (vect_create_vectorized_demotion_stmts): Always set + STMT_VINFO_VEC_STMT, also with SLP. + + 2015-05-22 Richard Biener + + PR tree-optimization/66251 + * tree-vect-stmts.c (vectorizable_conversion): Properly + set STMT_VINFO_VEC_STMT even for the SLP case. + + 2015-03-23 Richard Biener + + PR tree-optimization/65518 + * tree-vect-stmts.c (vectorizable_load): Reject single-element + interleaving cases we generate absymal code for. + + 2015-05-13 Richard Biener + + PR tree-optimization/66123 + * tree-ssa-dom.c (propagate_rhs_into_lhs): Check if we found + a taken edge. + + 2015-05-27 Richard Biener + + PR tree-optimization/66272 + Revert parts of + 2014-08-15 Richard Biener + + PR tree-optimization/62031 + * tree-data-ref.c (dr_analyze_indices): Do not set + DR_UNCONSTRAINED_BASE. + (dr_may_alias_p): All indirect accesses have to go the + formerly DR_UNCONSTRAINED_BASE path. + * tree-data-ref.h (struct indices): Remove + unconstrained_base member. + (DR_UNCONSTRAINED_BASE): Remove. + +2015-06-01 Dominik Vogt + + Backport from mainline + 2015-05-29 Dominik Vogt + + PR target/66215 + * config/s390/s390.c (s390_reorg): Fix placement of post-label NOPs + with -mhotpatch=. + +2015-05-28 Mike Frysinger + + * config/microblaze/linux.h (CPP_SPEC): Define. + +2015-05-28 Mike Frysinger + + * config/pa/pa-linux.h (CPP_SPEC): Change so -D_REENTRANT is used when + -pthread is specified. + +2015-05-27 John David Anglin + + PR target/66148 + * config/pa/pa.c (pa_emit_move_sequence): Correct placement of + REG_EQUAL note when doing insert. + +2015-05-26 Rohit Arul Raj + + Backported from mainline + 2015-05-14 Rohit Arul Raj + + * varasm.c (output_constant_pool_1): Pass down alignment from + constant pool entry's descriptor to output_constant_pool_2. + (output_object_block): Add comment prior to call to + output_constant_pool_1. + +2015-05-21 Sandra Loosemore + + Backport from mainline r223418: + * config.gcc [powerpc*-*-linux*]: Allow --enable-targets=all + to build a biarch toolchain again. + +2015-05-19 Andreas Krebbel + + * doc/invoke.texi: Add missing cpu types for march option: z196 + and zEC12. + +2015-05-18 Andreas Krebbel + + Backport from mainline + 2015-05-12 Andreas Krebbel + + * config/s390/2827.md: Split zEC12_simple into zEC12_simple_int + and zEC12_simple_fp. + * config/s390/s390.c (s390_issue_rate): Set issue rate for zEC12 + to 1. + +2015-05-16 Uros Bizjak + + PR target/66140 + * config/alpha/alpha.c (get_aligned_mem): Also look for reload + replacements in memory addresses. + (get_unaligned_address): Ditto. + +2015-05-11 Michael Meissner + + * config/rs6000/rs6000.opt (-mcompat-align-parm): Reset initial + value that was modified by accident in my last change. + +2015-05-05 Shanyao Chen + + Backported from mainline + 2015-01-19 Jiong Wang + Andrew Pinski + + PR target/64304 + * config/aarch64/aarch64.md (define_insn "*ashl3_insn"): Deleted. + (ashl3): Don't expand if operands[2] is not constant. + +2015-05-05 Peter Bergner + + Backport from mainline. + 2015-04-27 Peter Bergner + + PR target/64579 + * config/rs6000/htm.md: Remove all define_expands. + (UNSPECV_HTM_TABORTDC, UNSPECV_HTM_TABORTDCI, UNSPECV_HTM_TABORTWC, + UNSPECV_HTM_TABORTWCI): Remove. + (UNSPECV_HTM_TABORTXC, UNSPECV_HTM_TABORTXCI, UNSPECV_HTM_TTEST): New. + (tabort_internal, tbegin_internal, tcheck_internal, tend_internal, + trechkpt_internal, treclaim_internal, tsr_internal): Rename from this... + (tabort, tbegin, tcheck, tend, trechkpt, treclaim, tsr): ...to this. + (tabortdc_internal, tabortdci_internal, tabortwc_internal, + tabortwci_internal): Remove define_insns. + (tabortc, tabortci): New define_insns. + (tabort): Use gpc_reg_operand. + (tcheck): Remove operand. + (htm_mfspr_, htm_mtspr_): Use GPR mode macro. + * config/rs6000/htmxlintrin.h (__TM_end): Use _HTM_TRANSACTIONAL as + expected value. + * config/rs6000/rs6000-builtin.def (BU_HTM_SPR0): Remove. + (BU_HTM_SPR1): Rename to BU_HTM_V1. Remove use of RS6000_BTC_SPR. + (tabort, tabortdc, tabortdci, tabortwc, tabortwci, tbegin, + tcheck, tend, tendall, trechkpt, treclaim, tresume, tsuspend, + tsr, ttest): Pass in the RS6000_BTC_CR attribute. + (get_tfhar, set_tfhar, get_tfiar, set_tfiar, get_texasr, set_texasr, + get_texasru, set_texasru): Pass in the RS6000_BTC_SPR attribute. + (tcheck): Remove builtin argument. + * config/rs6000/rs6000.c (rs6000_htm_spr_icode): Use TARGET_POWERPC64 + not TARGET_64BIT. + (htm_expand_builtin): Fix usage of expandedp. Disallow usage of the + tabortdc and tabortdci builtins when not in 64-bit mode. + Modify code to handle the loss of the HTM define_expands. + Emit code to copy the CR register to TARGET. + (htm_init_builtins): Modify code to handle the loss of the HTM + define_expands. + * config/rs6000/rs6000.h (RS6000_BTC_32BIT): Delete. + (RS6000_BTC_64BIT): Likewise. + (RS6000_BTC_CR): New macro. + * doc/extend.texi: Update documentation for htm builtins. + +2015-04-30 Marek Polacek + + Backported from mainline + 2014-12-03 Martin Jambor + + PR ipa/64153 + * ipa-inline-analysis.c (evaluate_conditions_for_known_args): Check + type sizes before view_converting. + + 2014-12-01 Martin Jambor + + PR ipa/63551 + * ipa-inline-analysis.c (evaluate_conditions_for_known_args): Convert + value of the argument to the type of the value in the condition. + +2015-04-24 Bill Schmidt + + Backport from mainline r222385 + 2015-04-23 Bill Schmidt + + * config/rs6000/altivec.md (*altivec_lvx__internal): Remove + asterisk from name so this can be generated directly. + (*altivec_stvx__internal): Likewise. + * config/rs6000/rs6000.c (rs6000_emit_le_vsx_store): Add assert + that this is never called during or after reload/lra. + (rs6000_frame_related): Remove split_reg + argument and logic that references it. + (emit_frame_save): Remove last parameter from call to + rs6000_frame_related. + (rs6000_emit_prologue): Remove last parameter from eight calls to + rs6000_frame_related. Force generation of stvx instruction for + Altivec register saves. Remove split_reg handling, which is no + longer needed. + (rs6000_emit_epilogue): Force generation of lvx instruction for + Altivec register restores. + +2015-04-24 Michael Meissner + + Backport from mainline + 2015-04-24 Michael Meissner + + PR target/65849 + * config/rs6000/rs6000.opt (-mvsx-align-128): Make options that + save to independent variables use the Save attribute. This will + allow these options to be modified with the #pragma/attribute + target support. + (-mallow-movmisalign): Likewise. + (-mallow-df-permute): Likewise. + (-msched-groups): Likewise. + (-malways-hint): Likewise. + (-malign-branch-targets): Likewise. + (-mvectorize-builtins): Likewise. + (-msave-toc-indirect): Likewise. + + * config/rs6000/rs6000.c (rs6000_opt_masks): Add more options that + can be set via the #pragma/attribute target support. + (rs6000_opt_vars): Likewise. + (rs6000_inner_target_options): If VSX was set, also set + -mno-avoid-indexed-addresses. + +2015-04-24 Bill Schmidt + + Backport from mainline r222362 + 2015-04-23 Bill Schmidt + + * config/rs6000/crypto.md (crypto_vpmsum): Change + TARGET_CRYPTO to TARGET_P8_VECTOR> + (crypto_vpermxor_): Likewise. + * config/rs6000/rs6000-builtin.def (BU_CRYPTO_2A): New #define. + (BU_CRYPTO_3A): Likewise. + (BU_CRYPTO_OVERLOAD_2A): Rename from BU_CRYPTO_OVERLOAD_2. + (BU_CRYPTO_OVERLOAD_3A): New #define. + (VPMSUMB): Change from BU_CRYPTO_2 to BU_CRYPTO_2A. + (VPMSUMH): Likewise. + (VPMSUMW): Likewise. + (VPMSUMD): Likewise. + (VPERMXOR_V2DI): Change from BU_CRYPTO_3 to BU_CRYPTO_3A. + (VPERMXOR_V4SI): Likewise. + (VPERMXOR_V8HI): Likewise. + (VPERMXOR_V16QI): Likewise. + (VPMSUM): Change from BU_CRYPTO_OVERLOAD_2 to + BU_CRYPTO_OVERLOAD_2A. + (VPERMXOR): Change from BU_CRYPTO_OVERLOAD3 to + BU_CRYPTO_OVERLOAD_3A. + * config/rs6000/rs6000.opt (mcrypto): Change description of + option. + + Backport from mainline r222362 + 2015-04-23 Bill Schmidt + + * config/rs6000/rs6000.opt (mcrypto): Change option description to + match category changes in ISA 2.07B. + +2015-04-24 Bill Schmidt + + Backport from mainline r222351 + 2015-04-22 Bill Schmidt + + * config/rs6000/rs6000.c (rtx_is_swappable_p): Commentary + adjustments. + (insn_is_swappable_p): Return 1 for a convert from double to + single precision when all of its uses are splats of BE element + zero. + +2015-04-24 Bill Schmidt + + Backport from mainline r222349 + 2015-04-22 Bill Schmidt + + PR target/65456 + * config/rs6000/rs6000.c (rs6000_option_override_internal): For + VSX + POWER8, enable TARGET_ALLOW_MOVMISALIGN and + TARGET_EFFICIENT_UNALIGNED_VSX if not selected by command line + option. + (rs6000_builtin_mask_for_load): Return 0 for targets with + efficient unaligned VSX accesses so that the vectorizer will use + direct unaligned loads. + (rs6000_builtin_support_vector_misalignment): Always return true + for targets with efficient unaligned VSX accesses. + (rs6000_builtin_vectorization_cost): Cost of unaligned loads and + stores on targets with efficient unaligned VSX accesses is almost + always the same as the cost of an aligned load or store, so model + it that way. + * config/rs6000/rs6000.h (SLOW_UNALIGNED_ACCESS): Return 0 for + unaligned vectors if we have efficient unaligned VSX accesses. + * config/rs6000/rs6000.opt (mefficient-unaligned-vector): New + undocumented option. + +2015-04-18 Bill Schmidt + Jakub Jelinek + + Backport from mainline r222205 + 2015-04-17 Bill Schmidt + Jakub Jelinek + + PR target/65787 + * config/rs6000/rs6000.c (rtx_is_swappable_p): Ensure that a + subsequent SH_NONE operand does not overwrite an existing *special + value. + (adjust_extract): Handle case where a vec_extract operation is + wrapped in a PARALLEL. + +2015-04-02 John David Anglin + + * config/pa/pa.c (pa_output_move_double): Directly handle register + indexed memory operand. Simplify handling of scaled register indexed + memory operands. + +2015-03-31 Dominik Vogt + + * config/s390/s390.c (s390_function_num_hotpatch_hw): Allow hotpatching + nested functions. + (s390_reorg): Adapt to new signature of s390_function_num_hotpatch_hw. + (s390_asm_output_function_label): Adapt to new signature of + s390_function_num_hotpatch_hw + Optimise the code generating assembler output. + Add comments to assembler file. + +2015-03-31 Dominik Vogt + + * config/s390/s390.c (s390_function_num_hotpatch_hw): Remove special + cases for not hotpatching main () and artificial functions. + +2015-03-26 Bill Schmidt + + Backport of r214242, r214254, and bug fix patches from mainline + * config/rs6000/rs6000.c (tree-pass.h): New #include. + (rs6000_analyze_swaps): New declaration. + (gate_analyze_swaps): New function. + (execute_analyze_swaps): Likewise. + (pass_analyze_swaps): New struct rtl_opt_pass. + (rs6000_option_override): Register swap-optimization pass. + (swap_web_entry): New class. + (special_handling_values): New enum. + (union_defs): New function. + (union_uses): Likewise. + (insn_is_load_p): Likewise. + (insn_is_store_p): Likewise. + (insn_is_swap_p): Likewise. + (rtx_is_swappable_p): Likewise. + (insn_is_swappable_p): Likewise. + (chain_purpose): New enum. + (chain_contains_only_swaps): New function. + (mark_swaps_for_removal): Likewise. + (swap_const_vector_halves): Likewise. + (adjust_subreg_index): Likewise. + (permute_load): Likewise. + (permute_store): Likewise. + (adjust_extract): Likewise. + (adjust_splat): Likewise. + (handle_special_swappables): Likewise. + (replace_swap_with_copy): Likewise. + (dump_swap_insn_table): Likewise. + (rs6000_analyze_swaps): Likewise. + * config/rs6000/rs6000.opt (moptimize-swaps): New option. + * df.h (web_entry_base): New class, replacing struct web_entry. + (web_entry_base::pred): New method. + (web_entry_base::set_pred): Likewise. + (web_entry_base::unionfind_root): Likewise. + (web_entry_base::unionfind_union): Likewise. + (unionfind_root): Delete external reference. + (unionfind_union): Likewise. + (union_defs): Likewise. + * web.c (web_entry_base::unionfind_root): Convert to method. + (web_entry_base::unionfind_union): Likewise. + (web_entry): New class. + (union_match_dups): Convert to use class structure. + (union_defs): Likewise. + (entry_register): Likewise. + (web_main): Likewise. + +2015-03-26 Bill Schmidt + + * config/rs6000/vsx.md (*vsx_extract__zero): Remove + endianness requirement. + (*vsx_extract__one_le): Remove define_insn. + +2015-03-26 Oleg Endo + + Backport from mainline + 2015-03-26 Oleg Endo + + * config/sh/t-sh (MULTILIB_EXCEPTIONS): Handle default endian. + +2015-03-16 Eric Botcazou + + PR middle-end/65409 + * expr.c (store_field): Do not do a direct block copy if the source is + a PARALLEL with BLKmode. + +2015-03-12 Dominik Vogt + + * config/s390/s390.c (s390_reorg): Move code to output nops after label + to s390_reorg (). + (s390_asm_output_function_label): Likewise. + * config/s390/s390.c (s390_asm_output_function_label): + Fix function label alignment with -mhtopatch. + * config/s390/s390.md ("unspecv"): New values UNSPECV_NOP_2_BYTE, + UNSPECV_NOP_4_BYTE and UNSPECV_NOP_6_BYTE + ("nop_2_byte"): New define_insn. + ("nop_4_byte"): Likewise. + ("nop_6_byte"): Likewise. + * doc/extend.texi (hotpatch): hotpatch attribute doc fixes. + * doc/invoke.texi (-mhotpatch): -mhotpatch doc fixes. + +2015-03-12 Marek Polacek + + Backport from mainline + 2015-03-11 Marek Polacek + + PR tree-optimization/65388 + * tree-ssa-tail-merge.c (same_succ_def::equal): Fix typo in comparison. + +2015-03-10 Jakub Jelinek + + PR target/65286 + * config/rs6000/t-linux: For powerpc64* target set + MULTILIB_OSDIRNAMES instead of MULTIARCH_DIRNAME. + +2015-03-10 Oleg Endo + + PR target/53988 + * config/sh/sh.md (*tst_t_zero): Remove insns. + +2015-03-10 Alan Modra + + PR target/65286 + * config.gcc (powerpc*-*-linux*): Arrange for powerpc64le-linux + to be single-arch by default. Set cpu_is_64bit for powerpc64 + given --with-cpu=native. + * config/rs6000/t-fprules: Do not set default MULTILIB vars. + * config/rs6000/t-linux (MULTIARCH_DIRNAME): Support powerpc64 + and powerpc64le. + * config/rs6000/linux64.h (SUBSUBTARGET_OVERRIDE_OPTIONS): Test + rs6000_isa_flags rather than TARGET_64BIT. + +2015-03-05 Michael Meissner + + Backport from trunk + 2015-03-03 Michael Meissner + + PR 65138/target + * config/rs6000/rs6000-cpus.def (powerpc64le): Add new generic + processor type for 64-bit little endian PowerPC. + + * config/rs6000/rs6000.c (rs6000_option_override_internal): If + -mdebug=reg, print TARGET_DEFAULT. Fix logic to use + TARGET_DEFAULT if there is no default cpu. Fix -mdebug=reg + printing built-in mask so it does not pass NULL pointers. + + * config/rs6000/rs6000-tables.opt: Regenerate. + + * doc/invoke.texi (IBM RS/6000 and PowerPC options): Document + -mcpu=powerpc64le. + + Backport from trunk + 2015-01-19 David Edelsohn + + * config/rs6000/default64.h: Include rs6000-cpus.def. + (TARGET_DEFAULT) [LITTLE_ENDIAN]: Use ISA 2.7 (POWER8). + (TARGET_DEFAULT) [BIG_ENDIAN]: Use POWER4. + * config/rs6000/driver-rs6000.c (detect_processor_aix): Add POWER7 + and POWER8. + * config/rs6000/linux64.h (PROCESSOR_DEFAULT64): Always default to + POWER8. + * config/rs6000/rs6000.c (rs6000_file_start): Emit .machine + pseudo-op to specify assembler dialect. + +2015-03-04 Thomas Preud'homme + + Backport from mainline + 2014-11-27 Thomas Preud'homme + + PR target/59593 + * config/arm/arm.c (dump_minipool): dispatch to consttable pattern + based on mode size. + * config/arm/arm.md (consttable_1): Make it TARGET_EITHER. + (consttable_2): Make it TARGET_EITHER and move HFmode handling from + consttable_4 to it. + (consttable_4): Move HFmode handling to consttable_2 pattern. + +2015-03-04 Thomas Preud'homme + + Backport from mainline + 2015-01-14 Thomas Preud'homme + + PR target/64453 + * config/arm/arm.c (callee_saved_reg_p): Define. + (arm_compute_save_reg0_reg12_mask): Use callee_saved_reg_p to check if + register is callee saved instead of !call_used_regs[reg]. + (thumb1_compute_save_reg_mask): Likewise. + +2015-02-27 Richard Biener + + PR lto/65193 + Backport from mainline + 2014-07-24 Jan Hubicka + + * lto-streamer-out.c (tree_is_indexable): Consider IMPORTED_DECL + as non-indexable. + +2015-02-26 Peter Bergner + + Backport from mainline + 2015-02-25 Adhemerval Zanella + + * config/rs6000/htm.md (tcheck): Fix assembly encoding. + +2015-02-26 Richard Biener + + Backport from mainline + 2014-11-27 Richard Biener + + PR tree-optimization/61634 + * tree-vect-slp.c: (vect_detect_hybrid_slp_stmts): Rewrite to + propagate hybrid down the SLP tree for one scalar statement. + (vect_detect_hybrid_slp_1): New walker function. + (vect_detect_hybrid_slp_2): Likewise. + (vect_detect_hybrid_slp): Properly handle pattern statements + in a pre-scan over all loop stmts. + +2015-02-25 Georg-Johann Lay + + PR target/65196 + * config/avr/avr.c (avr_adjust_insn_length): Call recog_memoized + only with NONDEBUG_INSN_P. + +2015-02-25 Richard Biener + + Backport from mainline + 2015-02-16 Richard Biener + + PR tree-optimization/63593 + * tree-predcom.c (execute_pred_commoning_chain): Delay removing + stmts and releasing SSA names until... + (execute_pred_commoning): ... after processing all chains. + + 2015-02-18 Richard Biener + + PR tree-optimization/65063 + * tree-predcom.c (determine_unroll_factor): Return 1 if we + have replaced looparound PHIs. + +2015-02-24 Richard Biener + + Backport from mainline + 2014-11-19 Richard Biener + + PR tree-optimization/63844 + * omp-low.c (fixup_child_record_type): Use a restrict qualified + referece type for the receiver parameter. + +2015-02-24 Richard Biener + + Backport from mainline + 2014-12-09 Richard Biener + + PR middle-end/64199 + * fold-const.c (fold_binary_loc): Use TREE_OVERFLOW_P. + + 2015-01-14 Richard Biener + + PR tree-optimization/64493 + PR tree-optimization/64495 + * tree-vect-loop.c (vect_finalize_reduction): For double-reductions + assign the proper vectorized PHI to the inner loop exit PHIs. + +2015-02-24 Richard Biener + + Backport from mainline + 2015-01-27 Richard Biener + + PR tree-optimization/56273 + PR tree-optimization/59124 + PR tree-optimization/64277 + * tree-vrp.c (vrp_finalize): Emit array-bound warnings only + from the first VRP pass. + +2015-02-24 Richard Biener + + Backport from mainline + 2015-02-11 Richard Biener + + PR lto/65015 + * dwarf2out.c (gen_producer_string): Drop -fltrans-output-list + and -fresolution. + + 2015-02-13 Richard Biener + + PR lto/65015 + * dwarf2out.c (dwarf2out_finish): Use as DW_AT_name + for LTO produced CUs. + + 2015-02-16 Richard Biener + + PR lto/65015 + * varasm.c (default_file_start): For LTO produced units + emit as file directive. + + 2015-01-17 Jan Kratochvil + + * dwarf2out.c (gen_producer_string): Ignore also OPT_fpreprocessed. + +2015-02-23 Oleg Endo + + Backport from mainline + 2015-02-23 Oleg Endo + + PR target/65163 + * config/sh/sh.md (swapbsi2, related peephole2): Use const_int -65536 + instead of const_int 4294901760. + +2015-02-23 Dominik Vogt + + Backport from mainline + 2015-01-27 Dominik Vogt + + * doc/extend.texi: s/390: Update documentation of hotpatch attribute. + * doc/invoke.texi (-mhotpatch): s/390: Update documentation of + -mhotpatch= option. + * config/s390/s390.opt (mhotpatch): s/390: Remove -mhotpatch and + -mno-hotpatch options. Change syntax of -mhotpatch= option. + * config/s390/s390.c (s390_hotpatch_trampoline_halfwords_default): + Renamed. + (s390_hotpatch_trampoline_halfwords_max): Renamed. + (s390_hotpatch_hw_max): New name. + (s390_hotpatch_trampoline_halfwords): Renamed. + (s390_hotpatch_hw_before_label): New name. + (get_hotpatch_attribute): Removed. + (s390_hotpatch_hw_after_label): New name. + (s390_handle_hotpatch_attribute): Add second parameter to hotpatch + attribute. + (s390_attribute_table): Ditto. + (s390_function_num_hotpatch_trampoline_halfwords): Renamed. + (s390_function_num_hotpatch_hw): New name. + Remove special handling of inline functions and hotpatching. + Return number of nops before and after the function label. + (s390_can_inline_p): Removed. + (s390_asm_output_function_label): Emit a configurable number of nops + after the function label. + (s390_option_override): Update -mhotpatch= syntax and remove -mhotpatch. + (TARGET_CAN_INLINE_P) Removed. + (TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P): New. + +2015-02-22 Uros Bizjak + + Backport from mainline + 2014-12-02 Uros Bizjak + + PR target/64113 + * config/alpha/alpha.md (call_value_osf_tlsgd): Do not split insn + using post-reload splitter. Use peephole2 pass instead. + (call_value_osf_tlsldm): Ditto. + (TLS_CALL): New int iterator. + (tls): New int attribute. + (call_value_osf_): Merge insn pattern from call_value_osf_tlsgd + and call_value_tlsldm using TLS_CALL int iterator. + +2015-02-20 Uros Bizjak + + Backport from mainline + 2015-01-22 Wei Mi + + PR rtl-optimization/64557 + * dse.c (record_store): Call get_addr for mem_addr. + (check_mem_read_rtx): Likewise. + + Backport from mainline + 2014-10-20 Uros Bizjak + + * varasm.c (const_alias_set): Remove. + (init_varasm_once): Remove initialization of const_alias_set. + (build_constant_desc): Do not set alias set to const_alias_set. + + Backport from mainline + 2014-10-14 Uros Bizjak + + PR rtl-optimization/63475 + * alias.c (true_dependence_1): Always use get_addr to extract + true address operands from x_addr and mem_addr. Use extracted + address operands to check for references with alignment ANDs. + Use extracted address operands with find_base_term and + base_alias_check. For noncanonicalized operands call canon_rtx with + extracted address operand. + (write_dependence_1): Ditto. + (may_alias_p): Ditto. Remove unused calls to canon_rtx. + + Backport from mainline + 2014-10-10 Uros Bizjak + + PR rtl-optimization/63483 + * alias.c (true_dependence_1): Do not exit early for MEM_READONLY_P + references when alignment ANDs are involved. + (write_dependence_p): Ditto. + (may_alias_p): Ditto. + + Backport from mainline + 2013-03-26 Richard Biener + + * alias.c (find_base_term): Avoid redundant and not used recursion. + (base_alias_check): Get the initial base term from the caller. + (true_dependence_1): Compute and pass base terms to base_alias_check. + (write_dependence_p): Likewise. + (may_alias_p): Likewise. + +2015-02-20 Georg-Johann Lay + + Backport from 2015-02-20 trunk r220847. + + PR target/64452 + * config/avr/avr.md (pushhi_insn): New insn. + (push1): Push virtual regs in one chunk using pushhi1_insn. + +2015-02-20 Uros Bizjak + + Backport from mainline + 2013-09-08 Richard Sandiford + + * ira.c (update_equiv_regs): Only call set_paradoxical_subreg + for non-debug insns. + * lra.c (new_insn_reg): Take the containing insn as a parameter. + Only modify lra_reg_info[].biggest_mode if it's non-debug insn. + (collect_non_operand_hard_regs, add_regs_to_insn_regno_info): Update + accordingly. + +2015-02-17 Ilya Tocar + + Backported from mainline + 2015-01-14 Ilya Tocar + + PR target/64387 + * config/i386/sse.md (vec_unpacks_hi_v8sf): Fix predicate. + +2015-02-12 Jakub Jelinek + + Backported from mainline + 2015-02-09 Jakub Jelinek + + PR target/64979 + * tree-stdarg.c (pass_stdarg::execute): Scan phi node args for + va_list escapes. + +2015-02-11 Uros Bizjak + + * config/alpha/alpha.md (reload_out_aligned): Make operands 2 + and 3 earlyclobber operands. + +2015-02-05 Segher Boessenkool + + PR target/64580 + Backport from mainline + * config.rs6000/rs6000.c (compute_vrsave_mask): Reverse loop order. + (rs6000_stack_info): Add assert. + (rs6000_output_savres_externs): New function, split off from... + (rs6000_output_function_prologue): ... here. Do not call it for + thunks. + +2015-02-04 Uros Bizjak + + Backport from mainline + 2015-01-31 Uros Bizjak + + PR target/64882 + * config/i386/predicates.md (address_no_seg_operand): Reject + non-CONST_INT_P operands in invalid mode. + + Backport from mainline + 2015-01-31 Uros Bizjak + + * config/i386/predicates.md (lea_address_operand): Call + address_operand with VOIDmode. + (vsib_address_operand): Ditto. + +2015-02-01 Jakub Jelinek + + Backported from mainline + 2015-01-27 Jakub Jelinek + + PR rtl-optimization/61058 + * jump.c (cleanup_barriers): Update basic block boundaries + if BLOCK_FOR_INSN is non-NULL on PREV. + + 2013-04-16 Steven Bosscher + + PR middle-end/43631 + * jump.c (cleanup_barriers): Use reorder_insns_nobb to avoid making + the moved barrier the tail of the basic block it follows. + + 2015-01-26 Jakub Jelinek + + * config/rs6000/rs6000-cpus.def (POWERPC_MASKS): Add + OPTION_MASK_QUAD_MEMORY_ATOMIC. + + 2015-01-12 Jakub Jelinek + + PR tree-optimization/64563 + * tree-vrp.c (vrp_evaluate_conditional): Check for VR_RANGE + instead of != VR_VARYING. + + PR target/64513 + * config/i386/i386.c (ix86_expand_prologue): Add + REG_FRAME_RELATED_EXPR to %rax and %r10 pushes. + +2015-01-29 Ilya Tocar + + * config/i386/avx2intrin.h (_mm256_bslli_epi128, + _mm256_bsrli_epi128): New. + * config/i386/emmintrin.h (_mm_bsrli_si128, _mm_bslli_si128): Ditto. + +2015-01-27 Mikael Pettersson + + Backport from mainline + + 2013-09-20 Bernd Edlinger + + PR middle-end/57748 + * expr.c (expand_assignment): Remove misalignp code path. + + 2014-01-08 Bernd Edlinger + + PR middle-end/57748 + * expr.h (expand_expr_real, expand_expr_real_1): Add new parameter + inner_reference_p. + (expand_expr, expand_normal): Adjust. + * expr.c (expand_expr_real, expand_expr_real_1): Add new parameter + inner_reference_p. Use inner_reference_p to expand inner references. + (store_expr): Adjust. + * cfgexpand.c (expand_call_stmt): Adjust. + +2015-01-26 Uros Bizjak + + Backport from mainline + 2015-01-26 Uros Bizjak + + PR target/64795 + * config/i386/i386.md (*movdi_internal): Also check operand 0 + to determine TYPE_LEA operand. + (*movsi_internal): Ditto. + + Backport from mainline + 2015-01-23 Uros Bizjak + + * config/i386/sse.md (sse2_loadld): Set attribute isa to sse2 for + alternative 1. + +2015-01-15 Martin Liska + + Backport from mainline + 2014-11-27 Richard Biener + + PR middle-end/63704 + * alias.c (mems_in_disjoint_alias_sets_p): Remove assert + and instead return false when !fstrict-aliasing. + +2015-01-14 Renlin Li + + Backport form mainline + 2014-08-12 Ramana Radhakrishnan + + PR target/61413 + * config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Fix definition + of __ARM_SIZEOF_WCHAR_T. + +2015-01-13 Pat Haugen + + Backport from mainline + 2014-12-20 Segher Boessenkool + + PR target/64358 + * config/rs6000/rs6000.c (rs6000_split_logical_inner): Swap the + input operands if only the second is inverted. + * config/rs6000/rs6000.md (*boolc3_internal1 for BOOL_128): + Swap BOOL_REGS_OP1 and BOOL_REGS_OP2. Correct arguments to + rs6000_split_logical. + (*boolc3_internal2 for TI2): Swap operands[1] and operands[2]. + +2015-01-13 Oleg Endo + + Backport form mainline + 2015-01-13 Oleg Endo + + PR target/64479 + * rtlanal.c (set_reg_p): Handle SEQUENCE constructs. + +2014-12-27 H.J. Lu + + Backport from mainline: + 2014-12-27 H.J. Lu + + PR target/64409 + * config/i386/i386.c (ix86_function_type_abi): Issue an error + when ms_abi attribute is used with x32. + +2014-12-19 H.J. Lu + + Backported from mainline + 2014-12-14 H.J. Lu + + PR rtl-optimization/64037 + * combine.c (setup_incoming_promotions): Pass the argument + before any promotions happen to promote_function_mode. + +2014-12-19 Jakub Jelinek + + * BASE-VER: Set to 4.8.5. + * DEV-PHASE: Set to prerelease. + +2014-12-19 Release Manager + + * GCC 4.8.4 released. + +2014-12-18 Francois-Xavier Coudert + + Backport from trunk. + PR fortran/61407 + * config/darwin-c.c (version_as_macro): Added extra 0 for OS X 10.10 + and above. + * config/darwin-driver.c (darwin_find_version_from_kernel): Removed + kernel version check to avoid incrementing it after every major OS X + release. + (darwin_default_min_version): Avoid static memory buffer. + +2014-12-15 Jakub Jelinek + + PR sanitizer/64265 + * tsan.c (instrument_func_entry): Insert __tsan_func_entry + call on edge from entry block to single succ instead + of after labels of single succ of entry block. + +2014-12-13 Jakub Jelinek + + Backported from mainline + 2014-12-12 Jakub Jelinek + + PR tree-optimization/64269 + * tree-ssa-forwprop.c (simplify_builtin_call): Bail out if + len2 or diff are too large. + +2014-12-11 Eric Botcazou + + * doc/md.texi (Insn Lengths): Fix description of (pc). + +2014-12-10 Bill Schmidt + + Backport from mainline + 2014-09-02 Bill Schmidt + + * config/rs6000/rs6000-builtin.def (XVCVSXDDP_SCALE): New + built-in definition. + (XVCVUXDDP_SCALE): Likewise. + (XVCVDPSXDS_SCALE): Likewise. + (XVCVDPUXDS_SCALE): Likewise. + * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add + entries for VSX_BUILTIN_XVCVSXDDP_SCALE, + VSX_BUILTIN_XVCVUXDDP_SCALE, VSX_BUILTIN_XVCVDPSXDS_SCALE, and + VSX_BUILTIN_XVCVDPUXDS_SCALE. + * config/rs6000/rs6000-protos.h (rs6000_scale_v2df): New + prototype. + * config/rs6000/rs6000.c (real.h): New include. + (rs6000_scale_v2df): New function. + * config/rs6000/vsx.md (UNSPEC_VSX_XVCVSXDDP): New unspec. + (UNSPEC_VSX_XVCVUXDDP): Likewise. + (UNSPEC_VSX_XVCVDPSXDS): Likewise. + (UNSPEC_VSX_XVCVDPUXDS): Likewise. + (vsx_xvcvsxddp_scale): New define_expand. + (vsx_xvcvsxddp): New define_insn. + (vsx_xvcvuxddp_scale): New define_expand. + (vsx_xvcvuxddp): New define_insn. + (vsx_xvcvdpsxds_scale): New define_expand. + (vsx_xvcvdpsxds): New define_insn. + (vsx_xvcvdpuxds_scale): New define_expand. + (vsx_xvcvdpuxds): New define_insn. + * doc/extend.texi (vec_ctf): Add new prototypes. + (vec_cts): Likewise. + (vec_ctu): Likewise. + (vec_splat): Likewise. + (vec_div): Likewise. + (vec_mul): Likewise. + + Backport from mainline + 2014-08-28 Bill Schmidt + + * config/rs6000/altivec.h (vec_xl): New #define. + (vec_xst): Likewise. + * config/rs6000/rs6000-builtin.def (XXSPLTD_V2DF): New built-in. + (XXSPLTD_V2DI): Likewise. + (DIV_V2DI): Likewise. + (UDIV_V2DI): Likewise. + (MUL_V2DI): Likewise. + * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add + entries for VSX_BUILTIN_XVRDPI, VSX_BUILTIN_DIV_V2DI, + VSX_BUILTIN_UDIV_V2DI, VSX_BUILTIN_MUL_V2DI, + VSX_BUILTIN_XXSPLTD_V2DF, and VSX_BUILTIN_XXSPLTD_V2DI). + * config/rs6000/vsx.md (UNSPEC_VSX_XXSPLTD): New unspec. + (UNSPEC_VSX_DIVSD): Likewise. + (UNSPEC_VSX_DIVUD): Likewise. + (UNSPEC_VSX_MULSD): Likewise. + (vsx_mul_v2di): New insn-and-split. + (vsx_div_v2di): Likewise. + (vsx_udiv_v2di): Likewise. + (vsx_xxspltd_): New insn. + + Backport from mainline + 2014-08-20 Bill Schmidt + + * config/rs6000/altivec.h (vec_cpsgn): New #define. + (vec_mergee): Likewise. + (vec_mergeo): Likewise. + (vec_cntlz): Likewise. + * config/rs600/rs6000-c.c (altivec_overloaded_builtins): Add new + entries for VEC_AND, VEC_ANDC, VEC_MERGEH, VEC_MERGEL, VEC_NOR, + VEC_OR, VEC_PACKSU, VEC_XOR, VEC_PERM, VEC_SEL, VEC_VCMPGT_P, + VMRGEW, and VMRGOW. + * doc/extend.texi: Document various forms of vec_cpsgn, + vec_splats, vec_and, vec_andc, vec_mergeh, vec_mergel, vec_nor, + vec_or, vec_perm, vec_sel, vec_sub, vec_xor, vec_all_eq, + vec_all_ge, vec_all_gt, vec_all_le, vec_all_lt, vec_all_ne, + vec_any_eq, vec_any_ge, vec_any_gt, vec_any_le, vec_any_lt, + vec_any_ne, vec_mergee, vec_mergeo, vec_packsu, and vec_cntlz. + + Backport from mainline + 2014-07-20 Bill Schmidt + + * config/rs6000/altivec.md (unspec enum): Fix typo in UNSPEC_VSLDOI. + (altivec_vsldoi_): Likewise. + +2014-12-10 Bill Schmidt + + Backport from mainline: + 2014-12-09 Bill Schmidt + + PR middle-end/64225 + * tree-ssa-reassoc.c (acceptable_pow_call): Disable transformation + for BUILT_IN_POW when flag_errno_math is present. + +2014-12-10 Marek Polacek + + Backport from mainline + 2014-12-10 Marek Polacek + + PR tree-optimization/61686 + * tree-ssa-reassoc.c (range_entry_cmp): Use q->high instead of + p->high. + +2014-12-09 David Edelsohn + + Backport from mainline + 2014-12-05 David Edelsohn + + * config/rs6000/xcoff.h (ASM_OUTPUT_ALIGNED_LOCAL): Append + alignment to section name. Increase default alignment to + word. + +2014-12-09 Uros Bizjak + + PR bootstrap/64213 + Revert: + 2014-11-28 H.J. Lu + + PR rtl-optimization/64037 + * combine.c (setup_incoming_promotions): Pass the argument + before any promotions happen to promote_function_mode. + +2014-12-08 Richard Biener + + Backport from 4.9 branch + * configure.ac + (ac_has_isl_schedule_constraints_compute_schedule): + New check. + * graphite-clast-to-gimple.c: For ISL 0.14, include deprecate headers. + * graphite-interchange.c: Ditto. + * graphite-poly.c: Ditto. + * graphite-sese-to-poly.c: Ditto. + * graphite-optimize-isl.c (getScheduleForBandList): Ditto. + Conditionally use ISL 0.13+ functions. + * config.in: Regenerate. + * configure: Regenerate. + +2014-12-07 Oleg Endo + + Backport from mainline + 2014-12-07 Oleg Endo + + PR target/50751 + * config/sh/sh.md (extendqihi2): Allow only for TARGET_SH1. + +2014-12-05 H.J. Lu + + Backport from mainline + 2014-11-28 H.J. Lu + + PR rtl-optimization/64037 + * combine.c (setup_incoming_promotions): Pass the argument + before any promotions happen to promote_function_mode. + +2014-12-04 Shanyao Chen + + Backport from mainline + 2014-11-20 Ramana Radhakrishnan + + PR target/59593 + * config/arm/arm.md (*movhi_insn): Use right formatting + for immediate. + + 2014-11-19 Felix Yang + Shanyao Chen + + PR target/59593 + * config/arm/arm.md (define_attr "arch"): Add v6t2. + (define_attr "arch_enabled"): Add test for the above. + (*movhi_insn_arch4): Add new alternative. + +2014-12-04 Jakub Jelinek + + PR c++/56493 + * convert.c (convert_to_real, convert_to_expr, convert_to_complex): + Handle COMPOUND_EXPR. + +2014-12-02 Ulrich Weigand + + PR target/64115 + * config/rs6000/rs6000.c (rs6000_delegitimize_address): Remove + invalid UNSPEC_TOCREL sanity check under ENABLE_CHECKING. + +2014-12-01 Richard Biener + + PR middle-end/64111 + * tree.c (int_cst_hash_hash): Use TYPE_UID instead of + htab_hash_pointer to not break PCH. + +2014-11-28 Jakub Jelinek + + Backported from mainline + 2014-11-27 Jakub Jelinek + + PR middle-end/64067 + * expr.c (expand_expr_addr_expr_1) : + Handle it by returning address of COMPOUND_LITERAL_EXPR_DECL + not only if modifier is EXPAND_INITIALIZER, but whenever + COMPOUND_LITERAL_EXPR_DECL is non-NULL and TREE_STATIC. + + 2014-10-31 Jakub Jelinek + + PR rtl-optimization/63659 + * ree.c (update_reg_equal_equiv_notes): New function. + (combine_set_extension, transform_ifelse): Use it. + + 2014-10-03 Jakub Jelinek + + PR libgomp/61200 + * omp-low.c (taskreg_contexts): New variable. + (scan_omp_parallel): Push newly created context into taskreg_contexts + vector and move record layout code to finish_taskreg_scan. + (scan_omp_task): Likewise. + (finish_taskreg_scan): New function. + (execute_lower_omp): Call finish_taskreg_scan on all taskreg_contexts + vector elements and release it. + +2014-11-26 Richard Biener + + Backport from mainline + 2014-10-08 Richard Biener + + PR tree-optimization/61969 + * tree-nrv.c (pass_nrv::execute): Properly test for automatic + variables. + + 2014-08-15 Richard Biener + + PR tree-optimization/62031 + * tree-data-ref.c (dr_analyze_indices): Do not set + DR_UNCONSTRAINED_BASE. + (dr_may_alias_p): All indirect accesses have to go the + formerly DR_UNCONSTRAINED_BASE path. + * tree-data-ref.h (struct indices): Remove + unconstrained_base member. + (DR_UNCONSTRAINED_BASE): Remove. + + 2014-10-10 Richard Biener + + PR tree-optimization/63379 + * tree-vect-slp.c (vect_get_constant_vectors): Do not compute + a neutral operand for min/max when it is not a reduction chain. + + 2014-11-07 Richard Biener + + PR tree-optimization/63605 + * fold-const.c (fold_binary_loc): Properly use element_precision + for types that may not be scalar. + + 2014-10-28 Richard Biener + + PR middle-end/63665 + * fold-const.c (fold_comparison): Properly guard simplifying + against INT_MAX/INT_MIN with !TYPE_OVERFLOW_WRAPS. + +2014-11-22 Oleg Endo + + Backport from mainline + 2014-11-20 Segher Boessenkool + + PR target/60111 + * config/sh/sh.c: Use signed char for signed field. + +2014-11-21 Bill Schmidt + + PR target/63673 + * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Allow + the base pointer of vec_vsx_ld and vec_vsx_st to take a pointer to + double. + +2014-11-19 Uros Bizjak + + PR target/63947 + * config/i386/i386.c (put_condition_code) : + Output "b" and "nb" suffix for FP mode. + +2014-11-19 Tom de Vries + + Backport from mainline + PR tree-optimization/62167 + * tree-ssa-tail-merge.c (stmt_local_def): Handle statements with vuse + conservatively. + (gimple_equal_p): Don't use vn_valueize to compare for lhs equality of + assigns. + +2014-11-18 Teresa Johnson + + Backport from mainline and gcc-4_9 branch. + 2014-11-13 Teresa Johnson + + PR tree-optimization/63841 + * tree-ssa-strlen.c (strlen_optimize_stmt): Ignore clobbers. + +2014-11-16 Eric Botcazou + + * doc/tm.texi.in (TARGET_FLAGS_REGNUM): Move around. + * doc/tm.texi: Regenerate. + + Backport from mainline + 2013-09-16 Andreas Schwab + + * doc/tm.texi.in (Cond Exec Macros): Remove node. + (Condition Code): Don't reference it. + * doc/tm.texi: Regenerate. + +2014-11-13 Christophe Lyon + + Backport from mainline + 2014-11-02 Michael Collison + + * config/arm/arm.h (CLZ_DEFINED_VALUE_AT_ZERO) : Update + to support vector modes. + (CTZ_DEFINED_VALUE_AT_ZERO): Ditto. + +2014-11-13 Eric Botcazou + + * doc/tm.texi.in (SELECT_CC_MODE): Update example. + (REVERSIBLE_CC_MODE): Fix example. + (REVERSE_CONDITION): Fix typo. + * doc/tm.texi: Regenerate. + +2014-11-12 Jakub Jelinek + + PR ipa/63838 + * ipa-pure-const.c (propagate_nothrow): Walk w->indirect_calls + chain instead of node->indirect_calls. + +2014-11-10 Daniel Hellstrom + + Backport from mainline + * config.gcc (sparc-*-rtems*): Clean away unused t-elf. + * config/sparc/t-rtems: Add leon3v7 and muser-mode multilibs. + +2014-11-07 Daniel Hellstrom + + * config.gcc (sparc*-*-*): Accept mcpu=leon3v7 processor. + * doc/invoke.texi (SPARC options): Add mcpu=leon3v7 comment. + * config/sparc/leon.md (leon3_load, leon_store, leon_fp_*): Handle + leon3v7 as leon3. + * config/sparc/sparc-opts.h (enum processor_type): Add LEON3V7. + * config/sparc/sparc.c (sparc_option_override): Add leon3v7 support. + * config/sparc/sparc.h (TARGET_CPU_leon3v7): New define. + * config/sparc/sparc.md (cpu): Add leon3v7. + * config/sparc/sparc.opt (enum processor_type): Add leon3v7. + +2014-11-06 John David Anglin + + * config/pa/pa.md (trap): New insn. Add "trap" to attribute type. + Don't allow trap insn in in_branch_delay, in_nullified_branch_delay + or in_call_delay. + +2014-11-06 Kyrylo Tkachov + + * config/aarch64/aarch64-elf-raw.h (CA53_ERR_835769_SPEC): Define. + (LINK_SPEC): Include CA53_ERR_835769_SPEC. + * config/aarch64/aarch64-linux.h + (CA53_ERR_835769_SPEC): Define. + (LINK_SPEC): Include CA53_ERR_835769_SPEC. + +2014-10-29 Kyrylo Tkachov + + * config/aarch64/aarch64.c (aarch64_madd_needs_nop): Restore + recog state after aarch64_prev_real_insn call. + +2014-10-24 Kyrylo Tkachov + + * config.gcc (aarch64*-*-*): Define TARGET_FIX_ERR_A53_835769_DEFAULT + if asked. + * configure.ac: Add --enable-fix-cortex-a53-835769 option. + * configure: Regenerate. + * config/aarch64/aarch64.c (aarch64_override_options): Handle + TARGET_FIX_ERR_A53_835769_DEFAULT. + * config/aarch64/aarch64.opt (mfix-cortex-a53-835769): Set Init value + to 2. + * doc/install.texi: Document --enable-fix-cortex-a53-835769 option. + +2014-10-24 Kyrylo Tkachov + + * config/aarch64/aarch64.opt (mfix-cortex-a53-835769): New option. + * config/aarch64/aarch64.h (ADJUST_INSN_LENGTH): Define. + (FINAL_PRESCAN_INSN): Likewise. + * config/aarch64/aarch64.h (is_mem_p): New function. + (has_memory_op): Likewise. + (aarch64_prev_real_insn): Likewise. + (is_madd_op): Likewise. + (dep_between_memop_and_curr): Likewise. + (aarch64_madd_needs_nop): Likewise. + (aarch64_final_prescan_insn): Likewise. + * doc/invoke.texi (Document new option). + +2014-10-15 Eric Botcazou + + * stor-layout.c (self_referential_size): Do not promote arguments. + +2014-10-12 Bill Schmidt + + Backport from mainline r215880 + 2014-10-03 Bill Schmidt + + * config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin): + Issue a warning message when vec_lvsl or vec_lvsr is used with a + little endian target. + + Backport from mainline r215882 + 2014-10-03 Bill Schmidt + + * altivec.md (altivec_lvsl): New define_expand. + (altivec_lvsl_direct): Rename define_insn from altivec_lvsl. + (altivec_lvsr): New define_expand. + (altivec_lvsr_direct): Rename define_insn from altivec_lvsr. + * rs6000.c (rs6000_expand_builtin): Change to use + altivec_lvs[lr]_direct; remove commented-out code. + +2014-10-09 Uros Bizjak + + Backport from mainline + 2014-10-09 Uros Bizjak + + PR rtl-optimization/57003 + * regcprop.c (copyprop_hardreg_forward_1): If ksvd.ignore_set_reg, + also check CALL_INSN_FUNCTION_USAGE for clobbers again after + killing regs_invalidated_by_call. + +2014-10-08 Oleg Endo + + Backport from mainline + 2014-10-08 Oleg Endo + + PR target/52941 + * config/sh/sync.md (atomic_exchangesi_hard, atomic_exchange_hard, + atomic_fetch_si_hard, + atomic_fetch__hard, atomic_fetch_nandsi_hard, + atomic_fetch_nand_hard, atomic__fetchsi_hard, + atomic__fetch_hard, atomic_nand_fetchsi_hard, + atomic_nand_fetch_hard): Add missing set of T_REG. + +2014-10-02 Martin Jambor + + PR tree-optimization/63375 + * tree-sra.c (build_access_from_expr_1): Disqualify volatile + references. + +2014-10-01 Jakub Jelinek + + PR debug/63342 + * dwarf2out.c (loc_list_from_tree): Handle TARGET_MEM_REF and + SSA_NAME. + + PR target/63428 + * config/i386/i386.c (expand_vec_perm_pshufb): Fix up rperm[0] + argument to avx2_permv2ti. + +2014-10-01 Uros Bizjak + + Backport from mainline + 2014-09-30 Uros Bizjak + + * config/i386/i386.md (fmodxf3): Enable for flag_finite_math_only only. + (fmod3): Ditto. + (fpremxf4_i387): Ditto. + (reminderxf3): Ditto. + (reminder3): Ditto. + (fprem1xf4_i387): Ditto. + +2014-09-30 Jakub Jelinek + + PR inline-asm/63282 + * ifcvt.c (dead_or_predicable): Don't call redirect_jump_1 + or invert_jump_1 if jump isn't any_condjump_p. + +2014-09-29 Charles Baylis + + Backport from mainline r212303 + PR target/49423 + * config/arm/arm-protos.h (arm_legitimate_address_p, + arm_is_constant_pool_ref): Add prototypes. + * config/arm/arm.c (arm_legitimate_address_p): Remove static. + (arm_is_constant_pool_ref) New function. + * config/arm/arm.md (unaligned_loadhis, arm_zero_extendhisi2_v6, + arm_zero_extendqisi2_v6): Use Uh constraint for memory operand. + (arm_extendhisi2, arm_extendhisi2_v6): Use Uh constraint for memory + operand and remove pool_range and neg_pool_range attributes. + (arm_extendqihi_insn, arm_extendqisi, arm_extendqisi_v6): Remove + pool_range and neg_pool_range attributes. + * config/arm/constraints.md (Uh): New constraint. (Uq): Don't allow + constant pool references. + +2014-09-28 John David Anglin + + * config/pa/pa.c (pa_output_function_epilogue): Only update + last_address when a nonnote insn is found. + +2014-09-25 Oleg Endo + + Backport from mainline + 2014-09-25 Nick Clifton + 2014-09-25 Oleg Endo + + PR target/62218 + * config/sh/sync.md (atomic_fetch_nand_soft_imask, + atomic_test_and_set_soft_imask): Fix typo in instruction sequence. + +2014-09-25 Bill Schmidt + + Backport from mainline r215559 + 2014-09-25 Bill Schmidt + + PR target/63335 + * config/rs6000/rs6000-c.c (altivec_build_resolved_builtin): + Exclude VSX_BUILTIN_XVCMPGEDP_P from special handling. + +2014-09-25 Jakub Jelinek + + PR tree-optimization/63341 + * tree-vectorizer.h (vect_create_data_ref_ptr, + vect_create_addr_base_for_vector_ref): Add another tree argument + defaulting to NULL_TREE. + * tree-vect-data-refs.c (vect_create_data_ref_ptr): Add byte_offset + argument, pass it down to vect_create_addr_base_for_vector_ref. + (vect_create_addr_base_for_vector_ref): Add byte_offset argument, + add that to base_offset too if non-NULL. + * tree-vect-stmts.c (vectorizable_load): Add byte_offset variable, + for dr_explicit_realign_optimized set it to vector byte size + - 1 instead of setting offset, pass byte_offset down to + vect_create_data_ref_ptr. + +2014-09-23 Michael Meissner + + Back port from trunk: + 2014-09-23 Michael Meissner + + * config/rs6000/rs6000.md (f32_vsx): New mode attributes to + refine the constraints used on 32/64-bit floating point moves. + (f32_av): Likewise. + (f64_vsx): Likewise. + (f64_dm): Likewise. + (f64_av): Likewise. + (BOOL_REGS_OUTPUT): Use wt constraint for TImode instead of wa. + (BOOL_REGS_OP1): Likewise. + (BOOL_REGS_OP2): Likewise. + (BOOL_REGS_UNARY): Likewise. + (mov_hardfloat, SFmode/SDmode): Tighten down constraints for + 32/64-bit floating point moves. Do not use wa, instead use ww/ws + for moves involving VSX registers. Do not use constraints that + target VSX registers for decimal types. + (mov_hardfloat32, DFmode/DDmode): Likewise. + (mov_hardfloat64, DFmode/DDmode): Likewise. + +2014-09-19 Michael Meissner + + Back port from trunk: + 2014-09-19 Michael Meissner + + * config/rs6000/predicates.md (fusion_gpr_mem_load): Move testing + for base_reg_operand to be common between LO_SUM and PLUS. + (fusion_gpr_mem_combo): New predicate to match a fused address + that combines the addis and memory offset address. + + * config/rs6000/rs6000-protos.h (fusion_gpr_load_p): Change + calling signature. + (emit_fusion_gpr_load): Likewise. + + * config/rs6000/rs6000.c (fusion_gpr_load_p): Change calling + signature to pass each argument separately, rather than + using an operands array. Rewrite the insns found by peephole2 to + be a single insn, rather than hoping the insns will still be + together when the peephole pass is done. Drop being called via a + normal peephole. + (emit_fusion_gpr_load): Change calling signature to be called from + the fusion_gpr_load_ insns with a combined memory address + instead of the peephole pass passing the addis and offset + separately. + + * config/rs6000/rs6000.md (UNSPEC_FUSION_GPR): New unspec for GPR + fusion. + (power8 fusion peephole): Drop support for doing power8 via a + normal peephole that was created by the peephole2 pass. + (power8 fusion peephole2): Create a new insn with the fused + address, so that the fused operation is kept together after + register allocation is done. + (fusion_gpr_load_): Likewise. + +2014-09-17 Jakub Jelinek + + PR debug/63284 + * tree-cfgcleanup.c (fixup_noreturn_call): Don't split block + if there are only debug stmts after the noreturn call, instead + remove the debug stmts. + +2014-09-10 Michael Meissner + + * config/rs6000/vsx.md (vsx_fmav4sf4): Use correct constraints for + V2DF, V4SF, DF, and DI modes. + (vsx_fmav2df2): Likewise. + (vsx_float_fix_2): Likewise. + (vsx_reduc__v2df_scalar): Likewise. + +2014-09-10 Alan Modra + + PR debug/60655 + * dwarf2out.c (mem_loc_descriptor ): Return NULL if addend + can't be output. + +2014-09-09 Richard Biener + + Backport from mainline + 2014-06-11 Richard Biener + + PR tree-optimization/61452 + * tree-ssa-sccvn.c (visit_phi): Remove pointless setting of + expr and has_constants in case we found a leader. + (simplify_binary_expression): Always valueize operands first. + (simplify_unary_expression): Likewise. + +2014-09-09 Richard Biener + + Backport from mainline + 2014-05-05 Richard Biener + + PR middle-end/61010 + * fold-const.c (fold_binary_loc): Consistently avoid + canonicalizing X & CST away from a CST that is the mask + of a mode. + + 2014-05-28 Richard Biener + + PR middle-end/61045 + * fold-const.c (fold_comparison): When folding + X +- C1 CMP Y +- C2 to X CMP Y +- C2 +- C1 also ensure + the sign of the remaining constant operand stays the same. + + 2014-08-11 Richard Biener + + PR tree-optimization/62075 + * tree-vect-slp.c (vect_detect_hybrid_slp_stmts): Properly + handle uses in patterns. + +2014-09-09 James Greenhalgh + + Backport from mainline. + 2014-09-09 James Greenhalgh + + * doc/invoke.texi (-march): Use GNU/Linux rather than Linux. + (-mtune): Likewise. + (-mcpu): Likewise. + +2014-09-08 Jakub Jelinek + + PR tree-optimization/60196 + PR tree-optimization/63189 + Backported from mainline + 2013-09-17 Cong Hou + + * tree-vect-patterns.c (vect_recog_dot_prod_pattern): Fix a bug + when checking the dot production pattern. The type of rhs operand + of multiply is now checked correctly. + +2014-09-08 Jakub Jelinek + + Backported from mainline + 2014-08-06 Vladimir Makarov + + PR debug/61923 + * haifa-sched.c (advance_one_cycle): Fix dump. + (schedule_block): Don't advance cycle if we are already at the + beginning of the cycle. + +2014-09-03 Martin Jambor + + PR ipa/62015 + * ipa-cp.c (intersect_aggregates_with_edge): Handle impermissible + pass-trough jump functions correctly. + +2014-09-03 Martin Jambor + + PR ipa/61986 + * ipa-cp.c (find_aggregate_values_for_callers_subset): Chain + created replacements in ascending order of offsets. + (known_aggs_to_agg_replacement_list): Likewise. + +2014-09-01 Marek Polacek + + Backport from mainline + 2014-08-21 Marek Polacek + + PR c/61271 + * expr.c (is_aligning_offset): Remove logical not. + +2014-09-01 Marek Polacek + + Backport from mainline + 2014-08-19 Marek Polacek + + PR c/61271 + * cgraphunit.c (handle_alias_pairs): Fix condition. + +2014-08-30 John David Anglin + + * config/pa/pa.c (pa_assemble_integer): Don't add PLABEL relocation + prefix to function labels when generating fast indirect calls. + +2014-08-26 Joel Sherrill + + * doc/invoke.texi: -fno-cxa-atexit should be -fno-use-cxa-atexit. + +2014-08-26 Marek Polacek + + Backport from mainline + 2014-08-26 Marek Polacek + + PR c/61271 + * tree-vectorizer.h (LOOP_REQUIRES_VERSIONING_FOR_ALIGNMENT, + LOOP_REQUIRES_VERSIONING_FOR_ALIAS): Wrap in parens. + +2014-08-24 Oleg Endo + + Backport from mainline + 2014-08-24 Oleg Endo + + PR target/61996 + * config/sh/sh.opt (musermode): Allow negative form. + * config/sh/sh.c (sh_option_override): Disable TARGET_USERMODE for + targets that don't support it. + * doc/invoke.texi (SH Options): Rename sh-*-linux* to sh*-*-linux*. + Document -mno-usermode option. + +2014-08-23 John David Anglin + + PR target/62038 + * config/pa/pa.c (pa_output_function_epilogue): Don't set + last_address when the current function is a thunk. + (pa_asm_output_mi_thunk): When we don't have named sections or they + are not being used, check that thunk can reach the stub table with a + short branch. + +2014-08-22 Michael Meissner + + Backport fro mainline + 2014-08-22 Michael Meissner + + PR target/62195 + * doc/md.texi (Machine Constraints): Update PowerPC wi constraint + documentation to state it is only for VSX operations. + + * config/rs6000/rs6000.c (rs6000_init_hard_regno_mode_ok): Make wi + constraint only active if VSX. + + * config/rs6000/rs6000.md (lfiwax): Use wj constraint instead of + wi cosntraint for ISA 2.07 lxsiwax/lxsiwzx instructions. + (lfiwzx): Likewise. + +2014-08-15 Tom de Vries + + Backport from mainline: + 2014-08-14 Tom de Vries + + PR rtl-optimization/62004 + PR rtl-optimization/62030 + * ifcvt.c (rtx_interchangeable_p): New function. + (noce_try_move, noce_process_if_block): Use rtx_interchangeable_p. + + 2014-08-05 Richard Biener + + * emit-rtl.h (mem_attrs_eq_p): Declare. + * emit-rtl.c (mem_attrs_eq_p): Export. + +2014-08-16 John David Anglin + + Backport from trunk: + 2014-04-06 John David Anglin + + PR debug/55794 + * config/pa/pa.c (pa_output_function_epilogue): Skip address and code + size accounting for thunks. + (pa_asm_output_mi_thunk): Use final_start_function() and + final_end_function() to output function start and end directives. + +2014-08-15 Oleg Endo + + Backport from mainline: + 2014-08-15 Oleg Endo + + * doc/invoke.texi (SH options): Document missing processor variant + options. Remove references to Hitachi. Undocument deprecated mspace + option. + +2014-08-13 Felix Yang + + PR tree-optimization/62073 + * tree-vect-loop.c (vect_is_simple_reduction_1): Check that DEF1 has + a basic block. + +2014-08-13 Thomas Preud'homme + + Backport from mainline + 2014-08-12 Thomas Preud'homme + + PR middle-end/62103 + * gimple-fold.c (fold_ctor_reference): Don't fold in presence of + bitfields, that is when size doesn't match the size of type or the + size of the constructor. + +2014-08-12 Michael Meissner + + Backport patch from mainline + 2014-08-11 Michael Meissner + + * config/rs6000/constraints.md (wh constraint): New constraint, + for FP registers if direct move is available. + (wi constraint): New constraint, for VSX/FP registers that can + handle 64-bit integers. + (wj constraint): New constraint for VSX/FP registers that can + handle 64-bit integers for direct moves. + (wk constraint): New constraint for VSX/FP registers that can + handle 64-bit doubles for direct moves. + (wy constraint): Make documentation match implementation. + + * config/rs6000/rs6000.c (struct rs6000_reg_addr): Add + scalar_in_vmx_p field to simplify tests of whether SFmode or + DFmode can go in the Altivec registers. + (rs6000_hard_regno_mode_ok): Use scalar_in_vmx_p field. + (rs6000_setup_reg_addr_masks): Likewise. + (rs6000_debug_print_mode): Add debug support for scalar_in_vmx_p + field, and wh/wi/wj/wk constraints. + (rs6000_init_hard_regno_mode_ok): Setup scalar_in_vmx_p field, and + the wh/wi/wj/wk constraints. + (rs6000_preferred_reload_class): If SFmode/DFmode can go in the + upper registers, prefer VSX registers unless the operation is a + memory operation with REG+OFFSET addressing. + + * config/rs6000/vsx.md (VSr mode attribute): Add support for + DImode. Change SFmode to use ww constraint instead of d to allow + SF registers in the upper registers. + (VSr2): Likewise. + (VSr3): Likewise. + (VSr5): Fix thinko in comment. + (VSa): New mode attribute that is an alternative to wa, that + returns the VSX register class that a mode can go in, but may not + be the preferred register class. + (VS_64dm): New mode attribute for appropriate register classes for + referencing 64-bit elements of vectors for direct moves and normal + moves. + (VS_64reg): Likewise. + (vsx_mov): Change wa constraint to to limit the + register allocator to only registers the data type can handle. + (vsx_le_perm_load_): Likewise. + (vsx_le_perm_store_): Likewise. + (vsx_xxpermdi2_le_): Likewise. + (vsx_xxpermdi4_le_): Likewise. + (vsx_lxvd2x2_le_): Likewise. + (vsx_lxvd2x4_le_): Likewise. + (vsx_stxvd2x2_le_): Likewise. + (vsx_add3): Likewise. + (vsx_sub3): Likewise. + (vsx_mul3): Likewise. + (vsx_div3): Likewise. + (vsx_tdiv3_internal): Likewise. + (vsx_fre2): Likewise. + (vsx_neg2): Likewise. + (vsx_abs2): Likewise. + (vsx_nabs2): Likewise. + (vsx_smax3): Likewise. + (vsx_smin3): Likewise. + (vsx_sqrt2): Likewise. + (vsx_rsqrte2): Likewise. + (vsx_tsqrt2_internal): Likewise. + (vsx_fms4): Likewise. + (vsx_nfma4): Likewise. + (vsx_eq): Likewise. + (vsx_gt): Likewise. + (vsx_ge): Likewise. + (vsx_eq_p): Likewise. + (vsx_gt_p): Likewise. + (vsx_ge_p): Likewise. + (vsx_xxsel): Likewise. + (vsx_xxsel_uns): Likewise. + (vsx_copysign3): Likewise. + (vsx_float2): Likewise. + (vsx_floatuns2): Likewise. + (vsx_fix_trunc2): Likewise. + (vsx_fixuns_trunc2): Likewise. + (vsx_xri): Likewise. + (vsx_xric): Likewise. + (vsx_btrunc2): Likewise. + (vsx_b2trunc2): Likewise. + (vsx_floor2): Likewise. + (vsx_ceil2): Likewise. + (vsx_): Likewise. + (vsx_xscvspdp): Likewise. + (vsx_xvcvspuxds): Likewise. + (vsx_float_fix_2): Likewise. + (vsx_set_): Likewise. + (vsx_extract__internal1): Likewise. + (vsx_extract__internal2): Likewise. + (vsx_extract__load): Likewise. + (vsx_extract__store): Likewise. + (vsx_splat_): Likewise. + (vsx_xxspltw_): Likewise. + (vsx_xxspltw__direct): Likewise. + (vsx_xxmrghw_): Likewise. + (vsx_xxmrglw_): Likewise. + (vsx_xxsldwi_): Likewise. + (vsx_xscvdpspn): Tighten constraints to only use register classes + the types use. + (vsx_xscvspdpn): Likewise. + (vsx_xscvdpspn_scalar): Likewise. + + * config/rs6000/rs6000.h (enum rs6000_reg_class_enum): Add wh, wi, + wj, and wk constraints. + (GPR_REG_CLASS_P): New helper macro for register classes targeting + general purpose registers. + + * config/rs6000/rs6000.md (f32_dm): Use wh constraint for SDmode + direct moves. + (zero_extendsidi2_lfiwz): Use wj constraint for direct move of + DImode instead of wm. Use wk constraint for direct move of DFmode + instead of wm. + (extendsidi2_lfiwax): Likewise. + (lfiwax): Likewise. + (lfiwzx): Likewise. + (movdi_internal64): Likewise. + + * doc/md.texi (PowerPC and IBM RS6000): Document wh, wi, wj, and + wk constraints. Make the wy constraint documentation match them + implementation. + +2014-08-01 Thomas Preud'homme + + Backport from mainline + 2014-06-13 Thomas Preud'homme + + PR tree-optimization/61375 + * tree-ssa-math-opts.c (find_bswap_or_nop_1): Cancel optimization if + symbolic number cannot be represented in an unsigned HOST_WIDE_INT. + (execute_optimize_bswap): Cancel optimization if CHAR_BIT != 8. + +2014-08-01 Richard Biener + + PR tree-optimization/61964 + * tree-ssa-tail-merge.c (gimple_operand_equal_value_p): New + function merged from trunk. + (gimple_equal_p): Handle non-SSA LHS solely by structural + equality. + +2014-07-25 Uros Bizjak + + * config/alpha/elf.h: Define TARGET_UNWIND_TABLES_DEFAULT. + +2014-07-24 Kyle McMartin + + * config/aarch64/aarch64-linux.h (TARGET_ASM_FILE_END): Define. + +2014-07-24 Ulrich Weigand + + * config/rs6000/rs6000-protos.h (rs6000_special_adjust_field_align_p): + Add prototype. + * config/rs6000/rs6000.c (rs6000_special_adjust_field_align_p): New + function. Issue -Wpsabi warning if future GCC releases will use + different field alignment rules for this type. + * config/rs6000/sysv4.h (ADJUST_FIELD_ALIGN): Call it. + * config/rs6000/linux64.h (ADJUST_FIELD_ALIGN): Likewise. + * config/rs6000/freebsd64.h (ADJUST_FIELD_ALIGN): Likewise. + +2014-07-24 Ulrich Weigand + + * config/rs6000/rs6000.c (rs6000_function_arg_boundary): Issue + -Wpsabi note when encountering a type where future GCC releases + will apply different alignment requirements. + +2014-07-24 Ulrich Weigand + + * config/rs6000/rs6000.c (rs6000_function_arg): If a float argument + does not fit fully into floating-point registers, and there is still + space in the register parameter area, issue -Wpsabi note that the ABI + will change in a future GCC release. + +2014-07-23 Sebastian Huber + + * config/arm/t-rtems-eabi: Add + mthumb/march=armv7-r/mfpu=vfpv3-d16/mfloat-abi=hard, + mthumb/march=armv7-m/mfpu=fpv4-sp-d16/mfloat-abi=hard, + mbig-endian/mthumb/march=armv7-r, and + mbig-endian/mthumb/march=armv7-r/mfpu=vfpv3-d16/mfloat-abi=hard + multilibs. + +2014-07-21 Peter Bergner + + * config/rs6000/sysv4.h (LIBASAN_EARLY_SPEC): Define. + (LIBTSAN_EARLY_SPEC): Likewise. + (STATIC_LIBASAN_LIBS): Likewise. + (STATIC_LIBTSAN_LIBS): Likewise. + +2014-07-19 Eric Botcazou + + * toplev.c (output_stack_usage): Adjust the location of the warning. + +2014-07-19 Daniel Cederman + + * config/sparc/sync.md (*membar_storeload_leon3): New insn. + (*membar_storeload): Disable for LEON3. + +2014-07-17 Richard Biener + + PR rtl-optimization/61801 + * sched-deps.c (sched_analyze_2): For ASM_OPERANDS and + ASM_INPUT don't set reg_pending_barrier if it appears in a + debug-insn. + +2014-07-16 Jakub Jelinek + + * omp-low.c (create_omp_child_function): Don't set DECL_NAMELESS + on the FUNCTION_DECL. + +2014-07-10 Tom G. Christensen + + * doc/install.texi: Remove links to defunct package providers for + Solaris. + +2014-07-10 Eric Botcazou + + PR middle-end/53590 + * function.c (allocate_struct_function): Revert r188667 change. + +2014-07-04 Jakub Jelinek + + PR tree-optimization/61684 + * tree-ssa-ifcombine.c (recognize_single_bit_test): Make sure + rhs1 of conversion is a SSA_NAME before using SSA_NAME_DEF_STMT on it. + +2014-06-30 Thomas Preud'homme + + Backport from Mainline + 2014-06-20 Jakub Jelinek + 2014-06-11 Thomas Preud'homme + + PR tree-optimization/61306 + * tree-ssa-math-opts.c (struct symbolic_number): Store type of + expression instead of its size. + (do_shift_rotate): Adapt to change in struct symbolic_number. Return + false to prevent optimization when the result is unpredictable due to + arithmetic right shift of signed type with highest byte is set. + (verify_symbolic_number_p): Adapt to change in struct symbolic_number. + (find_bswap_1): Likewise. Return NULL to prevent optimization when the + result is unpredictable due to sign extension. + (find_bswap): Adapt to change in struct symbolic_number. + +2014-06-27 Uros Bizjak + + Backport from mainline + 2014-06-26 Uros Bizjak + + PR target/61586 + * config/alpha/alpha.c (alpha_handle_trap_shadows): Handle BARRIER RTX. + +2014-06-26 Bill Schmidt + + PR target/61542 + * config/rs6000/vsx.md (vsx_extract_v4sf): Fix bug with element + extraction other than index 3. + +2014-06-24 Jakub Jelinek + + PR target/61570 + * config/i386/driver-i386.c (host_detect_local_cpu): For unknown + model family 6 CPU with has_longmode never use a CPU without + 64-bit support. + +2014-06-20 Chung-Lin Tang + + Backport from mainline + + 2014-06-20 Julian Brown + Chung-Lin Tang + + * config/arm/arm.c (arm_output_mi_thunk): Fix offset for + TARGET_THUMB1_ONLY. Add comments. + +2014-06-18 Uros Bizjak + + Backport from mainline + 2014-06-06 Uros Bizjak + + PR target/61423 + * config/i386/i386.md (*floatunssi2_i387_with_xmm): New + define_insn_and_split pattern, merged from *floatunssi2_1 + and corresponding splitters. Zero extend general register + or memory input operand to XMM temporary. Enable for + TARGET_SSE2 and TARGET_INTER_UNIT_MOVES_TO_VEC only. + (floatunssi2): Update expander predicate. + +2014-06-18 Richard Henderson + + PR target/61545 + * config/aarch64/aarch64.md (tlsdesc_small): Clobber CC_REGNUM. + +2014-06-17 Nagaraju Mekala + + Revert on gcc-4_8-branch. + * config/microblaze/microblaze.md: Add movsi4_rev insn pattern. + * config/microblaze/predicates.md: Add reg_or_mem_operand predicate. + +2014-06-17 Yufeng Zhang + + Backport from mainline + + PR target/61483 + * config/aarch64/aarch64.c (aarch64_layout_arg): Add new local + variable 'size'; calculate 'size' right in the front; use + 'size' to compute 'nregs' (when 'allocate_ncrn != 0') and + pcum->aapcs_stack_words. + +2014-06-13 Peter Bergner + + Backport from mainline + + 2014-06-13 Peter Bergner + PR target/61415 + * config/rs6000/rs6000-builtin.def (BU_MISC_1): Delete. + (BU_MISC_2): Rename to ... + (BU_LDBL128_2): ... this. + * config/rs6000/rs6000.h (RS6000_BTM_LDBL128): New define. + (RS6000_BTM_COMMON): Add RS6000_BTM_LDBL128. + * config/rs6000/rs6000.c (rs6000_builtin_mask_calculate): Handle + RS6000_BTM_LDBL128. + (rs6000_invalid_builtin): Add long double 128-bit builtin support. + (rs6000_builtin_mask_names): Add RS6000_BTM_LDBL128. + * config/rs6000/rs6000.md (unpacktf_0): Remove define)expand. + (unpacktf_1): Likewise. + * doc/extend.texi (__builtin_longdouble_dw0): Remove documentation. + (__builtin_longdouble_dw1): Likewise. + * doc/sourcebuild.texi (longdouble128): Document. + +2014-06-13 Jason Merrill + + PR c++/60731 + * common.opt (-fno-gnu-unique): Add. + * config/elfos.h (USE_GNU_UNIQUE_OBJECT): Check it. + +2014-06-12 Georg-Johann Lay + + Backport from 2014-05-09 trunk r210272 + + * config/avr/avr-fixed.md (round3): Use -1U instead of -1 in + unsigned int initializers for regno_in, regno_out. + + Backport from 2014-05-14 trunk r210418 + * config/avr/avr.h (REG_CLASS_CONTENTS): Use unsigned suffix for + shifted values to avoid build warning. + + Backport from 2014-06-12 trunk r211491 + + PR target/61443 + * config/avr/avr.md (push1): Avoid (subreg(mem)) when + loading from address spaces. + +2014-06-12 Alan Modra + + PR target/61300 + * doc/tm.texi.in (INCOMING_REG_PARM_STACK_SPACE): Document. + * doc/tm.texi: Regenerate. + * function.c (INCOMING_REG_PARM_STACK_SPACE): Provide default. + Use throughout in place of REG_PARM_STACK_SPACE. + * config/rs6000/rs6000.c (rs6000_reg_parm_stack_space): Add + "incoming" param. Pass to rs6000_function_parms_need_stack. + (rs6000_function_parms_need_stack): Add "incoming" param, ignore + prototype_p when incoming. Use function decl when incoming + to handle K&R style functions. + * config/rs6000/rs6000.h (REG_PARM_STACK_SPACE): Adjust. + (INCOMING_REG_PARM_STACK_SPACE): Define. + +2014-06-06 Michael Meissner + + Back port from trunk + 2014-06-06 Michael Meissner + + PR target/61431 + * config/rs6000/vsx.md (VSX_LE): Split VSX_D into 2 separate + iterators, VSX_D that handles 64-bit types, and VSX_LE that + handles swapping the two 64-bit double words on little endian + systems. Include V1TImode and optionally TImode in VSX_LE so that + these types are properly swapped. Change all of the insns and + splits that do the 64-bit swaps to use VSX_LE. + (vsx_le_perm_load_): Likewise. + (vsx_le_perm_store_): Likewise. + (splitters for little endian memory operations): Likewise. + (vsx_xxpermdi2_le_): Likewise. + (vsx_lxvd2x2_le_): Likewise. + (vsx_stxvd2x2_le_): Likewise. + +2014-06-05 Martin Jambor + + PR ipa/61393 + * ipa-cp.c (determine_versionability): Pretend that tm_clones are + not versionable. + +2014-06-04 Richard Biener + + PR tree-optimization/61383 + * tree-ssa-ifcombine.c (bb_no_side_effects_p): Make sure + stmts can't trap. + +2014-06-03 Andrey Belevantsev + + Backport from mainline + 2014-05-14 Andrey Belevantsev + + PR rtl-optimization/60866 + * sel-sched-ir (sel_init_new_insn): New parameter old_seqno. + Default it to -1. Pass it down to init_simplejump_data. + (init_simplejump_data): New parameter old_seqno. Pass it down + to get_seqno_for_a_jump. + (get_seqno_for_a_jump): New parameter old_seqno. Use it for + initializing new jump seqno as a last resort. Add comment. + (sel_redirect_edge_and_branch): Save old seqno of the conditional + jump and pass it down to sel_init_new_insn. + (sel_redirect_edge_and_branch_force): Likewise. + +2014-06-03 Andrey Belevantsev + + Backport from mainline + 2014-05-14 Andrey Belevantsev + + PR rtl-optimization/60901 + * config/i386/i386.c (ix86_dependencies_evaluation_hook): Check that + bb predecessor belongs to the same scheduling region. Adjust comment. + +2014-06-03 Uros Bizjak + + Backport from mainline + 2014-06-02 Uros Bizjak + + PR target/61239 + * config/i386/i386.c (ix86_expand_vec_perm) [case V32QImode]: Use + GEN_INT (-128) instead of GEN_INT (128) to set MSB of QImode constant. + +2014-05-28 Guozhi Wei + + PR target/61202 + * config/aarch64/arm_neon.h (vqdmulh_n_s16): Change the last operand's + constraint. + (vqdmulhq_n_s16): Likewise. + +2014-05-28 Eric Botcazou + + Backport from mainline + 2014-05-27 Eric Botcazou + + * double-int.c (div_and_round_double) : Use the proper + predicate to detect a negative quotient. + +2014-05-28 Georg-Johann Lay + + PR target/61044 + * doc/extend.texi (Local Labels): Note that label differences are + not supported for AVR. + +2014-05-26 Michael Tautschnig + + PR target/61249 + * doc/extend.texi (X86 Built-in Functions): Fix parameter lists of + __builtin_ia32_vfrczs[sd] and __builtin_ia32_mpsadbw256. + +2014-05-23 Alan Modra + + PR target/61231 + * config/rs6000/rs6000.c (mem_operand_gpr): Handle SImode. + * config/rs6000/rs6000.md (extendsidi2_lfiwax, extendsidi2_nocell): + Use "Y" constraint rather than "m". + +2014-05-22 Peter Bergner + + Backport from mainline + 2014-05-22 Peter Bergner + + * config/rs6000/htm.md (ttest): Use correct shift value to get CR0. + +2014-05-22 Richard Earnshaw + + PR target/61208 + * arm.md (arm_cmpdi_unsigned): Fix length calculation for Thumb2. + +2013-05-22 Richard Biener + + * BASE-VER: Set to 4.8.4. + * DEV-PHASE: Set to prerelease. + +2014-05-22 Release Manager + + * GCC 4.8.3 released. + +2014-05-15 Peter Bergner + + Backport from mainline + 2014-05-15 Peter Bergner + + PR target/61193 + * config/rs6000/htmxlintrin.h (_HTM_TBEGIN_STARTED): New define. + (__TM_simple_begin): Use it. + (__TM_begin): Likewise. + +2014-05-14 Eric Botcazou + + * config/sparc/sparc-protos.h (sparc_absnegfloat_split_legitimate): + Delete. + * config/sparc/sparc.c (sparc_absnegfloat_split_legitimate): Likewise. + * config/sparc/sparc.md (fptype_ut699): New attribute. + (in_branch_delay): Return false if -mfix-ut699 is specified and + fptype_ut699 is set to single. + (truncdfsf2): Add fptype_ut699 attribute. + (fix_truncdfsi2): Likewise. + (floatsisf2): Change fptype attribute. + (fix_truncsfsi2): Likewise. + (negtf2_notv9): Delete. + (negtf2_v9): Likewise. + (negtf2_hq): New instruction. + (negtf2): New instruction and splitter. + (negdf2_notv9): Rewrite. + (abstf2_notv9): Delete. + (abstf2_hq_v9): Likewise. + (abstf2_v9): Likewise. + (abstf2_hq): New instruction. + (abstf2): New instruction and splitter. + (absdf2_notv9): Rewrite. + +2014-05-14 Matthias Klose + + Revert: + 2014-05-08 Manuel López-Ibáñez + Matthias Klose + + PR driver/61106 + * optc-gen.awk: Fix option handling for -Wunused-parameter. + +2014-05-13 Peter Bergner + + * doc/sourcebuild.texi: (dfp_hw): Document. + (p8vector_hw): Likewise. + (powerpc_eabi_ok): Likewise. + (powerpc_elfv2): Likewise. + (powerpc_htm_ok): Likewise. + (ppc_recip_hw): Likewise. + (vsx_hw): Likewise. + +2014-05-12 Senthil Kumar Selvaraj + + Backport from mainline + 2014-05-12 Senthil Kumar Selvaraj + + PR target/60991 + * config/avr/avr.c (avr_out_store_psi): Use correct constant + to restore Y. + +2014-05-09 Georg-Johann Lay + + Backport from 2014-05-09 trunk r210267 + + PR target/61055 + * config/avr/avr.md (cc): Add new attribute set_vzn. + (addqi3, addqq3, adduqq3, subqi3, subqq3, subuqq3, negqi2) [cc]: + Set cc insn attribute to set_vzn instead of set_zn for alternatives + with INC, DEC or NEG. + * config/avr/avr.c (avr_notice_update_cc): Handle SET_VZN. + (avr_out_plus_1): ADIW sets cc0 to CC_SET_CZN. + INC, DEC and ADD+ADC set cc0 to CC_CLOBBER. + +2014-05-09 Richard Sandiford + + * builtins.c (expand_builtin_setjmp_receiver): Emit a use of + the hard frame pointer. Synchronize commentary with mainline. + * cse.c (cse_insn): Only check for volatile asms. + * cselib.c (cselib_process_insn): Likewise. + * dse.c (scan_insn): Likewise. + * stmt.c (expand_nl_goto_receiver): Emit a use and a clobber of + the hard frame pointer. + +2014-05-08 Manuel López-Ibáñez + Matthias Klose + + PR driver/61106 + * optc-gen.awk: Fix option handling for -Wunused-parameter. + +2014-05-08 Uros Bizjak + + PR target/59952 + * config/i386/i386.c (ix86_option_override_internal): Remove PTA_RTM + from core-avx2. + +2014-05-08 Charles Baylis + + Backport from mainline + 2014-04-07 Charles Baylis + + PR target/60609 + * config/arm/arm.h (ASM_OUTPUT_CASE_END): Remove. + (LABEL_ALIGN_AFTER_BARRIER): Align barriers which occur after + ADDR_DIFF_VEC. + +2014-05-06 Kyrylo Tkachov + + * config.gcc (aarch64*-*-*): Use ISA flags from aarch64-arches.def. + Do not define target_cpu_default2 to generic. + +2014-05-06 Richard Biener + + Backport from mainline + 2014-04-14 Richard Biener + + PR middle-end/55022 + * fold-const.c (negate_expr_p): Don't negate directional rounding + division. + (fold_negate_expr): Likewise. + +2014-05-06 Richard Biener + + Backport from mainline + 2014-04-17 Richard Biener + + PR middle-end/60849 + * tree-ssa-propagate.c (valid_gimple_rhs_p): Only allow effective + boolean results for comparisons. + + 2014-04-07 Richard Biener + + PR tree-optimization/60766 + * tree-ssa-loop-ivopts.c (cand_value_at): Compute in an + unsigned type. + (may_eliminate_iv): Convert cand_value_at result to desired + type. + + 2014-04-23 Richard Biener + + PR tree-optimization/60903 + * tree-ssa-loop-im.c (execute_sm_if_changed): Properly apply + IRREDUCIBLE_LOOP loop flags to newly created BBs and edges. + +2014-05-05 Richard Biener + + Backport from mainline + 2014-04-23 Richard Biener + + PR middle-end/60895 + * tree-inline.c (declare_return_variable): Use mark_addressable. + + 2014-04-07 Richard Biener + + PR middle-end/60750 + * tree-ssa-operands.c (maybe_add_call_vops): Also add VDEFs + for noreturn calls. + * tree-cfgcleanup.c (fixup_noreturn_call): Do not remove VDEFs. + + 2014-04-14 Richard Biener + + PR tree-optimization/59817 + PR tree-optimization/60453 + * graphite-scop-detection.c (graphite_can_represent_scev): Complete + recursion to catch all CHRECs in the scalar evolution and restrict + the predicate for the remains appropriately. + + 2014-04-17 Richard Biener + + PR tree-optimization/60836 + * tree-vect-loop.c (vect_create_epilog_for_reduction): Force + initial PHI args to be gimple values. + +2014-05-05 Jakub Jelinek + + Backported from mainline + 2014-04-25 Jakub Jelinek + + PR tree-optimization/60960 + * tree-vect-generic.c (expand_vector_operation): Only call + expand_vector_divmod if type's mode satisfies VECTOR_MODE_P. + +2014-05-04 Peter Bergner + + * config/rs6000/rs6000.h (RS6000_BTM_HARD_FLOAT): New define. + (RS6000_BTM_COMMON): Add RS6000_BTM_HARD_FLOAT. + (TARGET_EXTRA_BUILTINS): Add TARGET_HARD_FLOAT. + * config/rs6000/rs6000-builtin.def (BU_MISC_1): + Use RS6000_BTM_HARD_FLOAT. + (BU_MISC_2): Likewise. + * config/rs6000/rs6000.c (rs6000_builtin_mask_calculate): Handle + RS6000_BTM_HARD_FLOAT. + (rs6000_option_override_internal): Enforce -mhard-float if -mhard-dfp + is explicitly used. + (rs6000_invalid_builtin): Add hard floating builtin support. + (rs6000_expand_builtin): Relax the gcc_assert to allow the new + hard float builtins. + (rs6000_builtin_mask_names): Add RS6000_BTM_HARD_FLOAT. + +2014-05-03 Joey Ye + + Backport from mainline r209463 + 2014-04-17 Joey Ye + + * opts.c (OPT_fif_conversion, OPT_fif_conversion2): Disable for Og. + +2014-05-03 Oleg Endo + + Back port from mainline + PR target/61026 + * config/sh/sh.c: Include stdlib headers before everything else. + +2014-05-02 Bill Schmidt + + PR tree-optimization/60930 + * gimple-ssa-strength-reduction.c (create_mul_imm_cand): Reject + creating a multiply candidate by folding two constant + multiplicands when the result overflows. + +2014-05-02 Kyrylo Tkachov + + * config/aarch64/aarch64.h (TARGET_SIMD): Take AARCH64_ISA_SIMD + into account. + (TARGET_FLOAT): Take AARCH64_ISA_FP into account. + +2014-04-30 Michael Meissner + + Back port from mainline + 2014-04-24 Michael Meissner + + * doc/extend.texi (PowerPC Built-in Functions): Document new + powerpc extended divide, bcd, pack/unpack 128-bit, builtin + functions. + (PowerPC AltiVec/VSX Built-in Functions): Likewise. + + * config/rs6000/predicates.md (const_0_to_3_operand): New + predicate to match 0..3 integer constants. + + * config/rs6000/rs6000-builtin.def (BU_DFP_MISC_1): Add new macros + to support adding miscellaneous builtin functions. + (BU_DFP_MISC_2): Likewise. + (BU_P7_MISC_1): Likewise. + (BU_P7_MISC_2): Likewise. + (BU_P8V_MISC_3): Likewise. + (BU_MISC_1): Likewise. + (BU_MISC_2): Likewise. + (DIVWE): Add extended divide builtin functions. + (DIVWEO): Likewise. + (DIVWEU): Likewise. + (DIVWEUO): Likewise. + (DIVDE): Likewise. + (DIVDEO): Likewise. + (DIVDEU): Likewise. + (DIVDEUO): Likewise. + (DXEX): Add decimal floating-point builtin functions. + (DXEXQ): Likewise. + (DDEDPD): Likewise. + (DDEDPDQ): Likewise. + (DENBCD): Likewise. + (DENBCDQ): Likewise. + (DIEX): Likewise. + (DIEXQ): Likewise. + (DSCLI): Likewise. + (DSCLIQ): Likewise. + (DSCRI): Likewise. + (DSCRIQ): Likewise. + (CDTBCD): Add new BCD builtin functions. + (CBCDTD): Likewise. + (ADDG6S): Likewise. + (BCDADD): Likewise. + (BCDADD_LT): Likewise. + (BCDADD_EQ): Likewise. + (BCDADD_GT): Likewise. + (BCDADD_OV): Likewise. + (BCDSUB): Likewise. + (BCDSUB_LT): Likewise. + (BCDSUB_EQ): Likewise. + (BCDSUB_GT): Likewise. + (BCDSUB_OV): Likewise. + (PACK_TD): Add new pack/unpack 128-bit type builtin functions. + (UNPACK_TD): Likewise. + (PACK_TF): Likewise. + (UNPACK_TF): Likewise. + (UNPACK_TF_0): Likewise. + (UNPACK_TF_1): Likewise. + (PACK_V1TI): Likewise. + (UNPACK_V1TI): Likewise. + + * config/rs6000/rs6000.c (rs6000_builtin_mask_calculate): Add + support for decimal floating point builtin functions. + (rs6000_expand_ternop_builtin): Add checks for the new builtin + functions that take constant arguments. + (rs6000_invalid_builtin): Add decimal floating point builtin + support. + (rs6000_init_builtins): Setup long double, _Decimal64, and + _Decimal128 types for new builtin functions. + (builtin_function_type): Set the unsigned flags appropriately for + the new builtin functions. + (rs6000_opt_masks): Add support for decimal floating point builtin + functions. + + * config/rs6000/rs6000.h (RS6000_BTM_DFP): Add support for decimal + floating point builtin functions. + (RS6000_BTM_COMMON): Likewise. + (RS6000_BTI_long_double): Likewise. + (RS6000_BTI_dfloat64): Likewise. + (RS6000_BTI_dfloat128): Likewise. + (long_double_type_internal_node): Likewise. + (dfloat64_type_internal_node): Likewise. + (dfloat128_type_internal_node): Likewise. + + * config/rs6000/altivec.h (UNSPEC_BCDADD): Add support for ISA + 2.07 bcd arithmetic instructions. + (UNSPEC_BCDSUB): Likewise. + (UNSPEC_BCD_OVERFLOW): Likewise. + (UNSPEC_BCD_ADD_SUB): Likewise. + (bcd_add_sub): Likewise. + (BCD_TEST): Likewise. + (bcd): Likewise. + (bcd_test): Likewise. + (bcd_test2): Likewise. + (bcd_): Likewise. + (peephole2 for combined bcd ops): Likewise. + + * config/rs6000/dfp.md (UNSPEC_DDEDPD): Add support for new + decimal floating point builtin functions. + (UNSPEC_DENBCD): Likewise. + (UNSPEC_DXEX): Likewise. + (UNSPEC_DIEX): Likewise. + (UNSPEC_DSCLI): Likewise. + (UNSPEC_DSCRI): Likewise. + (D64_D128): Likewise. + (dfp_suffix): Likewise. + (dfp_ddedpd_): Likewise. + (dfp_denbcd_): Likewise. + (dfp_dxex_): Likewise. + (dfp_diex_): Likewise. + (dfp_dscli_): Likewise. + (dfp_dscri_): Likewise. + + * config/rs6000/rs6000.md (UNSPEC_ADDG6S): Add support for new BCD + builtin functions. + (UNSPEC_CDTBCD): Likewise. + (UNSPEC_CBCDTD): Likewise. + (UNSPEC_DIVE): Add support for new extended divide builtin + functions. + (UNSPEC_DIVEO): Likewise. + (UNSPEC_DIVEU): Likewise. + (UNSPEC_DIVEUO): Likewise. + (UNSPEC_UNPACK_128BIT): Add support for new builtin functions to + pack/unpack 128-bit types. + (UNSPEC_PACK_128BIT): Likewise. + (idiv_ldiv): New mode attribute to set the 32/64-bit divide type. + (udiv3): Use idiv_ldiv mode attribute. + (div3): Likewise. + (addg6s): Add new BCD builtin functions. + (cdtbcd): Likewise. + (cbcdtd): Likewise. + (UNSPEC_DIV_EXTEND): Add support for new extended divide + instructions. + (div_extend): Likewise. + (div_"): Likewise. + (FP128_64): Add support for new builtin functions to pack/unpack + 128-bit types. + (unpack): Likewise. + (unpacktf_0): Likewise. + (unpacktf_1): Likewise. + (unpack_dm): Likewise. + (unpack_nodm): Likewise. + (pack): Likewise. + (unpackv1ti): Likewise. + (packv1ti): Likewise. + +2014-04-29 Pat Haugen + + Backport from mainline + 2014-04-17 Pat Haugen + + * config/rs6000/rs6000.md (addti3, subti3): New. + +2014-04-28 Pat Haugen + + Backport from mainline + 2014-04-28 Pat Haugen + + * config/rs6000/sync.md (AINT mode_iterator): Move definition. + (loadsync_): Change mode. + (load_quadpti, store_quadpti): New. + (atomic_load, atomic_store): Add support for TI mode. + * config/rs6000/rs6000.md (unspec enum): Add UNSPEC_LSQ. + +2014-04-28 Eric Botcazou + + * configure.ac: Tweak GAS check for LEON instructions on SPARC. + * configure: Regenerate. + * config/sparc/sparc.opt (muser-mode): New option. + * config/sparc/sync.md (atomic_compare_and_swap_1): Do not enable + for LEON3. + (atomic_compare_and_swap_leon3_1): New instruction for LEON3. + * doc/invoke.texi (SPARC options): Document -muser-mode. + +2014-04-25 Eric Botcazou + + PR target/60941 + * config/sparc/sparc.md (ashlsi3_extend): Delete. + +2014-04-22 Michael Meissner + + Back port from main line: + 2014-03-27 Michael Meissner + + * config/rs6000/rs6000-builtins.def (VBPERMQ): Add vbpermq builtin + for ISA 2.07. + + * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add + vbpermq builtins. + + * config/rs6000/altivec.md (UNSPEC_VBPERMQ): Add support for the + vbpermq instruction. + (altivec_vbpermq): Likewise. + + PR target/60672 + * config/rs6000/altivec.h (vec_xxsldwi): Add missing define to + enable use of xxsldwi and xxpermdi builtin functions. + (vec_xxpermdi): Likewise. + + * doc/extend.texi (PowerPC AltiVec/VSX Built-in Functions): + Document use of vec_xxsldwi and vec_xxpermdi builtins. + +2014-04-23 Uros Bizjak + + Backport from mainline + 2014-04-21 Uros Bizjak + + PR target/60909 + * config/i386/i386.c (ix86_expand_builtin) + : Use temporary + register for target RTX. + : Ditto. + +2014-04-23 Richard Biener + + Backport from mainline + 2014-04-02 Richard Biener + + PR middle-end/60729 + * optabs.c (expand_abs_nojump): Honor flag_trapv only for + MODE_INTs. Properly use negv_optab. + (expand_abs): Likewise. + + 2014-04-03 Richard Biener + + PR tree-optimization/60740 + * graphite-scop-detection.c (stmt_simple_for_scop_p): Iterate + over all GIMPLE_COND operands. + +2014-04-23 Richard Biener + + PR middle-end/60635 + * gimplify.c (gimple_regimplify_operands): Update the + re-gimplifed stmt. + +2014-04-21 Michael Meissner + + Back port from the trunk, subversion id 209546. + + 2014-04-21 Michael Meissner + + PR target/60735 + * config/rs6000/rs6000.md (mov_softfloat32, FMOVE64 case): + If mode is DDmode and TARGET_E500_DOUBLE allow move. + + * config/rs6000/rs6000.c (rs6000_debug_reg_global): Print some + more debug information for E500 if -mdebug=reg. + +2014-04-18 Richard Henderson + + * config/aarch64/aarch64.c (aarch64_register_move_cost): Pass a mode + to GET_MODE_SIZE, not a reg_class_t. + +2014-04-17 Bill Schmidt + + * config/rs6000/vsx.md (vsx_xxmrghw_): Adjust for + little-endian. + (vsx_xxmrglw_): Likewise. + +2014-04-15 Bill Schmidt + + PR target/60839 + Revert the following patch + + 2014-04-04 Bill Schmidt + + Back port mainline subversion id 209025. + 2014-04-02 Michael Meissner + + PR target/60735 + * config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): If we have + software floating point or no floating point registers, do not + allow any type in the FPRs. Eliminate a test for SPE SIMD types + in GPRs that occurs after we tested for GPRs that would never be + true. + + * config/rs6000/rs6000.md (mov_softfloat32, FMOVE64): + Rewrite tests to use TARGET_DOUBLE_FLOAT and TARGET_E500_DOUBLE, + since the FMOVE64 type is DFmode/DDmode. If TARGET_E500_DOUBLE, + specifically allow DDmode, since that does not use the SPE SIMD + instructions. + +2014-04-10 Vladimir Makarov + + PR rtl-optimization/60769 + * lra-constraints.c (simplify_operand_subreg): Force reload of + paradoxical subreg if it is not in the class contents. + +2014-04-10 Jakub Jelinek + + Backport from mainline + 2014-03-12 Jakub Jelinek + Marc Glisse + + PR tree-optimization/60502 + * tree-ssa-reassoc.c (eliminate_not_pairs): Use build_all_ones_cst + instead of build_low_bits_mask. + + 2013-06-13 Marc Glisse + + * tree.c (build_all_ones_cst): New function. + * tree.h (build_all_ones_cst): Declare it. + + 2013-05-10 Marc Glisse + + * tree.c (build_minus_one_cst): New function. + * tree.h (build_minus_one_cst): Declare new function. + +2014-04-10 Jakub Jelinek + + Backport from mainline + 2014-03-28 Jakub Jelinek + + PR target/60693 + * config/i386/i386.c (ix86_copy_addr_to_reg): Call copy_addr_to_reg + also if addr has VOIDmode. + + 2014-03-17 Jakub Jelinek + + PR target/60516 + * config/i386/i386.c (ix86_expand_epilogue): Adjust REG_CFA_ADJUST_CFA + note creation for the 2010-08-31 changes. + + 2014-03-06 Jakub Jelinek + Meador Inge + + PR target/58595 + * config/arm/arm.c (arm_tls_symbol_p): Remove. + (arm_legitimize_address): Call legitimize_tls_address for any + arm_tls_referenced_p expression, handle constant addend. Call it + before testing for !TARGET_ARM. + (thumb_legitimize_address): Don't handle arm_tls_symbol_p here. + +2014-04-09 Bill Schmidt + + Backport from mainline r208750 + 2014-03-21 Bill Schmidt + + * config/rs6000/rs6000.c (rs6000_expand_vector_set): Generate a + pattern for vector nor instead of subtract from splat(-1). + (altivec_expand_vec_perm_const_le): Likewise. + + Backport from mainline r209235 + 2014-04-08 Bill Schmidt + + * config/rs6000/rs6000.c (rs6000_expand_vector_set): Use vnand + instead of vnor to exploit possible fusion opportunity in the + future. + (altivec_expand_vec_perm_const_le): Likewise. + +2014-04-09 Bill Schmidt + + Revert following patch + 2014-04-08 Pat Haugen + + Backport from mainline + 2014-04-08 Pat Haugen + + * config/rs6000/sync.md (AINT mode_iterator): Move definition. + (loadsync_): Change mode. + (load_quadpti, store_quadpti): New. + (atomic_load, atomic_store): Add support for TI mode. + * config/rs6000/rs6000.md (unspec enum): Add UNSPEC_LSQ. + +2014-04-09 Bill Schmidt + + Backport from mainline r202642 + 2013-09-17 Alan Modra + + PR target/57589 + * config/rs6000/driver-rs6000.c (elf_platform): Revert 2013-06-11 + patch (r199972). + +2014-04-08 Pat Haugen + + Backport from mainline + 2014-04-08 Pat Haugen + + * config/rs6000/sync.md (AINT mode_iterator): Move definition. + (loadsync_): Change mode. + (load_quadpti, store_quadpti): New. + (atomic_load, atomic_store): Add support for TI mode. + * config/rs6000/rs6000.md (unspec enum): Add UNSPEC_LSQ. + +2014-04-07 Martin Jambor + + PR ipa/60640 + * ipa-cp.c (propagate_constants_accross_call): Do not propagate + accross thunks. + +2014-04-07 Dominique d'Humieres + + Backport from mainline + 2013-09-14 Iain Sandoe + + PR target/48094 + * config/darwin.c (darwin_objc2_section): Note if ObjC Metadata + is seen. + (darwin_objc1_section): Likewise. + (darwin_file_end): Emit Image Info section when required. + +2014-04-05 Alan Modra + + Apply from mainline + 2014-01-28 Alan Modra + * Makefile.in (BUILD_CPPFLAGS): Do not use ALL_CPPFLAGS. + * configure.ac : Define + GENERATOR_FILE. Comment. Use CXX_FOR_BUILD, CXXFLAGS_FOR_BUILD + and LD_FOR_BUILD too. + * configure: Regenerate. + +2014-04-04 Ulrich Weigand + + Backport from mainline r208895: + 2014-03-28 Ulrich Weigand + + * config/rs6000/rs6000.c (fusion_gpr_load_p): Refuse optimization + if it would clobber the stack pointer, even temporarily. + +2014-04-04 Bill Schmidt + + Back port from main line: + 2014-04-01 Michael Meissner + + * doc/extend.texi (PowerPC AltiVec/VSX Built-in Functions): + Document vec_vgbbd. + +2014-04-04 Bill Schmidt + + Back port mainline subversion id 209025. + 2014-04-02 Michael Meissner + + PR target/60735 + * config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): If we have + software floating point or no floating point registers, do not + allow any type in the FPRs. Eliminate a test for SPE SIMD types + in GPRs that occurs after we tested for GPRs that would never be + true. + + * config/rs6000/rs6000.md (mov_softfloat32, FMOVE64): + Rewrite tests to use TARGET_DOUBLE_FLOAT and TARGET_E500_DOUBLE, + since the FMOVE64 type is DFmode/DDmode. If TARGET_E500_DOUBLE, + specifically allow DDmode, since that does not use the SPE SIMD + instructions. + +2014-04-04 Bill Schmidt + + Backport from mainline r205308 + 2013-11-23 David Edelsohn + + * config/rs6000/rs6000.c (IN_NAMED_SECTION): New macro. + (rs6000_xcoff_select_section): Place decls with stricter alignment + into named sections. + (rs6000_xcoff_unique_section): Allow unique sections for + uninitialized data with strict alignment. + +2014-04-04 Bill Schmidt + + Backport from mainline + 2013-11-15 Ulrich Weigand + + * gcc/configure: Regenerate. + +2014-04-04 Bill Schmidt + + Back port from trunk + 2013-04-25 Alan Modra + + PR target/57052 + * config/rs6000/rs6000.md (rotlsi3_internal7): Rename to + rotlsi3_internal7le and condition on !BYTES_BIG_ENDIAN. + (rotlsi3_internal8be): New BYTES_BIG_ENDIAN insn. + Repeat for many other rotate/shift and mask patterns using subregs. + Name lshiftrt insns. + (ashrdisi3_noppc64): Rename to ashrdisi3_noppc64be and condition + on WORDS_BIG_ENDIAN. + + 2013-06-07 Alan Modra + + * config/rs6000/rs6000.c (rs6000_option_override_internal): Don't + override user -mfp-in-toc. + (offsettable_ok_by_alignment): Consider just the current access + rather than the whole object, unless BLKmode. Handle + CONSTANT_POOL_ADDRESS_P constants that lack a decl too. + (use_toc_relative_ref): Allow CONSTANT_POOL_ADDRESS_P constants + for -mcmodel=medium. + * config/rs6000/linux64.h (SUBSUBTARGET_OVERRIDE_OPTIONS): Don't + override user -mfp-in-toc or -msum-in-toc. Default to + -mno-fp-in-toc for -mcmodel=medium. + + 2013-06-18 Alan Modra + + * config/rs6000/rs6000.h (enum data_align): New. + (LOCAL_ALIGNMENT, DATA_ALIGNMENT): Use rs6000_data_alignment. + (DATA_ABI_ALIGNMENT): Define. + (CONSTANT_ALIGNMENT): Correct comment. + * config/rs6000/rs6000-protos.h (rs6000_data_alignment): Declare. + * config/rs6000/rs6000.c (rs6000_data_alignment): New function. + + 2013-07-11 Ulrich Weigand + + * config/rs6000/rs6000.md (""*tls_gd_low"): + Require GOT register as additional operand in UNSPEC. + ("*tls_ld_low"): Likewise. + ("*tls_got_dtprel_low"): Likewise. + ("*tls_got_tprel_low"): Likewise. + ("*tls_gd"): Update splitter. + ("*tls_ld"): Likewise. + ("tls_got_dtprel_"): Likewise. + ("tls_got_tprel_"): Likewise. + + 2014-01-23 Pat Haugen + + * config/rs6000/rs6000.c (rs6000_option_override_internal): Don't + force flag_ira_loop_pressure if set via command line. + + 2014-02-06 Alan Modra + + PR target/60032 + * config/rs6000/rs6000.c (rs6000_secondary_memory_needed_mode): Only + change SDmode to DDmode when lra_in_progress. + +2014-04-04 Bill Schmidt + + V1TImode Support + Back port from trunk + 2014-03-12 Michael Meissner + + * config/rs6000/vector.md (VEC_L): Add V1TI mode to vector types. + (VEC_M): Likewise. + (VEC_N): Likewise. + (VEC_R): Likewise. + (VEC_base): Likewise. + (mov, VEC_M modes): If we are loading TImode into VSX + registers, we need to swap double words in little endian mode. + + * config/rs6000/rs6000-modes.def (V1TImode): Add new vector mode + to be a container mode for 128-bit integer operations added in ISA + 2.07. Unlike TImode and PTImode, the preferred register set is + the Altivec/VMX registers for the 128-bit operations. + + * config/rs6000/rs6000-protos.h (rs6000_move_128bit_ok_p): Add + declarations. + (rs6000_split_128bit_ok_p): Likewise. + + * config/rs6000/rs6000-builtin.def (BU_P8V_AV_3): Add new support + macros for creating ISA 2.07 normal and overloaded builtin + functions with 3 arguments. + (BU_P8V_OVERLOAD_3): Likewise. + (VPERM_1T): Add support for V1TImode in 128-bit vector operations + for use as overloaded functions. + (VPERM_1TI_UNS): Likewise. + (VSEL_1TI): Likewise. + (VSEL_1TI_UNS): Likewise. + (ST_INTERNAL_1ti): Likewise. + (LD_INTERNAL_1ti): Likewise. + (XXSEL_1TI): Likewise. + (XXSEL_1TI_UNS): Likewise. + (VPERM_1TI): Likewise. + (VPERM_1TI_UNS): Likewise. + (XXPERMDI_1TI): Likewise. + (SET_1TI): Likewise. + (LXVD2X_V1TI): Likewise. + (STXVD2X_V1TI): Likewise. + (VEC_INIT_V1TI): Likewise. + (VEC_SET_V1TI): Likewise. + (VEC_EXT_V1TI): Likewise. + (EQV_V1TI): Likewise. + (NAND_V1TI): Likewise. + (ORC_V1TI): Likewise. + (VADDCUQ): Add support for 128-bit integer arithmetic instructions + added in ISA 2.07. Add both normal 'altivec' builtins, and the + overloaded builtin. + (VADDUQM): Likewise. + (VSUBCUQ): Likewise. + (VADDEUQM): Likewise. + (VADDECUQ): Likewise. + (VSUBEUQM): Likewise. + (VSUBECUQ): Likewise. + + * config/rs6000/rs6000-c.c (__int128_type): New static to hold + __int128_t and __uint128_t types. + (__uint128_type): Likewise. + (altivec_categorize_keyword): Add support for vector __int128_t, + vector __uint128_t, vector __int128, and vector unsigned __int128 + as a container type for TImode operations that need to be done in + VSX/Altivec registers. + (rs6000_macro_to_expand): Likewise. + (altivec_overloaded_builtins): Add ISA 2.07 overloaded functions + to support 128-bit integer instructions vaddcuq, vadduqm, + vaddecuq, vaddeuqm, vsubcuq, vsubuqm, vsubecuq, vsubeuqm. + (altivec_resolve_overloaded_builtin): Add support for V1TImode. + + * config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): Add support + for V1TImode, and set up preferences to use VSX/Altivec + registers. Setup VSX reload handlers. + (rs6000_debug_reg_global): Likewise. + (rs6000_init_hard_regno_mode_ok): Likewise. + (rs6000_preferred_simd_mode): Likewise. + (vspltis_constant): Do not allow V1TImode as easy altivec + constants. + (easy_altivec_constant): Likewise. + (output_vec_const_move): Likewise. + (rs6000_expand_vector_set): Convert V1TImode set and extract to + simple move. + (rs6000_expand_vector_extract): Likewise. + (reg_offset_addressing_ok_p): Setup V1TImode to use VSX reg+reg + addressing. + (rs6000_const_vec): Add support for V1TImode. + (rs6000_emit_le_vsx_load): Swap double words when loading or + storing TImode/V1TImode. + (rs6000_emit_le_vsx_store): Likewise. + (rs6000_emit_le_vsx_move): Likewise. + (rs6000_emit_move): Add support for V1TImode. + (altivec_expand_ld_builtin): Likewise. + (altivec_expand_st_builtin): Likewise. + (altivec_expand_vec_init_builtin): Likewise. + (altivec_expand_builtin): Likewise. + (rs6000_init_builtins): Add support for V1TImode type. Add + support for ISA 2.07 128-bit integer builtins. Define type names + for the VSX/Altivec vector types. + (altivec_init_builtins): Add support for overloaded vector + functions with V1TImode type. + (rs6000_preferred_reload_class): Prefer Altivec registers for + V1TImode. + (rs6000_move_128bit_ok_p): Move 128-bit move/split validation to + external function. + (rs6000_split_128bit_ok_p): Likewise. + (rs6000_handle_altivec_attribute): Create V1TImode from vector + __int128_t and vector __uint128_t. + + * config/rs6000/vsx.md (VSX_L): Add V1TImode to vector iterators + and mode attributes. + (VSX_M): Likewise. + (VSX_M2): Likewise. + (VSm): Likewise. + (VSs): Likewise. + (VSr): Likewise. + (VSv): Likewise. + (VS_scalar): Likewise. + (VS_double): Likewise. + (vsx_set_v1ti): New builtin function to create V1TImode from + TImode. + + * config/rs6000/rs6000.h (TARGET_VADDUQM): New macro to say + whether we support the ISA 2.07 128-bit integer arithmetic + instructions. + (ALTIVEC_OR_VSX_VECTOR_MODE): Add V1TImode. + (enum rs6000_builtin_type_index): Add fields to hold V1TImode + and TImode types for use with the builtin functions. + (V1TI_type_node): Likewise. + (unsigned_V1TI_type_node): Likewise. + (intTI_type_internal_node): Likewise. + (uintTI_type_internal_node): Likewise. + + * config/rs6000/altivec.md (UNSPEC_VADDCUQ): New unspecs for ISA + 2.07 128-bit builtin functions. + (UNSPEC_VADDEUQM): Likewise. + (UNSPEC_VADDECUQ): Likewise. + (UNSPEC_VSUBCUQ): Likewise. + (UNSPEC_VSUBEUQM): Likewise. + (UNSPEC_VSUBECUQ): Likewise. + (VM): Add V1TImode to vector mode iterators. + (VM2): Likewise. + (VI_unit): Likewise. + (altivec_vadduqm): Add ISA 2.07 128-bit binary builtins. + (altivec_vaddcuq): Likewise. + (altivec_vsubuqm): Likewise. + (altivec_vsubcuq): Likewise. + (altivec_vaddeuqm): Likewise. + (altivec_vaddecuq): Likewise. + (altivec_vsubeuqm): Likewise. + (altivec_vsubecuq): Likewise. + + * config/rs6000/rs6000.md (FMOVE128_GPR): Add V1TImode to vector + mode iterators. + (BOOL_128): Likewise. + (BOOL_REGS_OUTPUT): Likewise. + (BOOL_REGS_OP1): Likewise. + (BOOL_REGS_OP2): Likewise. + (BOOL_REGS_UNARY): Likewise. + (BOOL_REGS_AND_CR0): Likewise. + + * config/rs6000/altivec.h (vec_vaddcuq): Add support for ISA 2.07 + 128-bit integer builtin support. + (vec_vadduqm): Likewise. + (vec_vaddecuq): Likewise. + (vec_vaddeuqm): Likewise. + (vec_vsubecuq): Likewise. + (vec_vsubeuqm): Likewise. + (vec_vsubcuq): Likewise. + (vec_vsubuqm): Likewise. + + * doc/extend.texi (PowerPC AltiVec/VSX Built-in Functions): + Document vec_vaddcuq, vec_vadduqm, vec_vaddecuq, vec_vaddeuqm, + vec_subecuq, vec_subeuqm, vec_vsubcuq, vec_vsubeqm builtins adding + 128-bit integer add/subtract to ISA 2.07. + +2014-04-04 Bill Schmidt + + Apply mainline r207798 + 2014-02-26 Alan Modra + PR target/58675 + PR target/57935 + * config/rs6000/rs6000.c (rs6000_secondary_reload_inner): Use + find_replacement on parts of insn rtl that might be reloaded. + + Backport from mainline r208287 + 2014-03-03 Bill Schmidt + + * config/rs6000/rs6000.c (rs6000_preferred_reload_class): Disallow + reload of PLUS rtx's outside of GENERAL_REGS or BASE_REGS; relax + constraint on constants to permit them being loaded into + GENERAL_REGS or BASE_REGS. + +2014-04-04 Bill Schmidt + + Backport from mainline r207699. + 2014-02-11 Michael Meissner + + PR target/60137 + * config/rs6000/rs6000.md (128-bit GPR splitter): Add a splitter + for VSX/Altivec vectors that land in GPR registers. + + Backport from mainline r207808. + 2014-02-15 Michael Meissner + + PR target/60203 + * config/rs6000/rs6000.md (rreg): Add TFmode, TDmode constraints. + (mov_internal, TFmode/TDmode): Split TFmode/TDmode moves + into 64-bit and 32-bit moves. On 64-bit moves, add support for + using direct move instructions on ISA 2.07. Also adjust + instruction length for 64-bit. + (mov_64bit, TFmode/TDmode): Likewise. + (mov_32bit, TFmode/TDmode): Likewise. + + Backport from mainline r207868. + 2014-02-18 Michael Meissner + + PR target/60203 + * config/rs6000/rs6000.md (mov_64bit, TF/TDmode moves): + Split 64-bit moves into 2 patterns. Do not allow the use of + direct move for TDmode in little endian, since the decimal value + has little endian bytes within a word, but the 64-bit pieces are + ordered in a big endian fashion, and normal subreg's of TDmode are + not allowed. + (mov_64bit_dm): Likewise. + (movtd_64bit_nodm): Likewise. + +2014-04-04 Bill Schmidt + + Backport from mainline r207658 + 2014-02-06 Ulrich Weigand + + * config/rs6000/sysv4.h (ENDIAN_SELECT): Do not attempt to enforce + big-endian mode for -mcall-aixdesc, -mcall-freebsd, -mcall-netbsd, + -mcall-openbsd, or -mcall-linux. + (CC1_ENDIAN_BIG_SPEC): Remove. + (CC1_ENDIAN_LITTLE_SPEC): Remove. + (CC1_ENDIAN_DEFAULT_SPEC): Remove. + (CC1_SPEC): Remove (always empty) %cc1_endian_... spec. + (SUBTARGET_EXTRA_SPECS): Remove %cc1_endian_big, %cc1_endian_little, + and %cc1_endian_default. + * config/rs6000/sysv4le.h (CC1_ENDIAN_DEFAULT_SPEC): Remove. + +2014-04-04 Bill Schmidt + + Little Endian Vector API Support + Backport from mainline r206443 + 2014-01-08 Bill Schmidt + + * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Remove + two duplicate entries. + + Backport from mainline r206494 + 2014-01-09 Bill Schmidt + + * doc/invoke.texi: Add -maltivec={be,le} options, and document + default element-order behavior for -maltivec. + * config/rs6000/rs6000.opt: Add -maltivec={be,le} options. + * config/rs6000/rs6000.c (rs6000_option_override_internal): Ensure + that -maltivec={le,be} implies -maltivec; disallow -maltivec=le + when targeting big endian, at least for now. + * config/rs6000/rs6000.h: Add #define of VECTOR_ELT_ORDER_BIG. + + Backport from mainline r206541 + 2014-01-10 Bill Schmidt + + * config/rs6000/rs6000-builtin.def: Fix pasto for VPKSDUS. + + Backport from mainline r206590 + 2014-01-13 Bill Schmidt + + * config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin): + Implement -maltivec=be for vec_insert and vec_extract. + + Backport from mainline r206641 + 2014-01-15 Bill Schmidt + + * config/rs6000/altivec.md (mulv8hi3): Explicitly generate vmulesh + and vmulosh rather than call gen_vec_widen_smult_*. + (vec_widen_umult_even_v16qi): Test VECTOR_ELT_ORDER_BIG rather + than BYTES_BIG_ENDIAN to determine use of even or odd instruction. + (vec_widen_smult_even_v16qi): Likewise. + (vec_widen_umult_even_v8hi): Likewise. + (vec_widen_smult_even_v8hi): Likewise. + (vec_widen_umult_odd_v16qi): Likewise. + (vec_widen_smult_odd_v16qi): Likewise. + (vec_widen_umult_odd_v8hi): Likewise. + (vec_widen_smult_odd_v8hi): Likewise. + (vec_widen_umult_hi_v16qi): Explicitly generate vmuleub and + vmuloub rather than call gen_vec_widen_umult_*. + (vec_widen_umult_lo_v16qi): Likewise. + (vec_widen_smult_hi_v16qi): Explicitly generate vmulesb and + vmulosb rather than call gen_vec_widen_smult_*. + (vec_widen_smult_lo_v16qi): Likewise. + (vec_widen_umult_hi_v8hi): Explicitly generate vmuleuh and vmulouh + rather than call gen_vec_widen_umult_*. + (vec_widen_umult_lo_v8hi): Likewise. + (vec_widen_smult_hi_v8hi): Explicitly gnerate vmulesh and vmulosh + rather than call gen_vec_widen_smult_*. + (vec_widen_smult_lo_v8hi): Likewise. + + Backport from mainline r207062 + 2014-01-24 Bill Schmidt + + * config/rs6000/rs6000.c (rs6000_expand_vec_perm_const_1): Remove + correction for little endian... + * config/rs6000/vsx.md (vsx_xxpermdi2__1): ...and move it to + here. + + Backport from mainline r207262 + 2014-01-29 Bill Schmidt + + * config/rs6000/rs6000.c (altivec_expand_vec_perm_const): Use + CODE_FOR_altivec_vmrg*_direct rather than CODE_FOR_altivec_vmrg*. + * config/rs6000/vsx.md (vsx_mergel_): Adjust for + -maltivec=be with LE targets. + (vsx_mergeh_): Likewise. + * config/rs6000/altivec.md (UNSPEC_VMRG[HL]_DIRECT): New + unspecs. + (mulv8hi3): Use gen_altivec_vmrg[hl]w_direct. + (altivec_vmrghb): Replace with define_expand and new + *altivec_vmrghb_internal insn; adjust for -maltivec=be with LE + targets. + (altivec_vmrghb_direct): New define_insn. + (altivec_vmrghh): Replace with define_expand and new + *altivec_vmrghh_internal insn; adjust for -maltivec=be with LE + targets. + (altivec_vmrghh_direct): New define_insn. + (altivec_vmrghw): Replace with define_expand and new + *altivec_vmrghw_internal insn; adjust for -maltivec=be with LE + targets. + (altivec_vmrghw_direct): New define_insn. + (*altivec_vmrghsf): Adjust for endianness. + (altivec_vmrglb): Replace with define_expand and new + *altivec_vmrglb_internal insn; adjust for -maltivec=be with LE + targets. + (altivec_vmrglb_direct): New define_insn. + (altivec_vmrglh): Replace with define_expand and new + *altivec_vmrglh_internal insn; adjust for -maltivec=be with LE + targets. + (altivec_vmrglh_direct): New define_insn. + (altivec_vmrglw): Replace with define_expand and new + *altivec_vmrglw_internal insn; adjust for -maltivec=be with LE + targets. + (altivec_vmrglw_direct): New define_insn. + (*altivec_vmrglsf): Adjust for endianness. + (vec_widen_umult_hi_v16qi): Use gen_altivec_vmrghh_direct. + (vec_widen_umult_lo_v16qi): Use gen_altivec_vmrglh_direct. + (vec_widen_smult_hi_v16qi): Use gen_altivec_vmrghh_direct. + (vec_widen_smult_lo_v16qi): Use gen_altivec_vmrglh_direct. + (vec_widen_umult_hi_v8hi): Use gen_altivec_vmrghw_direct. + (vec_widen_umult_lo_v8hi): Use gen_altivec_vmrglw_direct. + (vec_widen_smult_hi_v8hi): Use gen_altivec_vmrghw_direct. + (vec_widen_smult_lo_v8hi): Use gen_altivec_vmrglw_direct. + + Backport from mainline r207318 + 2014-01-30 Bill Schmidt + + * gcc/config/rs6000/rs6000.c (rs6000_expand_vector_init): Use + gen_vsx_xxspltw_v4sf_direct instead of gen_vsx_xxspltw_v4sf; + remove element index adjustment for endian (now handled in vsx.md + and altivec.md). + (altivec_expand_vec_perm_const): Use + gen_altivec_vsplt[bhw]_direct instead of gen_altivec_vsplt[bhw]. + * gcc/config/rs6000/vsx.md (UNSPEC_VSX_XXSPLTW): New unspec. + (vsx_xxspltw_): Adjust element index for little endian. + * gcc/config/rs6000/altivec.md (altivec_vspltb): Divide into a + define_expand and a new define_insn *altivec_vspltb_internal; + adjust for -maltivec=be on a little endian target. + (altivec_vspltb_direct): New. + (altivec_vsplth): Divide into a define_expand and a new + define_insn *altivec_vsplth_internal; adjust for -maltivec=be on a + little endian target. + (altivec_vsplth_direct): New. + (altivec_vspltw): Divide into a define_expand and a new + define_insn *altivec_vspltw_internal; adjust for -maltivec=be on a + little endian target. + (altivec_vspltw_direct): New. + (altivec_vspltsf): Divide into a define_expand and a new + define_insn *altivec_vspltsf_internal; adjust for -maltivec=be on + a little endian target. + + Backport from mainline r207326 + 2014-01-30 Bill Schmidt + + * config/rs6000/rs6000.c (rs6000_expand_vector_init): Remove + unused variable "field". + * config/rs6000/vsx.md (vsx_mergel_): Add missing DONE. + (vsx_mergeh_): Likewise. + * config/rs6000/altivec.md (altivec_vmrghb): Likewise. + (altivec_vmrghh): Likewise. + (altivec_vmrghw): Likewise. + (altivec_vmrglb): Likewise. + (altivec_vmrglh): Likewise. + (altivec_vmrglw): Likewise. + (altivec_vspltb): Add missing uses. + (altivec_vsplth): Likewise. + (altivec_vspltw): Likewise. + (altivec_vspltsf): Likewise. + + Backport from mainline r207414 + 2014-02-02 Bill Schmidt + + * config/rs6000/altivec.md (UNSPEC_VSUMSWS_DIRECT): New unspec. + (altivec_vsumsws): Add handling for -maltivec=be with a little + endian target. + (altivec_vsumsws_direct): New. + (reduc_splus_): Call gen_altivec_vsumsws_direct instead of + gen_altivec_vsumsws. + + Backport from mainline r207415 + 2014-02-02 Bill Schmidt + + * config/rs6000/rs6000.c (altivec_expand_vec_perm_le): Generalize + for vector types other than V16QImode. + * config/rs6000/altivec.md (altivec_vperm_): Change to a + define_expand, and call altivec_expand_vec_perm_le when producing + code with little endian element order. + (*altivec_vperm__internal): New insn having previous + behavior of altivec_vperm_. + (altivec_vperm__uns): Change to a define_expand, and call + altivec_expand_vec_perm_le when producing code with little endian + element order. + (*altivec_vperm__uns_internal): New insn having previous + behavior of altivec_vperm__uns. + + Backport from mainline r207520 + 2014-02-05 Bill Schmidt + + * altivec.md (UNSPEC_VPACK_UNS_UNS_MOD_DIRECT): New unspec. + (UNSPEC_VUNPACK_HI_SIGN_DIRECT): Likewise. + (UNSPEC_VUNPACK_LO_SIGN_DIRECT): Likewise. + (mulv8hi3): Use gen_altivec_vpkuwum_direct instead of + gen_altivec_vpkuwum. + (altivec_vpkpx): Test for VECTOR_ELT_ORDER_BIG instead of for + BYTES_BIG_ENDIAN. + (altivec_vpksss): Likewise. + (altivec_vpksus): Likewise. + (altivec_vpkuus): Likewise. + (altivec_vpkuum): Likewise. + (altivec_vpkuum_direct): New (copy of + altivec_vpkuum that still relies on BYTES_BIG_ENDIAN, for + internal use). + (altivec_vupkhs): Emit vupkls* instead of vupkhs* when + target is little endian and -maltivec=be is not specified. + (*altivec_vupkhs_direct): New (copy of + altivec_vupkhs that always emits vupkhs*, for internal + use). + (altivec_vupkls): Emit vupkhs* instead of vupkls* when + target is little endian and -maltivec=be is not specified. + (*altivec_vupkls_direct): New (copy of + altivec_vupkls that always emits vupkls*, for internal + use). + (altivec_vupkhpx): Emit vupklpx instead of vupkhpx when target is + little endian and -maltivec=be is not specified. + (altivec_vupklpx): Emit vupkhpx instead of vupklpx when target is + little endian and -maltivec=be is not specified. + + Backport from mainline r207521 + 2014-02-05 Bill Schmidt + + * config/rs6000/altivec.md (altivec_vsum2sws): Adjust code + generation for -maltivec=be. + (altivec_vsumsws): Simplify redundant test. + + Backport from mainline r207525 + 2014-02-05 Bill Schmidt + + * config/rs6000/rs6000.c (altivec_expand_vec_perm_const): Change + CODE_FOR_altivec_vpku[hw]um to + CODE_FOR_altivec_vpku[hw]um_direct. + * config/rs6000/altivec.md (vec_unpacks_hi_): Change + UNSPEC_VUNPACK_HI_SIGN to UNSPEC_VUNPACK_HI_SIGN_DIRECT. + (vec_unpacks_lo_): Change UNSPEC_VUNPACK_LO_SIGN to + UNSPEC_VUNPACK_LO_SIGN_DIRECT. + + Backport from mainline r207814. + 2014-02-16 Bill Schmidt + + * config/rs6000/vsx.md (vsx_xxpermdi_): Handle little + endian targets. + + Backport from mainline r207815. + 2014-02-16 Bill Schmidt + + * config/rs6000/altivec.md (p8_vmrgew): Handle little endian + targets. + (p8_vmrgow): Likewise. + + Backport from mainline r207919. + 2014-02-19 Bill Schmidt + + * config/rs6000/rs6000.c (vspltis_constant): Fix most significant + bit of zero. + + Backport from mainline 208019 + 2014-02-21 Bill Schmidt + + * config/rs6000/altivec.md (altivec_lvxl): Rename as + *altivec_lvxl__internal and use VM2 iterator instead of + V4SI. + (altivec_lvxl_): New define_expand incorporating + -maltivec=be semantics where needed. + (altivec_lvx): Rename as *altivec_lvx__internal. + (altivec_lvx_): New define_expand incorporating -maltivec=be + semantics where needed. + (altivec_stvx): Rename as *altivec_stvx__internal. + (altivec_stvx_): New define_expand incorporating + -maltivec=be semantics where needed. + (altivec_stvxl): Rename as *altivec_stvxl__internal and use + VM2 iterator instead of V4SI. + (altivec_stvxl_): New define_expand incorporating + -maltivec=be semantics where needed. + * config/rs6000/rs6000-builtin.def: Add new built-in definitions + LVXL_V2DF, LVXL_V2DI, LVXL_V4SF, LVXL_V4SI, LVXL_V8HI, LVXL_V16QI, + LVX_V2DF, LVX_V2DI, LVX_V4SF, LVX_V4SI, LVX_V8HI, LVX_V16QI, + STVX_V2DF, STVX_V2DI, STVX_V4SF, STVX_V4SI, STVX_V8HI, STVX_V16QI, + STVXL_V2DF, STVXL_V2DI, STVXL_V4SF, STVXL_V4SI, STVXL_V8HI, + STVXL_V16QI. + * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Replace + ALTIVEC_BUILTIN_LVX with ALTIVEC_BUILTIN_LVX_ throughout; + similarly for ALTIVEC_BUILTIN_LVXL, ALTIVEC_BUILTIN_STVX, and + ALTIVEC_BUILTIN_STVXL. + * config/rs6000/rs6000-protos.h (altivec_expand_lvx_be): New + prototype. + (altivec_expand_stvx_be): Likewise. + * config/rs6000/rs6000.c (swap_selector_for_mode): New function. + (altivec_expand_lvx_be): Likewise. + (altivec_expand_stvx_be): Likewise. + (altivec_expand_builtin): Add cases for + ALTIVEC_BUILTIN_STVX_, ALTIVEC_BUILTIN_STVXL_, + ALTIVEC_BUILTIN_LVXL_, and ALTIVEC_BUILTIN_LVX_. + (altivec_init_builtins): Add definitions for + __builtin_altivec_lvxl_, __builtin_altivec_lvx_, + __builtin_altivec_stvx_, and + __builtin_altivec_stvxl_. + + Backport from mainline 208021 + 2014-02-21 Bill Schmidt + + * config/rs6000/altivec.md (altivec_vsumsws): Replace second + vspltw with vsldoi. + (reduc_uplus_v16qi): Use gen_altivec_vsumsws_direct instead of + gen_altivec_vsumsws. + + Backport from mainline 208049 + 2014-02-23 Bill Schmidt + + * config/rs6000/altivec.md (altivec_lvex): Replace + define_insn with define_expand and new define_insn + *altivec_lvex_internal. + (altivec_stvex): Replace define_insn with define_expand + and new define_insn *altivec_stvex_internal. + * config/rs6000/rs6000-protos.h (altivec_expand_stvex_be): New + prototype. + * config/rs6000/rs6000.c (altivec_expand_lvx_be): Document use by + lve*x built-ins. + (altivec_expand_stvex_be): New function. + + Backport from mainline + 2014-02-23 Bill Schmidt + * config/rs6000/rs6000.c (rs6000_emit_le_vsx_move): Relax assert + to permit subregs. + + Backport from mainline + 2014-02-25 Bill Schmidt + * config/rs6000/vector.md (*vector_unordered): Change split + to use canonical form for nor3. + +2014-04-04 Bill Schmidt + + Backport from mainline + 2014-02-04 Michael Meissner + + * config/rs6000/rs6000.opt (-mlra): Add switch to enable the LRA + register allocator. + + * config/rs6000/rs6000.c (TARGET_LRA_P): Add support for -mlra to + enable the LRA register allocator. Back port the changes from the + trunk to enable LRA. + (rs6000_legitimate_offset_address_p): Likewise. + (legitimate_lo_sum_address_p): Likewise. + (use_toc_relative_ref): Likewise. + (rs6000_legitimate_address_p): Likewise. + (rs6000_emit_move): Likewise. + (rs6000_secondary_memory_needed_mode): Likewise. + (rs6000_alloc_sdmode_stack_slot): Likewise. + (rs6000_lra_p): Likewise. + + * config/rs6000/sync.md (load_lockedti): Copy TI/PTI variables by + 64-bit parts to force the register allocator to allocate even/odd + register pairs for the quad word atomic instructions. + (store_conditionalti): Likewise. + +2014-04-04 Bill Schmidt + + Back port from mainline + 2014-01-23 Michael Meissner + + PR target/59909 + * doc/invoke.texi (RS/6000 and PowerPC Options): Document + -mquad-memory-atomic. Update -mquad-memory documentation to say + it is only used for non-atomic loads/stores. + + * config/rs6000/predicates.md (quad_int_reg_operand): Allow either + -mquad-memory or -mquad-memory-atomic switches. + + * config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Add + -mquad-memory-atomic to ISA 2.07 support. + + * config/rs6000/rs6000.opt (-mquad-memory-atomic): Add new switch + to separate support of normal quad word memory operations (ldq, + stq) from the atomic quad word memory operations. + + * config/rs6000/rs6000.c (rs6000_option_override_internal): Add + support to separate non-atomic quad word operations from atomic + quad word operations. Disable non-atomic quad word operations in + little endian mode so that we don't have to swap words after the + load and before the store. + (quad_load_store_p): Add comment about atomic quad word support. + (rs6000_opt_masks): Add -mquad-memory-atomic to the list of + options printed with -mdebug=reg. + + * config/rs6000/rs6000.h (TARGET_SYNC_TI): Use + -mquad-memory-atomic as the test for whether we have quad word + atomic instructions. + (TARGET_SYNC_HI_QI): If either -mquad-memory-atomic, + -mquad-memory, or -mp8-vector are used, allow byte/half-word + atomic operations. + + * config/rs6000/sync.md (load_lockedti): Insure that the address + is a proper indexed or indirect address for the lqarx instruction. + On little endian systems, swap the hi/lo registers after the lqarx + instruction. + (load_lockedpti): Use indexed_or_indirect_operand predicate to + insure the address is valid for the lqarx instruction. + (store_conditionalti): Insure that the address is a proper indexed + or indirect address for the stqcrx. instruction. On little endian + systems, swap the hi/lo registers before doing the stqcrx. + instruction. + (store_conditionalpti): Use indexed_or_indirect_operand predicate to + insure the address is valid for the stqcrx. instruction. + + * gcc/config/rs6000/rs6000-c.c (rs6000_target_modify_macros): + Define __QUAD_MEMORY__ and __QUAD_MEMORY_ATOMIC__ based on what + type of quad memory support is available. + +2014-04-04 Bill Schmidt + + Apply mainline r202190, powerpc64le multilibs and multiarch dir + 2013-09-03 Alan Modra + + * config.gcc (powerpc*-*-linux*): Add support for little-endian + multilibs to big-endian target and vice versa. + * config/rs6000/t-linux64: Use := assignment on all vars. + (MULTILIB_EXTRA_OPTS): Remove fPIC. + (MULTILIB_OSDIRNAMES): Specify using mapping from multilib_options. + * config/rs6000/t-linux64le: New file. + * config/rs6000/t-linux64bele: New file. + * config/rs6000/t-linux64lebe: New file. + +2014-04-04 Bill Schmidt + + Back port from mainline + 2014-01-16 Michael Meissner + + PR target/59844 + * config/rs6000/rs6000.md (reload_vsx_from_gprsf): Add little + endian support, remove tests for WORDS_BIG_ENDIAN. + (p8_mfvsrd_3_): Likewise. + (reload_gpr_from_vsx): Likewise. + (reload_gpr_from_vsxsf): Likewise. + (p8_mfvsrd_4_disf): Likewise. + +2014-04-04 Bill Schmidt + + Backport from mainline + 2013-04-05 Bill Schmidt + + PR target/56843 + * config/rs6000/rs6000.c (rs6000_emit_swdiv_high_precision): Remove. + (rs6000_emit_swdiv_low_precision): Remove. + (rs6000_emit_swdiv): Rewrite to handle between one and four + iterations of Newton-Raphson generally; modify required number of + iterations for some cases. + * config/rs6000/rs6000.h (RS6000_RECIP_HIGH_PRECISION_P): Remove. + +2014-04-04 Bill Schmidt + + Backport from mainline + 2013-08-19 Peter Bergner + Jakub Jelinek + + * builtins.def (BUILT_IN_FABSD32): New DFP ABS builtin. + (BUILT_IN_FABSD64): Likewise. + (BUILT_IN_FABSD128): Likewise. + * builtins.c (expand_builtin): Add support for + new DFP ABS builtins. + (fold_builtin_1): Likewise. + * config/rs6000/dfp.md + (*abstd2_fpr): Handle non-overlapping destination + and source operands. + (*nabstd2_fpr): Likewise. + +2014-04-04 Bill Schmidt + + Apply mainline r205060. + 2013-11-20 Alan Modra + * config/rs6000/sysv4.h (CC1_ENDIAN_LITTLE_SPEC): Define as empty. + * config/rs6000/rs6000.c (rs6000_option_override_internal): Default + to strict alignment on older processors when little-endian. + * config/rs6000/linux64.h (PROCESSOR_DEFAULT64): Default to power8 + for ELFv2. + +2014-04-04 Bill Schmidt + + POWER ELFv2 ABI Support + Backport from mainline r204842: + + 2013-11-15 Ulrich Weigand + + * doc/invoke.texi (-mabi=elfv1, -mabi=elfv2): Document. + + Backport from mainline r204809: + + 2013-11-14 Ulrich Weigand + + * config/rs6000/sysv4le.h (LINUX64_DEFAULT_ABI_ELFv2): Define. + + Backport from mainline r204808: + + 2013-11-14 Ulrich Weigand + Alan Modra + + * config/rs6000/rs6000.h (RS6000_SAVE_AREA): Handle ABI_ELFv2. + (RS6000_SAVE_TOC): Remove. + (RS6000_TOC_SAVE_SLOT): New macro. + * config/rs6000/rs6000.c (rs6000_parm_offset): New function. + (rs6000_parm_start): Use it. + (rs6000_function_arg_advance_1): Likewise. + (rs6000_emit_prologue): Use RS6000_TOC_SAVE_SLOT. + (rs6000_emit_epilogue): Likewise. + (rs6000_call_aix): Likewise. + (rs6000_output_function_prologue): Do not save/restore r11 + around calling _mcount for ABI_ELFv2. + + 2013-11-14 Ulrich Weigand + Alan Modra + + * config/rs6000/rs6000-protos.h (rs6000_reg_parm_stack_space): + Add prototype. + * config/rs6000/rs6000.h (RS6000_REG_SAVE): Remove. + (REG_PARM_STACK_SPACE): Call rs6000_reg_parm_stack_space. + * config/rs6000/rs6000.c (rs6000_parm_needs_stack): New function. + (rs6000_function_parms_need_stack): Likewise. + (rs6000_reg_parm_stack_space): Likewise. + (rs6000_function_arg): Do not replace BLKmode by Pmode when + returning a register argument. + + 2013-11-14 Ulrich Weigand + Michael Gschwind + + * config/rs6000/rs6000.h (FP_ARG_MAX_RETURN): New macro. + (ALTIVEC_ARG_MAX_RETURN): Likewise. + (FUNCTION_VALUE_REGNO_P): Use them. + * config/rs6000/rs6000.c (TARGET_RETURN_IN_MSB): Define. + (rs6000_return_in_msb): New function. + (rs6000_return_in_memory): Handle ELFv2 homogeneous aggregates. + Handle aggregates of up to 16 bytes for ELFv2. + (rs6000_function_value): Handle ELFv2 homogeneous aggregates. + + 2013-11-14 Ulrich Weigand + Michael Gschwind + + * config/rs6000/rs6000.h (AGGR_ARG_NUM_REG): Define. + * config/rs6000/rs6000.c (rs6000_aggregate_candidate): New function. + (rs6000_discover_homogeneous_aggregate): Likewise. + (rs6000_function_arg_boundary): Handle homogeneous aggregates. + (rs6000_function_arg_advance_1): Likewise. + (rs6000_function_arg): Likewise. + (rs6000_arg_partial_bytes): Likewise. + (rs6000_psave_function_arg): Handle BLKmode arguments. + + 2013-11-14 Ulrich Weigand + Michael Gschwind + + * config/rs6000/rs6000.h (AGGR_ARG_NUM_REG): Define. + * config/rs6000/rs6000.c (rs6000_aggregate_candidate): New function. + (rs6000_discover_homogeneous_aggregate): Likewise. + (rs6000_function_arg_boundary): Handle homogeneous aggregates. + (rs6000_function_arg_advance_1): Likewise. + (rs6000_function_arg): Likewise. + (rs6000_arg_partial_bytes): Likewise. + (rs6000_psave_function_arg): Handle BLKmode arguments. + + 2013-11-14 Ulrich Weigand + + * config/rs6000/rs6000.c (machine_function): New member + r2_setup_needed. + (rs6000_emit_prologue): Set r2_setup_needed if necessary. + (rs6000_output_mi_thunk): Set r2_setup_needed. + (rs6000_output_function_prologue): Output global entry point + prologue and local entry point marker if needed for ABI_ELFv2. + Output -mprofile-kernel code here. + (output_function_profiler): Do not output -mprofile-kernel + code here; moved to rs6000_output_function_prologue. + (rs6000_file_start): Output ".abiversion 2" for ABI_ELFv2. + + (rs6000_emit_move): Do not handle dot symbols for ABI_ELFv2. + (rs6000_output_function_entry): Likewise. + (rs6000_assemble_integer): Likewise. + (rs6000_elf_encode_section_info): Likewise. + (rs6000_elf_declare_function_name): Do not create dot symbols + or .opd section for ABI_ELFv2. + + (rs6000_trampoline_size): Update for ABI_ELFv2 trampolines. + (rs6000_trampoline_init): Likewise. + (rs6000_elf_file_end): Call file_end_indicate_exec_stack + for ABI_ELFv2. + + (rs6000_call_aix): Handle ELFv2 indirect calls. Do not check + for function descriptors in ABI_ELFv2. + + * config/rs6000/rs6000.md ("*call_indirect_aix"): Support + on ABI_AIX only, not ABI_ELFv2. + ("*call_value_indirect_aix"): Likewise. + ("*call_indirect_elfv2"): New pattern. + ("*call_value_indirect_elfv2"): Likewise. + + * config/rs6000/predicates.md ("symbol_ref_operand"): Do not + check for function descriptors in ABI_ELFv2. + ("current_file_function_operand"): Likewise. + + * config/rs6000/ppc-asm.h [__powerpc64__ && _CALL_ELF == 2]: + (toc): Undefine. + (FUNC_NAME): Define ELFv2 variant. + (JUMP_TARGET): Likewise. + (FUNC_START): Likewise. + (HIDDEN_FUNC): Likewise. + (FUNC_END): Likeiwse. + + 2013-11-14 Ulrich Weigand + + * config.gcc [powerpc*-*-* | rs6000-*-*]: Support --with-abi=elfv1 + and --with-abi=elfv2. + * config/rs6000/option-defaults.h (OPTION_DEFAULT_SPECS): Add "abi". + * config/rs6000/rs6000.opt (mabi=elfv1): New option. + (mabi=elfv2): Likewise. + * config/rs6000/rs6000-opts.h (enum rs6000_abi): Add ABI_ELFv2. + * config/rs6000/linux64.h (DEFAULT_ABI): Do not hard-code to AIX_ABI + if !RS6000_BI_ARCH. + (ELFv2_ABI_CHECK): New macro. + (SUBSUBTARGET_OVERRIDE_OPTIONS): Use it to decide whether to set + rs6000_current_abi to ABI_AIX or ABI_ELFv2. + (GLIBC_DYNAMIC_LINKER64): Support ELFv2 ld.so version. + * config/rs6000/rs6000-c.c (rs6000_cpu_cpp_builtins): Predefine + _CALL_ELF and __STRUCT_PARM_ALIGN__ if appropriate. + + * config/rs6000/rs6000.c (rs6000_debug_reg_global): Handle ABI_ELFv2. + (debug_stack_info): Likewise. + (rs6000_file_start): Treat ABI_ELFv2 the same as ABI_AIX. + (rs6000_legitimize_tls_address): Likewise. + (rs6000_conditional_register_usage): Likewise. + (rs6000_emit_move): Likewise. + (init_cumulative_args): Likewise. + (rs6000_function_arg_advance_1): Likewise. + (rs6000_function_arg): Likewise. + (rs6000_arg_partial_bytes): Likewise. + (rs6000_output_function_entry): Likewise. + (rs6000_assemble_integer): Likewise. + (rs6000_savres_strategy): Likewise. + (rs6000_stack_info): Likewise. + (rs6000_function_ok_for_sibcall): Likewise. + (rs6000_emit_load_toc_table): Likewise. + (rs6000_savres_routine_name): Likewise. + (ptr_regno_for_savres): Likewise. + (rs6000_emit_prologue): Likewise. + (rs6000_emit_epilogue): Likewise. + (rs6000_output_function_epilogue): Likewise. + (output_profile_hook): Likewise. + (output_function_profiler): Likewise. + (rs6000_trampoline_size): Likewise. + (rs6000_trampoline_init): Likewise. + (rs6000_elf_output_toc_section_asm_op): Likewise. + (rs6000_elf_encode_section_info): Likewise. + (rs6000_elf_reloc_rw_mask): Likewise. + (rs6000_elf_declare_function_name): Likewise. + (rs6000_function_arg_boundary): Treat ABI_ELFv2 the same as ABI_AIX, + except that rs6000_compat_align_parm is always assumed false. + (rs6000_gimplify_va_arg): Likewise. + (rs6000_call_aix): Update comment. + (rs6000_sibcall_aix): Likewise. + * config/rs6000/rs6000.md ("tls_gd_aix"): + Treat ABI_ELFv2 the same as ABI_AIX. + ("*tls_gd_call_aix"): Likewise. + ("tls_ld_aix"): Likewise. + ("*tls_ld_call_aix"): Likewise. + ("load_toc_aix_si"): Likewise. + ("load_toc_aix_di"): Likewise. + ("call"): Likewise. + ("call_value"): Likewise. + ("*call_local_aix"): Likewise. + ("*call_value_local_aix"): Likewise. + ("*call_nonlocal_aix"): Likewise. + ("*call_value_nonlocal_aix"): Likewise. + ("*call_indirect_aix"): Likewise. + ("*call_value_indirect_aix"): Likewise. + ("sibcall"): Likewise. + ("sibcall_value"): Likewise. + ("*sibcall_aix"): Likewise. + ("*sibcall_value_aix"): Likewise. + * config/rs6000/predicates.md ("symbol_ref_operand"): Likewise. + ("current_file_function_operand"): Likewise. + + Backport from mainline r204807: + + 2013-11-14 Ulrich Weigand + + * config/rs6000/rs6000.c (rs6000_arg_partial_bytes): Simplify logic + by making use of the fact that for vector / floating point arguments + passed both in VRs/FPRs and in the fixed parameter area, the partial + bytes mechanism is in fact not used. + + Backport from mainline r204806: + + 2013-11-14 Ulrich Weigand + + * config/rs6000/rs6000.c (rs6000_psave_function_arg): New function. + (rs6000_finish_function_arg): Likewise. + (rs6000_function_arg): Use rs6000_psave_function_arg and + rs6000_finish_function_arg to handle both vector and floating + point arguments that are also passed in GPRs / the stack. + + Backport from mainline r204805: + + 2013-11-14 Ulrich Weigand + + * config/rs6000/rs6000.c (USE_FP_FOR_ARG_P): Remove TYPE argument. + (USE_ALTIVEC_FOR_ARG_P): Likewise. + (rs6000_darwin64_record_arg_advance_recurse): Update uses. + (rs6000_function_arg_advance_1):Likewise. + (rs6000_darwin64_record_arg_recurse): Likewise. + (rs6000_function_arg): Likewise. + (rs6000_arg_partial_bytes): Likewise. + + Backport from mainline r204804: + + 2013-11-14 Ulrich Weigand + + * config/rs6000/rs6000.c (rs6000_option_override_internal): Replace + "DEFAULT_ABI != ABI_AIX" test by testing for ABI_V4 or ABI_DARWIN. + (rs6000_savres_strategy): Likewise. + (rs6000_return_addr): Likewise. + (rs6000_emit_load_toc_table): Replace "DEFAULT_ABI != ABI_AIX" by + testing for ABI_V4 (since ABI_DARWIN is impossible here). + (rs6000_emit_prologue): Likewise. + (legitimate_lo_sum_address_p): Simplify DEFAULT_ABI test. + (rs6000_elf_declare_function_name): Remove duplicated test. + * config/rs6000/rs6000.md ("load_toc_v4_PIC_1"): Explicitly test + for ABI_V4 (instead of "DEFAULT_ABI != ABI_AIX" test). + ("load_toc_v4_PIC_1_normal"): Likewise. + ("load_toc_v4_PIC_1_476"): Likewise. + ("load_toc_v4_PIC_1b"): Likewise. + ("load_toc_v4_PIC_1b_normal"): Likewise. + ("load_toc_v4_PIC_1b_476"): Likewise. + ("load_toc_v4_PIC_2"): Likewise. + ("load_toc_v4_PIC_3b"): Likewise. + ("load_toc_v4_PIC_3c"): Likewise. + * config/rs6000/rs6000.h (RS6000_REG_SAVE): Simplify DEFAULT_ABI test. + (RS6000_SAVE_AREA): Likewise. + (FP_ARG_MAX_REG): Likewise. + (RETURN_ADDRESS_OFFSET): Likewise. + * config/rs6000/sysv.h (TARGET_TOC): Test for ABI_V4 instead + of ABI_AIX. + (SUBTARGET_OVERRIDE_OPTIONS): Likewise. + (MINIMAL_TOC_SECTION_ASM_OP): Likewise. + + Backport from mainline r204803: + + 2013-11-14 Ulrich Weigand + + * config/rs6000/rs6000.c (rs6000_call_indirect_aix): Rename to ... + (rs6000_call_aix): ... this. Handle both direct and indirect calls. + Create call insn directly instead of via various gen_... routines. + Mention special registers used by the call in CALL_INSN_FUNCTION_USAGE. + (rs6000_sibcall_aix): New function. + * config/rs6000/rs6000.md (TOC_SAVE_OFFSET_32BIT): Remove. + (TOC_SAVE_OFFSET_64BIT): Likewise. + (AIX_FUNC_DESC_TOC_32BIT): Likewise. + (AIX_FUNC_DESC_TOC_64BIT): Likewise. + (AIX_FUNC_DESC_SC_32BIT): Likewise. + (AIX_FUNC_DESC_SC_64BIT): Likewise. + ("call" expander): Call rs6000_call_aix. + ("call_value" expander): Likewise. + ("call_indirect_aix"): Replace this pattern ... + ("call_indirect_aix_nor11"): ... and this pattern ... + ("*call_indirect_aix"): ... by this insn pattern. + ("call_value_indirect_aix"): Replace this pattern ... + ("call_value_indirect_aix_nor11"): ... and this pattern ... + ("*call_value_indirect_aix"): ... by this insn pattern. + ("*call_nonlocal_aix32", "*call_nonlocal_aix64"): Replace by ... + ("*call_nonlocal_aix"): ... this pattern. + ("*call_value_nonlocal_aix32", "*call_value_nonlocal_aix64"): Replace + ("*call_value_nonlocal_aix"): ... by this pattern. + ("*call_local_aix"): New insn pattern. + ("*call_value_local_aix"): Likewise. + ("sibcall" expander): Call rs6000_sibcall_aix. + ("sibcall_value" expander): Likewise. Move earlier in file. + ("*sibcall_nonlocal_aix"): Replace by ... + ("*sibcall_aix"): ... this pattern. + ("*sibcall_value_nonlocal_aix"): Replace by ... + ("*sibcall_value_aix"): ... this pattern. + * config/rs6000/rs6000-protos.h (rs6000_call_indirect_aix): Remove. + (rs6000_call_aix): Add prototype. + (rs6000_sibcall_aix): Likewise. + + Backport from mainline r204799: + + 2013-11-14 Ulrich Weigand + + * config/rs6000/rs6000.c (rs6000_emit_prologue): Do not place a + RTX_FRAME_RELATED_P marker on the UNSPEC_MOVESI_FROM_CR insn. + Instead, add USEs of all modified call-saved CR fields to the + insn storing the result to the stack slot, and provide an + appropriate REG_FRAME_RELATED_EXPR for that insn. + * config/rs6000/rs6000.md ("*crsave"): New insn pattern. + * config/rs6000/predicates.md ("crsave_operation"): New predicate. + +2014-04-04 Bill Schmidt + + ELFv2 ABI Call Support + Backport from mainline r204798: + + 2013-11-14 Ulrich Weigand + Alan Modra + + * function.c (assign_parms): Use all.reg_parm_stack_space instead + of re-evaluating REG_PARM_STACK_SPACE target macro. + (locate_and_pad_parm): New parameter REG_PARM_STACK_SPACE. Use it + instead of evaluating target macro REG_PARM_STACK_SPACE every time. + (assign_parm_find_entry_rtl): Update call. + * calls.c (initialize_argument_information): Update call. + (emit_library_call_value_1): Likewise. + * expr.h (locate_and_pad_parm): Update prototype. + + Backport from mainline r204797: + + 2013-11-14 Ulrich Weigand + + * calls.c (store_unaligned_arguments_into_pseudos): Skip PARALLEL + arguments. + + Backport from mainline r197003: + + 2013-03-23 Eric Botcazou + + * calls.c (expand_call): Add missing guard to code handling return + of non-BLKmode structures in MSB. + * function.c (expand_function_end): Likewise. + +2014-04-04 Bill Schmidt + + Backport from mainline r201750. + Note: Default setting of -mcompat-align-parm inverted! + + 2013-08-14 Bill Schmidt + + PR target/57949 + * doc/invoke.texi: Add documentation of mcompat-align-parm + option. + * config/rs6000/rs6000.opt: Add mcompat-align-parm option. + * config/rs6000/rs6000.c (rs6000_function_arg_boundary): For AIX + and Linux, correct BLKmode alignment when 128-bit alignment is + required and compatibility flag is not set. + (rs6000_gimplify_va_arg): For AIX and Linux, honor specified + alignment for zero-size arguments when compatibility flag is not + set. + +2014-04-04 Bill Schmidt + + Little Endian Vector Support + Backport from mainline r205333 + 2013-11-24 Bill Schmidt + + * config/rs6000/rs6000.c (rs6000_expand_vec_perm_const_1): Correct + for little endian. + + Backport from mainline r205241 + 2013-11-21 Bill Schmidt + + * config/rs6000/vector.md (vec_pack_trunc_v2df): Revert previous + little endian change. + (vec_pack_sfix_trunc_v2df): Likewise. + (vec_pack_ufix_trunc_v2df): Likewise. + * config/rs6000/rs6000.c (rs6000_expand_interleave): Correct + double checking of endianness. + + Backport from mainline r205146 + 2013-11-20 Bill Schmidt + + * config/rs6000/vsx.md (vsx_set_): Adjust for little endian. + (vsx_extract_): Likewise. + (*vsx_extract__one_le): New LE variant on + *vsx_extract__zero. + (vsx_extract_v4sf): Adjust for little endian. + + Backport from mainline r205080 + 2013-11-19 Bill Schmidt + + * config/rs6000/rs6000.c (altivec_expand_vec_perm_const): Adjust + V16QI vector splat case for little endian. + + Backport from mainline r205045: + + 2013-11-19 Ulrich Weigand + + * config/rs6000/vector.md ("mov"): Do not call + rs6000_emit_le_vsx_move to move into or out of GPRs. + * config/rs6000/rs6000.c (rs6000_emit_le_vsx_move): Assert + source and destination are not GPR hard regs. + + Backport from mainline r204920 + 2011-11-17 Bill Schmidt + + * config/rs6000/rs6000.c (rs6000_frame_related): Add split_reg + parameter and use it in REG_FRAME_RELATED_EXPR note. + (emit_frame_save): Call rs6000_frame_related with extra NULL_RTX + parameter. + (rs6000_emit_prologue): Likewise, but for little endian VSX + stores, pass the source register of the store instead. + + Backport from mainline r204862 + 2013-11-15 Bill Schmidt + + * config/rs6000/altivec.md (UNSPEC_VPERM_X, UNSPEC_VPERM_UNS_X): + Remove. + (altivec_vperm_): Revert earlier little endian change. + (*altivec_vperm__internal): Remove. + (altivec_vperm__uns): Revert earlier little endian change. + (*altivec_vperm__uns_internal): Remove. + * config/rs6000/vector.md (vec_realign_load_): Revise + commentary. + + Backport from mainline r204441 + 2013-11-05 Bill Schmidt + + * config/rs6000/rs6000.c (rs6000_option_override_internal): + Remove restriction against use of VSX instructions when generating + code for little endian mode. + + Backport from mainline r204440 + 2013-11-05 Bill Schmidt + + * config/rs6000/altivec.md (mulv4si3): Ensure we generate vmulouh + for both big and little endian. + (mulv8hi3): Swap input operands for merge high and merge low + instructions for little endian. + + Backport from mainline r204439 + 2013-11-05 Bill Schmidt + + * config/rs6000/altivec.md (vec_widen_umult_even_v16qi): Change + define_insn to define_expand that uses even patterns for big + endian and odd patterns for little endian. + (vec_widen_smult_even_v16qi): Likewise. + (vec_widen_umult_even_v8hi): Likewise. + (vec_widen_smult_even_v8hi): Likewise. + (vec_widen_umult_odd_v16qi): Likewise. + (vec_widen_smult_odd_v16qi): Likewise. + (vec_widen_umult_odd_v8hi): Likewise. + (vec_widen_smult_odd_v8hi): Likewise. + (altivec_vmuleub): New define_insn. + (altivec_vmuloub): Likewise. + (altivec_vmulesb): Likewise. + (altivec_vmulosb): Likewise. + (altivec_vmuleuh): Likewise. + (altivec_vmulouh): Likewise. + (altivec_vmulesh): Likewise. + (altivec_vmulosh): Likewise. + + Backport from mainline r204395 + 2013-11-05 Bill Schmidt + + * config/rs6000/vector.md (vec_pack_sfix_trunc_v2df): Adjust for + little endian. + (vec_pack_ufix_trunc_v2df): Likewise. + + Backport from mainline r204363 + 2013-11-04 Bill Schmidt + + * config/rs6000/altivec.md (vec_widen_umult_hi_v16qi): Swap + arguments to merge instruction for little endian. + (vec_widen_umult_lo_v16qi): Likewise. + (vec_widen_smult_hi_v16qi): Likewise. + (vec_widen_smult_lo_v16qi): Likewise. + (vec_widen_umult_hi_v8hi): Likewise. + (vec_widen_umult_lo_v8hi): Likewise. + (vec_widen_smult_hi_v8hi): Likewise. + (vec_widen_smult_lo_v8hi): Likewise. + + Backport from mainline r204350 + 2013-11-04 Bill Schmidt + + * config/rs6000/vsx.md (*vsx_le_perm_store_ for VSX_D): + Replace the define_insn_and_split with a define_insn and two + define_splits, with the split after reload re-permuting the source + register to its original value. + (*vsx_le_perm_store_ for VSX_W): Likewise. + (*vsx_le_perm_store_v8hi): Likewise. + (*vsx_le_perm_store_v16qi): Likewise. + + Backport from mainline r204321 + 2013-11-04 Bill Schmidt + + * config/rs6000/vector.md (vec_pack_trunc_v2df): Adjust for + little endian. + + Backport from mainline r204321 + 2013-11-02 Bill Schmidt + + * config/rs6000/rs6000.c (rs6000_expand_vector_set): Adjust for + little endian. + + Backport from mainline r203980 + 2013-10-23 Bill Schmidt + + * config/rs6000/altivec.md (mulv8hi3): Adjust for little endian. + + Backport from mainline r203930 + 2013-10-22 Bill Schmidt + + * config/rs6000/rs6000.c (altivec_expand_vec_perm_const): Reverse + meaning of merge-high and merge-low masks for little endian; avoid + use of vector-pack masks for little endian for mismatched modes. + + Backport from mainline r203877 + 2013-10-20 Bill Schmidt + + * config/rs6000/altivec.md (vec_unpacku_hi_v16qi): Adjust for + little endian. + (vec_unpacku_hi_v8hi): Likewise. + (vec_unpacku_lo_v16qi): Likewise. + (vec_unpacku_lo_v8hi): Likewise. + + Backport from mainline r203863 + 2013-10-19 Bill Schmidt + + * config/rs6000/rs6000.c (vspltis_constant): Make sure we check + all elements for both endian flavors. + + Backport from mainline r203714 + 2013-10-16 Bill Schmidt + + * gcc/config/rs6000/vector.md (vec_unpacks_hi_v4sf): Correct for + endianness. + (vec_unpacks_lo_v4sf): Likewise. + (vec_unpacks_float_hi_v4si): Likewise. + (vec_unpacks_float_lo_v4si): Likewise. + (vec_unpacku_float_hi_v4si): Likewise. + (vec_unpacku_float_lo_v4si): Likewise. + + Backport from mainline r203713 + 2013-10-16 Bill Schmidt + + * config/rs6000/vsx.md (vsx_concat_): Adjust output for LE. + (vsx_concat_v2sf): Likewise. + + Backport from mainline r203458 + 2013-10-11 Bill Schmidt + + * config/rs6000/vsx.md (*vsx_le_perm_load_v2di): Generalize to + handle vector float as well. + (*vsx_le_perm_load_v4si): Likewise. + (*vsx_le_perm_store_v2di): Likewise. + (*vsx_le_perm_store_v4si): Likewise. + + Backport from mainline r203457 + 2013-10-11 Bill Schmidt + + * config/rs6000/vector.md (vec_realign_load): Generate vperm + directly to circumvent subtract from splat{31} workaround. + * config/rs6000/rs6000-protos.h (altivec_expand_vec_perm_le): New + prototype. + * config/rs6000/rs6000.c (altivec_expand_vec_perm_le): New. + * config/rs6000/altivec.md (define_c_enum "unspec"): Add + UNSPEC_VPERM_X and UNSPEC_VPERM_UNS_X. + (altivec_vperm_): Convert to define_insn_and_split to + separate big and little endian logic. + (*altivec_vperm__internal): New define_insn. + (altivec_vperm__uns): Convert to define_insn_and_split to + separate big and little endian logic. + (*altivec_vperm__uns_internal): New define_insn. + (vec_permv16qi): Add little endian logic. + + Backport from mainline r203247 + 2013-10-07 Bill Schmidt + + * config/rs6000/rs6000.c (altivec_expand_vec_perm_const_le): New. + (altivec_expand_vec_perm_const): Call it. + + Backport from mainline r203246 + 2013-10-07 Bill Schmidt + + * config/rs6000/vector.md (mov): Emit permuted move + sequences for LE VSX loads and stores at expand time. + * config/rs6000/rs6000-protos.h (rs6000_emit_le_vsx_move): New + prototype. + * config/rs6000/rs6000.c (rs6000_const_vec): New. + (rs6000_gen_le_vsx_permute): New. + (rs6000_gen_le_vsx_load): New. + (rs6000_gen_le_vsx_store): New. + (rs6000_gen_le_vsx_move): New. + * config/rs6000/vsx.md (*vsx_le_perm_load_v2di): New. + (*vsx_le_perm_load_v4si): New. + (*vsx_le_perm_load_v8hi): New. + (*vsx_le_perm_load_v16qi): New. + (*vsx_le_perm_store_v2di): New. + (*vsx_le_perm_store_v4si): New. + (*vsx_le_perm_store_v8hi): New. + (*vsx_le_perm_store_v16qi): New. + (*vsx_xxpermdi2_le_): New. + (*vsx_xxpermdi4_le_): New. + (*vsx_xxpermdi8_le_V8HI): New. + (*vsx_xxpermdi16_le_V16QI): New. + (*vsx_lxvd2x2_le_): New. + (*vsx_lxvd2x4_le_): New. + (*vsx_lxvd2x8_le_V8HI): New. + (*vsx_lxvd2x16_le_V16QI): New. + (*vsx_stxvd2x2_le_): New. + (*vsx_stxvd2x4_le_): New. + (*vsx_stxvd2x8_le_V8HI): New. + (*vsx_stxvd2x16_le_V16QI): New. + + Backport from mainline r201235 + 2013-07-24 Bill Schmidt + Anton Blanchard + + * config/rs6000/altivec.md (altivec_vpkpx): Handle little endian. + (altivec_vpksss): Likewise. + (altivec_vpksus): Likewise. + (altivec_vpkuus): Likewise. + (altivec_vpkuum): Likewise. + + Backport from mainline r201208 + 2013-07-24 Bill Schmidt + Anton Blanchard + + * config/rs6000/vector.md (vec_realign_load_): Reorder input + operands to vperm for little endian. + * config/rs6000/rs6000.c (rs6000_expand_builtin): Use lvsr instead + of lvsl to create the control mask for a vperm for little endian. + + Backport from mainline r201195 + 2013-07-23 Bill Schmidt + Anton Blanchard + + * config/rs6000/rs6000.c (altivec_expand_vec_perm_const): Reverse + two operands for little-endian. + + Backport from mainline r201193 + 2013-07-23 Bill Schmidt + Anton Blanchard + + * config/rs6000/rs6000.c (altivec_expand_vec_perm_const): Correct + selection of field for vector splat in little endian mode. + + Backport from mainline r201149 + 2013-07-22 Bill Schmidt + Anton Blanchard + + * config/rs6000/rs6000.c (rs6000_expand_vector_init): Fix + endianness when selecting field to splat. + +2014-04-04 Bill Schmidt + + Backport from mainline r205123: + + 2013-11-20 Ulrich Weigand + + * config/rs6000/rs6000.c (rs6000_cannot_change_mode_class): Do not + allow subregs of TDmode in FPRs of smaller size in little-endian. + (rs6000_split_multireg_move): When splitting an access to TDmode + in FPRs, do not use simplify_gen_subreg. + + Backport from mainline r204927: + + 2013-11-17 Ulrich Weigand + + * config/rs6000/rs6000.c (rs6000_emit_move): Use low word of + sdmode_stack_slot also in little-endian mode. + +2014-04-04 Bill Schmidt + + Power8 HTM Support + Backport from mainline + 2013-12-03 Peter Bergner + + * config/rs6000/htmintrin.h (_TEXASR_INSTRUCTION_FETCH_CONFLICT): Fix + typo in macro name. + (_TEXASRU_INSTRUCTION_FETCH_CONFLICT): Likewise. + + Backport from mainline r205233. + 2013-11-21 Peter Bergner + + * doc/extend.texi: Document htm builtins. + + Backport from mainline + 2013-07-17 Iain Sandoe + + * config/rs6000/darwin.h (REGISTER_NAMES): Add HTM registers. + + Backport from mainline + 2013-07-16 Peter Bergner + + * config/rs6000/rs6000.c (rs6000_option_override_internal): Do not + enable extra ISA flags with TARGET_HTM. + + 2013-07-16 Jakub Jelinek + Peter Bergner + + * config/rs6000/rs6000.h (FIRST_PSEUDO_REGISTERS): Mention HTM + registers in the comment. + (DWARF_FRAME_REGISTERS): Subtract also the 3 HTM registers. + (DWARF_REG_TO_UNWIND_COLUMN): Use DWARF_FRAME_REGISTERS + rather than FIRST_PSEUDO_REGISTERS. + + * config.gcc (powerpc*-*-*): Install htmintrin.h and htmxlintrin.h. + * config/rs6000/t-rs6000 (MD_INCLUDES): Add htm.md. + * config/rs6000/rs6000.opt: Add -mhtm option. + * config/rs6000/rs6000-cpus.def (POWERPC_MASKS): Add OPTION_MASK_HTM. + (ISA_2_7_MASKS_SERVER): Add OPTION_MASK_HTM. + * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Define + __HTM__ if the HTM instructions are available. + * config/rs6000/predicates.md (u3bit_cint_operand, u10bit_cint_operand) + (htm_spr_reg_operand): New define_predicates. + * config/rs6000/rs6000.md (define_attr "type"): Add htm. + (TFHAR_REGNO, TFIAR_REGNO, TEXASR_REGNO): New define_constants. + Include htm.md. + * config/rs6000/rs6000-builtin.def (BU_HTM_0, BU_HTM_1, BU_HTM_2) + (BU_HTM_3, BU_HTM_SPR0, BU_HTM_SPR1): Add support macros for defining + HTM builtin functions. + * config/rs6000/rs6000.c (RS6000_BUILTIN_H): New macro. + (rs6000_reg_names, alt_reg_names): Add HTM SPR register names. + (rs6000_init_hard_regno_mode_ok): Add support for HTM instructions. + (rs6000_builtin_mask_calculate): Likewise. + (rs6000_option_override_internal): Likewise. + (bdesc_htm): Add new HTM builtin support. + (htm_spr_num): New function. + (htm_spr_regno): Likewise. + (rs6000_htm_spr_icode): Likewise. + (htm_expand_builtin): Likewise. + (htm_init_builtins): Likewise. + (rs6000_expand_builtin): Add support for HTM builtin functions. + (rs6000_init_builtins): Likewise. + (rs6000_invalid_builtin, rs6000_opt_mask): Add support for -mhtm option. + * config/rs6000/rs6000.h (ASM_CPU_SPEC): Add support for -mhtm. + (TARGET_HTM, MASK_HTM): Define macros. + (FIRST_PSEUDO_REGISTER): Adjust for new HTM SPR registers. + (FIXED_REGISTERS): Likewise. + (CALL_USED_REGISTERS): Likewise. + (CALL_REALLY_USED_REGISTERS): Likewise. + (REG_ALLOC_ORDER): Likewise. + (enum reg_class): Likewise. + (REG_CLASS_NAMES): Likewise. + (REG_CLASS_CONTENTS): Likewise. + (REGISTER_NAMES): Likewise. + (ADDITIONAL_REGISTER_NAMES): Likewise. + (RS6000_BTC_SPR, RS6000_BTC_VOID, RS6000_BTC_32BIT, RS6000_BTC_64BIT) + (RS6000_BTC_MISC_MASK, RS6000_BTM_HTM): New macros. + (RS6000_BTM_COMMON): Add RS6000_BTM_HTM. + * config/rs6000/htm.md: New file. + * config/rs6000/htmintrin.h: New file. + * config/rs6000/htmxlintrin.h: New file. + +2014-04-04 Bill Schmidt + + Power8 Base Support + Apply mainline + 2013-11-23 Alan Modra + * config/rs6000/vsx.md (fusion peepholes): Disable when !TARGET_VSX. + + Backport from mainline + 2013-11-12 Michael Meissner + + PR target/59054 + * config/rs6000/rs6000.md (movdi_internal32): Eliminate + constraints that would allow DImode into the traditional Altivec + registers, but cause undesirable code generation when loading 0 as + a constant. + (movdi_internal64): Likewise. + (cmp_fpr): Do not use %x for CR register output. + (extendsfdf2_fpr): Fix constraints when -mallow-upper-df and + -mallow-upper-sf debug switches are used. + + Backport from mainline + 2013-10-17 Michael Meissner + + * config/rs6000/rs6000.c (enum rs6000_reload_reg_type): Add new + fields to the reg_addr array that describes the valid addressing + mode for any register, general purpose registers, floating point + registers, and Altivec registers. + (FIRST_RELOAD_REG_CLASS): Likewise. + (LAST_RELOAD_REG_CLASS): Likewise. + (struct reload_reg_map_type): Likewise. + (reload_reg_map_type): Likewise. + (RELOAD_REG_VALID): Likewise. + (RELOAD_REG_MULTIPLE): Likewise. + (RELOAD_REG_INDEXED): Likewise. + (RELOAD_REG_OFFSET): Likewise. + (RELOAD_REG_PRE_INCDEC): Likewise. + (RELOAD_REG_PRE_MODIFY): Likewise. + (reg_addr): Likewise. + (mode_supports_pre_incdec_p): New helper functions to say whether + a given mode supports PRE_INC, PRE_DEC, and PRE_MODIFY. + (mode_supports_pre_modify_p): Likewise. + (rs6000_debug_vector_unit): Rearrange the -mdebug=reg output to + print the valid address mode bits for each mode. + (rs6000_debug_print_mode): Likewise. + (rs6000_debug_reg_global): Likewise. + (rs6000_setup_reg_addr_masks): New function to set up the address + mask bits for each type. + (rs6000_init_hard_regno_mode_ok): Use memset to clear arrays. + Call rs6000_setup_reg_addr_masks to set up the address mask bits. + (rs6000_legitimate_address_p): Use mode_supports_pre_incdec_p and + mode_supports_pre_modify_p to determine if PRE_INC, PRE_DEC, and + PRE_MODIFY are supported. + (rs6000_output_move_128bit): Change to use {src,dest}_vmx_p for altivec + registers, instead of {src,dest}_av_p. + (rs6000_print_options_internal): Tweak the debug output slightly. + + Backport from mainline + 2013-10-03 Michael Meissner + + * config/rs6000/rs6000-builtin.def (XSRDPIM): Use floatdf2, + ceildf2, btruncdf2, instead of vsx_* name. + + * config/rs6000/vsx.md (vsx_add3): Change arithmetic + iterators to only do V2DF and V4SF here. Move the DF code to + rs6000.md where it is combined with SF mode. Replace with + just 'v' since only vector operations are handled with these insns + after moving the DF support to rs6000.md. + (vsx_sub3): Likewise. + (vsx_mul3): Likewise. + (vsx_div3): Likewise. + (vsx_fre2): Likewise. + (vsx_neg2): Likewise. + (vsx_abs2): Likewise. + (vsx_nabs2): Likewise. + (vsx_smax3): Likewise. + (vsx_smin3): Likewise. + (vsx_sqrt2): Likewise. + (vsx_rsqrte2): Likewise. + (vsx_fms4): Likewise. + (vsx_nfma4): Likewise. + (vsx_copysign3): Likewise. + (vsx_btrunc2): Likewise. + (vsx_floor2): Likewise. + (vsx_ceil2): Likewise. + (vsx_smaxsf3): Delete scalar ops that were moved to rs6000.md. + (vsx_sminsf3): Likewise. + (vsx_fmadf4): Likewise. + (vsx_fmsdf4): Likewise. + (vsx_nfmadf4): Likewise. + (vsx_nfmsdf4): Likewise. + (vsx_cmpdf_internal1): Likewise. + + * config/rs6000/rs6000.h (TARGET_SF_SPE): Define macros to make it + simpler to select whether a target has SPE or traditional floating + point support in iterators. + (TARGET_DF_SPE): Likewise. + (TARGET_SF_FPR): Likewise. + (TARGET_DF_FPR): Likewise. + (TARGET_SF_INSN): Macros to say whether floating point support + exists for a given operation for expanders. + (TARGET_DF_INSN): Likewise. + + * config/rs6000/rs6000.c (Ftrad): New mode attributes to allow + combining of SF/DF mode operations, using both traditional and VSX + registers. + (Fvsx): Likewise. + (Ff): Likewise. + (Fv): Likewise. + (Fs): Likewise. + (Ffre): Likewise. + (FFRE): Likewise. + (abs2): Combine SF/DF modes using traditional floating point + instructions. Add support for using the upper DF registers with + VSX support, and SF registers with power8-vector support. Update + expanders for operations supported by both the SPE and traditional + floating point units. + (abs2_fpr): Likewise. + (nabs2): Likewise. + (nabs2_fpr): Likewise. + (neg2): Likewise. + (neg2_fpr): Likewise. + (add3): Likewise. + (add3_fpr): Likewise. + (sub3): Likewise. + (sub3_fpr): Likewise. + (mul3): Likewise. + (mul3_fpr): Likewise. + (div3): Likewise. + (div3_fpr): Likewise. + (sqrt3): Likewise. + (sqrt3_fpr): Likewise. + (fre): Likewise. + (rsqrt2): Likewise. + (cmp_fpr): Likewise. + (smax3): Likewise. + (smin3): Likewise. + (smax3_vsx): Likewise. + (smin3_vsx): Likewise. + (negsf2): Delete SF operations that are merged with DF. + (abssf2): Likewise. + (addsf3): Likewise. + (subsf3): Likewise. + (mulsf3): Likewise. + (divsf3): Likewise. + (fres): Likewise. + (fmasf4_fpr): Likewise. + (fmssf4_fpr): Likewise. + (nfmasf4_fpr): Likewise. + (nfmssf4_fpr): Likewise. + (sqrtsf2): Likewise. + (rsqrtsf_internal1): Likewise. + (smaxsf3): Likewise. + (sminsf3): Likewise. + (cmpsf_internal1): Likewise. + (copysign3_fcpsgn): Add VSX/power8-vector support. + (negdf2): Delete DF operations that are merged with SF. + (absdf2): Likewise. + (nabsdf2): Likewise. + (adddf3): Likewise. + (subdf3): Likewise. + (muldf3): Likewise. + (divdf3): Likewise. + (fred): Likewise. + (rsqrtdf_internal1): Likewise. + (fmadf4_fpr): Likewise. + (fmsdf4_fpr): Likewise. + (nfmadf4_fpr): Likewise. + (nfmsdf4_fpr): Likewise. + (sqrtdf2): Likewise. + (smaxdf3): Likewise. + (smindf3): Likewise. + (cmpdf_internal1): Likewise. + (lrintdi2): Use TARGET__FPR macro. + (btrunc2): Delete separate expander, and combine with the + insn and add VSX instruction support. Use TARGET__FPR. + (btrunc2_fpr): Likewise. + (ceil2): Likewise. + (ceil2_fpr): Likewise. + (floor2): Likewise. + (floor2_fpr): Likewise. + (fma4_fpr): Combine SF and DF fused multiply/add support. + Add support for using the upper registers with VSX and + power8-vector. Move insns to be closer to the define_expands. On + VSX systems, prefer the traditional form of FMA over the VSX + version, since the traditional form allows the target not to + overlap with the inputs. + (fms4_fpr): Likewise. + (nfma4_fpr): Likewise. + (nfms4_fpr): Likewise. + + Backport from mainline + 2013-09-27 Michael Meissner + + * config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): Allow + DFmode, DImode, and SFmode in the upper VSX registers based on the + -mupper-regs-{df,sf} flags. Fix wu constraint to be ALTIVEC_REGS + if -mpower8-vector. Combine -mvsx-timode handling with the rest + of the VSX register handling. + + * config/rs6000/rs6000.md (f32_lv): Use %x0 for VSX regsters. + (f32_sv): Likewise. + (zero_extendsidi2_lfiwzx): Add support for loading into the + Altivec registers with -mpower8-vector. Use wu/wv constraints to + only do VSX memory options on Altivec registers. + (extendsidi2_lfiwax): Likewise. + (extendsfdf2_fpr): Likewise. + (mov_hardfloat, SF/SD modes): Likewise. + (mov_hardfloat32, DF/DD modes): Likewise. + (mov_hardfloat64, DF/DD modes): Likewise. + (movdi_internal64): Likewise. + + Backport from mainline + 2013-09-23 Michael Meissner + + * config/rs6000/rs6000.c (rs6000_vector_reload): Delete, combine + reload helper function arrays into a single array reg_addr. + (reload_fpr_gpr): Likewise. + (reload_gpr_vsx): Likewise. + (reload_vsx_gpr): Likewise. + (struct rs6000_reg_addr): Likewise. + (reg_addr): Likewise. + (rs6000_debug_reg_global): Change rs6000_vector_reload, + reload_fpr_gpr, reload_gpr_vsx, reload_vsx_gpr uses to reg_addr. + (rs6000_init_hard_regno_mode_ok): Likewise. + (rs6000_secondary_reload_direct_move): Likewise. + (rs6000_secondary_reload): Likewise. + + * config/rs6000/rs6000.h (enum r6000_reg_class_enum): Add new + constraints: wu, ww, and wy. Repurpose wv constraint added during + power8 changes. Put wg constraint in alphabetical order. + + * config/rs6000/rs6000.opt (-mvsx-scalar-float): New debug switch + for future work to add ISA 2.07 VSX single precision support. + (-mvsx-scalar-double): Change default from -1 to 1, update + documentation comment. + (-mvsx-scalar-memory): Rename debug switch to -mupper-regs-df. + (-mupper-regs-df): New debug switch to control whether DF values + can go in the traditional Altivec registers. + (-mupper-regs-sf): New debug switch to control whether SF values + can go in the traditional Altivec registers. + + * config/rs6000/rs6000.c (rs6000_debug_reg_global): Print wu, ww, + and wy constraints. + (rs6000_init_hard_regno_mode_ok): Use ssize_t instead of int for + loop variables. Rename -mvsx-scalar-memory to -mupper-regs-df. + Add new constraints, wu/ww/wy. Repurpose wv constraint. + (rs6000_debug_legitimate_address_p): Print if we are running + before, during, or after reload. + (rs6000_secondary_reload): Add a comment. + (rs6000_opt_masks): Add -mupper-regs-df, -mupper-regs-sf. + + * config/rs6000/constraints.md (wa constraint): Sort w + constraints. Update documentation string. + (wd constraint): Likewise. + (wf constraint): Likewise. + (wg constraint): Likewise. + (wn constraint): Likewise. + (ws constraint): Likewise. + (wt constraint): Likewise. + (wx constraint): Likewise. + (wz constraint): Likewise. + (wu constraint): New constraint for ISA 2.07 SFmode scalar + instructions. + (ww constraint): Likewise. + (wy constraint): Likewise. + (wv constraint): Repurpose ISA 2.07 constraint that did not use in + the previous submissions. + * doc/md.texi (PowerPC and IBM RS6000): Likewise. + + Backport from mainline + 2013-10-17 Michael Meissner + + PR target/58673 + * config/rs6000/rs6000.c (rs6000_legitimate_address_p): Only + restrict TImode addresses to single indirect registers if both + -mquad-memory and -mvsx-timode are used. + (rs6000_output_move_128bit): Use quad_load_store_p to determine if + we should emit load/store quad. Remove using %y for quad memory + addresses. + + * config/rs6000/rs6000.md (mov_ppc64, TI/PTImode): Add + constraints to allow load/store quad on machines where TImode is + not allowed in VSX registers. Use 'n' instead of 'F' constraint + for TImode to load integer constants. + + Backport from mainline + 2013-10-02 Michael Meissner + + PR target/58587 + * config/rs6000/rs6000-cpus.def (ISA_2_6_MASKS_SERVER): Turn off + setting -mvsx-timode by default until the underlying problem is + fixed. + (RS6000_CPU, power7 defaults): Likewise. + + Backport from trunk + 2013-08-16 Michael Meissner + + PR target/58160 + * config/rs6000/predicates.md (fusion_gpr_mem_load): Allow the + memory rtx to contain ZERO_EXTEND and SIGN_EXTEND. + + * config/rs6000/rs6000-protos.h (fusion_gpr_load_p): Pass operands + array instead of each individual operand as a separate argument. + (emit_fusion_gpr_load): Likewise. + (expand_fusion_gpr_load): Add new function declaration. + + * config/rs6000/rs6000.c (fusion_gpr_load_p): Change the calling + signature to have the operands passed as an array, instead of as + separate arguments. Allow ZERO_EXTEND to be in the memory + address, and also SIGN_EXTEND if -mpower8-fusion-sign. Do not + depend on the register live/dead flags when peepholes are run. + (expand_fusion_gpr_load): New function to be called from the + peephole2 pass, to change the register that addis sets to be the + target register. + (emit_fusion_gpr_load): Change the calling signature to have the + operands passed as an array, instead of as separate arguments. + Allow ZERO_EXTEND to be in the memory address, and also + SIGN_EXTEND if -mpower8-fusion-sign. + + * config/rs6000/rs6000.md (UNSPEC_FUSION_GPR): Delete unused + unspec enumeration. + (power8 fusion peephole/peephole2): Rework the fusion peepholes to + adjust the register addis loads up in the peephole2 pass. Do not + depend on the register live/dead state when the peephole pass is + done. + + Backport from trunk + 2013-07-23 Michael Meissner + + * config/rs6000/vector.md (xor3): Move 128-bit boolean + expanders to rs6000.md. + (ior3): Likewise. + (and3): Likewise. + (one_cmpl2): Likewise. + (nor3): Likewise. + (andc3): Likewise. + (eqv3): Likewise. + (nand3): Likewise. + (orc3): Likewise. + + * config/rs6000/rs6000-protos.h (rs6000_split_logical): New + declaration. + + * config/rs6000/rs6000.c (rs6000_split_logical_inner): Add support + to split multi-word logical operations. + (rs6000_split_logical_di): Likewise. + (rs6000_split_logical): Likewise. + + * config/rs6000/vsx.md (VSX_L2): Delete, no longer used. + (vsx_and3_32bit): Move 128-bit logical insns to rs6000.md, + and allow TImode operations in 32-bit. + (vsx_and3_64bit): Likewise. + (vsx_ior3_32bit): Likewise. + (vsx_ior3_64bit): Likewise. + (vsx_xor3_32bit): Likewise. + (vsx_xor3_64bit): Likewise. + (vsx_one_cmpl2_32bit): Likewise. + (vsx_one_cmpl2_64bit): Likewise. + (vsx_nor3_32bit): Likewise. + (vsx_nor3_64bit): Likewise. + (vsx_andc3_32bit): Likewise. + (vsx_andc3_64bit): Likewise. + (vsx_eqv3_32bit): Likewise. + (vsx_eqv3_64bit): Likewise. + (vsx_nand3_32bit): Likewise. + (vsx_nand3_64bit): Likewise. + (vsx_orc3_32bit): Likewise. + (vsx_orc3_64bit): Likewise. + + * config/rs6000/rs6000.h (VLOGICAL_REGNO_P): Always allow vector + logical types in GPRs. + + * config/rs6000/altivec.md (altivec_and3): Move 128-bit + logical insns to rs6000.md, and allow TImode operations in + 32-bit. + (altivec_ior3): Likewise. + (altivec_xor3): Likewise. + (altivec_one_cmpl2): Likewise. + (altivec_nor3): Likewise. + (altivec_andc3): Likewise. + + * config/rs6000/rs6000.md (BOOL_128): New mode iterators and mode + attributes for moving the 128-bit logical operations into + rs6000.md. + (BOOL_REGS_OUTPUT): Likewise. + (BOOL_REGS_OP1): Likewise. + (BOOL_REGS_OP2): Likewise. + (BOOL_REGS_UNARY): Likewise. + (BOOL_REGS_AND_CR0): Likewise. + (one_cmpl2): Add support for DI logical operations on + 32-bit, splitting the operations to 32-bit. + (anddi3): Likewise. + (iordi3): Likewise. + (xordi3): Likewise. + (and3, 128-bit types): Rewrite 2013-06-06 logical operator + changes to combine the 32/64-bit code, allow logical operations on + TI mode in 32-bit, and to use similar match_operator patterns like + scalar mode uses. Combine the Altivec and VSX code for logical + operations, and move it here. + (ior3, 128-bit types): Likewise. + (xor3, 128-bit types): Likewise. + (one_cmpl3, 128-bit types): Likewise. + (nor3, 128-bit types): Likewise. + (andc3, 128-bit types): Likewise. + (eqv3, 128-bit types): Likewise. + (nand3, 128-bit types): Likewise. + (orc3, 128-bit types): Likewise. + (and3_internal): Likewise. + (bool3_internal): Likewise. + (boolc3_internal1): Likewise. + (boolc3_internal2): Likewise. + (boolcc3_internal1): Likewise. + (boolcc3_internal2): Likewise. + (eqv3_internal1): Likewise. + (eqv3_internal2): Likewise. + (one_cmpl13_internal): Likewise. + + Back port from mainline: + 2013-06-06 Michael Meissner + Pat Haugen + Peter Bergner + + * lib/target-supports.exp (check_p8vector_hw_available) Add power8 + support. + (check_effective_target_powerpc_p8vector_ok): Likewise. + (is-effective-target): Likewise. + (check_vect_support_and_set_flags): Likewise. + + Backport from mainline + 2013-07-31 Michael Meissner + + * config/rs6000/predicates.md (fusion_gpr_addis): New predicates + to support power8 load fusion. + (fusion_gpr_mem_load): Likewise. + + * config/rs6000/rs6000-modes.def (PTImode): Update a comment. + + * config/rs6000/rs6000-protos.h (fusion_gpr_load_p): New + declarations for power8 load fusion. + (emit_fusion_gpr_load): Likewise. + + * config/rs6000/rs6000.c (rs6000_option_override_internal): If + tuning for power8, turn on fusion mode by default. Turn on sign + extending fusion mode if normal fusion mode is on, and we are at + -O2 or -O3. + (fusion_gpr_load_p): New function, return true if we can fuse an + addis instruction with a dependent load to a GPR. + (emit_fusion_gpr_load): Emit the instructions for power8 load + fusion to GPRs. + + * config/rs6000/vsx.md (VSX_M2): New iterator for fusion + peepholes. + (VSX load fusion peepholes): New peepholes to fuse together an + addi instruction with a VSX load instruction. + + * config/rs6000/rs6000.md (GPR load fusion peepholes): New + peepholes to fuse an addis instruction with a load to a GPR base + register. If we are supporting sign extending fusions, convert + sign extending loads to zero extending loads and add an explicit + sign extension. + + Backport from mainline + 2013-07-18 Pat Haugen + + * config/rs6000/rs6000.c (rs6000_option_override_internal): Adjust flag + interaction for new Power8 flags and VSX. + + Back port from the trunk + 2013-06-28 Michael Meissner + + PR target/57744 + * config/rs6000/rs6000.h (MODES_TIEABLE_P): Do not allow PTImode + to tie with any other modes. Eliminate Altivec vector mode tests, + since these are a subset of ALTIVEC or VSX vector modes. Simplify + code, to return 0 if testing MODE2 for a condition, if we've + already tested MODE1 for the same condition. + + Backport from mainline + 2013-06-28 Pat Haugen + + * config/rs6000/rs6000.md (define_insn ""): Fix insn type. + + Back port from the trunk + 2013-06-26 Michael Meissner + Pat Haugen + Peter Bergner + + * config/rs6000/power8.md: New. + * config/rs6000/rs6000-cpus.def (RS6000_CPU table): Adjust processor + setting for power8 entry. + * config/rs6000/t-rs6000 (MD_INCLUDES): Add power8.md. + * config/rs6000/rs6000.c (is_microcoded_insn, is_cracked_insn): Adjust + test for Power4/Power5 only. + (insn_must_be_first_in_group, insn_must_be_last_in_group): Add Power8 + support. + (force_new_group): Adjust comment. + * config/rs6000/rs6000.md: Include power8.md. + + Back port from the trunk + 2013-06-14 Michael Meissner + + PR target/57615 + * config/rs6000/rs6000.md (mov_ppc64): Call + rs6000_output_move_128bit to handle emitting quad memory + operations. Set attribute length to 8 bytes. + + Back port from the trunk + 2013-06-13 Michael Meissner + + * config/rs6000/rs6000.c (rs6000_option_override_internal): Move + test for clearing quad memory on 32-bit later. + + Back port from the trunk + + 2013-06-12 Michael Meissner + Pat Haugen + Peter Bergner + + * config/rs6000/rs6000.c (emit_load_locked): Add support for + power8 byte, half-word, and quad-word atomic instructions. + (emit_store_conditional): Likewise. + (rs6000_expand_atomic_compare_and_swap): Likewise. + (rs6000_expand_atomic_op): Likewise. + + * config/rs6000/sync.md (larx): Add new modes for power8. + (stcx): Likewise. + (AINT): New mode iterator to include TImode as well as normal + integer modes on power8. + (fetchop_pred): Use int_reg_operand instead of gpc_reg_operand so + that VSX registers are not considered. Use AINT mode iterator + instead of INT1 to allow inclusion of quad word atomic operations + on power8. + (load_locked): Likewise. + (store_conditional): Likewise. + (atomic_compare_and_swap): Likewise. + (atomic_exchange): Likewise. + (atomic_nand): Likewise. + (atomic_fetch_): Likewise. + (atomic_nand_fetch): Likewise. + (mem_thread_fence): Use gen_loadsync_ instead of enumerating + each type. + (ATOMIC): On power8, add QImode, HImode modes. + (load_locked_si): Varients of load_locked for QI/HI + modes that promote to SImode. + (load_lockedti): Convert TImode arguments to PTImode, so that we + get a guaranteed even/odd register pair. + (load_lockedpti): Likewise. + (store_conditionalti): Likewise. + (store_conditionalpti): Likewise. + + * config/rs6000/rs6000.md (QHI): New mode iterator for power8 + atomic load/store instructions. + (HSI): Likewise. + + Back port from the trunk + + 2013-06-10 Michael Meissner + Pat Haugen + Peter Bergner + + * config/rs6000/vector.md (GPR move splitter): Do not split moves + of vectors in GPRS if they are direct moves or quad word load or + store moves. + + * config/rs6000/rs6000-protos.h (rs6000_output_move_128bit): Add + declaration. + (direct_move_p): Likewise. + (quad_load_store_p): Likewise. + + * config/rs6000/rs6000.c (enum rs6000_reg_type): Simplify register + classes into bins based on the physical register type. + (reg_class_to_reg_type): Likewise. + (IS_STD_REG_TYPE): Likewise. + (IS_FP_VECT_REG_TYPE): Likewise. + (reload_fpr_gpr): Arrays to determine what insn to use if we can + use direct move instructions. + (reload_gpr_vsx): Likewise. + (reload_vsx_gpr): Likewise. + (rs6000_init_hard_regno_mode_ok): Precalculate the register type + information that is a simplification of register classes. Also + precalculate direct move reload helpers. + (direct_move_p): New function to return true if the operation can + be done as a direct move instruciton. + (quad_load_store_p): New function to return true if the operation + is a quad memory operation. + (rs6000_legitimize_address): If quad memory, only allow register + indirect for TImode addresses. + (rs6000_legitimate_address_p): Likewise. + (enum reload_reg_type): Delete, replace with rs6000_reg_type. + (rs6000_reload_register_type): Likewise. + (register_to_reg_type): Return register type. + (rs6000_secondary_reload_simple_move): New helper function for + secondary reload and secondary memory needed to identify anything + that is a simple move, and does not need reloading. + (rs6000_secondary_reload_direct_move): New helper function for + secondary reload to identify cases that can be done with several + instructions via the direct move instructions. + (rs6000_secondary_reload_move): New helper function for secondary + reload to identify moves between register types that can be done. + (rs6000_secondary_reload): Add support for quad memory operations + and for direct move. + (rs6000_secondary_memory_needed): Likewise. + (rs6000_debug_secondary_memory_needed): Change argument names. + (rs6000_output_move_128bit): New function to return the move to + use for 128-bit moves, including knowing about the various + limitations of quad memory operations. + + * config/rs6000/vsx.md (vsx_mov): Add support for quad + memory operations. call rs6000_output_move_128bit for the actual + instruciton(s) to generate. + (vsx_movti_64bit): Likewise. + + * config/rs6000/rs6000.md (UNSPEC_P8V_FMRGOW): New unspec values. + (UNSPEC_P8V_MTVSRWZ): Likewise. + (UNSPEC_P8V_RELOAD_FROM_GPR): Likewise. + (UNSPEC_P8V_MTVSRD): Likewise. + (UNSPEC_P8V_XXPERMDI): Likewise. + (UNSPEC_P8V_RELOAD_FROM_VSX): Likewise. + (UNSPEC_FUSION_GPR): Likewise. + (FMOVE128_GPR): New iterator for direct move. + (f32_lv): New mode attribute for load/store of SFmode/SDmode + values. + (f32_sv): Likewise. + (f32_dm): Likewise. + (zero_extenddi2_internal1): Add support for power8 32-bit + loads and direct move instructions. + (zero_extendsidi2_lfiwzx): Likewise. + (extendsidi2_lfiwax): Likewise. + (extendsidi2_nocell): Likewise. + (floatsi2_lfiwax): Likewise. + (lfiwax): Likewise. + (floatunssi2_lfiwzx): Likewise. + (lfiwzx): Likewise. + (fix_trunc_stfiwx): Likewise. + (fixuns_trunc_stfiwx): Likewise. + (mov_hardfloat, 32-bit floating point): Likewise. + (mov_hardfloat64, 64-bit floating point): Likewise. + (parity2_cmpb): Set length/type attr. + (unnamed shift right patterns, mov_internal2): Change type attr + for 'mr.' to fast_compare. + (bpermd_): Change type attr to popcnt. + (p8_fmrgow_): New insns for power8 direct move support. + (p8_mtvsrwz_1): Likewise. + (p8_mtvsrwz_2): Likewise. + (reload_fpr_from_gpr): Likewise. + (p8_mtvsrd_1): Likewise. + (p8_mtvsrd_2): Likewise. + (p8_xxpermdi_): Likewise. + (reload_vsx_from_gpr): Likewise. + (reload_vsx_from_gprsf): Likewise. + (p8_mfvsrd_3_): LIkewise. + (reload_gpr_from_vsx): Likewise. + (reload_gpr_from_vsxsf): Likewise. + (p8_mfvsrd_4_disf): Likewise. + (multi-word GPR splits): Do not split direct moves or quad memory + operations. + + Backport from the trunk + + 2013-06-06 Michael Meissner + Pat Haugen + Peter Bergner + + * doc/extend.texi (PowerPC AltiVec/VSX Built-in Functions): + Document new power8 builtins. + + * config/rs6000/vector.md (and3): Add a clobber/scratch of a + condition code register, to allow 128-bit logical operations to be + done in the VSX or GPR registers. + (nor3): Use the canonical form for nor. + (eqv3): Add expanders for power8 xxleqv, xxlnand, xxlorc, + vclz*, and vpopcnt* vector instructions. + (nand3): Likewise. + (orc3): Likewise. + (clz2): LIkewise. + (popcount2): Likewise. + + * config/rs6000/predicates.md (int_reg_operand): Rework tests so + that only the GPRs are recognized. + + * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add + support for new power8 builtins. + + * config/rs6000/rs6000-builtin.def (xscvspdpn): Add new power8 + builtin functions. + (xscvdpspn): Likewise. + (vclz): Likewise. + (vclzb): Likewise. + (vclzh): Likewise. + (vclzw): Likewise. + (vclzd): Likewise. + (vpopcnt): Likewise. + (vpopcntb): Likewise. + (vpopcnth): Likewise. + (vpopcntw): Likewise. + (vpopcntd): Likewise. + (vgbbd): Likewise. + (vmrgew): Likewise. + (vmrgow): Likewise. + (eqv): Likewise. + (eqv_v16qi3): Likewise. + (eqv_v8hi3): Likewise. + (eqv_v4si3): Likewise. + (eqv_v2di3): Likewise. + (eqv_v4sf3): Likewise. + (eqv_v2df3): Likewise. + (nand): Likewise. + (nand_v16qi3): Likewise. + (nand_v8hi3): Likewise. + (nand_v4si3): Likewise. + (nand_v2di3): Likewise. + (nand_v4sf3): Likewise. + (nand_v2df3): Likewise. + (orc): Likewise. + (orc_v16qi3): Likewise. + (orc_v8hi3): Likewise. + (orc_v4si3): Likewise. + (orc_v2di3): Likewise. + (orc_v4sf3): Likewise. + (orc_v2df3): Likewise. + + * config/rs6000/rs6000.c (rs6000_option_override_internal): Only + allow power8 quad mode in 64-bit. + (rs6000_builtin_vectorized_function): Add support to vectorize + ISA 2.07 count leading zeros, population count builtins. + (rs6000_expand_vector_init): On ISA 2.07 use xscvdpspn to form + V4SF vectors instead of xscvdpsp to avoid IEEE related traps. + (builtin_function_type): Add vgbbd builtin function which takes an + unsigned argument. + (altivec_expand_vec_perm_const): Add support for new power8 merge + instructions. + + * config/rs6000/vsx.md (VSX_L2): New iterator for 128-bit types, + that does not include TImdoe for use with 32-bit. + (UNSPEC_VSX_CVSPDPN): Support for power8 xscvdpspn and xscvspdpn + instructions. + (UNSPEC_VSX_CVDPSPN): Likewise. + (vsx_xscvdpspn): Likewise. + (vsx_xscvspdpn): Likewise. + (vsx_xscvdpspn_scalar): Likewise. + (vsx_xscvspdpn_directmove): Likewise. + (vsx_and3): Split logical operations into 32-bit and + 64-bit. Add support to do logical operations on TImode as well as + VSX vector types. Allow logical operations to be done in either + VSX registers or in general purpose registers in 64-bit mode. Add + splitters if GPRs were used. For AND, add clobber of CCmode to + allow use of ANDI on GPRs. Rewrite nor to use the canonical RTL + encoding. + (vsx_and3_32bit): Likewise. + (vsx_and3_64bit): Likewise. + (vsx_ior3): Likewise. + (vsx_ior3_32bit): Likewise. + (vsx_ior3_64bit): Likewise. + (vsx_xor3): Likewise. + (vsx_xor3_32bit): Likewise. + (vsx_xor3_64bit): Likewise. + (vsx_one_cmpl2): Likewise. + (vsx_one_cmpl2_32bit): Likewise. + (vsx_one_cmpl2_64bit): Likewise. + (vsx_nor3): Likewise. + (vsx_nor3_32bit): Likewise. + (vsx_nor3_64bit): Likewise. + (vsx_andc3): Likewise. + (vsx_andc3_32bit): Likewise. + (vsx_andc3_64bit): Likewise. + (vsx_eqv3_32bit): Add support for power8 xxleqv, xxlnand, + and xxlorc instructions. + (vsx_eqv3_64bit): Likewise. + (vsx_nand3_32bit): Likewise. + (vsx_nand3_64bit): Likewise. + (vsx_orc3_32bit): Likewise. + (vsx_orc3_64bit): Likewise. + + * config/rs6000/rs6000.h (VLOGICAL_REGNO_P): Update comment. + + * config/rs6000/altivec.md (UNSPEC_VGBBD): Add power8 vgbbd + instruction. + (p8_vmrgew): Add power8 vmrgew and vmrgow instructions. + (p8_vmrgow): Likewise. + (altivec_and3): Add clobber of CCmode to allow AND using + GPRs to be split under VSX. + (p8v_clz2): Add power8 count leading zero support. + (p8v_popcount2): Add power8 population count support. + (p8v_vgbbd): Add power8 gather bits by bytes by doubleword + support. + + * config/rs6000/rs6000.md (eqv3): Add support for powerp eqv + instruction. + + * config/rs6000/altivec.h (vec_eqv): Add defines to export power8 + builtin functions. + (vec_nand): Likewise. + (vec_vclz): Likewise. + (vec_vclzb): Likewise. + (vec_vclzd): Likewise. + (vec_vclzh): Likewise. + (vec_vclzw): Likewise. + (vec_vgbbd): Likewise. + (vec_vmrgew): Likewise. + (vec_vmrgow): Likewise. + (vec_vpopcnt): Likewise. + (vec_vpopcntb): Likewise. + (vec_vpopcntd): Likewise. + (vec_vpopcnth): Likewise. + (vec_vpopcntw): Likewise. + + Backport from trunk + + 2013-05-29 Michael Meissner + Pat Haugen + Peter Bergner + + * config/rs6000/vector.md (VEC_I): Add support for new power8 V2DI + instructions. + (VEC_A): Likewise. + (VEC_C): Likewise. + (vrotl3): Likewise. + (vashl3): Likewise. + (vlshr3): Likewise. + (vashr3): Likewise. + + * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add + support for power8 V2DI builtins. + + * config/rs6000/rs6000-builtin.def (abs_v2di): Add support for + power8 V2DI builtins. + (vupkhsw): Likewise. + (vupklsw): Likewise. + (vaddudm): Likewise. + (vminsd): Likewise. + (vmaxsd): Likewise. + (vminud): Likewise. + (vmaxud): Likewise. + (vpkudum): Likewise. + (vpksdss): Likewise. + (vpkudus): Likewise. + (vpksdus): Likewise. + (vrld): Likewise. + (vsld): Likewise. + (vsrd): Likewise. + (vsrad): Likewise. + (vsubudm): Likewise. + (vcmpequd): Likewise. + (vcmpgtsd): Likewise. + (vcmpgtud): Likewise. + (vcmpequd_p): Likewise. + (vcmpgtsd_p): Likewise. + (vcmpgtud_p): Likewise. + (vupkhsw): Likewise. + (vupklsw): Likewise. + (vaddudm): Likewise. + (vmaxsd): Likewise. + (vmaxud): Likewise. + (vminsd): Likewise. + (vminud): Likewise. + (vpksdss): Likewise. + (vpksdus): Likewise. + (vpkudum): Likewise. + (vpkudus): Likewise. + (vrld): Likewise. + (vsld): Likewise. + (vsrad): Likewise. + (vsrd): Likewise. + (vsubudm): Likewise. + + * config/rs6000/rs6000.c (rs6000_init_hard_regno_mode_ok): Add + support for power8 V2DI instructions. + + * config/rs6000/altivec.md (UNSPEC_VPKUHUM): Add support for + power8 V2DI instructions. Combine pack and unpack insns to use an + iterator for each mode. Check whether a particular mode supports + Altivec instructions instead of just checking TARGET_ALTIVEC. + (UNSPEC_VPKUWUM): Likewise. + (UNSPEC_VPKSHSS): Likewise. + (UNSPEC_VPKSWSS): Likewise. + (UNSPEC_VPKUHUS): Likewise. + (UNSPEC_VPKSHUS): Likewise. + (UNSPEC_VPKUWUS): Likewise. + (UNSPEC_VPKSWUS): Likewise. + (UNSPEC_VPACK_SIGN_SIGN_SAT): Likewise. + (UNSPEC_VPACK_SIGN_UNS_SAT): Likewise. + (UNSPEC_VPACK_UNS_UNS_SAT): Likewise. + (UNSPEC_VPACK_UNS_UNS_MOD): Likewise. + (UNSPEC_VUPKHSB): Likewise. + (UNSPEC_VUNPACK_HI_SIGN): Likewise. + (UNSPEC_VUNPACK_LO_SIGN): Likewise. + (UNSPEC_VUPKHSH): Likewise. + (UNSPEC_VUPKLSB): Likewise. + (UNSPEC_VUPKLSH): Likewise. + (VI2): Likewise. + (VI_char): Likewise. + (VI_scalar): Likewise. + (VI_unit): Likewise. + (VP): Likewise. + (VP_small): Likewise. + (VP_small_lc): Likewise. + (VU_char): Likewise. + (add3): Likewise. + (altivec_vaddcuw): Likewise. + (altivec_vaddus): Likewise. + (altivec_vaddss): Likewise. + (sub3): Likewise. + (altivec_vsubcuw): Likewise. + (altivec_vsubus): Likewise. + (altivec_vsubss): Likewise. + (altivec_vavgs): Likewise. + (altivec_vcmpbfp): Likewise. + (altivec_eq): Likewise. + (altivec_gt): Likewise. + (altivec_gtu): Likewise. + (umax3): Likewise. + (smax3): Likewise. + (umin3): Likewise. + (smin3): Likewise. + (altivec_vpkuhum): Likewise. + (altivec_vpkuwum): Likewise. + (altivec_vpkshss): Likewise. + (altivec_vpkswss): Likewise. + (altivec_vpkuhus): Likewise. + (altivec_vpkshus): Likewise. + (altivec_vpkuwus): Likewise. + (altivec_vpkswus): Likewise. + (altivec_vpksss): Likewise. + (altivec_vpksus): Likewise. + (altivec_vpkuus): Likewise. + (altivec_vpkuum): Likewise. + (altivec_vrl): Likewise. + (altivec_vsl): Likewise. + (altivec_vsr): Likewise. + (altivec_vsra): Likewise. + (altivec_vsldoi_): Likewise. + (altivec_vupkhsb): Likewise. + (altivec_vupkhs): Likewise. + (altivec_vupkls): Likewise. + (altivec_vupkhsh): Likewise. + (altivec_vupklsb): Likewise. + (altivec_vupklsh): Likewise. + (altivec_vcmpequ_p): Likewise. + (altivec_vcmpgts_p): Likewise. + (altivec_vcmpgtu_p): Likewise. + (abs2): Likewise. + (vec_unpacks_hi_v16qi): Likewise. + (vec_unpacks_hi_v8hi): Likewise. + (vec_unpacks_lo_v16qi): Likewise. + (vec_unpacks_hi_): Likewise. + (vec_unpacks_lo_v8hi): Likewise. + (vec_unpacks_lo_): Likewise. + (vec_pack_trunc_v8h): Likewise. + (vec_pack_trunc_v4si): Likewise. + (vec_pack_trunc_): Likewise. + + * config/rs6000/altivec.h (vec_vaddudm): Add defines for power8 + V2DI builtins. + (vec_vmaxsd): Likewise. + (vec_vmaxud): Likewise. + (vec_vminsd): Likewise. + (vec_vminud): Likewise. + (vec_vpksdss): Likewise. + (vec_vpksdus): Likewise. + (vec_vpkudum): Likewise. + (vec_vpkudus): Likewise. + (vec_vrld): Likewise. + (vec_vsld): Likewise. + (vec_vsrad): Likewise. + (vec_vsrd): Likewise. + (vec_vsubudm): Likewise. + (vec_vupkhsw): Likewise. + (vec_vupklsw): Likewise. + + 2013-05-22 Michael Meissner + Pat Haugen + Peter Bergner + + * doc/extend.texi (PowerPC AltiVec/VSX Built-in Functions): Add + documentation for the power8 crypto builtins. + + * config/rs6000/t-rs6000 (MD_INCLUDES): Add crypto.md. + + * config/rs6000/rs6000-builtin.def (BU_P8V_AV_1): Add support + macros for defining power8 builtin functions. + (BU_P8V_AV_2): Likewise. + (BU_P8V_AV_P): Likewise. + (BU_P8V_VSX_1): Likewise. + (BU_P8V_OVERLOAD_1): Likewise. + (BU_P8V_OVERLOAD_2): Likewise. + (BU_CRYPTO_1): Likewise. + (BU_CRYPTO_2): Likewise. + (BU_CRYPTO_3): Likewise. + (BU_CRYPTO_OVERLOAD_1): Likewise. + (BU_CRYPTO_OVERLOAD_2): Likewise. + (XSCVSPDP): Fix typo, point to the correct instruction. + (VCIPHER): Add power8 crypto builtins. + (VCIPHERLAST): Likewise. + (VNCIPHER): Likewise. + (VNCIPHERLAST): Likewise. + (VPMSUMB): Likewise. + (VPMSUMH): Likewise. + (VPMSUMW): Likewise. + (VPERMXOR_V2DI): Likewise. + (VPERMXOR_V4SI: Likewise. + (VPERMXOR_V8HI: Likewise. + (VPERMXOR_V16QI: Likewise. + (VSHASIGMAW): Likewise. + (VSHASIGMAD): Likewise. + (VPMSUM): Likewise. + (VPERMXOR): Likewise. + (VSHASIGMA): Likewise. + + * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Define + __CRYPTO__ if the crypto instructions are available. + (altivec_overloaded_builtins): Add support for overloaded power8 + builtins. + + * config/rs6000/rs6000.c (rs6000_expand_ternop_builtin): Add + support for power8 crypto builtins. + (builtin_function_type): Likewise. + (altivec_init_builtins): Add support for builtins that take vector + long long (V2DI) arguments. + + * config/rs6000/crypto.md: New file, define power8 crypto + instructions. + + 2013-05-22 Michael Meissner + Pat Haugen + Peter Bergner + + * doc/invoke.texi (Option Summary): Add power8 options. + (RS/6000 and PowerPC Options): Likewise. + + * doc/md.texi (PowerPC and IBM RS6000 constraints): Update to use + constraints.md instead of rs6000.h. Reorder w* constraints. Add + wm, wn, wr documentation. + + * gcc/config/rs6000/constraints.md (wm): New constraint for VSX + registers if direct move instructions are enabled. + (wn): New constraint for no registers. + (wq): New constraint for quad word even GPR registers. + (wr): New constraint if 64-bit instructions are enabled. + (wv): New constraint if power8 vector instructions are enabled. + (wQ): New constraint for quad word memory locations. + + * gcc/config/rs6000/predicates.md (const_0_to_15_operand): New + constraint for 0..15 for crypto instructions. + (gpc_reg_operand): If VSX allow registers in VSX registers as well + as GPR and floating point registers. + (int_reg_operand): New predicate to match only GPR registers. + (base_reg_operand): New predicate to match base registers. + (quad_int_reg_operand): New predicate to match even GPR registers + for quad memory operations. + (vsx_reg_or_cint_operand): New predicate to allow vector logical + operations in both GPR and VSX registers. + (quad_memory_operand): New predicate for quad memory operations. + (reg_or_indexed_operand): New predicate for direct move support. + + * gcc/config/rs6000/rs6000-cpus.def (ISA_2_5_MASKS_EMBEDDED): + Inherit from ISA_2_4_MASKS, not ISA_2_2_MASKS. + (ISA_2_7_MASKS_SERVER): New mask for ISA 2.07 (i.e. power8). + (POWERPC_MASKS): Add power8 options. + (power8 cpu): Use ISA_2_7_MASKS_SERVER instead of specifying the + various options. + + * gcc/config/rs6000/rs6000-c.c (rs6000_target_modify_macros): + Define _ARCH_PWR8 and __POWER8_VECTOR__ for power8. + + * gcc/config/rs6000/rs6000.opt (-mvsx-timode): Add documentation. + (-mpower8-fusion): New power8 options. + (-mpower8-fusion-sign): Likewise. + (-mpower8-vector): Likewise. + (-mcrypto): Likewise. + (-mdirect-move): Likewise. + (-mquad-memory): Likewise. + + * gcc/config/rs6000/rs6000.c (power8_cost): Initial definition for + power8. + (rs6000_hard_regno_mode_ok): Make PTImode only match even GPR + registers. + (rs6000_debug_reg_print): Print the base register class if + -mdebug=reg. + (rs6000_debug_vector_unit): Add p8_vector. + (rs6000_debug_reg_global): If -mdebug=reg, print power8 constraint + definitions. Also print fusion state. + (rs6000_init_hard_regno_mode_ok): Set up power8 constraints. + (rs6000_builtin_mask_calculate): Add power8 builtin support. + (rs6000_option_override_internal): Add support for power8. + (rs6000_common_init_builtins): Add debugging for skipped builtins + if -mdebug=builtin. + (rs6000_adjust_cost): Add power8 support. + (rs6000_issue_rate): Likewise. + (insn_must_be_first_in_group): Likewise. + (insn_must_be_last_in_group): Likewise. + (force_new_group): Likewise. + (rs6000_register_move_cost): Likewise. + (rs6000_opt_masks): Likewise. + + * config/rs6000/rs6000.h (ASM_CPU_POWER8_SPEC): If we don't have a + power8 capable assembler, default to power7 options. + (TARGET_DIRECT_MOVE): Likewise. + (TARGET_CRYPTO): Likewise. + (TARGET_P8_VECTOR): Likewise. + (VECTOR_UNIT_P8_VECTOR_P): Define power8 vector support. + (VECTOR_UNIT_VSX_OR_P8_VECTOR_P): Likewise. + (VECTOR_MEM_P8_VECTOR_P): Likewise. + (VECTOR_MEM_VSX_OR_P8_VECTOR_P): Likewise. + (VECTOR_MEM_ALTIVEC_OR_VSX_P): Likewise. + (TARGET_XSCVDPSPN): Likewise. + (TARGET_XSCVSPDPN): Likewsie. + (TARGET_SYNC_HI_QI): Likewise. + (TARGET_SYNC_TI): Likewise. + (MASK_CRYPTO): Likewise. + (MASK_DIRECT_MOVE): Likewise. + (MASK_P8_FUSION): Likewise. + (MASK_P8_VECTOR): Likewise. + (REG_ALLOC_ORDER): Move fr13 to be lower in priority so that the + TFmode temporary used by some of the direct move instructions to + get two FP temporary registers does not force creation of a stack + frame. + (VLOGICAL_REGNO_P): Allow vector logical operations in GPRs. + (MODES_TIEABLE_P): Move the VSX tests above the Altivec tests so + that any VSX registers are tieable, even if they are also an + Altivec vector mode. + (r6000_reg_class_enum): Add wm, wr, wv constraints. + (RS6000_BTM_P8_VECTOR): Power8 builtin support. + (RS6000_BTM_CRYPTO): Likewise. + (RS6000_BTM_COMMON): Likewise. + + * config/rs6000/rs6000.md (cpu attribute): Add power8. + * config/rs6000/rs6000-opts.h (PROCESSOR_POWER8): Likewise. + (enum rs6000_vector): Add power8 vector support. + + + Backport from mainline + 2013-03-20 Pat Haugen + + * config/rs6000/predicates.md (indexed_address, update_address_mem + update_indexed_address_mem): New predicates. + * config/rs6000/vsx.md (vsx_extract__zero): Set correct "type" + attribute for load/store instructions. + * config/rs6000/dfp.md (movsd_store): Likewise. + (movsd_load): Likewise. + * config/rs6000/rs6000.md (zero_extenddi2_internal1): Likewise. + (unnamed HI->DI extend define_insn): Likewise. + (unnamed SI->DI extend define_insn): Likewise. + (unnamed QI->SI extend define_insn): Likewise. + (unnamed QI->HI extend define_insn): Likewise. + (unnamed HI->SI extend define_insn): Likewise. + (unnamed HI->SI extend define_insn): Likewise. + (extendsfdf2_fpr): Likewise. + (movsi_internal1): Likewise. + (movsi_internal1_single): Likewise. + (movhi_internal): Likewise. + (movqi_internal): Likewise. + (movcc_internal1): Correct mnemonic for stw insn. Set correct "type" + attribute for load/store instructions. + (mov_hardfloat): Set correct "type" attribute for load/store + instructions. + (mov_softfloat): Likewise. + (mov_hardfloat32): Likewise. + (mov_hardfloat64): Likewise. + (mov_softfloat64): Likewise. + (movdi_internal32): Likewise. + (movdi_internal64): Likewise. + (probe_stack_): Likewise. + + Backport from mainline + 2013-03-20 Michael Meissner + + * config/rs6000/vector.md (VEC_R): Add 32-bit integer, binary + floating point, and decimal floating point to reload iterator. + + * config/rs6000/constraints.md (wl constraint): New constraints to + return FLOAT_REGS if certain options are used to reduce the number + of separate patterns that exist in the file. + (wx constraint): Likewise. + (wz constraint): Likewise. + + * config/rs6000/rs6000.c (rs6000_debug_reg_global): If + -mdebug=reg, print wg, wl, wx, and wz constraints. + (rs6000_init_hard_regno_mode_ok): Initialize new constraints. + Initialize the reload functions for 64-bit binary/decimal floating + point types. + (reg_offset_addressing_ok_p): If we are on a power7 or later, use + LFIWZX and STFIWX to load/store 32-bit decimal types, and don't + create the buffer on the stack to overcome not having a 32-bit + load and store. + (rs6000_emit_move): Likewise. + (rs6000_secondary_memory_needed_rtx): Likewise. + (rs6000_alloc_sdmode_stack_slot): Likewise. + (rs6000_preferred_reload_class): On VSX, we can create SFmode 0.0f + via xxlxor, just like DFmode 0.0. + + * config/rs6000/rs6000.h (TARGET_NO_SDMODE_STACK): New macro) + (define as 1 if we are running on a power7 or newer. + (enum r6000_reg_class_enum): Add new constraints. + + * config/rs6000/dfp.md (movsd): Delete, combine with binary + floating point moves in rs6000.md. Combine power6x (mfpgpr) moves + with other moves by using conditional constraits (wg). Use LFIWZX + and STFIWX for loading SDmode on power7. Use xxlxor to create + 0.0f. + (movsd splitter): Likewise. + (movsd_hardfloat): Likewise. + (movsd_softfloat): Likewise. + + * config/rs6000/rs6000.md (FMOVE32): New iterators to combine + binary and decimal floating point moves. + (fmove_ok): New attributes to combine binary and decimal floating + point moves, and to combine power6x (mfpgpr) moves along normal + floating moves. + (real_value_to_target): Likewise. + (f32_lr): Likewise. + (f32_lm): Likewise. + (f32_li): Likewise. + (f32_sr): Likewise. + (f32_sm): Likewise. + (f32_si): Likewise. + (movsf): Combine binary and decimal floating point moves. Combine + power6x (mfpgpr) moves with other moves by using conditional + constraits (wg). Use LFIWZX and STFIWX for loading SDmode on + power7. + (mov for SFmode/SDmode); Likewise. + (SFmode/SDmode splitters): Likewise. + (movsf_hardfloat): Likewise. + (mov_hardfloat for SFmode/SDmode): Likewise. + (movsf_softfloat): Likewise. + (mov_softfloat for SFmode/SDmode): Likewise. + + * doc/md.texi (PowerPC and IBM RS6000 constraints): Document wl) + (wx and wz constraints. + + * config/rs6000/constraints.md (wg constraint): New constraint to + return FLOAT_REGS if -mmfpgpr (power6x) was used. + + * config/rs6000/rs6000.h (enum r6000_reg_class_enum): Add wg + constraint. + + * config/rs6000/rs6000.c (rs6000_debug_reg_global): If + -mdebug=reg, print wg, wl, wx, and wz constraints. + (rs6000_init_hard_regno_mode_ok): Initialize new constraints. + Initialize the reload functions for 64-bit binary/decimal floating + point types. + (reg_offset_addressing_ok_p): If we are on a power7 or later, use + LFIWZX and STFIWX to load/store 32-bit decimal types, and don't + create the buffer on the stack to overcome not having a 32-bit + load and store. + (rs6000_emit_move): Likewise. + (rs6000_secondary_memory_needed_rtx): Likewise. + (rs6000_alloc_sdmode_stack_slot): Likewise. + (rs6000_preferred_reload_class): On VSX, we can create SFmode 0.0f + via xxlxor, just like DFmode 0.0. + + + * config/rs6000/dfp.md (movdd): Delete, combine with binary + floating point moves in rs6000.md. Combine power6x (mfpgpr) moves + with other moves by using conditional constraits (wg). Use LFIWZX + and STFIWX for loading SDmode on power7. + (movdd splitters): Likewise. + (movdd_hardfloat32): Likewise. + (movdd_softfloat32): Likewise. + (movdd_hardfloat64_mfpgpr): Likewise. + (movdd_hardfloat64): Likewise. + (movdd_softfloat64): Likewise. + + * config/rs6000/rs6000.md (FMOVE64): New iterators to combine + 64-bit binary and decimal floating point moves. + (FMOVE64X): Likewise. + (movdf): Combine 64-bit binary and decimal floating point moves. + Combine power6x (mfpgpr) moves with other moves by using + conditional constraits (wg). + (mov for DFmode/DDmode): Likewise. + (DFmode/DDmode splitters): Likewise. + (movdf_hardfloat32): Likewise. + (mov_hardfloat32 for DFmode/DDmode): Likewise. + (movdf_softfloat32): Likewise. + (movdf_hardfloat64_mfpgpr): Likewise. + (movdf_hardfloat64): Likewise. + (mov_hardfloat64 for DFmode/DDmode): Likewise. + (movdf_softfloat64): Likewise. + (mov_softfloat64 for DFmode/DDmode): Likewise. + (reload__load): Move to later in the file so they aren't in + the middle of the floating point move insns. + (reload__store): Likewise. + + * doc/md.texi (PowerPC and IBM RS6000 constraints): Document wg + constraint. + + * config/rs6000/rs6000.c (rs6000_debug_reg_global): Print out wg + constraint if -mdebug=reg. + (rs6000_initi_hard_regno_mode_ok): Enable wg constraint if + -mfpgpr. Enable using dd reload support if needed. + + * config/rs6000/dfp.md (movtd): Delete, combine with 128-bit + binary and decimal floating point moves in rs6000.md. + (movtd_internal): Likewise. + + * config/rs6000/rs6000.md (FMOVE128): Combine 128-bit binary and + decimal floating point moves. + (movtf): Likewise. + (movtf_internal): Likewise. + (mov_internal, TDmode/TFmode): Likewise. + (movtf_softfloat): Likewise. + (mov_softfloat, TDmode/TFmode): Likewise. + + * config/rs6000/rs6000.md (movdi_mfpgpr): Delete, combine with + movdi_internal64, using wg constraint for move direct operations. + (movdi_internal64): Likewise. + + * config/rs6000/rs6000.c (rs6000_debug_reg_global): Print + MODES_TIEABLE_P for selected modes. Print the numerical value of + the various virtual registers. Use GPR/FPR first/last values) + (instead of hard coding the register numbers. Print which modes + have reload functions registered. + (rs6000_option_override_internal): If -mdebug=reg, trace the + options settings before/after setting cpu, target and subtarget + settings. + (rs6000_secondary_reload_trace): Improve the RTL dump for + -mdebug=addr and for secondary reload failures in + rs6000_secondary_reload_inner. + (rs6000_secondary_reload_fail): Likewise. + (rs6000_secondary_reload_inner): Likewise. + + * config/rs6000/rs6000.md (FIRST_GPR_REGNO): Add convenience + macros for first/last GPR and FPR registers. + (LAST_GPR_REGNO): Likewise. + (FIRST_FPR_REGNO): Likewise. + (LAST_FPR_REGNO): Likewise. + + * config/rs6000/vector.md (mul3): Use the combined macro + VECTOR_UNIT_ALTIVEC_OR_VSX_P instead of separate calls to + VECTOR_UNIT_ALTIVEC_P and VECTOR_UNIT_VSX_P. + (vcond): Likewise. + (vcondu): Likewise. + (vector_gtu): Likewise. + (vector_gte): Likewise. + (xor3): Don't allow logical operations on TImode in 32-bit + to prevent the compiler from converting DImode operations to + TImode. + (ior3): Likewise. + (and3): Likewise. + (one_cmpl2): Likewise. + (nor3): Likewise. + (andc3): Likewise. + + * config/rs6000/constraints.md (wt constraint): New constraint + that returns VSX_REGS if TImode is allowed in VSX registers. + + * config/rs6000/predicates.md (easy_fp_constant): 0.0f is an easy + constant under VSX. + + * config/rs6000/rs6000-modes.def (PTImode): Define, PTImode is + similar to TImode, but it is restricted to being in the GPRs. + + * config/rs6000/rs6000.opt (-mvsx-timode): New switch to allow + TImode to occupy a single VSX register. + + * config/rs6000/rs6000-cpus.def (ISA_2_6_MASKS_SERVER): Default to + -mvsx-timode for power7/power8. + (power7 cpu): Likewise. + (power8 cpu): Likewise. + + * config/rs6000/rs6000.c (rs6000_hard_regno_nregs_internal): Make + sure that TFmode/TDmode take up two registers if they are ever + allowed in the upper VSX registers. + (rs6000_hard_regno_mode_ok): If -mvsx-timode, allow TImode in VSX + registers. + (rs6000_init_hard_regno_mode_ok): Likewise. + (rs6000_debug_reg_global): Add debugging for PTImode and wt + constraint. Print if LRA is turned on. + (rs6000_option_override_internal): Give an error if -mvsx-timode + and VSX is not enabled. + (invalid_e500_subreg): Handle PTImode, restricting it to GPRs. If + -mvsx-timode, restrict TImode to reg+reg addressing, and PTImode + to reg+offset addressing. Use PTImode when checking offset + addresses for validity. + (reg_offset_addressing_ok_p): Likewise. + (rs6000_legitimate_offset_address_p): Likewise. + (rs6000_legitimize_address): Likewise. + (rs6000_legitimize_reload_address): Likewise. + (rs6000_legitimate_address_p): Likewise. + (rs6000_eliminate_indexed_memrefs): Likewise. + (rs6000_emit_move): Likewise. + (rs6000_secondary_reload): Likewise. + (rs6000_secondary_reload_inner): Handle PTImode. Allow 64-bit + reloads to fpr registers to continue to use reg+offset addressing) + (but 64-bit reloads to altivec registers need reg+reg addressing. + Drop test for PRE_MODIFY, since VSX loads/stores no longer support + it. Treat LO_SUM like a PLUS operation. + (rs6000_secondary_reload_class): If type is 64-bit, prefer to use + FLOAT_REGS instead of VSX_RGS to allow use of reg+offset + addressing. + (rs6000_cannot_change_mode_class): Do not allow TImode in VSX + registers to share a register with a smaller sized type, since VSX + puts scalars in the upper 64-bits. + (print_operand): Add support for PTImode. + (rs6000_register_move_cost): Use VECTOR_MEM_VSX_P instead of + VECTOR_UNIT_VSX_P to catch types that can be loaded in VSX + registers, but don't have arithmetic support. + (rs6000_memory_move_cost): Add test for VSX. + (rs6000_opt_masks): Add -mvsx-timode. + + * config/rs6000/vsx.md (VSm): Change to use 64-bit aligned moves + for TImode. + (VSs): Likewise. + (VSr): Use wt constraint for TImode. + (VSv): Drop TImode support. + (vsx_movti): Delete, replace with versions for 32-bit and 64-bit. + (vsx_movti_64bit): Likewise. + (vsx_movti_32bit): Likewise. + (vec_store_): Use VSX iterator instead of vector iterator. + (vsx_and3): Delete use of '?' constraint on inputs, just put + one '?' on the appropriate output constraint. Do not allow TImode + logical operations on 32-bit systems. + (vsx_ior3): Likewise. + (vsx_xor3): Likewise. + (vsx_one_cmpl2): Likewise. + (vsx_nor3): Likewise. + (vsx_andc3): Likewise. + (vsx_concat_): Likewise. + (vsx_xxpermdi_): Fix thinko for non V2DF/V2DI modes. + + * config/rs6000/rs6000.h (MASK_VSX_TIMODE): Map from + OPTION_MASK_VSX_TIMODE. + (enum rs6000_reg_class_enum): Add RS6000_CONSTRAINT_wt. + (STACK_SAVEAREA_MODE): Use PTImode instead of TImode. + + * config/rs6000/rs6000.md (INT mode attribute): Add PTImode. + (TI2 iterator): New iterator for TImode, PTImode. + (wd mode attribute): Add values for vector types. + (movti_string): Replace TI move operations with operations for + TImode and PTImode. Add support for TImode being allowed in VSX + registers. + (mov_string, TImode/PTImode): Likewise. + (movti_ppc64): Likewise. + (mov_ppc64, TImode/PTImode): Likewise. + (TI mode splitters): Likewise. + + * doc/md.texi (PowerPC and IBM RS6000 constraints): Document wt + constraint. + +2014-04-04 Richard Biener + + * tree-ssanames.c (make_ssa_name_fn): Fix assert. + +2014-04-02 Andreas Krebbel + + * config/s390/s390.c (s390_expand_insv): Use GET_MODE_BITSIZE. + +2014-04-01 Richard Biener + + * gimple.h (struct gimple_statement_base): Align subcode to + 16 bits. + +2014-04-01 Sebastian Huber + + * doc/invoke.texi (mapp-regs): Clarify. + +2014-03-31 H.J. Lu + + PR rtl-optimization/60700 + Backport from mainline + 2013-07-30 Zhenqiang Chen + + PR rtl-optimization/57637 + * function.c (move_insn_for_shrink_wrap): Also check the + GEN set of the LIVE problem for the liveness analysis + if it exists, otherwise give up. + +2014-03-30 Kaz Kojima + + Backport from mainline + 2014-03-19 Kaz Kojima + + PR target/60039 + * config/sh/sh.md (udivsi3_i1): Clobber R1 register. + +2014-03-26 Martin Jambor + + PR ipa/60419 + * ipa.c (symtab_remove_unreachable_nodes): Clear thunk and + alias flags of nodes in the border. + +2014-03-26 Eric Botcazou + + PR rtl-optimization/60452 + * rtlanal.c (rtx_addr_can_trap_p_1): Fix head comment. + : Return 1 for invalid offsets from the frame pointer. + +2014-03-24 Richard Biener + + PR tree-optimization/60429 + * tree-ssa-structalias.c (get_constraint_for_ptr_offset): Remove + duplicated line. + +2014-03-23 Eric Botcazou + + PR rtl-optimization/60601 + * bb-reorder.c (fix_up_fall_thru_edges): Test EDGE_FALLTHRU everywhere. + + * gcc.c (eval_spec_function): Initialize save_growing_value. + +2014-03-20 Jakub Jelinek + + PR target/60568 + * config/i386/i386.c (x86_output_mi_thunk): Surround UNSPEC_GOT + into CONST, put pic register as first operand of PLUS. Use + gen_const_mem for both 32-bit and 64-bit PIC got loads. + +2014-03-20 Eric Botcazou + + * config/sparc/sparc.c (sparc_do_work_around_errata): Implement work + around for store forwarding issue in the FPU on the UT699. + * config/sparc/sparc.md (in_branch_delay): Return false for single FP + loads and operations if -mfix-ut699 is specified. + (divtf3_hq): Tweak attribute. + (sqrttf2_hq): Likewise. + +2014-03-18 Kai Tietz + + PR rtl-optimization/56356 + * sdbout.c (sdbout_parms): Verify that parms' + incoming argument is valid. + (sdbout_reg_parms): Likewise. + +2014-03-18 Eric Botcazou + + * config/sparc/sparc.c (sparc_do_work_around_errata): Speed up and use + proper constant for the store mode. + +2014-03-17 Mikael Pettersson + Committed by Bill Schmidt + + Backport from mainline: + + 2013-06-20 Joern Rennecke + + PR rtl-optimization/57425 + PR rtl-optimization/57569 + * alias.c (write_dependence_p): Remove parameters mem_mode and + canon_mem_addr. Add parameters x_mode, x_addr and x_canonicalized. + Changed all callers. + (canon_anti_dependence): Get comments and semantics in sync. + Add parameter mem_canonicalized. Changed all callers. + * rtl.h (canon_anti_dependence): Update prototype. + + 2013-06-16 Joern Rennecke + + PR rtl-optimization/57425 + PR rtl-optimization/57569 + * alias.c (write_dependence_p): Add new parameters mem_mode, + canon_mem_addr and mem_canonicalized. Change type of writep to bool. + Changed all callers. + (canon_anti_dependence): New function. + * cse.c (check_dependence): Use canon_anti_dependence. + * cselib.c (cselib_invalidate_mem): Likewise. + * rtl.h (canon_anti_dependence): Declare. + +2014-03-17 Richard Biener + + Backport from mainline + 2014-03-11 Richard Biener + + PR tree-optimization/60429 + PR tree-optimization/60485 + * tree-ssa-structalias.c (set_union_with_increment): Properly + take into account all fields that overlap the shifted vars. + (do_sd_constraint): Likewise. + (do_ds_constraint): Likewise. + (get_constraint_for_ptr_offset): Likewise. + +2014-03-15 Eric Botcazou + + * config/sparc/sparc-protos.h (tls_call_delay): Delete. + (eligible_for_call_delay): New prototype. + * config/sparc/sparc.c (tls_call_delay): Rename into... + (eligible_for_call_delay): ...this. Return false if the instruction + cannot be put in the delay slot of a branch. + (eligible_for_restore_insn): Simplify. + (eligible_for_return_delay): Return false if the instruction cannot be + put in the delay slot of a branch and simplify. + (eligible_for_sibcall_delay): Return false if the instruction cannot be + put in the delay slot of a branch. + * config/sparc/sparc.md (fix_ut699): New attribute. + (tls_call_delay): Delete. + (in_call_delay): Reimplement. + (eligible_for_sibcall_delay): Rename into... + (in_sibcall_delay): ...this. + (eligible_for_return_delay): Rename into... + (in_return_delay): ...this. + (in_branch_delay): Reimplement. + (in_uncond_branch_delay): Delete. + (in_annul_branch_delay): Delete. + +2014-03-14 Georg-Johann Lay + + Backport from 2014-03-14 trunk r208562. + + PR target/59396 + * config/avr/avr.c (avr_set_current_function): Pass function name + through default_strip_name_encoding before sanity checking instead + of skipping the first char of the assembler name. + +2014-03-13 Georg-Johann Lay + + Backport from 2014-03-13 trunk r208532. + + PR target/60486 + * config/avr/avr.c (avr_out_plus): Swap cc_plus and cc_minus in + calls of avr_out_plus_1. + +2014-03-13 Joey Ye + + Backport from mainline + 2014-03-12 Thomas Preud'homme + + PR tree-optimization/60454 + * tree-ssa-math-opts.c (find_bswap_1): Fix bswap detection. + +2014-03-06 Matthias Klose + + * Makefile.in (s-mlib): Only pass MULTIARCH_DIRNAME if + MULTILIB_OSDIRNAMES is not defined. + +2014-03-06 Jakub Jelinek + + PR tree-optimization/60276 + * tree-vect-data-refs.c (vect_analyze_data_ref_dependence): Avoid + a -Wsign-compare warning. + + * Makefile.in (tree-ssa-uninit.o): Depend on $(PARAMS_H). + + Backport from mainline + 2014-02-21 Jakub Jelinek + + PR tree-optimization/56490 + * params.def (PARAM_UNINIT_CONTROL_DEP_ATTEMPTS): New param. + * tree-ssa-uninit.c: Include params.h. + (compute_control_dep_chain): Add num_calls argument, return false + if it exceed PARAM_UNINIT_CONTROL_DEP_ATTEMPTS param, pass + num_calls to recursive call. + (find_predicates): Change dep_chain into normal array, add num_calls + variable and adjust compute_control_dep_chain caller. + (find_def_preds): Likewise. + + 2014-02-13 Jakub Jelinek + + PR target/43546 + * expr.c (compress_float_constant): If x is a hard register, + extend into a pseudo and then move to x. + + 2014-02-11 Richard Henderson + Jakub Jelinek + + PR debug/59776 + * tree-sra.c (load_assign_lhs_subreplacements): Add VIEW_CONVERT_EXPR + around drhs if type conversion to lacc->type is not useless. + + 2014-02-08 Jakub Jelinek + + PR ipa/60026 + * ipa-cp.c (determine_versionability): Fail at -O0 + or __attribute__((optimize (0))) or -fno-ipa-cp functions. + * tree-sra.c (ipa_sra_preliminary_function_checks): Similarly. + + 2014-02-06 Jakub Jelinek + + PR target/60062 + * tree.h (opts_for_fn): New inline function. + (opt_for_fn): Define. + * config/i386/i386.c (ix86_function_regparm): Use + opt_for_fn (decl, optimize) instead of optimize. + + 2014-02-05 Jakub Jelinek + + PR middle-end/57499 + * tree-eh.c (cleanup_empty_eh): Bail out on totally empty + bb with no successors. + +2014-03-04 Richard Biener + + PR tree-optimization/60382 + * tree-vect-loop.c (vect_is_simple_reduction_1): Do not consider + dead PHIs a reduction. + +2014-02-25 Richard Biener + + Backport from mainline + 2014-02-21 Richard Biener + + PR tree-optimization/60276 + * tree-vectorizer.h (struct _stmt_vec_info): Add min_neg_dist field. + (STMT_VINFO_MIN_NEG_DIST): New macro. + * tree-vect-data-refs.c (vect_analyze_data_ref_dependence): Record + STMT_VINFO_MIN_NEG_DIST. + * tree-vect-stmts.c (vectorizable_load): Verify if assumptions + made for negative dependence distances still hold. + +2014-02-25 Richard Biener + + Backport from mainline + 2014-02-21 Richard Biener + + PR middle-end/60291 + * tree-ssa-live.c (mark_all_vars_used_1): Do not walk + DECL_INITIAL for globals not in the current function context. + + 2014-02-20 Richard Biener + + PR middle-end/60221 + * tree-eh.c (execute_cleanup_eh_1): Also cleanup empty EH + regions at -O0. + + 2014-02-14 Richard Biener + + PR tree-optimization/60183 + * tree-ssa-phiprop.c (propagate_with_phi): Avoid speculating + loads. + (tree_ssa_phiprop): Calculate and free post-dominators. + +2014-02-25 Kyrylo Tkachov + + PR target/55426 + * config/arm/arm.h (CANNOT_CHANGE_MODE_CLASS): Allow 128 to 64-bit + conversions. + +2014-02-24 John David Anglin + + * config/pa/pa.c (pa_output_move_double): Don't valididate when + adjusting offsetable addresses. + +2014-02-23 David Holsgrove + + * config/microblaze/microblaze.md: Correct ashrsi_reg / lshrsi_reg names + +2014-02-23 Edgar E. Iglesias + + * config/microblaze/microblaze.h: Remove SECONDARY_MEMORY_NEEDED + definition. + +2014-02-23 David Holsgrove + + * /config/microblaze/microblaze.c: Add microblaze_asm_output_mi_thunk + and define TARGET_ASM_OUTPUT_MI_THUNK and + TARGET_ASM_CAN_OUTPUT_MI_THUNK. + +2014-02-23 David Holsgrove + + * config/microblaze/predicates.md: Add cmp_op predicate. + * config/microblaze/microblaze.md: Add branch_compare instruction + which uses cmp_op predicate and emits cmp insn before branch. + * config/microblaze/microblaze.c (microblaze_emit_compare): Rename + to microblaze_expand_conditional_branch and consolidate logic. + (microblaze_expand_conditional_branch): emit branch_compare + insn instead of handling cmp op separate from branch insn. + +2014-02-21 Martin Jambor + + PR ipa/55260 + * ipa-cp.c (cgraph_edge_brings_all_agg_vals_for_node): Uce correct + info when checking whether lattices are bottom. + +2014-02-21 Jakub Jelinek + + * config/i386/i386.c (ix86_expand_vec_perm): Use V8SImode + mode for mask of V8SFmode permutation. + +2014-02-20 Richard Henderson + + PR c++/60272 + * builtins.c (expand_builtin_atomic_compare_exchange): Conditionalize + on failure the store back into EXPECT. Always make a new pseudo for + OLDVAL. + +2014-02-20 Jakub Jelinek + + PR target/57896 + * config/i386/i386.c (expand_vec_perm_interleave2): Don't call + gen_reg_rtx if d->testing_p. + (expand_vec_perm_pshufb2, expand_vec_perm_even_odd_1, + expand_vec_perm_broadcast_1): Return early if d->testing_p and + we will certainly return true. + +2014-02-20 Richard Biener + + * tree-cfg.c (replace_uses_by): Mark altered BBs before + doing the substitution. + +2014-02-19 H.J. Lu + + Backport from mainline + 2014-02-19 H.J. Lu + + PR target/60207 + * config/i386/i386.c (construct_container): Remove TFmode check + for X86_64_INTEGER_CLASS. + +2014-02-19 Uros Bizjak + + Backport from mainline + 2014-02-19 Uros Bizjak + + PR target/59794 + * config/i386/i386.c (type_natural_mode): Warn for ABI changes + only when -Wpsabi is enabled. + +2014-02-19 Terry Guo + + Backport from mainline + 2014-02-08 Terry Guo + + * doc/invoke.texi: Document ARM -march=armv7e-m. + +2014-02-18 Kai Tietz + + Backport from mainline + 2014-02-18 Kai Tietz + + PR target/60193 + * config/i386/i386.c (ix86_expand_prologue): Use + rax register as displacement for restoring %r10, %rax. + Additional fix wrong offset for restoring both-registers. + +2014-02-18 Eric Botcazou + + * ipa-prop.c (compute_complex_ancestor_jump_func): Replace overzealous + assertion with conditional return. + +2014-02-18 Jakub Jelinek + Uros Bizjak + + PR driver/60233 + * config/i386/driver-i386.c (host_detect_local_cpu): If + YMM state is not saved by the OS, also clear has_f16c. Move + CPUID 0x80000001 handling before YMM state saving checking. + +2014-02-14 Roland McGrath + + * configure.ac (HAVE_AS_IX86_UD2): New test for 'ud2' mnemonic. + * configure: Regenerated. + * config.in: Regenerated. + * config/i386/i386.md (trap) [HAVE_AS_IX86_UD2]: Use the mnemonic + instead of ASM_SHORT. + +2014-02-13 Uros Bizjak + + Backport from mainline + 2014-02-13 Uros Bizjak + + * config/i386/sse.md (xop_vmfrcz2): Generate const0 in + operands[2], not operands[3]. + +2014-02-13 Dominik Vogt + + * config/s390/s390.c (s390_asm_output_function_label): Fix crash + caused by bad second argument to warning_at() with -mhotpatch and + nested functions (e.g. with gfortran). + +2014-02-12 H.J. Lu + + Backport from mainline + 2014-02-12 H.J. Lu + Uros Bizjak + + PR target/60151 + * configure.ac (HAVE_AS_GOTOFF_IN_DATA): Pass --32 to GNU assembler. + +2014-02-12 Eric Botcazou + + PR rtl-optimization/60116 + * combine.c (try_combine): Also remove dangling REG_DEAD notes on the + other_insn once the combination has been validated. + +2014-02-10 Nagaraju Mekala + + * config/microblaze/microblaze.md: Add movsi4_rev insn pattern. + * config/microblaze/predicates.md: Add reg_or_mem_operand predicate. + +2014-02-10 Nagaraju Mekala + + * config/microblaze/microblaze.c: Extend mcpu version format + +2014-02-10 David Holsgrove + + * config/microblaze/microblaze.h: Define SIZE_TYPE and PTRDIFF_TYPE. + +2014-02-10 Richard Biener + + Backport from mainline + 2014-01-30 Richard Biener + + PR tree-optimization/59903 + * tree-vect-loop.c (vect_transform_loop): Guard multiple-types + check properly. + + 2014-02-10 Richard Biener + + PR tree-optimization/60115 + * tree-eh.c (tree_could_trap_p): Unify TARGET_MEM_REF and + MEM_REF handling. Properly verify that the accesses are not + out of the objects bound. + +2014-02-05 James Greenhalgh + + Backport from mainline. + 2014-02-05 James Greenhalgh + + PR target/59718 + * doc/invoke.texi (-march): Clarify documentation for ARM. + (-mtune): Likewise. + (-mcpu): Likewise. + +2014-02-04 John David Anglin + + PR target/59777 + * config/pa/pa.c (legitimize_tls_address): Return original address + if not passed a SYMBOL_REF rtx. + (hppa_legitimize_address): Call legitimize_tls_address for all TLS + addresses. + (pa_emit_move_sequence): Simplify TLS source operands. + (pa_legitimate_constant_p): Reject all TLS constants. + * config/pa/pa.h (PA_SYMBOL_REF_TLS_P): Correct comment. + (CONSTANT_ADDRESS_P): Reject TLS CONST addresses. + +2014-02-04 Uros Bizjak + + Backport from mainline + 2014-02-02 Uros Bizjak + + PR target/60017 + * config/i386/i386.c (classify_argument): Fix handling of bit_offset + when calculating size of integer atomic types. + +2014-02-02 Uros Bizjak + + Backport from mainline + 2014-01-30 Jakub Jelinek + + * config/i386/f16cintrin.h (_cvtsh_ss): Avoid -Wnarrowing warning. + +2014-01-31 Richard Henderson + + PR middle-end/60004 + * tree-eh.c (lower_try_finally_switch): Delay lowering finally block + until after else_eh is processed. + +2014-01-30 David Holsgrove + + Backport from mainline + * config/microblaze/microblaze.md(cstoresf4, cbranchsf4): Replace + comparison_operator with ordered_comparison_operator. + +2014-01-25 Walter Lee + + Backport from mainline + 2014-01-25 Walter Lee + + * config/tilegx/sync.md (atomic_fetch_sub): Fix negation and + avoid clobbering a live register. + +2014-01-25 Walter Lee + + Backport from mainline + 2014-01-25 Walter Lee + + * config/tilegx/tilegx-c.c (tilegx_cpu_cpp_builtins): + Define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_{1,2}. + * config/tilegx/tilepro-c.c (tilepro_cpu_cpp_builtins): + Define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_{1,2,4,8}. + +2014-01-25 Walter Lee + + Backport from mainline + 2014-01-25 Walter Lee + + * config/tilegx/tilegx.c (tilegx_gen_bundles): Delete barrier + insns before bundling. + * config/tilegx/tilegx.md (tile_network_barrier): Update comment. + +2014-01-25 Walter Lee + + Backport from mainline + 2014-01-25 Walter Lee + + * config/tilegx/tilegx.c (tilegx_expand_builtin): Set + PREFETCH_SCHEDULE_BARRIER_P to true for prefetches. + * config/tilepro/tilepro.c (tilepro_expand_builtin): Ditto. + +2014-01-25 Walter Lee + + Backport from mainline + 2014-01-25 Walter Lee + + * config/tilepro/tilepro.md (ctzdi2): Use register_operand + predicate. + (clzdi2): Ditto. + (ffsdi2): Ditto. + +2014-01-25 Walter Lee + + Backport from mainline + 2014-01-25 Walter Lee + + * config/tilegx/tilegx.c (tilegx_expand_to_rtl_hook): New. + (TARGET_EXPAND_TO_RTL_HOOK): Define. + +2014-01-24 H.J. Lu + + Backport from mainline + 2014-01-23 H.J. Lu + + PR target/59929 + * config/i386/i386.md (pushsf splitter): Get stack adjustment + from push operand if code of push isn't PRE_DEC. + +2014-01-23 David Holsgrove + + Backport from mainline. + * config/microblaze/microblaze.md: Add trap insn and attribute + +2014-01-23 Marek Polacek + + Backport from mainline + 2013-10-21 Marek Polacek + + PR middle-end/58809 + * fold-const.c (fold_range_test): Return 0 if the type is not + an integral type. + +2014-01-22 David Holsgrove + + * config/microblaze/microblaze.md: Correct bswaphi2 insn. + +2014-01-22 Uros Bizjak + + Backport from mainline + 2014-01-20 Uros Bizjak + + * config/i386/i386.c (ix86_avoid_lea_for_addr): Return false + for SImode_address_operand operands, having only a REG argument. + + 2014-01-20 Jakub Jelinek + + PR target/59880 + * config/i386/i386.c (ix86_avoid_lea_for_addr): Return false + if operands[1] is a REG or ZERO_EXTEND of a REG. + + 2014-01-18 Uros Bizjak + H.J. Lu + + PR target/59379 + * config/i386/i386.md (*lea): Zero-extend return register + to DImode for zero-extended addresses. + +2014-01-21 Andrew Pinski + Steve Ellcey + + PR target/59462 + * config/mips/mips.c (mips_print_operand): Check operand mode instead + of operator mode. + +2014-01-21 Andrey Belevantsev + + Backport from mainline + 2013-12-23 Andrey Belevantsev + + PR rtl-optimization/57422 + * sel-sched.c (mark_unavailable_hard_regs): Fix typo when calling + add_to_hard_reg_set. + +2014-01-20 Jakub Jelinek + + PR middle-end/59860 + * tree.h (fold_builtin_strcat): New prototype. + * builtins.c (fold_builtin_strcat): No longer static. Add len + argument, if non-NULL, don't call c_strlen. Optimize + directly into __builtin_memcpy instead of __builtin_strcpy. + (fold_builtin_2): Adjust fold_builtin_strcat caller. + * gimple-fold.c (gimple_fold_builtin): Handle BUILT_IN_STRCAT. + +2014-01-20 Richard Biener + + PR middle-end/59860 + * builtins.c (fold_builtin_strcat): Remove case better handled + by tree-ssa-strlen.c. + +2014-01-19 John David Anglin + + * config/pa/pa.c (pa_attr_length_millicode_call): Correct length of + long non-pic millicode calls. + +2014-01-17 John David Anglin + + * config/pa/pa.c (pa_attr_length_indirect_call): Don't output a short + call to $$dyncall when TARGET_LONG_CALLS is true. + +2014-01-17 H.J. Lu + + Backport from mainline + 2014-01-14 H.J. Lu + + PR target/59794 + * config/i386/i386.c (type_natural_mode): Add a bool parameter + to indicate if type is used for function return value. Warn + ABI change if the vector mode isn't available for function + return value. + (ix86_function_arg_advance): Pass false to type_natural_mode. + (ix86_function_arg): Likewise. + (ix86_gimplify_va_arg): Likewise. + (function_arg_32): Don't warn ABI change. + (ix86_function_value): Pass true to type_natural_mode. + (ix86_return_in_memory): Likewise. + (ix86_struct_value_rtx): Removed. + (TARGET_STRUCT_VALUE_RTX): Likewise. + +2014-01-17 Charles Baylis + + Backport from mainline + 2013-12-19 Charles Baylis + + PR target/59142 + * config/arm/arm-ldmstm.ml: Use low_register_operand for Thumb + patterns. + * config/arm/ldmstm.md: Regenerate. + + 2013-12-19 Charles Baylis + + PR target/59142 + * config/arm/predicates.md (arm_hard_general_register_operand): + New predicate. + (arm_hard_register_operand): Remove. + * config/arm/arm-ldmstm.ml: Use arm_hard_general_register_operand + for all patterns. + * config/arm/ldmstm.md: Regenerate. + + 2013-12-19 Charles Baylis + + PR target/59142 + * config/arm/predicates.md (vfp_hard_register_operand): New predicate. + * config/arm/arm.md (vfp_pop_multiple_with_writeback): Use + vfp_hard_register_operand. + +2014-01-17 Kugan Vivekanandarajah + + Backport from mainline + 2014-01-15 Matthew Gretton-Dann + Kugan Vivekanandarajah + + PR target/59695 + * config/aarch64/aarch64.c (aarch64_build_constant): Fix incorrect + truncation. + +2014-01-17 Terry Guo + + PR target/59826 + * config/arm/arm.md (prefetch): Set insn type attribute to load1. + +2014-01-16 Jakub Jelinek + + PR target/59839 + * config/i386/i386.c (ix86_expand_builtin): If target doesn't + satisfy operand 0 predicate for gathers, use a new pseudo as + subtarget. + +2014-01-16 Richard Henderson + + PR debug/54694 + * reginfo.c (global_regs_decl): Globalize. + * rtl.h (global_regs_decl): Declare. + * ira.c (do_reload): Diagnose frame_pointer_needed and it + reserved via global_regs. + +2014-01-16 Peter Bergner + + Backport from mainline + 2014-01-15 Uros Bizjak + + * config/i386/i386.c (ix86_hard_regno_mode_ok): Use + VALID_AVX256_REG_OR_OI_MODE. + + 2013-09-05 Peter Bergner + + PR target/58139 + * reginfo.c (choose_hard_reg_mode): Scan through all mode classes + looking for widest mode. + +2014-01-16 Marek Polacek + + Backported from mainline + 2014-01-16 Marek Polacek + + PR middle-end/59827 + * gimple-low.c (gimple_check_call_args): Don't use DECL_ARG_TYPE if + it is error_mark_node. + +2014-01-15 Andreas Krebbel + + PR target/59803 + * config/s390/s390.c (s390_preferred_reload_class): Don't return + ADDR_REGS for invalid symrefs in non-PIC code. + +2014-01-14 Uros Bizjak + + Revert: + 2014-01-08 Uros Bizjak + + * config/i386/i386.c (ix86_data_alignment): Calculate max_align + from prefetch_block tune setting. + +2014-01-13 Jakub Jelinek + + Backported from mainline + 2014-01-10 Jakub Jelinek + + PR tree-optimization/59745 + * tree-predcom.c (tree_predictive_commoning_loop): Call + free_affine_expand_cache if giving up because components is NULL. + +2014-01-10 Yufeng Zhang + + * config/arm/arm.c (arm_expand_neon_args): Call expand_expr + with EXPAND_MEMORY for NEON_ARG_MEMORY; check if the returned + rtx is const0_rtx or not. + +2014-01-10 Andreas Krebbel + + * config/s390/s390.c (s390_expand_tbegin): Remove jump over CC + extraction in good case. + +2014-01-10 Huacai Chen + + * config/mips/driver-native.c (host_detect_local_cpu): Handle new + kernel strings for Loongson-2E/2F/3A. + +2014-01-10 Richard Biener + + PR tree-optimization/59715 + * tree-flow.h (split_critical_edges): Declare. + * tree-cfg.c (split_critical_edges): Export. + * tree-ssa-sink.c (execute_sink_code): Split critical edges. + +2014-01-09 Richard Sandiford + + * config/mips/mips.h (ISA_HAS_WSBH): Define. + * config/mips/mips.md (UNSPEC_WSBH, UNSPEC_DSBH, UNSPEC_DSHD): New + constants. + (bswaphi2, bswapsi2, bswapdi2, wsbh, dsbh, dshd): New patterns. + +2014-01-09 Richard Sandiford + + PR rtl-optimization/59137 + * reorg.c (steal_delay_list_from_target): Call update_block for + elided insns. + (steal_delay_list_from_fallthrough, relax_delay_slots): Likewise. + +2014-01-09 Richard Sandiford + + Revert: + 2012-10-07 Richard Sandiford + + * config/mips/mips.c (mips_truncated_op_cost): New function. + (mips_rtx_costs): Adjust test for BADDU. + * config/mips/mips.md (*baddu_di): Push truncates to operands. + + 2012-10-02 Richard Sandiford + + * config/mips/mips.md (*baddu_si_eb, *baddu_si_el): Merge into... + (*baddu_si): ...this new pattern. + +2014-01-09 Richard Biener + + Backport from mainline + 2013-11-18 Richard Biener + + PR tree-optimization/59125 + PR tree-optimization/54570 + * tree-ssa-sccvn.c (copy_reference_ops_from_ref): When inlining + is not complete do not treat component-references with offset zero + but different fields as equal. + * tree-object-size.c: Include tree-phinodes.h and ssa-iterators.h. + (compute_object_sizes): Apply TLC. Propagate the constant + results into all uses and fold their stmts. + * passes.def (pass_all_optimizations): Move pass_object_sizes + after the first pass_forwprop and before pass_fre. + + 2013-12-03 Jakub Jelinek + + PR tree-optimization/59362 + * tree-object-size.c (object_sizes): Change into array of + vec. + (compute_builtin_object_size): Check computed bitmap for + non-NULL instead of object_sizes. Call safe_grow on object_sizes + vector if new SSA_NAMEs appeared. + (init_object_sizes): Check computed bitmap for non-NULL. + Call safe_grow on object_sizes elements instead of initializing + it with XNEWVEC. + (fini_object_sizes): Call release on object_sizes elements, don't + set it to NULL. + +2014-01-09 Richard Earnshaw + + PR rtl-optimization/54300 + * regcprop.c (copyprop_hardreg_forward_1): Ensure any unused + outputs in a single-set are killed from the value chains. + +2014-01-09 Jakub Jelinek + + PR rtl-optimization/59724 + * ifcvt.c (cond_exec_process_if_block): Don't call + flow_find_head_matching_sequence with 0 longest_match. + * cfgcleanup.c (flow_find_head_matching_sequence): Count even + non-active insns if !stop_after. + (try_head_merge_bb): Revert 2014-01-07 changes. + +2014-01-09 Hans-Peter Nilsson + + Backport from mainline + 2013-12-23 Hans-Peter Nilsson + + PR middle-end/59584 + * config/cris/predicates.md (cris_nonsp_register_operand): + New define_predicate. + * config/cris/cris.md: Replace register_operand with + cris_nonsp_register_operand for destinations in all + define_splits where a register is set more than once. + +2014-01-08 H.J. Lu + + Backport from mainline + 2013-12-25 H.J. Lu + + PR target/59587 + * config/i386/i386.c (struct ptt): Add a field for processor name. + (processor_target_table): Sync with processor_type. Add + processor names. + (cpu_names): Removed. + (ix86_option_override_internal): Default x_ix86_tune_string + to processor_target_table[TARGET_CPU_DEFAULT].name. + (ix86_function_specific_print): Assert arch and tune < + PROCESSOR_max. Use processor_target_table to print arch and + tune names. + * config/i386/i386.h (TARGET_CPU_DEFAULT): Default to + PROCESSOR_GENERIC32. + (target_cpu_default): Removed. + (processor_type): Reordered. + +2014-01-08 Uros Bizjak + + Backport from mainline + 2014-01-05 Uros Bizjak + + * config/i386/i386.c (ix86_data_alignment): Calculate max_align + from prefetch_block tune setting. + (nocona_cost): Correct size of prefetch block to 64. + +2014-01-08 Martin Jambor + + PR ipa/59610 + * ipa-prop.c (ipa_compute_jump_functions): Bail out if not optimizing. + (parm_preserved_before_stmt_p): Assume modification present when not + optimizing. + +2014-01-07 John David Anglin + + PR target/59652 + * config/pa/pa.c (pa_legitimate_address_p): Return false before reload + for 14-bit register offsets when INT14_OK_STRICT is false. + +2014-01-07 Roland Stigge + Michael Meissner + + PR 57386/target + * config/rs6000/rs6000.c (rs6000_legitimate_offset_address_p): + Only check TFmode for SPE constants. Don't check TImode or TDmode. + +2014-01-07 Jakub Jelinek + + PR rtl-optimization/58668 + * cfgcleanup.c (flow_find_cross_jump): Don't count + any jumps if dir_p is NULL. Remove p1 variable and make USE/CLOBBER + check consistent with other places. + (flow_find_head_matching_sequence): Don't count USE or CLOBBER insns. + (try_head_merge_bb): Adjust for the flow_find_head_matching_sequence + counting change. + * ifcvt.c (count_bb_insns): Don't count USE or CLOBBER insns. + +2014-01-07 Mike Stump + Jakub Jelinek + + PR pch/59436 + * tree.h (struct tree_optimization_option): Change optabs + type from unsigned char * to void *. + * optabs.c (init_tree_optimization_optabs): Adjust + TREE_OPTIMIZATION_OPTABS initialization. + +2014-01-07 Jakub Jelinek + + Backported from mainline + 2013-12-16 Jakub Jelinek + + PR middle-end/58956 + PR middle-end/59470 + * gimple.h (walk_stmt_load_store_addr_fn): New typedef. + (walk_stmt_load_store_addr_ops, walk_stmt_load_store_ops): Use it + for callback params. + * gimple.c (walk_stmt_load_store_ops): Likewise. + (walk_stmt_load_store_addr_ops): Likewise. Adjust all callback + calls to supply the gimple operand containing the base tree + as an extra argument. + * tree-ssa-ter.c (find_ssaname, find_ssaname_in_store): New helper + functions. + (find_replaceable_in_bb): For calls or GIMPLE_ASM, only set + same_root_var if USE is used somewhere in the stores of the stmt. + * ipa-prop.c (visit_ref_for_mod_analysis): Remove name of the stmt + argument and ATTRIBUTE_UNUSED, add another unnamed tree argument. + * ipa-pure-const.c (check_load, check_store, check_ipa_load, + check_ipa_store): Likewise. + * gimple.c (gimple_ior_addresses_taken_1): Likewise. + * ipa-split.c (test_nonssa_use, mark_nonssa_use): Likewise. + (verify_non_ssa_vars, visit_bb): Adjust their callers. + * cfgexpand.c (add_scope_conflicts_1): Use + walk_stmt_load_store_addr_fn type for visit variable. + (visit_op, visit_conflict): Remove name of the stmt + argument and ATTRIBUTE_UNUSED, add another unnamed tree argument. + * tree-sra.c (asm_visit_addr): Likewise. Remove name of the data + argument and ATTRIBUTE_UNUSED. + * cgraphbuild.c (mark_address, mark_load, mark_store): Add another + unnamed tree argument. + +2014-01-03 Andreas Schwab + + * config/m68k/m68k.c (handle_move_double): Handle pushes with + overlapping registers also for registers other than the stack + pointer. + +2014-01-03 Jakub Jelinek + + PR target/59625 + * config/i386/i386.c (ix86_avoid_jump_mispredicts): Don't consider + asm goto as jump. + +2014-01-01 Jakub Jelinek + + PR rtl-optimization/59647 + * cse.c (cse_process_notes_1): Don't substitute negative VOIDmode + new_rtx into UNSIGNED_FLOAT rtxes. + +2013-12-28 Eric Botcazou + + * doc/invoke.texi (output file options): Document -fada-spec-parent. + +2013-12-26 Uros Bizjak + + * config/i386/driver-i386.c (decode_caches_intel): Add missing entries. + +2013-12-20 Jakub Jelinek + + PR c++/59255 + Backported from mainline + 2013-08-19 Dehao Chen + + * value-prof.c (gimple_ic): Fix the bug of adding EH edge. + +2013-12-19 James Greenhalgh + + Backport from Mainline. + 2013-05-01 James Greenhalgh + + * config/aarch64/aarch64-simd-builtins.def (cmhs): Rename to... + (cmgeu): ...This. + (cmhi): Rename to... + (cmgtu): ...This. + * config/aarch64/aarch64-simd.md + (simd_mode): Add SF. + (aarch64_vcond_internal): Use new names for unsigned comparison insns. + (aarch64_cm): Rewrite to not use UNSPECs. + * config/aarch64/aarch64.md (*cstore_neg): Rename to... + (cstore_neg): ...This. + * config/aarch64/iterators.md + (VALLF): new. + (unspec): Remove UNSPEC_CM. + (COMPARISONS): New. + (UCOMPARISONS): Likewise. + (optab): Add missing comparisons. + (n_optab): New. + (cmp_1): Likewise. + (cmp_2): Likewise. + (CMP): Likewise. + (cmp): Remove. + (VCMP_S): Likewise. + (VCMP_U): Likewise. + (V_cmp_result): Add DF, SF modes. + (v_cmp_result): Likewise. + (v): Likewise. + (vmtype): Likewise. + * config/aarch64/predicates.md (aarch64_reg_or_fp_zero): New. + + Partial Backport from mainline. + 2013-05-01 James Greenhalgh + + * config/aarch64/arm_neon.h + (vc_<8,16,32,64>): Remap + to builtins or C as appropriate. + +2013-12-19 Dominik Vogt + Andreas Krebbel + + Backport from mainline + 2013-12-19 Dominik Vogt + * config/s390/s390.c (s390_hotpatch_trampoline_halfwords_default): New + constant + (s390_hotpatch_trampoline_halfwords_max): New constant + (s390_hotpatch_trampoline_halfwords): New static variable + (get_hotpatch_attribute): New function + (s390_handle_hotpatch_attribute): New function + (s390_attribute_table): New target specific attribute table to implement + the hotpatch attribute + (s390_option_override): Parse hotpatch options + (s390_function_num_hotpatch_trampoline_halfwords): New function + (s390_can_inline_p): Implement target hook to + suppress hotpatching for explicitly inlined functions + (s390_asm_output_function_label): Generate hotpatch prologue + (TARGET_ATTRIBUTE_TABLE): Define to implement target attribute table + (TARGET_CAN_INLINE_P): Define to implement target hook + * config/s390/s390.opt (mhotpatch): New options -mhotpatch, -mhotpatch= + * config/s390/s390-protos.h (s390_asm_output_function_label): Add + prototype + * config/s390/s390.h (ASM_OUTPUT_FUNCTION_LABEL): Target specific + function label generation for hotpatching + (FUNCTION_BOUNDARY): Align functions to eight bytes + * doc/extend.texi: Document hotpatch attribute + * doc/invoke.texi: Document -mhotpatch option + +2013-12-18 Eric Botcazou + + * config/arm/arm.c (arm_expand_epilogue_apcs_frame): Fix thinko. + +2013-12-12 Vladimir Makarov + + PR middle-end/59470 + * lra-coalesce.c (lra_coalesce): Invalidate inheritance pseudo + values if necessary. + +2013-12-12 Jakub Jelinek + + PR libgomp/59467 + * gimplify.c (omp_check_private): Add copyprivate argument, if it + is true, don't check omp_privatize_by_reference. + (gimplify_scan_omp_clauses): For OMP_CLAUSE_COPYPRIVATE verify + decl is private in outer context. Adjust omp_check_private caller. + +2013-12-10 Eric Botcazou + + PR rtl-optimization/58295 + * simplify-rtx.c (simplify_truncation): Restrict the distribution for + WORD_REGISTER_OPERATIONS targets. + +2013-12-10 Kai Tietz + + PR target/56807 + * config/i386/i386.c (ix86_expand_prologue): Address saved + registers stack-relative, not via frame-pointer. + +2013-12-09 Alan Modra + + Apply from mainline + 2013-12-05 Alan Modra + * configure.ac (BUILD_CXXFLAGS) Don't use ALL_CXXFLAGS for + build != host. + : Clear GMPINC. Don't bother + saving CFLAGS. + * configure: Regenerate. + +2013-12-08 Uros Bizjak + + Backport from mainline + 2013-12-06 Uros Bizjak + + PR target/59405 + * config/i386/i386.c (type_natural_mode): Properly handle + size 8 for !TARGET_64BIT. + +2013-12-07 Ralf Corsépius + + * config.gcc (microblaze*-*-rtems*): Add TARGET_BIG_ENDIAN_DEFAULT. + +2013-12-06 Jakub Jelinek + + PR tree-optimization/59388 + * tree-ssa-reassoc.c (update_range_test): If op == range->exp, + gimplify tem after stmt rather than before it. + +2013-12-06 Oleg Endo + + Backport from mainline + 2013-11-26 Oleg Endo + + PR target/58314 + PR target/50751 + * config/sh/sh.c (max_mov_insn_displacement, disp_addr_displacement): + Prefix function names with 'sh_'. Make them non-static. + * config/sh/sh-protos.h (sh_disp_addr_displacement, + sh_max_mov_insn_displacement): Add declarations. + * config/sh/constraints.md (Q): Reject QImode. + (Sdd): Use match_code "mem". + (Snd): Fix erroneous matching of non-memory operands. + * config/sh/predicates.md (short_displacement_mem_operand): New + predicate. + (general_movsrc_operand): Disallow PC relative QImode loads. + * config/sh/sh.md (*mov_reg_reg): Remove it. + (*movqi, *movhi): Merge both insns into... + (*mov): ... this new insn. Replace generic 'm' constraints with + 'Snd' and 'Sdd' constraints. Calculate insn length dynamically based + on the operand types. + +2013-12-06 Richard Biener + + Backport from mainline + 2013-11-29 Richard Biener + + PR tree-optimization/59334 + * tree-ssa-dce.c (eliminate_unnecessary_stmts): Fix bug + in previous commit. + + 2013-11-28 Richard Biener + + PR tree-optimization/59330 + * tree-ssa-dce.c (eliminate_unnecessary_stmts): Simplify + and fix delayed marking of free calls not necessary. + +2013-12-06 Richard Biener + + Backport from mainline + 2013-11-27 Richard Biener + + PR tree-optimization/59288 + * tree-vect-loop.c (get_initial_def_for_induction): Do not + re-analyze the PHI but use STMT_VINFO_LOOP_PHI_EVOLUTION_PART. + + 2013-11-19 Richard Biener + + PR tree-optimization/59164 + * tree-vect-loop.c (vect_analyze_loop_operations): Adjust + check whether we can create an epilogue loop to reflect the + cases where we create one. + + 2013-09-05 Richard Biener + + PR tree-optimization/58137 + * tree-vect-stmts.c (get_vectype_for_scalar_type_and_size): + Do not create vectors of pointers. + * tree-vect-loop.c (get_initial_def_for_induction): Use proper + types for the components of the vector initializer. + * tree-cfg.c (verify_gimple_assign_binary): Remove special-casing + allowing pointer vectors with PLUS_EXPR/MINUS_EXPR. + +2013-12-06 Oleg Endo + + PR target/51244 + PR target/59343 + * config/sh/sh.md (*cbranch_t): Check that there are no labels between + the s1 insn and the testing insn. Remove REG_DEAD note from s1 insn. + +2013-12-05 Richard Biener + + Backport from mainline + 2013-11-19 Richard Biener + + PR middle-end/58956 + * tree-ssa-ter.c (find_replaceable_in_bb): Avoid forwarding + loads into stmts that may clobber it. + +2013-12-04 Jakub Jelinek + + PR rtl-optimization/58726 + * combine.c (force_to_mode): Fix comment typo. Don't destructively + modify x for ROTATE, ROTATERT and IF_THEN_ELSE. + +2013-12-04 Jakub Jelinek + Uros Bizjak + + PR target/59163 + * config/i386/i386.c (ix86_legitimate_combined_insn): If for + !TARGET_AVX there is misaligned MEM operand with vector mode + and get_attr_ssememalign is 0, return false. + (ix86_expand_special_args_builtin): Add get_pointer_alignment + computed alignment and for non-temporal loads/stores also + at least GET_MODE_ALIGNMENT as MEM_ALIGN. + * config/i386/sse.md + (_loadu, + _storeu, + _loaddqu, + _storedqu, _lddqu, + sse_vmrcpv4sf2, sse_vmrsqrtv4sf2, sse2_cvtdq2pd, sse_movhlps, + sse_movlhps, sse_storehps, sse_loadhps, sse_loadlps, + *vec_interleave_highv2df, *vec_interleave_lowv2df, + *vec_extractv2df_1_sse, sse2_loadhpd, sse2_loadlpd, sse2_movsd, + sse4_1_v8qiv8hi2, sse4_1_v4qiv4si2, + sse4_1_v4hiv4si2, sse4_1_v2qiv2di2, + sse4_1_v2hiv2di2, sse4_1_v2siv2di2, sse4_2_pcmpestr, + *sse4_2_pcmpestr_unaligned, sse4_2_pcmpestri, sse4_2_pcmpestrm, + sse4_2_pcmpestr_cconly, sse4_2_pcmpistr, *sse4_2_pcmpistr_unaligned, + sse4_2_pcmpistri, sse4_2_pcmpistrm, sse4_2_pcmpistr_cconly): Add + ssememalign attribute. + * config/i386/i386.md (ssememalign): New define_attr. + +2013-12-03 Jakub Jelinek + + PR middle-end/59011 + * gimplify.c (nonlocal_vla_vars): New variable. + (gimplify_var_or_parm_decl): Put VAR_DECLs for VLAs into + nonlocal_vla_vars chain. + (gimplify_body): Call declare_vars on nonlocal_vla_vars chain + if outer_bind has DECL_INITIAL (current_function_decl) block. + + PR target/58864 + * optabs.c (emit_conditional_move): Save and restore + pending_stack_adjust and stack_pointer_delta if cmove can't be used. + +2013-12-02 Jakub Jelinek + + PR tree-optimization/59358 + * tree-vrp.c (union_ranges): To check for the partially + overlapping ranges or adjacent ranges, also compare *vr0max + with vr1max. + +2013-12-02 Richard Biener + + PR tree-optimization/59139 + * tree-ssa-loop-niter.c (chain_of_csts_start): Properly match + code in get_val_for. + (get_val_for): Use gcc_checking_asserts. + +2013-11-27 Tom de Vries + Marc Glisse + + PR middle-end/59037 + * fold-const.c (fold_indirect_ref_1): Don't create out-of-bounds + BIT_FIELD_REF. + * gimplify.c (gimple_fold_indirect_ref): Same. + +2013-12-01 Eric Botcazou + + * config/i386/winnt.c (i386_pe_asm_named_section): Be prepared for an + identifier node. + +2013-12-01 Bernd Edlinger + + * expr.c (emit_group_store): Fix off-by-one BITFIELD_END argument. + +2013-11-28 Kyrylo Tkachov + + Backport from mainline + 2013-11-28 Kyrylo Tkachov + + * config/arm/iterators.md (vrint_conds): New int attribute. + * config/arm/vfp.md (2): Set conds attribute. + (smax3): Likewise. + (smin3): Likewise. + +2013-11-28 Uros Bizjak + + Backport from mainline + 2013-11-27 Uros Bizjak + Ganesh Gopalasubramanian + + PR target/56788 + * gcc.target/i386/xop-frczX.c: New test. + +2013-11-28 Terry Guo + + Backport mainline r205391 + 2013-11-26 Terry Guo + + * config/arm/arm.c (require_pic_register): Handle high pic base + register for thumb-1. + (arm_load_pic_register): Also initialize high pic base register. + * doc/invoke.texi: Update documentation for option -mpic-register. + +2013-11-27 Jakub Jelinek + + Backported from mainline + 2013-11-26 Jakub Jelinek + + PR tree-optimization/59014 + * tree-vrp.c (register_edge_assert_for_1): Don't look + through conversions from non-integral types or through + narrowing conversions. + +2013-11-27 Eric Botcazou + + PR middle-end/59138 + * expr.c (emit_group_store): Don't write past the end of the structure. + (store_bit_field): Fix formatting. + +2013-11-24 Sebastian Huber + + Backport from mainline + 2013-09-17 Sebastian Huber + + * config/sparc/t-rtems: Add leon3 multilibs. + +2013-11-24 Sebastian Huber + + Backport from mainline + 2013-08-09 Eric Botcazou + + * configure.ac: Add GAS check for LEON instructions on SPARC. + * configure: Regenerate. + * config.in: Likewise. + * config.gcc (with_cpu): Remove sparc-leon*-* and deal with LEON in the + sparc*-*-* block. + * config/sparc/sparc.opt (LEON, LEON3): New masks. + * config/sparc/sparc.h (ASM_CPU32_DEFAULT_SPEC): Set to AS_LEON_FLAG + for LEON or LEON3. + (ASM_CPU_SPEC): Pass AS_LEON_FLAG if -mcpu=leon or -mcpu=leon3. + (AS_LEON_FLAG): New macro. + * config/sparc/sparc.c (sparc_option_override): Set MASK_LEON for leon + and MASK_LEON3 for leon3 and unset them if HAVE_AS_LEON is not defined. + Deal with LEON and LEON3 for the memory model. + * config/sparc/sync.md (atomic_compare_and_swap): Enable if LEON3 + (atomic_compare_and_swap_1): Likewise. + (*atomic_compare_and_swap_1): Likewise. + +2013-11-24 Sebastian Huber + + Backport from mainline + 2013-07-23 Eric Botcazou + + * doc/invoke.texi (SPARC Options): Document new leon3 processor value. + +2013-11-24 Sebastian Huber + + Backport from mainline + 2013-07-22 Eric Botcazou + + * config.gcc (sparc*-*-*): Accept leon3 processor. + (sparc-leon*-*): Merge with sparc*-*-* and add leon3 support. + * doc/invoke.texi (SPARC Options): Adjust -mfix-ut699 entry. + * config/sparc/sparc-opts.h (enum processor_type): Add PROCESSOR_LEON3. + * config/sparc/sparc.opt (enum processor_type): Add leon3. + (mfix-ut699): Adjust comment. + * config/sparc/sparc.h (TARGET_CPU_leon3): New define. + (CPP_CPU32_DEFAULT_SPEC): Add leon3 support. + (CPP_CPU_SPEC): Likewise. + (ASM_CPU_SPEC): Likewise. + * config/sparc/sparc.c (leon3_cost): New constant. + (sparc_option_override): Add leon3 support. + (mem_ref): New function. + (sparc_gate_work_around_errata): Return true if -mfix-ut699 is enabled. + (sparc_do_work_around_errata): Look into the instruction in the delay + slot and adjust accordingly. Add fix for the data cache nullify issues + of the UT699. Change insertion position for the NOP. + * config/sparc/leon.md (leon_fpalu, leon_fpmds, write_buf): Delete. + (leon3_load): New reservation. + (leon_store): Bump latency to 2. + (grfpu): New automaton. + (grfpu_alu): New unit. + (grfpu_ds): Likewise. + (leon_fp_alu): Adjust. + (leon_fp_mult): Delete. + (leon_fp_div): Split into leon_fp_divs and leon_fp_divd. + (leon_fp_sqrt): Split into leon_fp_sqrts and leon_fp_sqrtd. + * config/sparc/sparc.md (cpu): Add leon3. + * config/sparc/sync.md (atomic_exchangesi): Disable if -mfix-ut699. + (swapsi): Likewise. + (atomic_test_and_set): Likewise. + (ldstub): Likewise. + +2013-11-24 Sebastian Huber + + Backport from mainline + 2013-04-10 Steven Bosscher + + * config/sparc/sparc.c: Include tree-pass.h. + (TARGET_MACHINE_DEPENDENT_REORG): Do not redefine. + (sparc_reorg): Rename to sparc_do_work_around_errata. Move to + head of file. Change return type. Split off gate function. + (sparc_gate_work_around_errata): New function. + (pass_work_around_errata): New pass definition. + (insert_pass_work_around_errata) New pass insert definition to + insert pass_work_around_errata just after delayed-branch scheduling. + (sparc_option_override): Insert the pass. + * config/sparc/t-sparc (sparc.o): Add TREE_PASS_H dependence. + +2013-11-24 Sebastian Huber + + Backport from mainline + 2013-05-28 Eric Botcazou + + * doc/invoke.texi (SPARC Options): Document -mfix-ut699. + * builtins.c (expand_builtin_mathfn) : Try to widen the + mode if the instruction isn't available in the original mode. + * config/sparc/sparc.opt (mfix-ut699): New option. + * config/sparc/sparc.md (muldf3_extend): Disable if -mfix-ut699. + (divdf3): Turn into expander. + (divdf3_nofix): New insn. + (divdf3_fix): Likewise. + (divsf3): Disable if -mfix-ut699. + (sqrtdf2): Turn into expander. + (sqrtdf2_nofix): New insn. + (sqrtdf2_fix): Likewise. + (sqrtsf2): Disable if -mfix-ut699. + +2013-11-22 Eric Botcazou + + * print-rtl.c (print_rtx) : Output a space if no MEM_EXPR. + +2013-11-21 Zhenqiang Chen + + PR bootstrap/57683 + Backport from mainline: r197467 and r198999. + 2013-04-03 Jeff Law + + * Makefile.in (lra-constraints.o): Depend on $(OPTABS_H). + (lra-eliminations.o): Likewise. + + 2013-05-16 Jeff Law + + * Makefile.in (tree-switch-conversion.o): Depend on $(OPTABS_H). + +2013-11-20 Eric Botcazou + + PR target/59207 + * config/sparc/sparc.c (sparc_fold_builtin) : + Make sure neg2_ovf is set before being used. + +2013-11-20 Andreas Krebbel + Dominik Vogt + + Backport from mainline + * config/s390/s390.c (s390_canonicalize_comparison): Don't fold + int comparisons with an out of range condition code. + (s390_optimize_nonescaping_tx): Skip empty BBs. + Generate the new tbegin RTX when removing the FPR clobbers (with + two SETs). + (s390_expand_tbegin): Fix the retry loop counter. Copy CC to the + result before doing the retry calculations. + (s390_init_builtins): Make tbegin "returns_twice" and tabort + "noreturn". + * config/s390/s390.md (UNSPECV_TBEGIN_TDB): New constant used for + the TDB setting part of an tbegin. + ("tbegin_1", "tbegin_nofloat_1"): Add a set for the TDB. + ("tx_assist"): Set unused argument to an immediate zero instead of + loading zero into a GPR and pass it as argument. + * config/s390/htmxlintrin.h (__TM_simple_begin, __TM_begin): + Remove inline and related attributes. + (__TM_nesting_depth, __TM_is_user_abort, __TM_is_named_user_abort) + (__TM_is_illegal, __TM_is_footprint_exceeded) + (__TM_is_nested_too_deep, __TM_is_conflict): Fix format value + check. + +2013-11-19 Uros Bizjak + + Backport from mainline + 2013-11-18 Uros Bizjak + + * config/i386/i386.c (ix86_decompose_address): Use REG_P instead of + ix86_address_subreg_operand. Move subreg checks to + ix86_validate_address_register. Move address override check to + ix86_legitimate_address_p. + (ix86_validate_address_register): New function. + (ix86_legitimate_address_p): Call ix86_validate_address_register + to validate base and index registers. Add address override check + from ix86_decompose_address. + (ix86_decompose_address): Remove. + + Backport from mainline + 2013-11-17 Uros Bizjak + + PR target/59153 + * config/i386/i386.c (ix86_address_subreg_operand): Do not + reject non-integer subregs. + (ix86_decompose_address): Do not reject invalid CONST_INT RTXes. + Move check for invalid x32 constant addresses ... + (ix86_legitimate_address_p): ... here. + +2013-11-19 Richard Biener + + Backport from mainline + 2013-11-07 Richard Biener + + * tree-dfa.c (get_ref_base_and_extent): Fix casting. + +2013-11-19 Richard Biener + + PR tree-optimization/57517 + * tree-predcom.c (combinable_refs_p): Verify the combination + is always executed when the refs are. + +2013-11-19 Richard Biener + + Backport from mainline + 2013-11-05 Richard Biener + + PR middle-end/58941 + * tree-dfa.c (get_ref_base_and_extent): Merge common code + in MEM_REF and TARGET_MEM_REF handling. Make sure to + process trailing array detection before diving into the + view-converted object (and possibly apply some extra offset). + +2013-11-18 Richard Biener + + Backport from mainline + 2013-10-21 Richard Biener + + PR tree-optimization/58794 + * fold-const.c (operand_equal_p): Compare FIELD_DECL operand + of COMPONENT_REFs with OEP_CONSTANT_ADDRESS_OF left in place. + + 2013-10-21 Richard Biener + + PR middle-end/58742 + * fold-const.c (fold_binary_loc): Fold ((T) (X /[ex] C)) * C + to (T) X for sign-changing conversions (or no conversion). + + 2013-11-06 Richard Biener + + PR tree-optimization/58653 + * tree-predcom.c (ref_at_iteration): Rewrite to generate + a MEM_REF. + (prepare_initializers_chain): Adjust. + + PR tree-optimization/59047 + * tree-predcom.c (ref_at_iteration): Handle bitfield accesses + properly. + + 2013-10-15 Richard Biener + + PR tree-optimization/58143 + * tree-ssa-loop-im.c (arith_code_with_undefined_signed_overflow): + New function. + (rewrite_to_defined_overflow): Likewise. + (move_computations_dom_walker::before_dom): Rewrite stmts + with undefined signed overflow that are not always executed + into unsigned arithmetic. + +2013-11-14 Uros Bizjak + + Backport from mainline + 2013-11-10 Uros Bizjak + + * mode-switching.c (optimize_mode_switching): Mark block as + nontransparent, if last_mode at block exit is different from no_mode. + + Backport from mainline + 2013-11-06 Uros Bizjak + + PR target/59021 + * config/i386/i386.c (ix86_avx_u128_mode_needed): Require + AVX_U128_DIRTY mode for call_insn RTXes that use AVX256 registers. + (ix86_avx_u128_mode_needed): Return AVX_U128_DIRTY mode for call_insn + RTXes that return in AVX256 register. + +2013-11-14 Jakub Jelinek + Uros Bizjak + + PR target/59101 + * config/i386/i386.md (*anddi_2): Only allow CCZmode if + operands[2] satisfies_constraint_Z that might have bit 31 set. + +2013-11-12 H.J. Lu + + Backported from mainline + 2013-11-12 H.J. Lu + + PR target/59088 + * config/i386/i386.c (initial_ix86_tune_features): Set + X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL and + X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL for m_HASWELL. + +2013-11-11 Ramana Radhakrishnan + + Backported from mainline + 2013-10-30 Ramana Radhakrishnan + + PR target/58854 + * config/arm/arm.c (arm_expand_epilogue_apcs_frame): Emit blockage + +2013-11-11 Jakub Jelinek + + Backported from mainline + 2013-11-06 Jakub Jelinek + + PR middle-end/58970 + * expr.c (get_bit_range): Handle *offset == NULL_TREE. + (expand_assignment): If *bitpos is negative, set *offset + and adjust *bitpos, so that it is not negative. + + 2013-11-05 Jakub Jelinek + + PR rtl-optimization/58997 + * loop-iv.c (iv_subreg): For IV_UNKNOWN_EXTEND, expect + get_iv_value to be in iv->mode rather than iv->extend_mode. + (iv_extend): Likewise. Otherwise, if iv->extend != extend, + use lowpart_subreg on get_iv_value before calling simplify_gen_unary. + * loop-unswitch.c (may_unswitch_on): Make sure op[i] is in the right + mode. + +2013-11-10 Karlson2k + Kai Tietz + + Merged from trunk + PR plugins/52872 + * configure.ac: Adding for exported symbols check + and for rdynamic-check executable-extension. + * configure: Regenerated. + +2013-11-07 H.J. Lu + + PR target/59034 + * config/i386/i386.md (push peepholer/splitter): Use Pmode + with stack_pointer_rtx. + +2013-11-05 Uros Bizjak + + * config/i386/t-rtems (MULTILIB_MATCHES): Fix option typos. + +2013-11-05 Jakub Jelinek + + PR tree-optimization/58984 + * ipa-prop.c (ipa_load_from_parm_agg_1): Add SIZE_P argument, + set *SIZE_P if non-NULL on success. + (ipa_load_from_parm_agg, ipa_analyze_indirect_call_uses): Adjust + callers. + (ipcp_transform_function): Likewise. Punt if size of access + is different from TYPE_SIZE on v->value's type. + +2013-11-03 H.J. Lu + + Backport from mainline + 2013-10-12 H.J. Lu + + PR target/58690 + * config/i386/i386.c (ix86_copy_addr_to_reg): New function. + (ix86_expand_movmem): Replace copy_addr_to_reg with + ix86_copy_addr_to_reg. + (ix86_expand_setmem): Likewise. + +2013-10-29 Uros Bizjak + + Backport from mainline + 2013-08-08 Richard Sandiford + + PR rtl-optimization/58079 + * combine.c (combine_simplify_rtx): Avoid using SUBST if + simplify_comparison has widened a comparison with an integer. + +2013-10-29 Martin Jambor + + PR middle-end/58789 + Backport from mainline + 2013-05-09 Martin Jambor + + PR lto/57084 + * gimple-fold.c (canonicalize_constructor_val): Call + cgraph_get_create_real_symbol_node instead of cgraph_get_create_node. + + Backport from mainline + 2013-03-16 Jan Hubicka + + * cgraph.h (cgraph_get_create_real_symbol_node): Declare. + * cgraph.c (cgraph_get_create_real_symbol_node): New function. + * cgrpahbuild.c: Use cgraph_get_create_real_symbol_node instead + of cgraph_get_create_node. + * ipa-prop.c (ipa_make_edge_direct_to_target): Likewise. + +2013-10-28 Tom de Vries + + * cfgexpand.c (gimple_expand_cfg): Remove test for parm_birth_insn. + Don't commit insertions after NOTE_INSN_FUNCTION_BEG. + +2013-10-26 Uros Bizjak + + Backport from mainline + 2013-10-22 Uros Bizjak + + PR target/58779 + * config/i386/i386.c (put_condition_code) : + Remove CCCmode handling. + : Return 'c' suffix for CCCmode. + : Return 'nc' suffix for CCCmode. + (ix86_cc_mode) : Do not generate overflow checks. + * config/i386/i386.md (*sub3_cconly_overflow): Remove. + (*sub3_cc_overflow): Ditto. + (*subsi3_zext_cc_overflow): Ditto. + +2013-10-26 Uros Bizjak + + Backport from mainline + 2013-10-19 Uros Bizjak + + PR target/58792 + * config/i386/i386.c (ix86_function_value_regno): Add DX_REG, + ST1_REG and XMM1_REG for 32bit and 64bit targets. Also add DI_REG + and SI_REG for 64bit SYSV ABI targets. + +2013-08-25 Richard Henderson + + PR rtl/58542 + * optabs.c (maybe_emit_atomic_exchange): Use create_input_operand + instead of create_convert_operand_to. + (maybe_emit_sync_lock_test_and_set): Likewise. + (expand_atomic_compare_and_swap): Likewise. + (maybe_emit_compare_and_swap_exchange_loop): Don't convert_modes. + +2013-10-25 Eric Botcazou + + PR rtl-optimization/58831 + * alias.c (init_alias_analysis): At the beginning of each iteration, set + the reg_seen[N] bit if static_reg_base_value[N] is non-null. + +2013-10-25 Eric Botcazou + + * recog.c (search_ofs): New static variable moved from... + (peep2_find_free_register): ...here. + (peephole2_optimize): Initialize it. + +2013-10-24 David Edelsohn + + Backport from mainline + 2013-10-23 David Edelsohn + + PR target/58838 + * config/rs6000/rs6000.md (mulsi3_internal1 and splitter): Add + TARGET_32BIT final condition. + (mulsi3_internal2 and splitter): Same. + +2013-10-23 Tom de Vries + + PR tree-optimization/58805 + * tree-ssa-tail-merge.c (stmt_local_def): Add gimple_vdef check. + +2013-10-23 Richard Biener + + Backport from mainline + 2013-06-24 Richard Biener + + PR tree-optimization/57488 + * tree-ssa-pre.c (insert): Clear NEW sets before each iteration. + +2013-10-16 Ganesh Gopalasubramanian + + Backport from mainline + 2013-10-16 Ganesh Gopalasubramanian + + + * config/i386/i386.c (ix86_option_override_internal): Enable FMA4 + for AMD bdver3. + +2013-10-16 Jakub Jelinek + + * BASE-VER: Set to 4.8.3. + * DEV-PHASE: Set to prerelease. + +2013-10-16 Release Manager + + * GCC 4.8.2 released. + +2013-10-12 James Greenhalgh + + Backport from mainline. + 2013-10-12 James Greenhalgh + + * config/aarch64/arm_neon.h + (vtbx<1,3>_8): Fix register constriants. + +2013-10-10 Jakub Jelinek + + PR middle-end/58670 + * stmt.c (expand_asm_operands): Add FALLTHRU_BB argument, + if any labels are in FALLTHRU_BB, use a special label emitted + immediately after the asm goto insn rather than label_rtx + of the LABEL_DECL. + (expand_asm_stmt): Adjust caller. + * cfgrtl.c (commit_one_edge_insertion): Force splitting of + edge if the last insn in predecessor is a jump with single successor, + but it isn't simplejump_p. + +2013-10-09 Jakub Jelinek + + Backport from mainline + 2013-09-26 Richard Biener + + PR tree-optimization/58539 + * tree-vect-loop.c (vect_create_epilog_for_reduction): Honor + the fact that debug statements are not taking part in loop-closed + SSA construction. + +2013-10-07 Andreas Krebbel + + * config/s390/s390.c (s390_register_info): Make the call-saved FPR + loop to work also for 31bit ABI. + Save the stack pointer for frame_size > 0. + +2013-10-07 Andreas Krebbel + + * config/s390/s390.md ("tbegin", "tbegin_nofloat", "tbegin_retry") + ("tbegin_retry_nofloat", "tend", "tabort", "tx_assist"): Remove + constraint letters from expanders. + ("tbegin_retry", "tbegin_retry_nofloat"): Change predicate of the + retry count to general_operand. + ("tabort"): Give operand 0 a mode. + ("tabort_1"): Add mode and constraint letter for operand 0. + * doc/extend.texi: Fix protoype of __builtin_non_tx_store. + +2013-10-04 Marcus Shawcroft + + Backport from mainline. + + PR target/58460 + * config/aarch64/aarch64.md (*add__) + (*add__si_uxtw,*add_mul_imm_) + (*sub__) + (*sub__si_uxtw,*sub_mul_imm_, *sub_mul_imm_si_uxtw): + Remove k constraint. + +2013-10-02 John David Anglin + + * config.gcc (hppa*64*-*-linux*): Don't add pa/t-linux to tmake_file. + +2013-10-01 Jakub Jelinek + Andreas Krebbel + + PR target/58574 + * config/s390/s390.c (s390_chunkify_start): Handle tablejump_p first, + continue when done, for other jumps look through PARALLEL + unconditionally. + +2013-09-30 Jakub Jelinek + + PR middle-end/58564 + * fold-const.c (fold_ternary_loc): For A < 0 : : 0 + optimization, punt if sign_bit_p looked through any zero extension. + +2013-09-27 Paulo Matos + + Backport from mainline. + + PR middle-end/58463 + 2013-03-27 Richard Biener + + PR tree-optimization/56716 + * tree-ssa-structalias.c (perform_var_substitution): Adjust + dumping for ref nodes. + +2013-09-27 Paulo Matos + + Backport from mainline. + + 2013-09-27 Paulo Matos + PR middle-end/58463 + * gcc.dg/pr58463.c: New test. + +2013-09-23 Eric Botcazou + + * tree-ssa-ccp.c (insert_clobber_before_stack_restore): Recurse on copy + assignment statements. + +2013-09-23 Alan Modra + + PR target/58330 + * config/rs6000/rs6000.md (bswapdi2_64bit): Disable for volatile mems. + +2013-09-23 Alan Modra + + * config/rs6000/predicates.md (add_cint_operand): New. + (reg_or_add_cint_operand, small_toc_ref): Use add_cint_operand. + * config/rs6000/rs6000.md (largetoc_high_plus): Restrict offset + using add_cint_operand. + (largetoc_high_plus_aix): Likewise. + * config/rs6000/rs6000.c (toc_relative_expr_p): Use add_cint_operand. + +2013-09-20 John David Anglin + + PR middle-end/56791 + * config/pa/pa.c (pa_option_override): Disable auto increment and + decrement instructions until reload is completed. + + * config/pa/pa.md: In "scc" insn patterns, change output template to + handle const0_rtx in reg_or_0_operand operands. + +2013-09-19 Jakub Jelinek + + * omp-low.c (expand_omp_sections): Always pass len - 1 to + GOMP_sections_start, even if !exit_reachable. + +2013-09-18 Richard Earnshaw + + * arm.c (arm_expand_prologue): Validate architecture supports + LDRD/STRD before accepting tuning preferences. + (arm_expand_epilogue): Likewise. + +2013-09-18 Daniel Morris + Paolo Carlini + + PR c++/58458 + * doc/implement-cxx.texi: Fix references to the C++ standards. + +2013-09-17 Kyrylo Tkachov + + PR tree-optimization/58088 + * fold-const.c (mask_with_trailing_zeros): New function. + (fold_binary_loc): Make sure we don't recurse infinitely + when the X in (X & C1) | C2 is a tree of the form (Y * K1) & K2. + Use mask_with_trailing_zeros where appropriate. + +2013-09-14 John David Anglin + + PR target/58382 + * config/pa/pa.c (pa_expand_prologue): Change mode in gen_rtx_POST_INC + calls to word_mode. + +2013-09-13 Christian Bruel + + PR target/58314 + * config/sh/sh.md (mov_reg_reg): Allow memory reloads. + +2013-09-11 Andi Kleen + + Backport from mainline + * doc/extend.texi: Use __atomic_store_n instead of + __atomic_store in HLE example. + +2013-09-11 Andi Kleen + + Backport from mainline + * doc/extend.texi: Dont use __atomic_clear in HLE + example. Fix typo. + +2013-09-11 Andi Kleen + + Backport from mainline + * doc/extend.texi: Document that __atomic_clear and + __atomic_test_and_set should only be used with bool. + +2013-09-11 Richard Biener + + PR middle-end/58377 + * passes.c (init_optimization_passes): Split critical edges + before late uninit warning pass in the -Og pipeline. + +2013-09-11 Jakub Jelinek + + PR tree-optimization/58385 + * fold-const.c (build_range_check): If both low and high are NULL, + use omit_one_operand_loc to preserve exp side-effects. + +2013-09-10 Richard Earnshaw + + PR target/58361 + * arm/vfp.md (combine_vcvt_f32_): Fix pattern to + support conditional execution. + (combine_vcvt_f64_): Likewise. + +2013-09-10 Jakub Jelinek + + PR rtl-optimization/58365 + * cfgcleanup.c (merge_memattrs): Also clear MEM_READONLY_P + resp. MEM_NOTRAP_P if they differ, or set MEM_VOLATILE_P if + it differs. + +2013-09-09 Jakub Jelinek + + PR tree-optimization/58364 + * tree-ssa-reassoc.c (init_range_entry): For BIT_NOT_EXPR on + BOOLEAN_TYPE, only invert in_p and continue with arg0 if + the current range can't be an unconditional true or false. + +2013-09-09 Kyrylo Tkachov + + PR target/57735 + Backport from mainline + 2013-04-30 Richard Sandiford + + * explow.c (plus_constant): Pass "mode" to immed_double_int_const. + Use gen_int_mode rather than GEN_INT. + +2013-09-09 Richard Biener + + Backport from mainline + 2013-08-27 Richard Biener + + PR tree-optimization/57521 + * tree-if-conv.c (if_convertible_bb_p): Verify that at least + one edge is non-critical. + (find_phi_replacement_condition): Make sure to use a non-critical + edge. Cleanup and remove old bug workarounds. + (bb_postdominates_preds): Remove. + (if_convertible_loop_p_1): Do not compute post-dominators. + (combine_blocks): Do not free post-dominators. + (main_tree_if_conversion): Likewise. + +2013-09-09 Richard Biener + + Backport from mainline + 2013-09-03 Richard Biener + + PR middle-end/57656 + * fold-const.c (negate_expr_p): Fix division case. + (negate_expr): Likewise. + +2013-09-09 Richard Biener + + Backport from mainline + 2013-08-29 Richard Biener + + PR tree-optimization/57685 + * tree-vrp.c (register_edge_assert_for_1): Recurse only for + single-use operands to avoid exponential complexity. + +2013-09-09 Richard Biener + + Backport from mainline + 2013-08-30 Richard Biener + + PR tree-optimization/58223 + * tree-loop-distribution.c (has_anti_dependence): Rename to ... + (has_anti_or_output_dependence): ... this and adjust to also + look for output dependences. + (mark_nodes_having_upstream_mem_writes): Adjust. + (rdg_flag_uses): Likewise. + +2013-09-03 Richard Biener + + Backport from mainline + 2013-08-29 Richard Biener + + PR tree-optimization/58246 + * tree-ssa-dce.c (mark_aliased_reaching_defs_necessary_1): Properly + handle the dominance check inside a basic-block. + +2013-09-03 Richard Biener + + Backport from mainline + 2013-08-30 Richard Biener + + PR tree-optimization/58228 + * tree-vect-data-refs.c (vect_analyze_data_ref_access): Do not + allow invariant loads in nested loop vectorization. + +2013-09-03 Richard Biener + + Backport from mainline + 2013-08-30 Richard Biener + + PR tree-optimization/58010 + * tree-vect-loop.c (vect_create_epilog_for_reduction): Remove + assert that we have a loop-closed PHI. + +2013-09-01 Uros Bizjak + + Backport from mainline + 2013-08-31 Uros Bizjak + + * config/alpha/alpha.c (alpha_emit_conditional_move): Update + "cmp" RTX before signed_comparison_operator check to account + for "code" changes. + +2013-09-01 John David Anglin + + * config/pa/pa.md: Allow "const 0" operand 1 in "scc" insns. + +2013-08-30 Jakub Jelinek + + PR tree-optimization/58277 + * tree-ssa-strlen.c (strlen_enter_block): If do_invalidate gave up + after seeing too many stmts with vdef in between dombb and current + bb, invalidate everything. + +2013-08-29 Oleg Endo + + Backport from mainline + 2013-08-05 Oleg Endo + + PR other/12081 + * recog.h (rtx (*insn_gen_fn) (rtx, ...)): Replace typedef with new + class insn_gen_fn. + * expr.c (move_by_pieces_1, store_by_pieces_2): Replace argument + rtx (*) (rtx, ...) with insn_gen_fn. + * genoutput.c (output_insn_data): Cast gen_? function pointers to + insn_gen_fn::stored_funcptr. Add initializer braces. + + Backport from mainline + 2013-08-07 Oleg Endo + + PR other/12081 + * config/rs6000/rs6000.c (gen_2arg_fn_t): Remove typedef. + (rs6000_emit_swdiv_high_precision, rs6000_emit_swdiv_low_precision, + rs6000_emit_swrsqrt): Don't cast result of GEN_FCN to gen_2arg_fn_t. + +2013-08-29 Jakub Jelinek + + Backported from mainline + 2013-05-27 Richard Biener + + PR middle-end/57381 + PR tree-optimization/57417 + * tree-ssa-sccvn.c (vn_reference_fold_indirect): Fix test + for unchanged base. + (set_ssa_val_to): Compare addresses using + get_addr_base_and_unit_offset. + + PR tree-optimization/57396 + * tree-affine.c (double_int_constant_multiple_p): Properly + return false for val == 0 and div != 0. + + PR tree-optimization/57343 + * tree-ssa-loop-niter.c (number_of_iterations_ne_max): Do not + use multiple_of_p if not TYPE_OVERFLOW_UNDEFINED. + (number_of_iterations_cond): Do not build the folded tree. + +2013-08-28 Jakub Jelinek + + PR middle-end/58257 + * omp-low.c (copy_var_decl): Copy over TREE_NO_WARNING flag. + +2013-08-28 Richard Biener + + Backport from mainline + 2013-06-24 Richard Biener + + PR middle-end/56977 + * passes.c (init_optimization_passes): Move pass_fold_builtins + and pass_dce earlier with -Og. + +2013-08-28 Uros Bizjak + + Backport from mainline + 2013-08-27 H.J. Lu + + * config/i386/driver-i386.c (host_detect_local_cpu): Update + Haswell processor detection. + + Backport from mainline + 2013-08-27 Christian Widmer + + PR target/57927 + * config/i386/driver-i386.c (host_detect_local_cpu): Add detection + of Ivy Bridge and Haswell processors. Assume core-avx2 for unknown + AVX2 capable processors. + +2013-08-23 Jakub Jelinek + + PR target/58218 + * config/i386/x86-64.h (TARGET_SECTION_TYPE_FLAGS): Define. + * config/i386/i386.c (x86_64_elf_section_type_flags): New function. + + PR tree-optimization/58209 + * tree-tailcall.c (find_tail_calls): Give up for pointer result types + if m or a is non-NULL. + +2013-08-21 Richard Earnshaw + + PR target/56979 + * arm.c (aapcs_vfp_allocate): Decompose the argument if the + suggested mode for the assignment isn't compatible with the + registers required. + +2013-08-20 Alan Modra + + PR target/57865 + * config/rs6000/rs6000.c (rs6000_emit_prologue): Correct ool_adjust. + (rs6000_emit_epilogue): Likewise. + +2013-08-19 Peter Bergner + Jakub Jelinek + + Backport from mainline + * config/rs6000/dfp.md (*negtd2_fpr): Handle non-overlapping + destination and source operands. + +2013-08-18 Jakub Jelinek + + PR tree-optimization/58006 + * tree-parloops.c (take_address_of): Don't ICE if get_name + returns NULL. + (eliminate_local_variables_stmt): Remove clobber stmts. + +2013-08-16 Jakub Jelinek + + PR tree-optimization/58164 + * gimple.c (walk_stmt_load_store_addr_ops): For visit_addr + walk gimple_goto_dest of GIMPLE_GOTO. + + PR tree-optimization/58165 + * tree-call-cdce.c (shrink_wrap_one_built_in_call): If + bi_call must be the last stmt in a bb, don't split_block, instead + use fallthru edge from it and give up if there is none. + Release conds vector when returning early. + +2013-08-15 David Given + + Backport from mainline + 2013-04-26 Vladimir Makarov + + * lra-constraints.c (process_alt_operands): Use #if HAVE_ATTR_enable + instead of #ifdef. + +2013-08-14 Jakub Jelinek + + PR tree-optimization/58145 + * tree-sra.c (build_ref_for_offset): If prev_base has + TREE_THIS_VOLATILE or TREE_SIDE_EFFECTS, propagate it to MEM_REF. + +2013-08-14 Andreas Krebbel + + * config/s390/htmxlintrin.h: Add file missing from last commit. + * config/s390/htmintrin.h: Likewise. + * config/s390/s390intrin.h: Likewise. + +2013-08-14 Uros Bizjak + + Backport from mainline + 2013-08-13 Uros Bizjak + + * config/i386/sse.md (*sse2_maskmovdqu): Emit addr32 prefix + when Pmode != word_mode. Add length_address attribute. + (sse3_monitor_): Merge from sse3_monitor and + sse3_monitor64_ insn patterns. Emit addr32 prefix when + Pmode != word_mode. Update insn length attribute. + * config/i386/i386.c (ix86_option_override_internal): Update + ix86_gen_monitor selection for merged sse3_monitor insn. + +2013-08-14 Jakub Jelinek + Alexandre Oliva + + PR target/58067 + * config/i386/i386.c (ix86_delegitimize_address): For CM_MEDIUM_PIC + and CM_LARGE_PIC ix86_cmodel fall thru into the -m32 code, handle + there also UNSPEC_PLTOFF. + +2013-08-13 Jakub Jelinek + + PR sanitizer/56417 + * asan.c (instrument_strlen_call): Fix typo in comment. + Use char * type even for the lhs of POINTER_PLUS_EXPR. + +2013-08-13 Vladimir Makarov + + Backport from mainline + 2013-06-06 Vladimir Makarov + + PR rtl-optimization/57459 + * lra-constraints.c (update_ebb_live_info): Fix typo for operand + type when setting live regs. + +2013-08-13 Marek Polacek + Jakub Jelinek + + PR tree-optimization/57980 + * tree-tailcall.c (process_assignment): Return false + when not dealing with integers or floats. + +2013-08-12 Andrew Haley + + Backport from mainline: + * 2013-07-11 Andreas Schwab + + * config/aarch64/aarch64-linux.h (CPP_SPEC): Define. + +2013-08-13 Uros Bizjak + + Backport from mainline + 2013-08-12 Perez Read + + PR target/58132 + * config/i386/i386.md (*movabs_1): Add PTR before + operand 0 for intel asm alternative. + (*movabs_2): Ditto for operand 1. + +2013-08-09 Zhenqiang Chen + + Backport from mainline: + 2013-08-09 Zhenqiang Chen + + * config/arm/neon.md (vcond): Fix floating-point vector + comparisons against 0. + +2013-08-08 Kyrylo Tkachov + + Backport from mainline: + 2013-08-08 Kyrylo Tkachov + + * config/arm/neon.md (movmisalign): Disable when we + don't allow unaligned accesses. + (*movmisalign_neon_store): Likewise. + (*movmisalign_neon_load): Likewise. + (*movmisalign_neon_store): Likewise. + (*movmisalign_neon_load): Likewise. + +2013-08-06 Martin Jambor + + PR middle-end/58041 + * gimple-ssa-strength-reduction.c (replace_ref): Make sure built + MEM_REF has proper alignment information. + +2013-08-05 Richard Earnshaw + + PR rtl-optimization/57708 + * recog.c (peep2_find_free_register): Validate all regs in a + multi-reg mode. + +2013-08-02 Eric Botcazou + + * config/sparc/sparc.c (sparc_emit_membar_for_model) : Add + the implied StoreLoad barrier for atomic operations if before. + +2013-08-02 Andreas Krebbel + + Backports from mainline: + 2013-06-27 Andreas Krebbel + + * config/s390/s390.c: Rename UNSPEC_CCU_TO_INT to + UNSPEC_STRCMPCC_TO_INT and UNSPEC_CCZ_TO_INT to UNSPEC_CC_TO_INT. + (struct machine_function): Add tbegin_p. + (s390_canonicalize_comparison): Fold CC mode compares to + conditional jump if possible. + (s390_emit_jump): Return the emitted jump. + (s390_branch_condition_mask, s390_branch_condition_mnemonic): + Handle CCRAWmode compares. + (s390_option_override): Default to -mhtm if available. + (s390_reg_clobbered_rtx): Handle floating point regs as well. + (s390_regs_ever_clobbered): Use s390_regs_ever_clobbered also for + FPRs instead of df_regs_ever_live_p. + (s390_optimize_nonescaping_tx): New function. + (s390_init_frame_layout): Extend clobbered_regs array to cover + FPRs as well. + (s390_emit_prologue): Call s390_optimize_nonescaping_tx. + (s390_expand_tbegin): New function. + (enum s390_builtin): New enum definition. + (code_for_builtin): New array definition. + (s390_init_builtins): New function. + (s390_expand_builtin): New function. + (TARGET_INIT_BUILTINS): Define. + (TARGET_EXPAND_BUILTIN): Define. + * common/config/s390/s390-common.c (processor_flags_table): Add PF_TX. + * config/s390/predicates.md (s390_comparison): Handle CCRAWmode. + (s390_alc_comparison): Likewise. + * config/s390/s390-modes.def: Add CCRAWmode. + * config/s390/s390.h (processor_flags): Add PF_TX. + (TARGET_CPU_HTM): Define macro. + (TARGET_HTM): Define macro. + (TARGET_CPU_CPP_BUILTINS): Define __HTM__ for htm. + * config/s390/s390.md: Rename UNSPEC_CCU_TO_INT to + UNSPEC_STRCMPCC_TO_INT and UNSPEC_CCZ_TO_INT to UNSPEC_CC_TO_INT. + (UNSPECV_TBEGIN, UNSPECV_TBEGINC, UNSPECV_TEND, UNSPECV_TABORT) + (UNSPECV_ETND, UNSPECV_NTSTG, UNSPECV_PPA): New unspecv enum + values. + (TBEGIN_MASK, TBEGINC_MASK): New constants. + ("*cc_to_int"): Move up. + ("*movcc", "*cjump_64", "*cjump_31"): Accept integer + constants other than 0. + ("*ccraw_to_int"): New insn and splitter definition. + ("tbegin", "tbegin_nofloat", "tbegin_retry") + ("tbegin_retry_nofloat", "tbeginc", "tend", "tabort") + ("tx_assist"): New expander. + ("tbegin_1", "tbegin_nofloat_1", "*tbeginc_1", "*tend_1") + ("*tabort_1", "etnd", "ntstg", "*ppa"): New insn definition. + * config/s390/s390.opt: Add -mhtm option. + * config/s390/s390-protos.h (s390_emit_jump): Add return type. + * config/s390/htmxlintrin.h: New file. + * config/s390/htmintrin.h: New file. + * config/s390/s390intrin.h: New file. + * doc/extend.texi: Document htm builtins. + * config.gcc: Add the new header files to extra_headers. + + 2013-07-17 Andreas Krebbel + + * config/s390/s390.c: (s390_expand_builtin): Allow -mhtm to be + enabled without -march=zEC12. + * config/s390/s390.h (TARGET_HTM): Do not require EC12 machine + flags to be set. + +2013-08-01 Ganesh Gopalasubramanian + + Backport from mainline + 2013-05-13 Ganesh Gopalasubramanian + + + * config/i386/i386.c (processor_target_table): Modified default + alignment values for AMD BD and BT architectures. + +2013-07-31 Sriraman Tallam + + * config/i386/i386.c (dispatch_function_versions): Fix array + indexing of function_version_info to match actual_versions. + +2013-07-31 Sebastian Huber + + * config.gcc (*-*-rtems*): Use __cxa_atexit by default. + * config/rs6000/rtems.h (TARGET_LIBGCC_SDATA_SECTION): Define. + +2013-07-31 Andreas Krebbel + + Backport from mainline + 2013-03-27 Andreas Krebbel + + * config/s390/s390.h (TARGET_FLT_EVAL_METHOD): Define. + + 2013-07-23 Andreas Krebbel + + * config/s390/linux-unwind.h: Use the proper dwarf to hard reg + mapping for FPRs when creating the fallback framestate. + + 2013-07-29 Dominik Vogt + + * config/s390/s390.md ("movcc"): Swap load and store instructions. + +2013-07-25 Terry Guo + + Backport from mainline: + 2013-07-25 Terry Guo + + * config/arm/arm.c (thumb1_size_rtx_costs): Assign proper cost for + shift_add/shift_sub0/shift_sub1 RTXs. + +2013-07-22 Iain Sandoe + + Backport from mainline: + 2013-07-22 Uros Bizjak + + * config/i386/i386.md (nonlocal_goto_receiver): Delete insn if + it is not needed after split. + + 2013-07-20 Iain Sandoe + + PR target/51784 + * config/i386/i386.c (output_set_got) [TARGET_MACHO]: Adjust to emit a + second label for nonlocal goto receivers. Don't output pic base labels + unless we're producing PIC; mark that action unreachable(). + (ix86_save_reg): If the function contains a nonlocal label, save the + PIC base reg. + * config/darwin-protos.h (machopic_should_output_picbase_label): New. + * gcc/config/darwin.c (emitted_pic_label_num): New GTY. + (update_pic_label_number_if_needed): New. + (machopic_output_function_base_name): Adjust for nonlocal receiver + case. + (machopic_should_output_picbase_label): New. + * config/i386/i386.md (enum unspecv): UNSPECV_NLGR: New. + (nonlocal_goto_receiver): New insn and split. + +2013-07-19 Wei Mi + + Backport from mainline: + 2013-07-18 Vladimir Makarov + Wei Mi + + PR rtl-optimization/57878 + * lra-assigns.c (assign_by_spills): Move non_reload_pseudos to the + top. Promote lra_assert to gcc_assert. + (reload_pseudo_compare_func): Check regs first for reload pseudos. + +2013-07-11 Georg-Johann Lay + + Backport from 2013-07-19 trunk r201051. + + PR target/57516 + * config/avr/avr-fixed.md (round3_const): Turn expander to insn. + * config/avr/avr.md (adjust_len): Add `round'. + * config/avr/avr-protos.h (avr_out_round): New prototype. + (avr_out_plus): Add `out_label' argument. + * config/avr/avr.c (avr_out_plus_1): Add `out_label' argument. + (avr_out_plus): Pass down `out_label' to avr_out_plus_1. + Handle the case where `insn' is just a pattern. + (avr_out_bitop): Handle the case where `insn' is just a pattern. + (avr_out_round): New function. + (avr_adjust_insn_length): Handle ADJUST_LEN_ROUND. + +2013-07-19 Kirill Yukhin + + * config/i386/bmiintrin.h (_bextr_u32): New. + (_bextr_u64): Ditto. + (_blsi_u32): New. + (_blsi_u64): Ditto. + (_blsr_u32): Ditto. + (_blsr_u64): Ditto. + (_blsmsk_u32): Ditto. + (_blsmsk_u64): Ditto. + (_tzcnt_u32): Ditto. + (_tzcnt_u64): Ditto. + +2013-07-17 James Greenhalgh + + Backport From mainline: + 2013-07-03 James Greenhalgh + + * config/aarch64/aarch64-builtins.c + (aarch64_simd_expand_builtin): Handle AARCH64_SIMD_STORE1. + * config/aarch64/aarch64-simd-builtins.def (ld1): New. + (st1): Likewise. + * config/aarch64/aarch64-simd.md + (aarch64_ld1): New. + (aarch64_st1): Likewise. + * config/aarch64/arm_neon.h + (vld1_<8, 16, 32, 64>): Convert to RTL builtins. + +2013-07-11 Georg-Johann Lay + + Backport from 2013-07-11 trunk r200901. + + PR target/57631 + * config/avr/avr.c (avr_set_current_function): Sanity-check signal + name seen by assembler/linker if available. + +2013-07-10 Georg-Johann Lay + + Backport from 2013-07-10 trunk r200872. + + PR target/57844 + * config/avr/avr.c (avr_prologue_setup_frame): Trunk -size to mode + of my_fp. + +2013-07-10 Georg-Johann Lay + + Backport from 2013-07-10 trunk r200870. + + PR target/57506 + * config/avr/avr-mcus.def (atmega16hva, atmega16hva2, atmega16hvb) + (atmega16m1, atmega16u4, atmega32a, atmega32c1, atmega32hvb) + (atmega32m1, atmega32u4, atmega32u6, atmega64c1, atmega64m1): + Remove duplicate devices. + * config/avr/gen-avr-mmcu-texi.c (print_mcus): Fail on duplicate MCUs. + * config/avr/t-multilib: Regenerate. + * config/avr/avr-tables.opt: Regenerate. + * doc/avr-mmcu.texi: Regenerate. + +2013-07-10 Georg-Johann Lay + + PR target/56987 + * config/avr/avr.opt (Waddr-space-convert): Fix typo. + +2013-07-09 Joseph Myers + + * config/rs6000/rs6000.c (rs6000_init_hard_regno_mode_ok): Only + adjust register size for TDmode and TFmode for VSX registers. + +2013-07-08 Kai Tietz + + Backport from mainline + PR target/56892 + * config/i386/i386.c (TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P): Define as + hook_bool_const_tree_true. + +2013-07-08 Uros Bizjak + + Backport from mainline + 2013-07-07 Uros Bizjak + + * config/i386/driver-i386.c (host_detect_local_cpu): Do not check + signature_TM2_ebx, it interferes with signature_INTEL_ebx. + + Backport from mainline + 2013-07-06 Uros Bizjak + + * config/i386/sse.md (sse_movlhps): Change alternative 3 + of operand 2 to "m". + +2013-07-08 Eric Botcazou + + * Makefile.in (tree-ssa-reassoc.o): Add dependency on $(PARAMS_H). + +2013-07-08 Jakub Jelinek + + PR rtl-optimization/57829 + * simplify-rtx.c (simplify_binary_operation_1) : Ensure that + mask bits outside of mode are just sign-extension from mode to HWI. + +2013-07-03 Jakub Jelinek + + PR target/57777 + * config/i386/predicates.md (vsib_address_operand): Disallow + SYMBOL_REF or LABEL_REF in parts.disp if TARGET_64BIT && flag_pic. + +2013-06-30 Terry Guo + + Backport from mainline + 2013-03-27 Bin Cheng + + PR target/56102 + * config/arm/arm.c (thumb1_rtx_costs, thumb1_size_rtx_costs): Fix + rtx costs for SET/ASHIFT/ASHIFTRT/LSHIFTRT/ROTATERT patterns with + mult-word mode. + +2013-06-28 Jakub Jelinek + + PR target/57736 + * config/i386/i386.c (ix86_expand_builtin): If target == NULL + and mode is VOIDmode, don't create a VOIDmode pseudo to copy result + into. + +2013-06-27 Jakub Jelinek + + PR target/57623 + * config/i386/i386.md (bmi_bextr_): Swap predicates and + constraints of operand 1 and 2. + + PR target/57623 + * config/i386/i386.md (bmi2_bzhi_3): Swap AND arguments + to match RTL canonicalization. Swap predicates and + constraints of operand 1 and 2. + + * tree-vect-stmts.c (vectorizable_store): Move ptr_incr var + decl before the loop, initialize to NULL. + (vectorizable_load): Initialize ptr_incr to NULL. + +2013-06-24 Martin Jambor + + PR tree-optimization/57358 + * ipa-prop.c (parm_ref_data_preserved_p): Always return true when + not optimizing. + +2013-06-24 Alan Modra + + * config/rs6000/rs6000.c (vspltis_constant): Correct for little-endian. + (gen_easy_altivec_constant): Likewise. + * config/rs6000/predicates.md (easy_vector_constant_add_self, + easy_vector_constant_msb): Likewise. + +2013-06-21 Uros Bizjak + + Backport from mainline + 2013-06-20 Uros Bizjak + + PR target/57655 + * config/i386/i386.c (construct_container): Report error if + long double is used with disabled x87 float returns. + +2013-06-20 Wei Mi + + Backport from mainline + 2013-06-19 Wei Mi + + PR rtl-optimization/57518 + * ira.c (set_paradoxical_subreg): Set pdx_subregs[regno] + if regno is used in paradoxical subreg. + (update_equiv_regs): Check pdx_subregs[regno] before + set a reg to be equivalent with a mem. + + +2013-06-20 David Edelsohn + + Backport from mainline + 2013-06-19 David Edelsohn + + PR driver/57652 + * collect2.c (collect_atexit): New. + (collect_exit): Delete. + (main): Register collect_atexit with atexit. + (collect_wait): Change collect_exit to exit. + (do_wait): Same. + * collect2.h (collect_exit): Delete. + * tlink.c (do_tlink): Rename exit to ret. Change collect_exit to exit. + +2013-06-19 Matthias Klose + + PR driver/57651 + * file-find.h (find_a_file): Add a mode parameter. + * file-find.c (find_a_file): Likewise. + * gcc-ar.c (main): Call find_a_file with R_OK for the plugin, + with X_OK for the executables. + * collect2.c (main): Call find_a_file with X_OK. + +2013-06-19 Igor Zamyatin + + * doc/invoke.texi (core-avx2): Document. + (atom): Updated with MOVBE. + +2013-06-19 Jakub Jelinek + + PR driver/57651 + * gcc-ar.c (main): If not CROSS_DIRECTORY_STRUCTURE, look for + PERSONALITY in $PATH derived prefixes. + +2013-06-19 Paolo Carlini + + PR c++/56544 + * doc/cpp.texi [Standard Predefined Macros, __cplusplus]: Document + that now in C++ the value is correct per the C++ standards. + +2013-06-19 Alan Modra + + Apply mainline patches + 2013-06-13 Alan Modra + * config/rs6000/rs6000.h (LONG_DOUBLE_LARGE_FIRST): Define. + * config/rs6000/rs6000.md (signbittf2): New insn. + (extenddftf2_internal): Use LONG_DOUBLE_LARGE_FIRST. + (abstf2_internal, cmptf_internal2): Likewise. + * config/rs6000/spe.md (spe_abstf2_cmp, spe_abstf2_tst): Likewise. + + 2013-06-11 Anton Blanchard + * config/rs6000/rs6000.c (rs6000_adjust_atomic_subword): Calculate + correct shift value in little-endian mode. + + 2013-06-07 Alan Modra + * config/rs6000/rs6000.c (setup_incoming_varargs): Round up + va_list_gpr_size. + + 2013-06-04 Alan Modra + * config/rs6000/rs6000.c (output_toc): Correct little-endian float + constant output. + + 2013-05-10 Alan Modra + * configure.ac (HAVE_AS_TLS): Swap powerpc64 and powerpc cases. + (HAVE_LD_LARGE_TOC): Don't mention AIX in help text. + * configure: Regenerate. + + 2013-05-09 Alan Modra + * configure.ac (HAVE_AS_TLS): Enable tests for powerpcle and + powerpc64le. + * configure: Regenerate. + + 2013-05-07 Anton Blanchard + * configure.ac (HAVE_LD_LARGE_TOC): Use right linker emulation + for powerpc64 little endian. + * configure: Regenerate. + + 2013-05-06 Alan Modra + * config/rs6000/linux.h (DEFAULT_ASM_ENDIAN): Define. + (LINK_OS_LINUX_EMUL): Use ENDIAN_SELECT. + * config/rs6000/linux64.h (DEFAULT_ASM_ENDIAN): Define. + * config/rs6000/sysv4le.h (DEFAULT_ASM_ENDIAN): Define. + (LINK_TARGET_SPEC): Use ENDIAN_SELECT. + * config/rs6000/sysv4.h (DEFAULT_ASM_ENDIAN): Define as -mbig. + + 2013-05-06 Alan Modra + * config/rs6000/sysv4.h (ENDIAN_SELECT): Define, extracted from + (ASM_SPEC): ..here. Emit DEFAULT_ASM_ENDIAN too. + (DEFAULT_ASM_ENDIAN): Define. + (CC1_SPEC, LINK_TARGET_SPEC): Use ENDIAN_SELECT. + * config/rs6000/linux64.h (ASM_SPEC32): Remove endian options. + Update -K PIC clause from sysv4.h. + (ASM_SPEC_COMMON): Use ENDIAN_SELECT. + (LINK_OS_LINUX_EMUL32, LINK_OS_LINUX_EMUL64): Likewise. + + 2013-05-06 Alan Modra + * config/rs6000/rs6000.md (bswapdi 2nd splitter): Don't swap words + twice for little-endian. + (ashrdi3_no_power, ashrdi3): Support little-endian. + + 2013-04-25 Alan Modra + * config.gcc: Support little-endian powerpc-linux targets. + * config/rs6000/linux.h (LINK_OS_LINUX_EMUL): Define. + (LINK_OS_LINUX_SPEC): Define. + * config/rs6000/linuxspe.h (TARGET_DEFAULT): + Preserve MASK_LITTLE_ENDIAN. + * config/rs6000/default64.h (TARGET_DEFAULT): Likewise. + * config/rs6000/linuxaltivec.h (TARGET_DEFAULT): Likewise. + * config/rs6000/linux64.h (OPTION_LITTLE_ENDIAN): Don't zero. + (LINK_OS_LINUX_EMUL32, LINK_OS_LINUX_EMUL64): Define. + (LINK_OS_LINUX_SPEC32, LINK_OS_LINUX_SPEC64): Use above. + * config/rs6000/rs6000.c (output_toc): Don't use .tc for TARGET_ELF. + Correct fp word order for little-endian. Don't shift toc entries + smaller than a word for little-endian. + * config/rs6000/rs6000.md (bswaphi2, bswapsi2 split): Comment. + (bswapdi2 splits): Correct low-part subreg for little-endian. + Remove wrong BYTES_BIG_ENDIAN tests, and rename vars to remove + low/high where such is correct only for be. + * config/rs6000/sysv4.h (SUBTARGET_OVERRIDE_OPTIONS): Allow + little-endian for -mcall-aixdesc. + +2013-06-12 Martin Jambor + + * ipa-cp.c (ipa_get_indirect_edge_target_1): Check that param_index is + within bounds at the beginning of the function. + +2013-06-12 Jakub Jelinek + + PR tree-optimization/57537 + * tree-vect-patterns.c (vect_recog_widen_mult_pattern): If + vect_handle_widen_op_by_const, convert oprnd1 to half_type1. + +2013-06-10 Uros Bizjak + + Backport from mainline + 2013-06-10 Uros Bizjak + + * config/alpha/alpha.c (alpha_emit_xfloating_compare): Also use + cmp_code to construct REG_EQUAL note. + +2013-06-10 Oleg Endo + + Backport from mainline + 2013-05-20 Oleg Endo + + PR target/56547 + * config/sh/sh.md (fmasf4): Remove empty constraints strings. + (*fmasf4, *fmasf4_media): New insns. + +2013-06-09 Jakub Jelinek + + PR target/57568 + * config/i386/i386.md (TARGET_READ_MODIFY_WRITE peepholes): Ensure + that operands[2] doesn't overlap with operands[0]. + +2013-06-07 Richard Sandiford + + * recog.c (offsettable_address_addr_space_p): Fix calculation of + address mode. Move pointer mode initialization to the same place. + +2013-06-07 Sofiane Naci + + Backport from mainline + * config/aarch64/aarch64.md (*movdi_aarch64): Define "simd" attribute. + +2013-06-07 Uros Bizjak + + Backport from mainline + 2013-06-05 Uros Bizjak + + * config/alpha/alpha.c (alpha_emit_conditional_move): Swap all + GE, GT, GEU and GTU compares, modulo DImode compares with zero. + + Backport from mainline + 2013-05-23 Uros Bizjak + + PR target/57379 + * config/alpha/alpha.md (unspec): Add UNSPEC_XFLT_COMPARE. + * config/alpha/alpha.c (alpha_emit_xfloating_compare): Construct + REG_EQUAL note as UNSPEC_XFLT_COMPARE unspec. + +2013-06-04 Bill Schmidt + + Backport from mainline. + 2013-05-22 Bill Schmidt + + * config/rs6000/rs6000.h (MALLOC_ABI_ALIGNMENT): New #define. + +2013-06-03 James Greenhalgh + + Backport from mainline. + 2013-04-25 James Greenhalgh + + * config/aarch64/aarch64.c (aarch64_print_operand): Fix asm_fprintf + format specifier in 'X' case. + +2013-05-31 Richard Henderson + + PR target/56742 + * config/i386/i386.c (ix86_seh_fixup_eh_fallthru): New. + (ix86_reorg): Call it. + +2012-05-31 Jakub Jelinek + + * BASE-VER: Set to 4.8.2. + * DEV-PHASE: Set to prerelease. + +2013-05-31 Release Manager + + * GCC 4.8.1 released. + +2013-05-24 Greta Yorsh + + Backport from mainline + 2013-05-02 Greta Yorsh + + PR target/56732 + * config/arm/arm.c (arm_expand_epilogue): Check really_return before + generating simple_return for naked functions. + +2013-05-24 Alexander Ivchenko + + PR tree-ssa/57385 + * tree-ssa-sccvn.c (fully_constant_vn_reference_p): Check + that index is not negative. + +2013-05-23 Martin Jambor + + PR middle-end/57347 + * tree.h (contains_bitfld_component_ref_p): Declare. + * tree-sra.c (contains_bitfld_comp_ref_p): Move... + * tree.c (contains_bitfld_component_ref_p): ...here. Adjust its caller. + * ipa-prop.c (determine_known_aggregate_parts): Check that LHS does + not access a bit-field. Assert all final offsets are byte-aligned. + +2013-05-23 Richard Biener + + PR rtl-optimization/57341 + * ira.c (validate_equiv_mem_from_store): Use anti_dependence + instead of true_dependence. + +2013-05-23 Jakub Jelinek + + PR middle-end/57344 + * expmed.c (store_split_bit_field): If op0 is a REG or + SUBREG of a REG, don't lower unit. Handle unit not being + always BITS_PER_WORD. + +2013-05-22 Uros Bizjak + + PR target/57356 + * config/i386/i386.md (*movti_internal_rex64): Emit movaps/movups + for non-sse2 targets. + (*movti_internal): Simplify mode attribute calculation. + +2013-05-22 Richard Biener + + Backport from mainline + 2013-05-21 Richard Biener + + PR tree-optimization/57318 + * tree-ssa-loop-ivcanon.c (tree_estimate_loop_size): Do not + estimate stmts with side-effects as likely eliminated. + + 2013-05-21 Richard Biener + + PR tree-optimization/57330 + * cgraph.c (cgraph_redirect_edge_call_stmt_to_callee): Properly + preserve the call stmts fntype. + + 2013-05-21 Richard Biener + + PR tree-optimization/57303 + * tree-ssa-sink.c (statement_sink_location): Properly handle + self-assignments. + +2013-05-21 Magnus Granberg + + PR plugins/56754 + * Makefile.in (PLUGIN_HEADERS): Add $(TARGET_H). + +2013-05-21 Eric Botcazou + + Backport from mainline + 2013-05-14 Eric Botcazou + + * config/sparc/sp64-elf.h (CPP_SUBTARGET_SPEC): Delete. + * config/sparc/openbsd64.h (CPP_SUBTARGET_SPEC): Likewise. + +2013-05-17 Jakub Jelinek + + PR rtl-optimization/57281 + PR rtl-optimization/57300 + * config/i386/i386.md (extendsidi2_1 dead reg splitter): Remove. + (extendsidi2_1 peephole2s): Add instead 2 new peephole2s, that undo + what the other splitter did if the registers are dead. + +2013-05-17 Uros Bizjak + + Backport from mainline + 2013-05-16 Uros Bizjak + + * config/i386/driver-i386.c (host_detect_local_cpu): Determine + cache parameters using detect_caches_amd also for CYRIX, + NSC and TM2 signatures. + + 2013-05-16 Uros Bizjak + Dzianis Kahanovich + + PR target/45359 + PR target/46396 + * config/i386/driver-i386.c (host_detect_local_cpu): Detect + VIA/Centaur processors and determine their cache parameters + using detect_caches_amd. + + 2013-05-15 Uros Bizjak + + * config/i386/i386.c (ix86_option_override_internal): Update + processor_alias_table for missing PTA_PRFCHW and PTA_FXSR flags. Add + PTA_POPCNT to corei7 entry. Do not enable SSE prefetch on + non-SSE 3dNow! targets. Enable TARGET_PRFCHW for TARGET_3DNOW targets. + * config/i386/i386.md (prefetch): Enable for TARGET_PRFCHW instead + of TARGET_3DNOW. + (*prefetch_3dnow): Enable for TARGET_PRFCHW only. + +2013-05-17 Jakub Jelinek + + * gcc.c (SANITIZER_SPEC): Reject -fsanitize=address -fsanitize=thread + linking. + + PR tree-optimization/57051 + * fold-const.c (const_binop) : Fix BYTES_BIG_ENDIAN handling. + +2013-05-16 Jakub Jelinek + + * omp-low.c (extract_omp_for_data): For collapsed loops, + if at least one of the loops is known at compile time to + iterate zero times, set count to 0. + (expand_omp_regimplify_p): New function. + (expand_omp_for_generic): For collapsed loops, if at least + one of the loops isn't known to iterate at least once, + add runtime check with setting count to 0. + (expand_omp_for_static_nochunk, expand_omp_for_static_chunk): + For unsigned types if it isn't known at compile time that + the loop will iterate at least once, add runtime check to bypass + the whole loop if initial condition isn't true. + +2013-05-14 Jakub Jelinek + + PR middle-end/57251 + * expr.c (expand_expr_real_2) : Handle + the case when both op0 and op1 have VOIDmode. + +2013-05-13 Jakub Jelinek + + PR tree-optimization/57230 + * tree-ssa-strlen.c (handle_char_store): Add missing integer_zerop + check. + +2013-05-12 Joern Rennecke + + * config/epiphany/epiphany.c (epiphany_init): Check size of + NUM_MODES_FOR_MODE_SWITCHING. + (epiphany_expand_prologue): + Remove CONFIG_REGNUM initial value handling code. + (epiphany_optimize_mode_switching): Handle EPIPHANY_MSW_ENTITY_CONFIG. + (epiphany_mode_needed, epiphany_mode_entry_exit): Likewise. + (emit_set_fp_mode, epiphany_mode_after): Likewise. + (epiphany_mode_needed) : + Don't return 1 for FP_MODE_NONE. + * config/epiphany/epiphany.h (NUM_MODES_FOR_MODE_SWITCHING): + Add value for EPIPHANY_MSW_ENTITY_CONFIG. + (EPIPHANY_MSW_ENTITY_CONFIG, EPIPHANY_MSW_ENTITY_NUM): Define. + * config/epiphany/epiphany.md (save_config): New pattern. + +2013-05-10 Sebastian Huber + + * config/arm/t-rtems-eabi: Remove mthumb/march=armv7 multilib. + Add mthumb/march=armv7-a multilib. + Add mthumb/march=armv7-r multilib. + Add mthumb/march=armv7-a/mfpu=neon/mfloat-abi=hard multilib. + +2013-05-10 Ralf Corsépius + + PR target/57237 + * config/v850/t-rtems: Add more multilibs. + +2013-05-10 Richard Biener + + PR tree-optimization/57214 + * tree-ssa-loop-ivcanon.c (propagate_constants_for_unrolling): Do + not propagate from SSA names that occur in abnormal PHI nodes. + +2013-05-10 Alan Modra + + PR target/55033 + * varasm.c (default_elf_select_section): Move !DECL_P check.. + (get_named_section): ..to here before calling get_section_name. + Adjust assertion. + (default_section_type_flags): Add DECL_P check. + * config/i386/winnt.c (i386_pe_section_type_flags): Likewise. + * config/rs6000/rs6000.c (rs6000_xcoff_section_type_flags): Likewise. + +2013-05-09 Joern Rennecke + + * config/epiphany/epiphany.c (epiphany_expand_prologue): + When using gen_stack_adjust_str with a register offset, add a + REG_FRAME_RELATED_EXPR note. + +2013-05-09 Martin Jambor + + PR middle-end/56988 + * ipa-prop.h (ipa_agg_replacement_value): New flag by_ref. + * ipa-cp.c (find_aggregate_values_for_callers_subset): Fill in the + by_ref flag of ipa_agg_replacement_value structures. + (known_aggs_to_agg_replacement_list): Likewise. + * ipa-prop.c (write_agg_replacement_chain): Stream by_ref flag. + (read_agg_replacement_chain): Likewise. + (ipcp_transform_function): Also check that by_ref flags match. + +2013-05-08 Diego Novillo + + PR bootstrap/54659 + + Revert: + + 2012-08-17 Diego Novillo + + PR bootstrap/54281 + * configure.ac: Add libintl.h to AC_CHECK_HEADERS list. + * config.in: Regenerate. + * configure: Regenerate. + * intl.h: Always include libintl.h if HAVE_LIBINTL_H is + set. + +2013-05-08 Paolo Carlini + + PR tree-optimization/57200 + * tree-ssa-loop-niter.c (do_warn_aggressive_loop_optimizations): + Only call inform if the preceding warning_at returns true. + +2013-05-07 Jakub Jelinek + + PR tree-optimization/57149 + * tree-ssa-uninit.c (uninit_undefined_value_p): New inline. + (can_skip_redundant_opnd, compute_uninit_opnds_pos, + collect_phi_def_edges, execute_late_warn_uninitialized): Use + uninit_undefined_value_p instead of ssa_undefined_value_p. + + PR debug/57184 + * expr.c (expand_expr_addr_expr_1): Handle COMPOUND_LITERAL_EXPR + for modifier == EXPAND_INITIALIZER. + +2013-05-07 Richard Biener + + Backport from mainline + 2013-05-06 Richard Biener + + PR tree-optimization/57185 + * tree-parloops.c (add_field_for_reduction): Handle anonymous + SSA names properly. + + 2013-04-19 Richard Biener + + PR tree-optimization/57000 + * tree-ssa-reassoc.c (pass_reassoc): Add TODO_update_ssa_only_virtuals. + +2013-05-06 Michael Meissner + + Backport from trunk + 2013-05-03 Michael Meissner + + PR target/57150 + * config/rs6000/rs6000.h (HARD_REGNO_CALLER_SAVE_MODE): Use DFmode + to save TFmode registers and DImode to save TImode registers for + caller save operations. + (HARD_REGNO_CALL_PART_CLOBBERED): TFmode and TDmode do not need to + mark being partially clobbered since they only use the first + double word. + + * config/rs6000/rs6000.c (rs6000_init_hard_regno_mode_ok): TFmode + and TDmode only use the upper 64-bits of each VSX register. + +2013-05-06 Oleg Endo + + PR target/57108 + * config/sh/sh.md (tstsi_t_zero_extract_eq): Use QIHISIDI mode iterator. + +2013-05-06 Uros Bizjak + + Backport from mainline + 2013-05-06 Uros Bizjak + + PR target/57106 + * config/i386/i386.c (add_parameter_dependencies): Add dependence + between "first_arg" and "insn", not "last" and "insn". + +2013-05-03 Jakub Jelinek + + PR rtl-optimization/57130 + * combine.c (make_compound_operation) : Pass + SET instead of COMPARE as in_code to the recursive call + if needed. + + Backported from mainline + 2013-04-26 Jakub Jelinek + + PR tree-optimization/57051 + * fold-const.c (const_binop): Handle VEC_LSHIFT_EXPR + and VEC_RSHIFT_EXPR if shift count is a multiple of element + bitsize. + + 2013-04-12 Marc Glisse + + * fold-const.c (fold_binary_loc): Call const_binop also for mixed + vector-scalar operations. + +2013-05-03 Marek Polacek + + Backport from mainline + 2013-04-25 Marek Polacek + + PR tree-optimization/57066 + * builtins.c (fold_builtin_logb): Return +Inf for -Inf. + +2013-05-02 Vladimir Makarov + + Backport from mainline + 2013-05-02 Vladimir Makarov + + * lra-constraints.c (process_alt_operands): Add checking alt + number to choose the best alternative. + + 2013-05-01 Vladimir Makarov + + PR target/57091 + * lra-constraints.c (best_small_class_operands_num): Remove. + (process_alt_operands): Remove small_class_operands_num. Take + small classes operands into losers and only if the operand is not + matched. Modify debugging output. + (curr_insn_transform): Remove best_small_class_operands_num. + Print insn name. + +2013-05-02 Vladimir Makarov + + Backport from mainline + 2013-04-29 Vladimir Makarov + + PR target/57097 + * lra-constraints.c (process_alt_operands): Discourage a bit more + using memory for pseudos. Print cost dump for alternatives. + Modify cost values for conflicts with early clobbers. + (curr_insn_transform): Spill pseudos reassigned to NO_REGS. + +2013-05-02 Vladimir Makarov + + Backport from mainline + 2013-04-24 Vladimir Makarov + + PR rtl-optimizations/57046 + * lra-constraints (split_reg): Set up lra_risky_transformations_p + for multi-reg splits. + +2013-05-02 Vladimir Makarov + + Backport from mainline + 2013-04-22 Vladimir Makarov + + PR target/57018 + * lra-eliminations.c (mark_not_eliminable): Prevent elimination of + a set sp if no stack realignment. + +2013-05-02 Vladimir Makarov + + Backport from mainline + 2013-04-18 Vladimir Makarov + + PR rtl-optimization/56999 + * lra-coalesce.c (coalescable_pseudo_p): Remove 2nd parameter and + related code. + (lra_coalesce): Remove split_origin_bitmap and related code. + * lra.c (lra): Coalesce after undoing inheritance. Recreate live + ranges if necessary. + +2013-05-02 Vladimir Makarov + + Backport from mainline + 2013-04-19 Vladimir Makarov + + PR rtl-optimization/56847 + * lra-constraints.c (process_alt_operands): Discourage alternative + with non-matche doffsettable memory constraint fro memory with + known offset. + +2013-05-02 Ian Bolton + + Backport from mainline + 2013-03-28 Ian Bolton + + * config/aarch64/aarch64.md (aarch64_can_eliminate): Keep frame + record only when desired or required. + +2013-04-30 Jakub Jelinek + + PR tree-optimization/57104 + * tsan.c (instrument_expr): Don't instrument accesses to + DECL_HARD_REGISTER VAR_DECLs. + +2013-04-30 Uros Bizjak + + Backport from mainline + 2013-04-29 Uros Bizjak + + PR target/44578 + * config/i386/i386.md (*zero_extendsidi2_rex64): Add "!" to m->?*y + alternative. + (*zero_extendsidi2): Ditto. + + Backport from mainline + 2013-04-29 Uros Bizjak + + PR target/57098 + * config/i386/i386.c (ix86_expand_vec_perm): Validize constant memory. + +2013-04-29 Richard Biener + + PR middle-end/57103 + * tree-cfg.c (move_stmt_op): Fix condition under which to update + TREE_BLOCK. + (move_stmt_r): Remove redundant checking. + +2013-04-29 Christian Bruel + + PR target/57108 + * sh.md (tstsi_t_zero_extract_eq): Set mode for operand 0. + +2013-04-29 Jakub Jelinek + + PR tree-optimization/57083 + * tree-vrp.c (extract_range_from_binary_expr_1): For LSHIFT_EXPR with + non-singleton shift count range, zero extend low_bound for uns case. + +2013-04-28 Eric Botcazou + + * stor-layout.c (finalize_size_functions): Allocate a structure and + reset cfun before dumping the functions. + +2013-04-27 Jakub Jelinek + + PR target/56866 + * config/i386/i386.c (ix86_expand_mul_widen_evenodd): Don't + use xop_pmacsdqh if uns_p. + * config/i386/sse.md (xop_rotr3): Fix up computation of + the immediate rotate count. + +2013-04-25 Jakub Jelinek + + PR rtl-optimization/57003 + * regcprop.c (copyprop_hardreg_forward_1): If ksvd.ignore_set_reg, + call note_stores with kill_clobbered_value callback again after + killing regs_invalidated_by_call. + +2013-04-25 Ian Bolton + + Backported from mainline. + 2013-03-22 Ian Bolton + + * config/aarch64/aarch64.c (aarch64_print_operand): New + format specifier for printing a constant in hex. + * config/aarch64/aarch64.md (insv_imm): Use the X + format specifier for printing second operand. + +2013-04-24 James Greenhalgh + + Backported from mainline. + 2013-04-24 James Greenhalgh + + * config/aarch64/arm_neon.h (vld1_lane*): Fix constraints. + (vld1_dup_<8, 16, 32, 64>): Likewise. + (vld1_<8, 16, 32, 64>): Likewise. + +2013-04-24 Greta Yorsh + + Backported from mainline. + PR target/56797 + * config/arm/arm.c (load_multiple_sequence): Require SP + as base register for loads if SP is in the register list. + +2013-04-23 Bill Schmidt + Steven Bosscher + + Backported from mainline. + PR rtl-optimization/56605 + * loop-iv.c (implies_p): Handle equal RTXs and subregs. + +2013-04-22 Marek Polacek + + Backported from mainline. + 2013-04-22 Marek Polacek + + PR sanitizer/56990 + * tsan.c (instrument_expr): Don't instrument expression + in case its size is zero. + +2013-04-22 Yufeng Zhang + + Backported from mainline. + 2013-04-10 Yufeng Zhang + * config/aarch64/aarch64.c (aarch64_print_extension): New function. + (aarch64_start_file): Use the new function. + +2013-04-18 Jakub Jelinek + + PR tree-optimization/56984 + * tree-vrp.c (register_edge_assert_for_2): For (x >> M) < N + and (x >> M) >= N don't register any assertion if N << M is the + minimum value. + +2013-04-17 David Edelsohn + + PR target/56948 + * config/rs6000/vsx.md (vsx_mov): Add j->r alternative. + +2013-04-15 Jakub Jelinek + + PR tree-optimization/56962 + * gimple-ssa-strength-reduction.c (record_increment): Only set + initializer if gimple_assign_rhs_code is {,POINTER_}PLUS_EXPR and + either rhs1 or rhs2 is equal to c->base_expr. + +2013-04-15 Andreas Krebbel + + * emit-rtl.c (reset_all_used_flags): New function. + (verify_rtl_sharing): Call reset_all_used_flags before and after + performing the checks. + +2013-04-15 Eric Botcazou + + PR target/56890 + * config/sparc/sparc.c (enum sparc_mode_class): Add H_MODE value. + (S_MODES): Set H_MODE bit. + (SF_MODES): Set only S_MODE and SF_MODE bits. + (DF_MODES): Set SF_MODES and only D_MODE and DF_MODE bits. + (sparc_init_modes) : Set H_MODE bit for sub-word modes. + : Do not set SF_MODE for sub-word modes. + : Likewise. + +2013-04-12 Vladimir Makarov + + PR target/56903 + * config/i386/i386.c (ix86_hard_regno_mode_ok): Add + lra_in_progress for return. + +2013-04-12 Jakub Jelinek + + PR tree-optimization/56918 + PR tree-optimization/56920 + * fold-const.c (int_const_binop_1): Use op1.mul_with_sign (op2, ...) + instead of op1 - op2. Pass 2 * TYPE_PRECISION (type) as second + argument to rshift method. + +2013-04-12 Andreas Krebbel + + * ifcvt.c (end_ifcvt_sequence): Mark a and b for unsharing as + well. + +2013-04-11 Marek Polacek + + PR tree-optimization/48184 + * params.def (PARAM_ALIGN_THRESHOLD): Increase the minimum + value to 1. + +2013-04-11 James Greenhalgh + + Backported from mainline. + 2013-04-11 James Greenhalgh + + * config/aarch64/aarch64-simd.md (aarch64_vcond_internal): Fix + floating-point vector comparisons against 0. + +2013-04-11 Jakub Jelinek + + PR tree-optimization/56899 + * fold-const.c (extract_muldiv_1): Apply distributive law + only if TYPE_OVERFLOW_WRAPS (ctype). + +2013-04-10 David S. Miller + + * config/sparc/sparc.h (ASM_CPU_SPEC): Pass -Av8 if -mcpu=supersparc + or -mcpu=hypersparc. + +2013-04-10 Jakub Jelinek + + Backported from mainline + 2013-04-09 Jakub Jelinek + + PR middle-end/56883 + * omp-low.c (expand_omp_for_generic, expand_omp_for_static_nochunk, + expand_omp_for_static_chunk): Use simple_p = true in + force_gimple_operand_gsi calls when assigning to addressable decls. + +2013-04-09 Marek Polacek + + PR tree-optimization/48762 + * params.def (PARAM_MAX_CSE_INSNS): Increase the minimum + value to 1. + +2013-04-08 Andreas Krebbel + + * config/s390/s390.c (s390_expand_insv): Only accept insertions + within mode size. + +2013-04-08 Marek Polacek + + PR rtl-optimization/48182 + * params.def (PARAM_MIN_CROSSJUMP_INSNS): Increase the minimum + value to 1. + +2013-04-06 John David Anglin + + PR target/55487 + * config/pa/pa.c (legitimize_pic_address): Before incrementing label + nuses, make sure we have a label. + +2013-04-04 Ian Lance Taylor + + Backport from mainline: + * doc/standards.texi (Standards): The Go frontend supports the Go + 1 language standard. + +2013-04-04 Marek Polacek + + Backport from mainline: + 2013-04-04 Marek Polacek + + PR tree-optimization/48186 + * predict.c (maybe_hot_frequency_p): Return false if + HOT_BB_FREQUENCY_FRACTION is 0. + (cgraph_maybe_hot_edge_p): Likewise. + +2013-04-04 Kyrylo Tkachov + + Backport from mainline: + 2013-03-25 Kyrylo Tkachov + + PR target/56720 + * config/arm/iterators.md (v_cmp_result): New mode attribute. + * config/arm/neon.md (vcond): Handle unordered cases. + +2013-04-04 Richard Biener + + PR tree-optimization/56837 + * tree-loop-distribution.c (classify_partition): For non-zero + values require that the value has the same precision as its + mode to be useful as memset value. + +2013-04-03 Roland McGrath + + Backport from mainline: + 2013-03-26 Roland McGrath + + * config/arm/arm.c (arm_print_operand: case 'w'): Use fputs rather + than fprintf with a non-constant, non-format string. + +2013-04-03 Marek Polacek + + Backport from mainline: + 2013-04-03 Marek Polacek + + PR sanitizer/55702 + * tsan.c (instrument_func_exit): Allow BUILT_IN_RETURN + functions. + +2013-04-03 Richard Biener + + PR tree-optimization/56817 + * tree-ssa-loop-ivcanon.c (tree_unroll_loops_completely): + Split out ... + (tree_unroll_loops_completely_1): ... new function to manually + walk the loop tree, properly defering outer loops of unrolled + loops to later iterations. + +2013-04-02 Jakub Jelinek + + PR rtl-optimization/56745 + * ifcvt.c (cond_exec_find_if_block): Don't try to optimize + if then_bb has no successors and else_bb is EXIT_BLOCK_PTR. + +2013-04-02 Wei Mi + + * config/i386/i386.c (ix86_rtx_costs): Set proper rtx cost for + ashl3_mask, *3_mask and + *3_mask in i386.md. + +2013-04-01 Wei Mi + + * config/i386/i386.md (*ashl3_mask): Rewrite as define_insn. + Truncate operand 2 using %b asm operand modifier. + (*3_mask): Ditto. + (*3_mask): Ditto. + +2013-04-01 Uros Bizjak + + * config/i386/i386.md (*movsf_internal): Change type of + alternatives 3,4 to imov. + +2013-03-29 Paolo Carlini + + PR lto/56777 + * doc/invoke.texi ([-fwhole-program]): Fix typo. + +2013-03-29 Kirill Yukhin + + * config/i386/avx2intrin.h (_mm256_broadcastsi128_si256): + Fix declaration name. + +2013-03-28 Gerald Pfeifer + + * doc/invoke.texi (AVR Options): Tweak link for AVR-LibC user manual. + * doc/extend.texi (Named Address Spaces): Ditto. + (Variable Attributes): Ditto. + +2013-03-28 Eric Botcazou + + * toplev.c (process_options): Do not disable -fomit-frame-pointer on a + general basis if unwind info is requested and ACCUMULATE_OUTGOING_ARGS + is not enabled. + +2013-03-27 Walter Lee + + Backport from mainline: + 2013-03-27 Walter Lee + + * config/tilegx/tilegx.c (tilegx_expand_prologue): Avoid + double-decrement of next_scratch_regno. + +2013-03-27 Walter Lee + + Backport from mainline: + 2013-03-27 Walter Lee + + * config/tilegx/tilegx.md (insn_v1mulu): Fix predicates on + input operands. + (insn_v1mulus): Ditto. + (insn_v2muls): Ditto. + +2013-03-27 Walter Lee + + Backport from mainline: + 2013-03-27 Walter Lee + + * config/tilegx/tilegx.h (ASM_OUTPUT_ADDR_VEC_ELT): Delete + extra tab. + (ASM_OUTPUT_ADDR_DIFF_ELT): Ditto. + +2013-03-27 Walter Lee + + Backport from mainline: + 2013-03-27 Walter Lee + + * config/tilegx/tilegx.md (*sibcall_insn): Fix type atribute for jr. + (*sibcall_value): Ditto. + +2013-03-27 Walter Lee + + Backport from mainline: + 2013-03-27 Walter Lee + + * config/tilegx/tilegx.md (insn_mnz_): Replaced by ... + (insn_mnz_v8qi): ... this ... + (insn_mnz_v4hi): ... and this. Replace (const_int 0) with the + vector equivalent. + (insn_vmnz): Replaced by ... + (insn_v1mnz): ... this ... + (insn_v2mnz): ... and this. Replace (const_int 0) with the vector + equivalent. + (insn_mz_): Replaced by ... + (insn_mz_v8qi): ... this ... + (insn_mz_v4hi): ... and this. Replace (const_int 0) with the + vector equivalent. + (insn_vmz): Replaced by ... + (insn_v1mz): ... this ... + (insn_v2mz): ... and this. Replace (const_int 0) with the vector + equivalent. + +2013-03-26 Eric Botcazou + + * doc/invoke.texi (SPARC options): Remove -mlittle-endian. + +2013-03-26 Sebastian Huber + + * config/rtems.opt: Add -pthread option. + +2013-03-26 Sofiane Naci + + * config/aarch64/aarch64.c (aarch64_classify_address): Support + PC-relative load in SI modes and above only. + +2013-03-26 Walter Lee + + Backport from mainline: + 2013-03-26 Walter Lee + + * config/tilegx/tilegx.h (PROFILE_BEFORE_PROLOGUE): Define. + * config/tilegx/tilepro.h (PROFILE_BEFORE_PROLOGUE): Define. + +2013-03-26 Walter Lee + + Backport from mainline: + 2013-03-25 Walter Lee + + * config/tilegx/tilegx-builtins.h (enum tilegx_builtin): Add + TILEGX_INSN_SHUFFLEBYTES1. + * config/tilegx/tilegx.c (tilegx_builtin_info): Add entry for + shufflebytes1. + (tilegx_builtins): Ditto. + * config/tilegx/tilegx.md (insn_shufflebytes1): New pattern. + +2013-03-26 Walter Lee + + Backport from mainline: + 2013-03-25 Walter Lee + + * config/tilegx/tilegx.c (expand_set_cint64_one_inst): Inline + tests for constraint J, K, N, P. + +2013-03-26 Walter Lee + + Backport from mainline: + 2013-03-25 Walter Lee + + * config/tilegx/tilegx.c (tilegx_asm_preferred_eh_data_format): + Use indirect/pcrel encoding. + * config/tilepro/tilepro.c (tilepro_asm_preferred_eh_data_format): + Ditto. + +2013-03-25 Richard Biener + + PR middle-end/56694 + * tree-eh.c (lower_eh_must_not_throw): Strip BLOCKs from the + must-not-throw stmt location. + +2012-03-22 Jakub Jelinek + + * BASE-VER: Set to 4.8.1. + * DEV-PHASE: Set to prerelease. + +2013-03-22 Release Manager + + * GCC 4.8.0 released. + +2013-03-21 Walter Lee + + * config/tilegx/sync.md (atomic_test_and_set): New pattern. + +2013-03-21 Mark Wielaard + + * dwarf2out.c (size_of_aranges): Skip DECL_IGNORED_P functions. + +2013-03-20 Richard Biener + + PR tree-optimization/56661 + * tree-ssa-sccvn.c (visit_use): Only value-number calls if + the result does not have to be distinct. + +2013-03-20 Jakub Jelinek + + PR tree-optimization/56635 + * tree-ssa-phiopt.c (cond_if_else_store_replacement_1): Give up + if lhs of then_assign and else_assign don't have compatible types. + +2013-03-17 Jakub Jelinek + + PR target/56640 + * config/arm/arm.h (REG_CLASS_NAMES): Add "SFP_REG" and "AFP_REG" + class names. Remove trailing comma after "ALL_REGS". + +2013-03-16 Jakub Jelinek + + * DEV-PHASE: Set to prerelease. + 2013-03-14 Andi Kleen PR target/56619 @@ -10,30 +9896,31 @@ * configure.ac: Add MicroBlaze TLS support detection. * configure: Regenerate. - * config/microblaze/microblaze-protos.h: (microblaze_cannot_force_const_mem, - microblaze_tls_referenced_p, symbol_mentioned_p, label_mentioned_p): - Add prototypes. - * config/microblaze/microblaze.c (microblaze_address_type): Add ADDRESS_TLS - and tls_reloc address types. + * config/microblaze/microblaze-protos.h + (microblaze_cannot_force_const_mem, microblaze_tls_referenced_p, + symbol_mentioned_p, label_mentioned_p): Add prototypes. + * config/microblaze/microblaze.c (microblaze_address_type): Add + ADDRESS_TLS and tls_reloc address types. (microblaze_address_info): Add tls_reloc. (TARGET_HAVE_TLS): Define. (get_tls_get_addr, microblaze_tls_symbol_p, microblaze_tls_operand_p_1, - microblaze_tls_referenced_p, microblaze_cannot_force_const_mem, - symbol_mentioned_p, label_mentioned_p, tls_mentioned_p, load_tls_operand, - microblaze_call_tls_get_addr, microblaze_legitimize_tls_address): New functions. + microblaze_tls_referenced_p, microblaze_cannot_force_const_mem, + symbol_mentioned_p, label_mentioned_p, tls_mentioned_p, + load_tls_operand, microblaze_call_tls_get_addr, + microblaze_legitimize_tls_address): New functions. (microblaze_classify_unspec): Handle UNSPEC_TLS. (get_base_reg): Use microblaze_tls_symbol_p. (microblaze_classify_address): Handle TLS. - (microblaze_legitimate_pic_operand): Use symbol_mentioned_p, label_mentioned_p - and microblaze_tls_referenced_p. + (microblaze_legitimate_pic_operand): Use symbol_mentioned_p, + label_mentioned_p and microblaze_tls_referenced_p. (microblaze_legitimize_address): Handle TLS. (microblaze_address_insns): Handle ADDRESS_TLS. (pic_address_needs_scratch): Handle TLS. (print_operand_address): Handle TLS. (microblaze_expand_prologue): Check TLS_NEEDS_GOT. (microblaze_expand_move): Handle TLS. - (microblaze_legitimate_constant_p): Check microblaze_cannot_force_const_mem - and microblaze_tls_symbol_p. + (microblaze_legitimate_constant_p): Check + microblaze_cannot_force_const_mem and microblaze_tls_symbol_p. (TARGET_CANNOT_FORCE_CONST_MEM): Define. * config/microblaze/microblaze.h (TLS_NEEDS_GOT): Define (PIC_OFFSET_TABLE_REGNUM): Set. @@ -41,7 +9928,8 @@ * config/microblaze/microblaze.md (UNSPEC_TLS): Define. (addsi3, movsi_internal2, movdf_internal): Update constraints * config/microblaze/predicates.md (arith_plus_operand): Define - (move_operand): Redefine as move_src_operand, check microblaze_tls_referenced_p. + (move_operand): Redefine as move_src_operand, check + microblaze_tls_referenced_p. 2013-03-14 Ian Bolton @@ -139,7 +10027,7 @@ PR target/56591 * config/avr/avr.c (avr_print_operand): Add space after '%c' in output_operand_lossage message. - + 2013-03-11 Richard Earnshaw PR target/56470 @@ -484,10 +10372,10 @@ 2013-03-04 David Holsgrove - * config/microblaze/microblaze.c (microblaze_valid_pic_const): New - (microblaze_legitimate_pic_operand): Likewise - * config/microblaze/microblaze.h (LEGITIMATE_PIC_OPERAND_P): calls - new function microblaze_legitimate_pic_operand + * config/microblaze/microblaze.c (microblaze_valid_pic_const): New. + (microblaze_legitimate_pic_operand): Likewise. + * config/microblaze/microblaze.h (LEGITIMATE_PIC_OPERAND_P): Call + new function microblaze_legitimate_pic_operand. * config/microblaze/microblaze-protos.h (microblaze_legitimate_pic_operand): Declare. @@ -538,8 +10426,8 @@ DRIVER_SELF_SPECS. * config/microblaze/microblaze.md: New bswapsi2 and bswaphi2. instructions emitted if TARGET_REORDER. - * config/microblaze/microblaze.opt: New option -mxl-reorder set to 1 - or 0 for -m/-mno case, but initialises as 2 to detect default use case + * config/microblaze/microblaze.opt: New option -mxl-reorder set to 1 + or 0 for -m/-mno case, but initialises as 2 to detect default use case separately. 2013-03-01 Xinliang David Li @@ -576,12 +10464,10 @@ (Other MIPS Built-in Functions): Move last MIPS entry before "picoChip Built-in Functions". (SH Built-in Functions): Move after RX Built-in Functions. - * doc/gcc.texi (Introduction): Change order in @menu - to match @node. + * doc/gcc.texi (Introduction): Change order in @menu to match @node. * doc/md.texi (Constraints): Ditto. * gty.texi (Type Information): Ditto. - (User-provided marking routines for template types): Make - subsection. + (User-provided marking routines for template types): Make subsection. * doc/invoke.texi (AArch64 Options): Move before "Adapteva Epiphany Options". @@ -709,8 +10595,7 @@ pointer_set_destroy on not_executed_last_iteration. PR middle-end/56461 - * tree-vect-loop.c (vectorizable_reduction): Release vect_defs - vector. + * tree-vect-loop.c (vectorizable_reduction): Release vect_defs vector. PR middle-end/56461 * ipa-pure-const.c (propagate): Use FOR_EACH_FUNCTION instead of @@ -871,8 +10756,9 @@ Iain Sandoe Nathan Froyd Chao-ying Fu - * doc/extend.texi: (micromips, nomicromips, nocompression): - Document new function attributes. + + * doc/extend.texi (micromips, nomicromips, nocompression): + Document new function attributes. * doc/invoke.texi (minterlink-compressed, mmicromips, m14k, m14ke, m14kec): Document new options. (minterlink-mips16): Update documentation. @@ -1021,8 +10907,8 @@ Nathan Froyd Chao-ying Fu - * doc/extend.texi: (micromips, nomicromips, nocompression): - Document new function attributes. + * doc/extend.texi (micromips, nomicromips, nocompression): + Document new function attributes. * doc/invoke.texi (minterlink-compressed, mmicromips, m14k, m14ke, m14kec): Document new options. (minterlink-mips16): Update documentation. @@ -1185,8 +11071,8 @@ ((dword_type) -1) << (BITS_PER_WORD - 1). Improve multiplication by ((dword_type) 1) << (BITS_PER_WORD - 1). Avoid undefined behavior in the compiler if coeff is HOST_WIDE_INT_MIN. - (expand_divmod): Don't make ext_op1 static, change it's type to - uhwi. Avoid undefined behavior in -INTVAL (op1). + (expand_divmod): Don't make ext_op1 static, change it's type to uhwi. + Avoid undefined behavior in -INTVAL (op1). PR rtl-optimization/50339 * lower-subreg.h (struct lower_subreg_choices): Add splitting_ashiftrt @@ -1257,8 +11143,8 @@ 2013-02-20 Jan Hubicka PR tree-optimization/56265 - * ipa-prop.c (ipa_make_edge_direct_to_target): Fixup callgraph when target is - referenced for firs ttime. + * ipa-prop.c (ipa_make_edge_direct_to_target): Fixup callgraph when + target is referenced for first time. 2013-02-20 Richard Biener @@ -1269,8 +11155,7 @@ not return anything. (rename_ssa_copies): Do not remove unused locals. * tree-ssa-ccp.c (do_ssa_ccp): Likewise. - * tree-ssanames.c (pass_release_ssa_names): Remove unused - locals first. + * tree-ssanames.c (pass_release_ssa_names): Remove unused locals first. * passes.c (execute_function_todo): Do not schedule unused locals removal if cleanup_tree_cfg did something. * tree-ssa-live.c (remove_unused_locals): Dump statistics @@ -1326,7 +11211,7 @@ * config/microblaze/microblaze.c: microblaze_has_clz = 0 Add version check for v8.10.a to enable microblaze_has_clz - * config/microblaze/microblaze.h: Add TARGET_HAS_CLZ as combined + * config/microblaze/microblaze.h: Add TARGET_HAS_CLZ as combined version and TARGET_PATTERN_COMPARE check * config/microblaze/microblaze.md: New clzsi2 instruction @@ -1344,11 +11229,10 @@ 2012-02-19 Andrey Belevantsev PR middle-end/55889 - * sel-sched.c: Include ira.h. (implicit_clobber_conflict_p): New function. (moveup_expr): Use it. - * Makefile.in (sel-sched.o): Depend on ira.h. + * Makefile.in (sel-sched.o): Depend on ira.h. 2013-02-19 Richard Biener @@ -1379,8 +11263,7 @@ * genopinit.c (raw_optab_handler): Use this_fn_optabs. (swap_optab_enable): Same. (init_all_optabs): Use argument instead of global. - * tree.h (struct tree_optimization_option): New field - target_optabs. + * tree.h (struct tree_optimization_option): New field target_optabs. * expr.h (init_all_optabs): Add argument to prototype. (TREE_OPTIMIZATION_OPTABS): New. (save_optabs_if_changed): Protoize. @@ -1404,8 +11287,8 @@ PR target/56214 * config/pa/predicates.md (base14_operand): Except for BLKmode, QImode - and HImode, require all displacements to be an integer multiple of their - mode size. + and HImode, require all displacements to be an integer multiple of + their mode size. * config/pa/pa.c (pa_legitimate_address_p): For REG+BASE addresses, only allow QImode and HImode when reload is in progress and strict is true. Likewise for symbolic addresses. Use base14_operand to check @@ -1446,10 +11329,10 @@ 2013-02-16 Edgar E. Iglesias - * config/microblaze/microblaze.c (microblaze_asm_trampoline_template): + * config/microblaze/microblaze.c (microblaze_asm_trampoline_template): Replace with a microblaze version. (microblaze_trampoline_init): Adapt for microblaze. - * gcc/config/microblaze/microblaze.h (TRAMPOLINE_SIZE): Adapt for + * config/microblaze/microblaze.h (TRAMPOLINE_SIZE): Adapt for microblaze. 2013-02-16 Jakub Jelinek diff --git a/gcc/ChangeLog-2012 b/gcc/ChangeLog-2012 index ee4c57444c309..ad72535e28dc1 100644 --- a/gcc/ChangeLog-2012 +++ b/gcc/ChangeLog-2012 @@ -4535,17 +4535,17 @@ * config/i386/i386.c (ix86_function_ok_for_sibcall): Put back exception to make a sibcall if one of the functions has void return type. -2012-11-07 Manuel López-Ibáñez +2012-11-07 Manuel López-Ibáñez PR c/53063 * doc/invoke.texi (Wformat): Update. -2012-11-07 Manuel López-Ibáñez +2012-11-07 Manuel López-Ibáñez * optc-gen.awk: Factor code out to... * opt-functions.awk (lang_enabled_by): ... this new function. -2012-11-07 Manuel López-Ibáñez +2012-11-07 Manuel López-Ibáñez PR c/53063 * common.opt (Wswitch,Wswitch-default,Wswitch-enum): Move to c.opt. @@ -5673,7 +5673,7 @@ * expmed.c (store_bit_field_1): Remove test for BLKmode values. -2012-10-31 Ralf Corsépius , +2012-10-31 Ralf Corsépius , Joel Sherrill * config/sparc/t-rtems: New (Custom multilibs). @@ -5886,7 +5886,7 @@ * lra-spills.c: Likewise. * lra.c: Likewise. -2012-10-29 Manuel López-Ibáñez +2012-10-29 Manuel López-Ibáñez PR c/53066 * tree.h (FUNCTION_POINTER_TYPE_P): New. @@ -6197,7 +6197,7 @@ * config/i386/x86intrin.h: Include xsaveintrin.h, fxsrintrin.h, xsaveoptintrin.h. -2012-10-26 Ralf Corsépius +2012-10-26 Ralf Corsépius * config/avr/t-rtems: Revert previous commit. @@ -6253,7 +6253,7 @@ * lra-constraints.c (check_and_process_move): Remove #if ENABLE_ASSERT_CHECKING. -2012-10-26 Ralf Corsépius +2012-10-26 Ralf Corsépius * config/avr/rtems.h (TARGET_OS_CPP_BUILTINS): Remove __USE_INIT_FINI__. @@ -6308,7 +6308,7 @@ * lra-assigns.c (assign_by_spills): Add non-reload pseudos assigned to hard register to changed_pseudo_bitmap. -2012-10-25 Ralf Corsépius +2012-10-25 Ralf Corsépius * config.gcc (microblaze*-*-rtems*): New target. * config/microblaze/rtems.h: New. @@ -6362,7 +6362,7 @@ * config/rs6000/rs6000.c (rs6000_density_test): Use dump_enabled_p instead of dump_kind_p. -2012-10-24 Manuel López-Ibáñez +2012-10-24 Manuel López-Ibáñez PR c++/54928 * tree-diagnostic.c (maybe_unwind_expanded_macro_loc): @@ -7023,7 +7023,7 @@ * loop-iv.c (iv_number_of_iterations): Record the upper bound only if there are no further conditions on it. -2012-10-20 Manuel López-Ibáñez +2012-10-20 Manuel López-Ibáñez PR c/53063 PR c/40989 @@ -7660,7 +7660,7 @@ out of ... (forwarder_block_p): ... here. -2012-10-16 Manuel López-Ibáñez +2012-10-16 Manuel López-Ibáñez PR c/53063 PR c/40989 @@ -7671,7 +7671,7 @@ * opts.c (finish_options): Do not handle them explicitly. * opt-functions.awk (search_var_name): New. -2012-10-16 Manuel López-Ibáñez +2012-10-16 Manuel López-Ibáñez PR c/53063 PR c/40989 @@ -11075,7 +11075,7 @@ and -meb. 2012-09-13 Paolo Carlini - Manuel López-Ibáñez + Manuel López-Ibáñez PR c++/53210 * doc/invoke.texi ([Winit-self]): Document as enabled by -Wall in C++. @@ -18313,7 +18313,7 @@ (ASM_SPEC): Pass mcu options to the assembler. * doc/invoke.texi (MIPS Options): Document -mmcu and -mno-mcu. -2012-07-18 Ralf Corsépius +2012-07-18 Ralf Corsépius * config.gcc (v850-*-rtems*): New target. * config/v850/rtems.h: New. @@ -22797,7 +22797,7 @@ (generate_code_for_partition): Generate code according to partition classification. -2012-06-01 Manuel López-Ibáñez +2012-06-01 Manuel López-Ibáñez Jonathan Wakely PR c++/50134 @@ -24303,7 +24303,7 @@ (decide_is_variable_needed): Handle externals. (varpool_remove_unreferenced_decls): Likewise. -2012-05-17 Manuel López-Ibáñez +2012-05-17 Manuel López-Ibáñez * opts.c (common_handle_option): -pedantic-errors enables -Wpedantic. (enable_warning_as_error): Do not special case Wuninitialized. @@ -24631,7 +24631,7 @@ strided loads. * tree-vect-stmts.c (vect_model_load_cost): Handle strided loads. -2012-05-14 Manuel López-Ibáñez +2012-05-14 Manuel López-Ibáñez PR 53063 * doc/options.texi: (LangEnabledBy): Document it. @@ -24705,7 +24705,7 @@ * config/pa/pa.md: Use define_c_enum for "unspec" and "unspecv". -2012-05-13 Manuel López-Ibáñez +2012-05-13 Manuel López-Ibáñez * common.opt (Wtype-limits): Use EnabledBy. @@ -24739,7 +24739,7 @@ (*3): Ditto. (tf3): Ditto. -2012-05-13 Manuel López-Ibáñez +2012-05-13 Manuel López-Ibáñez * optc-gen.awk: Error instead of warning for conflicting help. @@ -24786,7 +24786,7 @@ (delete_tree_ssa): Do not call fini_phinodes. * tree-flow.h (init_phinodes, fini_phinodes): Remove. -2012-05-11 Manuel López-Ibáñez +2012-05-11 Manuel López-Ibáñez PR 53063 * doc/options.texi (EnabledBy): Document @@ -24986,14 +24986,14 @@ (xop_mulv2div2di3_low): Remove insn_and_split pattern. (xop_mulv2div2di3_high): Ditto. -2012-05-09 Manuel López-Ibáñez +2012-05-09 Manuel López-Ibáñez PR c++/53289 * diagnostic.h (diagnostic_context): Add last_location. * diagnostic.c (diagnostic_initialize): Initialize it. (diagnostic_show_locus): Use it. -2012-05-09 Manuel López-Ibáñez +2012-05-09 Manuel López-Ibáñez * doc/extend.texi (Function Attributes): Point xref to section about Pragmas. @@ -25807,13 +25807,13 @@ Same stands for reloads with type RELOAD_FOR_OUTPUT_ADDRESS and RELOAD_FOR_OUTADDR_ADDRESS. -2012-05-04 Manuel López-Ibáñez +2012-05-04 Manuel López-Ibáñez PR c++/24985 * tree-diagnostic.c (maybe_unwind_expanded_macro_loc): Show caret for macro expansion. -2012-05-03 Manuel López-Ibáñez +2012-05-03 Manuel López-Ibáñez * flags.h (flag_permissive): Do not declare. * diagnostic.c (diagnostic_report_diagnostic): Handle fpermissive @@ -26743,7 +26743,7 @@ * config/i386/i386.c (ix86_handle_struct_attribute): Use the proper predicate to discriminate types. -2012-04-30 Manuel López-Ibáñez +2012-04-30 Manuel López-Ibáñez * doc/invoke.texi (Wmissing-format-attribute): Document as an alias of Wsuggest-attribute=format. @@ -26751,7 +26751,7 @@ Wmissing-format-attribute with Wsuggest-attribute=format. (digest_init): Likewise. -2012-04-29 Manuel López-Ibáñez +2012-04-29 Manuel López-Ibáñez * opts.c (finish_options): Do not handle -Wmissing-noreturn here. * common.opt (Wmissing-noreturn): Alias of @@ -26839,7 +26839,7 @@ PR middle-end/27139 * tree-ssa-forwprop.c (combine_conversions): Handle INT->FP->INT. -2012-04-25 Manuel López-Ibáñez +2012-04-25 Manuel López-Ibáñez PR c/53130 * c-typeck.c (pop_init_level): Use %qD instead of %qT. @@ -27001,7 +27001,7 @@ * reload.c (find_reloads): Change the loop nesting when trying an alternative with swapped operands. -2012-04-26 Manuel López-Ibáñez +2012-04-26 Manuel López-Ibáñez * tree-diagnostic.c (maybe_unwind_expanded_macro_loc): Fix comment. Delete unused parameter first_exp_point_map. @@ -27135,7 +27135,7 @@ set_nonincremental_init_from_string): Pass true instead of false as IMPLICIT to add_pending_init. -2012-04-25 Manuel López-Ibáñez +2012-04-25 Manuel López-Ibáñez * c-typeck.c (pop_init_level): Improve diagnostics. @@ -27252,7 +27252,7 @@ * config/vxworks.c (vxworks_override_options): Default to strict-dwarf and dwarf_version 2. -2012-04-24 Manuel López-Ibáñez +2012-04-24 Manuel López-Ibáñez * tree-pretty-print.h (default_tree_printer): Do not declare. * tree-diagnostic.c: Include tree-pretty-print.h, tree-pass.h and @@ -27536,7 +27536,7 @@ Likewise. * tree-switch-conversion.c (build_one_array): Likewise. -2012-04-22 Manuel López-Ibáñez +2012-04-22 Manuel López-Ibáñez PR c/44774 * doc/invoke.texi (pedantic): Rename to Wpedantic. @@ -27624,7 +27624,7 @@ * fold-const.c (fold_checksum_tree): Fix VECTOR_CST case. -2012-04-21 Manuel López-Ibáñez +2012-04-21 Manuel López-Ibáñez PR 35441 * c-typeck.c (inform_declaration): New. @@ -27811,7 +27811,7 @@ * config/arm/sync.md (sync_optab): Change ior attribute to "or". -2012-04-19 Manuel López-Ibáñez +2012-04-19 Manuel López-Ibáñez PR c/52283/37985 * stmt.c (warn_if_unused_value): Skip NOP_EXPR. @@ -28041,7 +28041,7 @@ * varpoo.c (varpool_node_name): Remove. (dump_varpool_node): Use dump_symtab_base; reformat. -2012-04-18 Manuel López-Ibáñez +2012-04-18 Manuel López-Ibáñez * doc/invoke.texi (Language Independent Options): @item should be before @opindex. @@ -28908,7 +28908,7 @@ * doc/extend.texi (Type Attributes): Move paragraph. -2012-04-11 Manuel López-Ibáñez +2012-04-11 Manuel López-Ibáñez PR 24985 * diagnostic.h (show_caret): Declare. @@ -28943,7 +28943,7 @@ manipulation code we are threading through a loop header to an exit destination. -2012-04-10 Manuel López-Ibáñez +2012-04-10 Manuel López-Ibáñez * tree.h (warn_if_unused_value): Move declaration from here. * stmt.c (warn_if_unused_value): Move definition from here. @@ -29083,7 +29083,7 @@ comment block. (Sr0): Remove unused memory constraint. -2012-04-08 Manuel López-Ibáñez +2012-04-08 Manuel López-Ibáñez * tree-pretty-print.h: Update comment. @@ -30605,7 +30605,7 @@ * tree-data-ref.c (subscript_dependence_tester_1): Check all dimensions for non-conflicting access functions. -2012-03-15 Manuel López-Ibáñez +2012-03-15 Manuel López-Ibáñez PR c++/44783 * doc/invoke.texi [C++ Language Options]: Document @@ -31556,7 +31556,7 @@ in new variable 'empty'. Increase issue_rate only for non-empty insns. -2012-03-07 Ralf Corsépius +2012-03-07 Ralf Corsépius PR target/51417 * Makefile.in: Let install-gcc-ar depend on installdirs, diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index 70b5b3b51d8ef..16d0f1f8f5da6 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20130316 +20150623 diff --git a/gcc/DEV-PHASE b/gcc/DEV-PHASE index 9839eb20815b5..e69de29bb2d1d 100644 --- a/gcc/DEV-PHASE +++ b/gcc/DEV-PHASE @@ -1 +0,0 @@ -experimental diff --git a/gcc/Makefile.in b/gcc/Makefile.in index 54ea04f644a1a..2a4475b750ee4 100644 --- a/gcc/Makefile.in +++ b/gcc/Makefile.in @@ -747,7 +747,8 @@ BUILD_LINKERFLAGS = $(BUILD_CXXFLAGS) # Native linker and preprocessor flags. For x-fragment overrides. BUILD_LDFLAGS=@BUILD_LDFLAGS@ -BUILD_CPPFLAGS=$(ALL_CPPFLAGS) +BUILD_CPPFLAGS= -I. -I$(@D) -I$(srcdir) -I$(srcdir)/$(@D) \ + -I$(srcdir)/../include @INCINTL@ $(CPPINC) $(CPPFLAGS) # Actual name to use when installing a native compiler. GCC_INSTALL_NAME := $(shell echo gcc|sed '$(program_transform_name)') @@ -1827,7 +1828,7 @@ s-mlib: $(srcdir)/genmultilib Makefile "$(MULTILIB_EXCLUSIONS)" \ "$(MULTILIB_OSDIRNAMES)" \ "$(MULTILIB_REQUIRED)" \ - "$(MULTIARCH_DIRNAME)" \ + "$(if $(MULTILIB_OSDIRNAMES),,$(MULTIARCH_DIRNAME))" \ "$(MULTILIB_REUSE)" \ "@enable_multilib@" \ > tmp-mlib.h; \ @@ -2256,7 +2257,7 @@ tree-ssa-uninit.o : tree-ssa-uninit.c $(TREE_FLOW_H) $(CONFIG_H) $(SYSTEM_H) \ $(FUNCTION_H) $(TM_H) coretypes.h \ $(TREE_PASS_H) $(BASIC_BLOCK_H) $(BITMAP_H) \ $(FLAGS_H) $(HASHTAB_H) pointer-set.h \ - $(GIMPLE_H) $(TREE_INLINE_H) $(GIMPLE_PRETTY_PRINT_H) + $(GIMPLE_H) $(TREE_INLINE_H) $(GIMPLE_PRETTY_PRINT_H) $(PARAMS_H) tree-ssa.o : tree-ssa.c $(TREE_FLOW_H) $(CONFIG_H) $(SYSTEM_H) \ $(TREE_H) $(TM_P_H) $(EXPR_H) $(DIAGNOSTIC_H) \ toplev.h $(FUNCTION_H) $(TM_H) coretypes.h \ @@ -2505,7 +2506,7 @@ tree-ssa-reassoc.o : tree-ssa-reassoc.c $(TREE_FLOW_H) $(CONFIG_H) \ $(TM_H) coretypes.h $(TREE_PASS_H) $(FLAGS_H) \ tree-iterator.h $(BASIC_BLOCK_H) $(GIMPLE_H) $(TREE_INLINE_H) \ $(VEC_H) langhooks.h alloc-pool.h pointer-set.h $(CFGLOOP_H) \ - $(TARGET_H) $(GIMPLE_PRETTY_PRINT_H) $(DIAGNOSTIC_CORE_H) + $(TARGET_H) $(GIMPLE_PRETTY_PRINT_H) $(DIAGNOSTIC_CORE_H) $(PARAMS_H) tree-optimize.o : tree-optimize.c $(TREE_FLOW_H) $(CONFIG_H) $(SYSTEM_H) \ $(TREE_H) $(TM_P_H) $(GGC_H) \ $(DIAGNOSTIC_H) $(BASIC_BLOCK_H) $(FLAGS_H) $(TM_H) \ @@ -3037,7 +3038,7 @@ tree-switch-conversion.o : tree-switch-conversion.c $(CONFIG_H) $(SYSTEM_H) \ $(TM_H) coretypes.h $(GIMPLE_H) \ $(TREE_PASS_H) $(FLAGS_H) $(EXPR_H) $(BASIC_BLOCK_H) \ $(GGC_H) $(OBSTACK_H) $(PARAMS_H) $(CPPLIB_H) $(PARAMS_H) \ - $(GIMPLE_PRETTY_PRINT_H) langhooks.h + $(GIMPLE_PRETTY_PRINT_H) langhooks.h $(OPTABS_H) tree-complex.o : tree-complex.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TREE_H) \ $(TM_H) $(FLAGS_H) $(TREE_FLOW_H) $(GIMPLE_H) \ tree-iterator.h $(TREE_PASS_H) tree-ssa-propagate.h @@ -3276,12 +3277,12 @@ lra-constraints.o : lra-constraints.c $(CONFIG_H) $(SYSTEM_H) coretypes.h \ $(TM_H) $(RTL_H) $(REGS_H) insn-config.h insn-codes.h $(DF_H) \ $(RECOG_H) output.h addresses.h $(REGS_H) hard-reg-set.h $(FLAGS_H) \ $(FUNCTION_H) $(EXPR_H) $(BASIC_BLOCK_H) $(TM_P_H) $(EXCEPT_H) \ - ira.h rtl-error.h $(LRA_INT_H) + ira.h rtl-error.h $(LRA_INT_H) $(OPTABS_H) lra-eliminations.o : lra-eliminations.c $(CONFIG_H) $(SYSTEM_H) coretypes.h \ $(TM_H) $(RTL_H) $(REGS_H) insn-config.h $(DF_H) \ $(RECOG_H) output.h $(REGS_H) hard-reg-set.h $(FLAGS_H) $(FUNCTION_H) \ $(EXPR_H) $(BASIC_BLOCK_H) $(TM_P_H) $(EXCEPT_H) ira.h \ - rtl-error.h $(LRA_INT_H) + rtl-error.h $(LRA_INT_H) $(OPTABS_H) lra-lives.o : lra-lives.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) \ $(RTL_H) $(REGS_H) insn-config.h $(DF_H) \ $(RECOG_H) output.h $(REGS_H) hard-reg-set.h $(FLAGS_H) $(FUNCTION_H) \ @@ -4601,7 +4602,7 @@ PLUGIN_HEADERS = $(TREE_H) $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) \ $(C_PRAGMA_H) $(CPPLIB_H) $(FUNCTION_H) \ cppdefault.h flags.h $(MD5_H) params.def params.h prefix.h tree-inline.h \ $(GIMPLE_PRETTY_PRINT_H) realmpfr.h \ - $(IPA_PROP_H) $(RTL_H) $(TM_P_H) $(CFGLOOP_H) $(EMIT_RTL_H) version.h + $(IPA_PROP_H) $(TARGET_H) $(RTL_H) $(TM_P_H) $(CFGLOOP_H) $(EMIT_RTL_H) version.h # generate the 'build fragment' b-header-vars s-header-vars: Makefile diff --git a/gcc/ada/ChangeLog b/gcc/ada/ChangeLog index 784448558adb1..5a60c4b5b572b 100644 --- a/gcc/ada/ChangeLog +++ b/gcc/ada/ChangeLog @@ -1,3 +1,175 @@ +2015-06-23 Release Manager + + * GCC 4.8.5 released. + +2015-03-16 Eric Botcazou + + * gcc-interface/utils2.c (gnat_invariant_expr): Return null if the type + of the expression ends up being composite. + +2014-12-19 Release Manager + + * GCC 4.8.4 released. + +2014-11-22 Eric Botcazou + + Backport from mainline + 2014-11-20 Vincent Celier + + PR ada/47500 + * back_end.adb (Scan_Back_End_Switches): Skip switch -G and + its argument. + +2014-10-13 Eric Botcazou + Alan Modra + + PR ada/63225 + * uintp.adb (Vector_To_Uint): Move from here to... + * uintp.ads (UI_Vector): Make public. + (Vector_To_Uint): ...here. + +2014-08-12 Joel Sherrill + + * socket.c: For RTEMS, use correct prototype of gethostbyname_r(). + * gsocket.h Add include of on RTEMS. + +2014-08-11 Joel Sherrill + + * s-osinte-rtems.adb: Correct formatting of line in license block. + +2014-05-22 Release Manager + + * GCC 4.8.3 released. + +2014-03-30 Eric Botcazou + + PR ada/60703 + * system-linux-alpha.ads: Adjust for Ada 2005. + * system-linux-mips.ads: Likewise. + * system-linux-mips64el.ads: Likewise. + * system-linux-mipsel.ads: Likewise. + * system-linux-s390.ads: Likewise. + * system-linux-s390x.ads: Likewise. + * system-linux-sparc.ads: Likewise. + * system-linux-sparcv9.ads: Likewise. + * system-rtems.ads: Likewise. + * system-vxworks-arm.ads: Likewise. + +2014-03-13 Eric Botcazou + + PR ada/51483 + * back_end.ads (Register_Type_Proc): Add 'precision' parameter. + * cstand.adb (Register_Float_Type): Add 'precision' parameter and use + it to set the RM size. Use directly 'size' for the Esize. + * gcc-interface/gigi.h (enumerate_modes): Add integer parameter. + * gcc-interface/misc.c (enumerate_modes): Likewise. Do not register + types for vector modes, pass the size in addition to the precision. + +2014-01-12 Eric Botcazou + + PR ada/59772 + * gcc-interface/cuintp.c (build_cst_from_int): Use 32-bit integer type + as intermediate type. + (UI_To_gnu): Likewise. + +2013-12-12 Eric Botcazou + Iain Sandoe + + PR ada/55946 + * gcc-interface/Make-lang.in (ada/doctools/xgnatugn): Use gnatmake. + * gcc-interface/Makefile.in (GCC_LINK): Add LDFLAGS. + (../../gnatmake): Remove LDFLAGS. + (../../gnatlink): Likewise. + +2013-12-04 Eric Botcazou + + PR ada/59382 + * indepsw-darwin.adb: New file. + +2013-10-19 Eric Botcazou + + * gcc-interface/utils.c (scale_by_factor_of): New function. + (rest_of_record_type_compilation): Use scale_by_factor_of in order to + scale the original offset for both rounding cases; in the second case, + take into accout the addend to compute the alignment. Tidy up. + +2013-10-19 Eric Botcazou + + * gcc-interface/utils.c (gnat_set_type_context): New function. + (gnat_pushdecl): Use it to set the context of the type. + +2013-10-16 Release Manager + + * GCC 4.8.2 released. + +2013-10-13 Eric Botcazou + + * gcc-interface/decl.c (gnat_to_gnu_param): Remove obsolete comment. + +2013-09-18 Eric Botcazou + + PR ada/58264 + * gcc-interface/trans.c (Attribute_to_gnu): Define GNAT_PREFIX local + variable and use it throughout. + : Note whether the prefix is the dereference of a pointer + to unconstrained array and, in this case, capture the result for both + Attr_First and Attr_Last. + +2013-09-18 Eric Botcazou + + * gcc-interface/trans.c (gigi): Remove dead code. + +2013-09-18 Eric Botcazou + + * gcc-interface/trans.c (Subprogram_Body_to_gnu): Pop the stack of + return variables for subprograms using the CICO mechanism. + +2013-08-13 Eric Botcazou + + * gcc-interface/trans.c (can_equal_min_or_max_val_p): Be prepared for + values outside of the range of the type. + +2013-06-13 Eric Botcazou + + * gcc-interface/ada-tree.h (DECL_BY_DOUBLE_REF_P): Delete. + * gcc-interface/gigi.h (annotate_object): Adjust prototype. + (convert_vms_descriptor): Likewise. + * gcc-interface/decl.c (gnat_to_gnu_param): Do not pass fat pointer + types by double dereference. + (annotate_object): Remove BY_DOUBLE_REF parameter and adjust. + (gnat_to_gnu_entity): Adjust calls to annotate_object. + * gcc-interface/trans.c (Identifier_to_gnu): Do not deal with double + dereference. + (Call_to_gnu): Likewise. + (build_function_stub): Adjust call to convert_vms_descriptor. + (Subprogram_Body_to_gnu): Adjust call to annotate_object. + * gcc-interface/utils.c (convert_vms_descriptor): Remove BY_REF + parameter and adjust. + +2013-05-31 Release Manager + + * GCC 4.8.1 released. + +2013-05-26 Eric Botcazou + + * gcc-interface/trans.c (Attribute_to_gnu) : Add kludge + to avoid generating an overflow for -1. + +2013-05-07 Eric Botcazou + + PR ada/56474 + * gcc-interface/decl.c (gnat_to_gnu_entity) : Use + int_const_binop to shift bounds by 1 when they are integer constants. + +2013-04-23 Kai Tietz + + PR target/55445 + * raise-gcc.c (__SEH__): Additional check that SjLj isn't active. + +2013-03-22 Release Manager + + * GCC 4.8.0 released. + 2013-03-08 Cesar Strauss PR ada/52123 diff --git a/gcc/ada/back_end.adb b/gcc/ada/back_end.adb index f23230ecf9d34..4313ca4500cf3 100644 --- a/gcc/ada/back_end.adb +++ b/gcc/ada/back_end.adb @@ -209,9 +209,10 @@ package body Back_End is Last : constant Natural := Switch_Last (Switch_Chars); begin - -- Skip -o or internal GCC switches together with their argument + -- Skip -o, -G or internal GCC switches together with their argument. if Switch_Chars (First .. Last) = "o" + or else Switch_Chars (First .. Last) = "G" or else Is_Internal_GCC_Switch (Switch_Chars) then Next_Arg := Next_Arg + 1; diff --git a/gcc/ada/back_end.ads b/gcc/ada/back_end.ads index bfa2eb5b440da..9d92ce39c5ceb 100644 --- a/gcc/ada/back_end.ads +++ b/gcc/ada/back_end.ads @@ -55,6 +55,7 @@ package Back_End is Complex : Boolean; -- True iff type has real and imaginary parts Count : Natural; -- Number of elements in vector, 0 otherwise Float_Rep : Float_Rep_Kind; -- Representation used for fpt type + Precision : Positive; -- Precision of representation in bits Size : Positive; -- Size of representation in bits Alignment : Natural); -- Required alignment in bits pragma Convention (C, Register_Type_Proc); diff --git a/gcc/ada/cstand.adb b/gcc/ada/cstand.adb index 82f8697bcb359..7f12fa03e81a9 100644 --- a/gcc/ada/cstand.adb +++ b/gcc/ada/cstand.adb @@ -151,6 +151,7 @@ package body CStand is Complex : Boolean; -- True iff type has real and imaginary parts Count : Natural; -- Number of elements in vector, 0 otherwise Float_Rep : Float_Rep_Kind; -- Representation used for fpt type + Precision : Positive; -- Precision of representation in bits Size : Positive; -- Size of representation in bits Alignment : Natural); -- Required alignment in bits pragma Convention (C, Register_Float_Type); @@ -2014,6 +2015,7 @@ package body CStand is Complex : Boolean; Count : Natural; Float_Rep : Float_Rep_Kind; + Precision : Positive; Size : Positive; Alignment : Natural) is @@ -2063,13 +2065,24 @@ package body CStand is else Write_Str ("mod 2**"); - Write_Int (Int (Size / Positive'Max (1, Count))); + Write_Int (Int (Precision / Positive'Max (1, Count))); Write_Line (";"); end if; - Write_Str ("for " & T & "'Size use "); - Write_Int (Int (Size)); - Write_Line (";"); + if Precision = Size then + Write_Str ("for " & T (1 .. Last) & "'Size use "); + Write_Int (Int (Size)); + Write_Line (";"); + + else + Write_Str ("for " & T (1 .. Last) & "'Value_Size use "); + Write_Int (Int (Precision)); + Write_Line (";"); + + Write_Str ("for " & T (1 .. Last) & "'Object_Size use "); + Write_Int (Int (Size)); + Write_Line (";"); + end if; Write_Str ("for " & T & "'Alignment use "); Write_Int (Int (Alignment / 8)); @@ -2092,15 +2105,13 @@ package body CStand is if Digs > 0 and then not Complex and then Count = 0 then declare Ent : constant Entity_Id := New_Standard_Entity; - Esize : constant Pos := Pos ((Size + Alignment - 1) - / Alignment * Alignment); begin Set_Defining_Identifier (New_Node (N_Full_Type_Declaration, Stloc), Ent); Make_Name (Ent, T (1 .. Last)); Set_Scope (Ent, Standard_Standard); - Build_Float_Type (Ent, Esize, Float_Rep, Pos (Digs)); - Set_RM_Size (Ent, UI_From_Int (Int (Size))); + Build_Float_Type (Ent, Int (Size), Float_Rep, Pos (Digs)); + Set_RM_Size (Ent, UI_From_Int (Int (Precision))); Set_Alignment (Ent, UI_From_Int (Int (Alignment / 8))); if No (Back_End_Float_Types) then diff --git a/gcc/ada/gcc-interface/Make-lang.in b/gcc/ada/gcc-interface/Make-lang.in index 57f90090dcf90..e1d3ed6ebf3de 100644 --- a/gcc/ada/gcc-interface/Make-lang.in +++ b/gcc/ada/gcc-interface/Make-lang.in @@ -625,7 +625,7 @@ ada.tags: force ada/doctools/xgnatugn$(build_exeext): ada/xgnatugn.adb -$(MKDIR) ada/doctools $(CP) $^ ada/doctools - cd ada/doctools && $(GNATMAKE) -q xgnatugn + cd ada/doctools && gnatmake -q xgnatugn # Note that doc/gnat_ugn.texi and doc/projects.texi do not depend on # xgnatugn being built so we can distribute a pregenerated doc/gnat_ugn.info diff --git a/gcc/ada/gcc-interface/Makefile.in b/gcc/ada/gcc-interface/Makefile.in index 0ddde72942505..ee610f789bba1 100644 --- a/gcc/ada/gcc-interface/Makefile.in +++ b/gcc/ada/gcc-interface/Makefile.in @@ -2397,7 +2397,7 @@ TOOLS_FLAGS_TO_PASS= \ "GNATLINK=$(GNATLINK)" \ "GNATBIND=$(GNATBIND)" -GCC_LINK=$(CC) $(GCC_LINK_FLAGS) $(ADA_INCLUDES) +GCC_LINK=$(CC) $(GCC_LINK_FLAGS) $(ADA_INCLUDES) $(LDFLAGS) # Build directory for the tools. Let's copy the target-dependent # sources using the same mechanism as for gnatlib. The other sources are @@ -2519,12 +2519,10 @@ gnatlink-re: ../stamp-tools link.o targext.o gnatmake-re # Likewise for the tools ../../gnatmake$(exeext): $(P) b_gnatm.o link.o targext.o $(GNATMAKE_OBJS) - $(GCC_LINK) $(ALL_CFLAGS) $(LDFLAGS) -o $@ b_gnatm.o $(GNATMAKE_OBJS) \ - $(TOOLS_LIBS) + +$(GCC_LINK) $(ALL_CFLAGS) -o $@ b_gnatm.o $(GNATMAKE_OBJS) $(TOOLS_LIBS) ../../gnatlink$(exeext): $(P) b_gnatl.o link.o targext.o $(GNATLINK_OBJS) - $(GCC_LINK) $(ALL_CFLAGS) $(LDFLAGS) -o $@ b_gnatl.o $(GNATLINK_OBJS) \ - $(TOOLS_LIBS) + +$(GCC_LINK) $(ALL_CFLAGS) -o $@ b_gnatl.o $(GNATLINK_OBJS) $(TOOLS_LIBS) ../stamp-gnatlib-$(RTSDIR): @if [ ! -f stamp-gnatlib-$(RTSDIR) ] ; \ diff --git a/gcc/ada/gcc-interface/ada-tree.h b/gcc/ada/gcc-interface/ada-tree.h index ec00cc4775f79..12062d52a21df 100644 --- a/gcc/ada/gcc-interface/ada-tree.h +++ b/gcc/ada/gcc-interface/ada-tree.h @@ -360,10 +360,6 @@ do { \ constant CONSTRUCTOR. */ #define DECL_CONST_ADDRESS_P(NODE) DECL_LANG_FLAG_0 (CONST_DECL_CHECK (NODE)) -/* Nonzero in a PARM_DECL if it is always used by double reference, i.e. a - pair of INDIRECT_REFs is needed to access the object. */ -#define DECL_BY_DOUBLE_REF_P(NODE) DECL_LANG_FLAG_0 (PARM_DECL_CHECK (NODE)) - /* Nonzero in a FIELD_DECL if it is declared as aliased. */ #define DECL_ALIASED_P(NODE) DECL_LANG_FLAG_0 (FIELD_DECL_CHECK (NODE)) diff --git a/gcc/ada/gcc-interface/cuintp.c b/gcc/ada/gcc-interface/cuintp.c index e077d9ce009cc..f4d75eca2eb0c 100644 --- a/gcc/ada/gcc-interface/cuintp.c +++ b/gcc/ada/gcc-interface/cuintp.c @@ -6,7 +6,7 @@ * * * C Implementation File * * * - * Copyright (C) 1992-2012, Free Software Foundation, Inc. * + * Copyright (C) 1992-2014, Free Software Foundation, Inc. * * * * GNAT is free software; you can redistribute it and/or modify it under * * terms of the GNU General Public License as published by the Free Soft- * @@ -59,8 +59,8 @@ static tree build_cst_from_int (tree type, HOST_WIDE_INT low) { - if (TREE_CODE (type) == REAL_TYPE) - return convert (type, build_int_cst (NULL_TREE, low)); + if (SCALAR_FLOAT_TYPE_P (type)) + return convert (type, build_int_cst (gnat_type_for_size (32, 0), low)); else return build_int_cst_type (type, low); } @@ -99,19 +99,12 @@ UI_To_gnu (Uint Input, tree type) gcc_assert (Length > 0); /* The computations we perform below always require a type at least as - large as an integer not to overflow. REAL types are always fine, but + large as an integer not to overflow. FP types are always fine, but INTEGER or ENUMERAL types we are handed may be too short. We use a base integer type node for the computations in this case and will - convert the final result back to the incoming type later on. - The base integer precision must be superior than 16. */ - - if (TREE_CODE (comp_type) != REAL_TYPE - && TYPE_PRECISION (comp_type) - < TYPE_PRECISION (long_integer_type_node)) - { - comp_type = long_integer_type_node; - gcc_assert (TYPE_PRECISION (comp_type) > 16); - } + convert the final result back to the incoming type later on. */ + if (!SCALAR_FLOAT_TYPE_P (comp_type) && TYPE_PRECISION (comp_type) < 32) + comp_type = gnat_type_for_size (32, 0); gnu_base = build_cst_from_int (comp_type, Base); diff --git a/gcc/ada/gcc-interface/decl.c b/gcc/ada/gcc-interface/decl.c index 7342fa3c9ed64..5a68e8eaec439 100644 --- a/gcc/ada/gcc-interface/decl.c +++ b/gcc/ada/gcc-interface/decl.c @@ -1019,7 +1019,7 @@ gnat_to_gnu_entity (Entity_Id gnat_entity, tree gnu_expr, int definition) save_gnu_tree (gnat_entity, gnu_decl, true); saved = true; annotate_object (gnat_entity, gnu_type, NULL_TREE, - false, false); + false); /* This assertion will fail if the renamed object isn't aligned enough as to make it possible to honor the alignment set on the renaming. */ @@ -1605,7 +1605,7 @@ gnat_to_gnu_entity (Entity_Id gnat_entity, tree gnu_expr, int definition) type of the object and not on the object directly, and makes it possible to support all confirming representation clauses. */ annotate_object (gnat_entity, TREE_TYPE (gnu_decl), gnu_object_size, - used_by_ref, false); + used_by_ref); } break; @@ -2447,15 +2447,17 @@ gnat_to_gnu_entity (Entity_Id gnat_entity, tree gnu_expr, int definition) gnu_orig_max, gnu_orig_min), gnu_min, - size_binop (PLUS_EXPR, gnu_max, - size_one_node)); + int_const_binop (PLUS_EXPR, gnu_max, + size_one_node)); } /* Finally we use (hb >= lb) ? hb : lb - 1 for the upper bound in all the other cases. Note that, here as well as above, the condition used in the comparison must be equivalent to the condition (length != 0). This is relied upon in order - to optimize array comparisons in compare_arrays. */ + to optimize array comparisons in compare_arrays. Moreover + we use int_const_binop for the shift by 1 if the bound is + constant to avoid any unwanted overflow. */ else gnu_high = build_cond_expr (sizetype, @@ -2464,8 +2466,11 @@ gnat_to_gnu_entity (Entity_Id gnat_entity, tree gnu_expr, int definition) gnu_orig_max, gnu_orig_min), gnu_max, - size_binop (MINUS_EXPR, gnu_min, - size_one_node)); + TREE_CODE (gnu_min) == INTEGER_CST + ? int_const_binop (MINUS_EXPR, gnu_min, + size_one_node) + : size_binop (MINUS_EXPR, gnu_min, + size_one_node)); /* Reuse the index type for the range type. Then make an index type with the size range in sizetype. */ @@ -5590,7 +5595,7 @@ gnat_to_gnu_param (Entity_Id gnat_param, Mechanism_Type mech, /* The parameter can be indirectly modified if its address is taken. */ bool ro_param = in_param && !Address_Taken (gnat_param); bool by_return = false, by_component_ptr = false; - bool by_ref = false, by_double_ref = false; + bool by_ref = false; tree gnu_param; /* Copy-return is used only for the first parameter of a valued procedure. @@ -5715,19 +5720,6 @@ gnat_to_gnu_param (Entity_Id gnat_param, Mechanism_Type mech, gnu_param_type = build_qualified_type (gnu_param_type, TYPE_QUAL_RESTRICT); by_ref = true; - - /* In some ABIs, e.g. SPARC 32-bit, fat pointer types are themselves - passed by reference. Pass them by explicit reference, this will - generate more debuggable code at -O0. */ - if (TYPE_IS_FAT_POINTER_P (gnu_param_type) - && targetm.calls.pass_by_reference (pack_cumulative_args (NULL), - TYPE_MODE (gnu_param_type), - gnu_param_type, - true)) - { - gnu_param_type = build_reference_type (gnu_param_type); - by_double_ref = true; - } } /* Pass In Out or Out parameters using copy-in copy-out mechanism. */ @@ -5770,14 +5762,9 @@ gnat_to_gnu_param (Entity_Id gnat_param, Mechanism_Type mech, gnu_param = create_param_decl (gnu_param_name, gnu_param_type, ro_param || by_ref || by_component_ptr); DECL_BY_REF_P (gnu_param) = by_ref; - DECL_BY_DOUBLE_REF_P (gnu_param) = by_double_ref; DECL_BY_COMPONENT_PTR_P (gnu_param) = by_component_ptr; - DECL_BY_DESCRIPTOR_P (gnu_param) = (mech == By_Descriptor || - mech == By_Short_Descriptor); - /* Note that, in case of a parameter passed by double reference, the - DECL_POINTS_TO_READONLY_P flag is meant for the second reference. - The first reference always points to read-only, as it points to - the second reference, i.e. the reference to the actual parameter. */ + DECL_BY_DESCRIPTOR_P (gnu_param) + = (mech == By_Descriptor || mech == By_Short_Descriptor); DECL_POINTS_TO_READONLY_P (gnu_param) = (ro_param && (by_ref || by_component_ptr)); DECL_CAN_NEVER_BE_NULL_P (gnu_param) = Can_Never_Be_Null (gnat_param); @@ -7422,18 +7409,13 @@ annotate_value (tree gnu_size) /* Given GNAT_ENTITY, an object (constant, variable, parameter, exception) and GNU_TYPE, its corresponding GCC type, set Esize and Alignment to the size and alignment used by Gigi. Prefer SIZE over TYPE_SIZE if non-null. - BY_REF is true if the object is used by reference and BY_DOUBLE_REF is - true if the object is used by double reference. */ + BY_REF is true if the object is used by reference. */ void -annotate_object (Entity_Id gnat_entity, tree gnu_type, tree size, bool by_ref, - bool by_double_ref) +annotate_object (Entity_Id gnat_entity, tree gnu_type, tree size, bool by_ref) { if (by_ref) { - if (by_double_ref) - gnu_type = TREE_TYPE (gnu_type); - if (TYPE_IS_FAT_POINTER_P (gnu_type)) gnu_type = TYPE_UNCONSTRAINED_ARRAY (gnu_type); else diff --git a/gcc/ada/gcc-interface/gigi.h b/gcc/ada/gcc-interface/gigi.h index 6fc3f347ed31c..c0db89bda95e2 100644 --- a/gcc/ada/gcc-interface/gigi.h +++ b/gcc/ada/gcc-interface/gigi.h @@ -177,10 +177,9 @@ extern tree choices_to_gnu (tree operand, Node_Id choices); /* Given GNAT_ENTITY, an object (constant, variable, parameter, exception) and GNU_TYPE, its corresponding GCC type, set Esize and Alignment to the size and alignment used by Gigi. Prefer SIZE over TYPE_SIZE if non-null. - BY_REF is true if the object is used by reference and BY_DOUBLE_REF is - true if the object is used by double reference. */ + BY_REF is true if the object is used by reference. */ extern void annotate_object (Entity_Id gnat_entity, tree gnu_type, tree size, - bool by_ref, bool by_double_ref); + bool by_ref); /* Return the variant part of RECORD_TYPE, if any. Otherwise return NULL. */ extern tree get_variant_part (tree record_type); @@ -930,11 +929,10 @@ extern tree fill_vms_descriptor (tree gnu_type, tree gnu_expr, /* Convert GNU_EXPR, a pointer to a VMS descriptor, to GNU_TYPE, a regular pointer or fat pointer type. GNU_EXPR_ALT_TYPE is the alternate (32-bit) - pointer type of GNU_EXPR. BY_REF is true if the result is to be used by - reference. GNAT_SUBPROG is the subprogram to which the VMS descriptor is - passed. */ + pointer type of GNU_EXPR. GNAT_SUBPROG is the subprogram to which the + descriptor is passed. */ extern tree convert_vms_descriptor (tree gnu_type, tree gnu_expr, - tree gnu_expr_alt_type, bool by_ref, + tree gnu_expr_alt_type, Entity_Id gnat_subprog); /* Indicate that we need to take the address of T and that it therefore @@ -1016,7 +1014,7 @@ extern Nat get_target_double_scalar_alignment (void); /* This function is called by the front-end to enumerate all the supported modes for the machine, as well as some predefined C types. */ extern void enumerate_modes (void (*f) (const char *, int, int, int, int, int, - int)); + int, int)); #ifdef __cplusplus } diff --git a/gcc/ada/gcc-interface/misc.c b/gcc/ada/gcc-interface/misc.c index 2fd2743bbe121..83620487bf969 100644 --- a/gcc/ada/gcc-interface/misc.c +++ b/gcc/ada/gcc-interface/misc.c @@ -648,7 +648,7 @@ must_pass_by_ref (tree gnu_type) /* This function is called by the front-end to enumerate all the supported modes for the machine, as well as some predefined C types. F is a function which is called back with the parameters as listed below, first a string, - then six ints. The name is any arbitrary null-terminated string and has + then seven ints. The name is any arbitrary null-terminated string and has no particular significance, except for the case of predefined C types, where it should be the name of the C type. For integer types, only signed types should be listed, unsigned versions are assumed. The order of types should @@ -664,11 +664,12 @@ must_pass_by_ref (tree gnu_type) COMPLEX_P nonzero is this represents a complex mode COUNT count of number of items, nonzero for vector mode FLOAT_REP Float_Rep_Kind for FP, otherwise undefined - SIZE number of bits used to store data + PRECISION number of bits used to store data + SIZE number of bits occupied by the mode ALIGN number of bits to which mode is aligned. */ void -enumerate_modes (void (*f) (const char *, int, int, int, int, int, int)) +enumerate_modes (void (*f) (const char *, int, int, int, int, int, int, int)) { const tree c_types[] = { float_type_node, double_type_node, long_double_type_node }; @@ -742,28 +743,26 @@ enumerate_modes (void (*f) (const char *, int, int, int, int, int, int)) /* First register any C types for this mode that the front end may need to know about, unless the mode should be skipped. */ - - if (!skip_p) + if (!skip_p && !vector_p) for (nameloop = 0; nameloop < ARRAY_SIZE (c_types); nameloop++) { - tree typ = c_types[nameloop]; - const char *nam = c_names[nameloop]; + tree type = c_types[nameloop]; + const char *name = c_names[nameloop]; - if (TYPE_MODE (typ) == i) + if (TYPE_MODE (type) == i) { - f (nam, digs, complex_p, - vector_p ? GET_MODE_NUNITS (i) : 0, float_rep, - TYPE_PRECISION (typ), TYPE_ALIGN (typ)); + f (name, digs, complex_p, 0, float_rep, TYPE_PRECISION (type), + TREE_INT_CST_LOW (TYPE_SIZE (type)), TYPE_ALIGN (type)); skip_p = true; } } /* If no predefined C types were found, register the mode itself. */ - if (!skip_p) f (GET_MODE_NAME (i), digs, complex_p, vector_p ? GET_MODE_NUNITS (i) : 0, float_rep, - GET_MODE_PRECISION (i), GET_MODE_ALIGNMENT (i)); + GET_MODE_PRECISION (i), GET_MODE_BITSIZE (i), + GET_MODE_ALIGNMENT (i)); } } diff --git a/gcc/ada/gcc-interface/trans.c b/gcc/ada/gcc-interface/trans.c index 39e455b83ea38..779174a68b357 100644 --- a/gcc/ada/gcc-interface/trans.c +++ b/gcc/ada/gcc-interface/trans.c @@ -286,9 +286,6 @@ gigi (Node_Id gnat_root, int max_gnat_node, int number_name ATTRIBUTE_UNUSED, tree int64_type = gnat_type_for_size (64, 0); struct elab_info *info; int i; -#ifdef ORDINARY_MAP_INSTANCE - struct line_map *map; -#endif max_gnat_nodes = max_gnat_node; @@ -303,10 +300,6 @@ gigi (Node_Id gnat_root, int max_gnat_node, int number_name ATTRIBUTE_UNUSED, type_annotate_only = (gigi_operating_mode == 1); - /* ??? Disable the generation of the SCO instance table until after the - back-end supports instance based debug info discriminators. */ - Generate_SCO_Instance_Table = False; - for (i = 0; i < number_file; i++) { /* Use the identifier table to make a permanent copy of the filename as @@ -326,11 +319,6 @@ gigi (Node_Id gnat_root, int max_gnat_node, int number_name ATTRIBUTE_UNUSED, /* We create the line map for a source file at once, with a fixed number of columns chosen to avoid jumping over the next power of 2. */ linemap_add (line_table, LC_ENTER, 0, filename, 1); -#ifdef ORDINARY_MAP_INSTANCE - map = LINEMAPS_ORDINARY_MAP_AT (line_table, i); - if (flag_debug_instances) - ORDINARY_MAP_INSTANCE (map) = file_info_ptr[i].Instance; -#endif linemap_line_start (line_table, file_info_ptr[i].Num_Source_Lines, 252); linemap_position_for_column (line_table, 252 - 1); linemap_add (line_table, LC_LEAVE, 0, NULL, 0); @@ -1075,19 +1063,6 @@ Identifier_to_gnu (Node_Id gnat_node, tree *gnu_result_type_p) { const bool read_only = DECL_POINTS_TO_READONLY_P (gnu_result); - /* First do the first dereference if needed. */ - if (TREE_CODE (gnu_result) == PARM_DECL - && DECL_BY_DOUBLE_REF_P (gnu_result)) - { - gnu_result = build_unary_op (INDIRECT_REF, NULL_TREE, gnu_result); - if (TREE_CODE (gnu_result) == INDIRECT_REF) - TREE_THIS_NOTRAP (gnu_result) = 1; - - /* The first reference, in case of a double reference, always points - to read-only, see gnat_to_gnu_param for the rationale. */ - TREE_READONLY (gnu_result) = 1; - } - /* If it's a PARM_DECL to foreign convention subprogram, convert it. */ if (TREE_CODE (gnu_result) == PARM_DECL && DECL_BY_COMPONENT_PTR_P (gnu_result)) @@ -1290,6 +1265,7 @@ Pragma_to_gnu (Node_Id gnat_node) static tree Attribute_to_gnu (Node_Id gnat_node, tree *gnu_result_type_p, int attribute) { + const Node_Id gnat_prefix = Prefix (gnat_node); tree gnu_prefix, gnu_type, gnu_expr; tree gnu_result_type, gnu_result = error_mark_node; bool prefix_unused = false; @@ -1299,13 +1275,13 @@ Attribute_to_gnu (Node_Id gnat_node, tree *gnu_result_type_p, int attribute) parameter types might be incomplete types coming from a limited with. */ if (Ekind (Etype (gnat_node)) == E_Access_Subprogram_Type && Is_Dispatch_Table_Entity (Etype (gnat_node)) - && Nkind (Prefix (gnat_node)) == N_Identifier - && Is_Subprogram (Entity (Prefix (gnat_node))) - && Is_Public (Entity (Prefix (gnat_node))) - && !present_gnu_tree (Entity (Prefix (gnat_node)))) - gnu_prefix = get_minimal_subprog_decl (Entity (Prefix (gnat_node))); + && Nkind (gnat_prefix) == N_Identifier + && Is_Subprogram (Entity (gnat_prefix)) + && Is_Public (Entity (gnat_prefix)) + && !present_gnu_tree (Entity (gnat_prefix))) + gnu_prefix = get_minimal_subprog_decl (Entity (gnat_prefix)); else - gnu_prefix = gnat_to_gnu (Prefix (gnat_node)); + gnu_prefix = gnat_to_gnu (gnat_prefix); gnu_type = TREE_TYPE (gnu_prefix); /* If the input is a NULL_EXPR, make a new one. */ @@ -1448,8 +1424,8 @@ Attribute_to_gnu (Node_Id gnat_node, tree *gnu_result_type_p, int attribute) since it can use a special calling convention on some platforms, which cannot be propagated to the access type. */ else if (attribute == Attr_Access - && Nkind (Prefix (gnat_node)) == N_Identifier - && is_cplusplus_method (Entity (Prefix (gnat_node)))) + && Nkind (gnat_prefix) == N_Identifier + && is_cplusplus_method (Entity (gnat_prefix))) post_error ("access to C++ constructor or member function not allowed", gnat_node); @@ -1560,13 +1536,12 @@ Attribute_to_gnu (Node_Id gnat_node, tree *gnu_result_type_p, int attribute) /* If this is a dereference and we have a special dynamic constrained subtype on the prefix, use it to compute the size; otherwise, use the designated subtype. */ - if (Nkind (Prefix (gnat_node)) == N_Explicit_Dereference) + if (Nkind (gnat_prefix) == N_Explicit_Dereference) { - Node_Id gnat_deref = Prefix (gnat_node); Node_Id gnat_actual_subtype - = Actual_Designated_Subtype (gnat_deref); + = Actual_Designated_Subtype (gnat_prefix); tree gnu_ptr_type - = TREE_TYPE (gnat_to_gnu (Prefix (gnat_deref))); + = TREE_TYPE (gnat_to_gnu (Prefix (gnat_prefix))); if (TYPE_IS_FAT_OR_THIN_POINTER_P (gnu_ptr_type) && Present (gnat_actual_subtype)) @@ -1627,7 +1602,6 @@ Attribute_to_gnu (Node_Id gnat_node, tree *gnu_result_type_p, int attribute) align = DECL_ALIGN (TREE_OPERAND (gnu_prefix, 1)) / BITS_PER_UNIT; else { - Node_Id gnat_prefix = Prefix (gnat_node); Entity_Id gnat_type = Etype (gnat_prefix); unsigned int double_align; bool is_capped_double, align_clause; @@ -1699,28 +1673,38 @@ Attribute_to_gnu (Node_Id gnat_node, tree *gnu_result_type_p, int attribute) : 1), i; struct parm_attr_d *pa = NULL; Entity_Id gnat_param = Empty; + bool unconstrained_ptr_deref = false; /* Make sure any implicit dereference gets done. */ gnu_prefix = maybe_implicit_deref (gnu_prefix); gnu_prefix = maybe_unconstrained_array (gnu_prefix); - /* We treat unconstrained array In parameters specially. */ - if (!Is_Constrained (Etype (Prefix (gnat_node)))) - { - Node_Id gnat_prefix = Prefix (gnat_node); - - /* This is the direct case. */ - if (Nkind (gnat_prefix) == N_Identifier - && Ekind (Entity (gnat_prefix)) == E_In_Parameter) - gnat_param = Entity (gnat_prefix); - - /* This is the indirect case. Note that we need to be sure that - the access value cannot be null as we'll hoist the load. */ - if (Nkind (gnat_prefix) == N_Explicit_Dereference - && Nkind (Prefix (gnat_prefix)) == N_Identifier - && Ekind (Entity (Prefix (gnat_prefix))) == E_In_Parameter - && Can_Never_Be_Null (Entity (Prefix (gnat_prefix)))) - gnat_param = Entity (Prefix (gnat_prefix)); + /* We treat unconstrained array In parameters specially. We also note + whether we are dereferencing a pointer to unconstrained array. */ + if (!Is_Constrained (Etype (gnat_prefix))) + switch (Nkind (gnat_prefix)) + { + case N_Identifier: + /* This is the direct case. */ + if (Ekind (Entity (gnat_prefix)) == E_In_Parameter) + gnat_param = Entity (gnat_prefix); + break; + + case N_Explicit_Dereference: + /* This is the indirect case. Note that we need to be sure that + the access value cannot be null as we'll hoist the load. */ + if (Nkind (Prefix (gnat_prefix)) == N_Identifier + && Ekind (Entity (Prefix (gnat_prefix))) == E_In_Parameter) + { + if (Can_Never_Be_Null (Entity (Prefix (gnat_prefix)))) + gnat_param = Entity (Prefix (gnat_prefix)); + } + else + unconstrained_ptr_deref = true; + break; + + default: + break; } /* If the prefix is the view conversion of a constrained array to an @@ -1855,22 +1839,54 @@ Attribute_to_gnu (Node_Id gnat_node, tree *gnu_result_type_p, int attribute) { gnu_result = build1 (SAVE_EXPR, TREE_TYPE (gnu_result), gnu_result); - if (attribute == Attr_First) - pa->first = gnu_result; - else if (attribute == Attr_Last) - pa->last = gnu_result; - else - pa->length = gnu_result; + switch (attribute) + { + case Attr_First: + pa->first = gnu_result; + break; + + case Attr_Last: + pa->last = gnu_result; + break; + + case Attr_Length: + case Attr_Range_Length: + pa->length = gnu_result; + break; + + default: + gcc_unreachable (); + } } - /* Set the source location onto the predicate of the condition in the - 'Length case but do not do it if the expression is cached to avoid - messing up the debug info. */ - else if ((attribute == Attr_Range_Length || attribute == Attr_Length) - && TREE_CODE (gnu_result) == COND_EXPR - && EXPR_P (TREE_OPERAND (gnu_result, 0))) - set_expr_location_from_node (TREE_OPERAND (gnu_result, 0), - gnat_node); + /* Otherwise, evaluate it each time it is referenced. */ + else + switch (attribute) + { + case Attr_First: + case Attr_Last: + /* If we are dereferencing a pointer to unconstrained array, we + need to capture the value because the pointed-to bounds may + subsequently be released. */ + if (unconstrained_ptr_deref) + gnu_result + = build1 (SAVE_EXPR, TREE_TYPE (gnu_result), gnu_result); + break; + + case Attr_Length: + case Attr_Range_Length: + /* Set the source location onto the predicate of the condition + but not if the expression is cached to avoid messing up the + debug info. */ + if (TREE_CODE (gnu_result) == COND_EXPR + && EXPR_P (TREE_OPERAND (gnu_result, 0))) + set_expr_location_from_node (TREE_OPERAND (gnu_result, 0), + gnat_node); + break; + + default: + gcc_unreachable (); + } break; } @@ -1956,14 +1972,19 @@ Attribute_to_gnu (Node_Id gnat_node, tree *gnu_result_type_p, int attribute) gnu_result = bitsize_int (bitpos % BITS_PER_UNIT); gnu_result = size_binop (PLUS_EXPR, gnu_result, TYPE_SIZE (TREE_TYPE (gnu_prefix))); - gnu_result = size_binop (MINUS_EXPR, gnu_result, - bitsize_one_node); + /* ??? Avoid a large unsigned result that will overflow when + converted to the signed universal_integer. */ + if (integer_zerop (gnu_result)) + gnu_result = integer_minus_one_node; + else + gnu_result + = size_binop (MINUS_EXPR, gnu_result, bitsize_one_node); break; case Attr_Bit_Position: gnu_result = gnu_field_bitpos; break; - } + } /* If this has a PLACEHOLDER_EXPR, qualify it by the object we are handling. */ @@ -2038,8 +2059,8 @@ Attribute_to_gnu (Node_Id gnat_node, tree *gnu_result_type_p, int attribute) case Attr_Mechanism_Code: { + Entity_Id gnat_obj = Entity (gnat_prefix); int code; - Entity_Id gnat_obj = Entity (Prefix (gnat_node)); prefix_unused = true; gnu_result_type = get_unpadded_type (Etype (gnat_node)); @@ -2074,10 +2095,11 @@ Attribute_to_gnu (Node_Id gnat_node, tree *gnu_result_type_p, int attribute) it has a side-effect. But don't do it if the prefix is just an entity name. However, if an access check is needed, we must do it. See second example in AARM 11.6(5.e). */ - if (prefix_unused && TREE_SIDE_EFFECTS (gnu_prefix) - && !Is_Entity_Name (Prefix (gnat_node))) - gnu_result = build_compound_expr (TREE_TYPE (gnu_result), gnu_prefix, - gnu_result); + if (prefix_unused + && TREE_SIDE_EFFECTS (gnu_prefix) + && !Is_Entity_Name (gnat_prefix)) + gnu_result + = build_compound_expr (TREE_TYPE (gnu_result), gnu_prefix, gnu_result); *gnu_result_type_p = gnu_result_type; return gnu_result; @@ -2275,7 +2297,10 @@ can_equal_min_or_max_val_p (tree val, tree type, bool max) if (TREE_CODE (val) != INTEGER_CST) return true; - return tree_int_cst_equal (val, min_or_max_val) == 1; + if (max) + return tree_int_cst_lt (val, min_or_max_val) == 0; + else + return tree_int_cst_lt (min_or_max_val, val) == 0; } /* Return true if VAL (of type TYPE) can equal the minimum value of TYPE. @@ -3246,7 +3271,6 @@ build_function_stub (tree gnu_subprog, Entity_Id gnat_subprog) = convert_vms_descriptor (TREE_TYPE (gnu_subprog_param), gnu_stub_param, DECL_PARM_ALT_TYPE (gnu_stub_param), - DECL_BY_DOUBLE_REF_P (gnu_subprog_param), gnat_subprog); } else @@ -3485,6 +3509,8 @@ Subprogram_Body_to_gnu (Node_Id gnat_node) { tree gnu_retval; + gnu_return_var_stack->pop (); + add_stmt (gnu_result); add_stmt (build1 (LABEL_EXPR, void_type_node, gnu_return_label_stack->last ())); @@ -3541,8 +3567,7 @@ Subprogram_Body_to_gnu (Node_Id gnat_node) bool is_var_decl = (TREE_CODE (gnu_param) == VAR_DECL); annotate_object (gnat_param, TREE_TYPE (gnu_param), NULL_TREE, - DECL_BY_REF_P (gnu_param), - !is_var_decl && DECL_BY_DOUBLE_REF_P (gnu_param)); + DECL_BY_REF_P (gnu_param)); if (is_var_decl) save_gnu_tree (gnat_param, NULL_TREE, false); @@ -4004,12 +4029,6 @@ Call_to_gnu (Node_Id gnat_node, tree *gnu_result_type_p, tree gnu_target, /* The symmetry of the paths to the type of an entity is broken here since arguments don't know that they will be passed by ref. */ gnu_formal_type = TREE_TYPE (gnu_formal); - - if (DECL_BY_DOUBLE_REF_P (gnu_formal)) - gnu_actual - = build_unary_op (ADDR_EXPR, TREE_TYPE (gnu_formal_type), - gnu_actual); - gnu_actual = build_unary_op (ADDR_EXPR, gnu_formal_type, gnu_actual); } else if (is_true_formal_parm && DECL_BY_COMPONENT_PTR_P (gnu_formal)) diff --git a/gcc/ada/gcc-interface/utils.c b/gcc/ada/gcc-interface/utils.c index 309cff6ad32c0..ec252829c63b8 100644 --- a/gcc/ada/gcc-interface/utils.c +++ b/gcc/ada/gcc-interface/utils.c @@ -232,6 +232,7 @@ static tree compute_related_constant (tree, tree); static tree split_plus (tree, tree *); static tree float_type_for_precision (int, enum machine_mode); static tree convert_to_fat_pointer (tree, tree); +static unsigned int scale_by_factor_of (tree, unsigned int); static bool potential_alignment_gap (tree, tree, tree); static void process_attributes (tree, struct attrib *); @@ -532,6 +533,22 @@ gnat_zaplevel (void) free_binding_level = level; } +/* Set the context of TYPE and its parallel types (if any) to CONTEXT. */ + +static void +gnat_set_type_context (tree type, tree context) +{ + tree decl = TYPE_STUB_DECL (type); + + TYPE_CONTEXT (type) = context; + + while (decl && DECL_PARALLEL_TYPE (decl)) + { + TYPE_CONTEXT (DECL_PARALLEL_TYPE (decl)) = context; + decl = TYPE_STUB_DECL (DECL_PARALLEL_TYPE (decl)); + } +} + /* Record DECL as belonging to the current lexical scope and use GNAT_NODE for location information and flag propagation. */ @@ -613,7 +630,7 @@ gnat_pushdecl (tree decl, Node_Id gnat_node) if (TREE_CODE (t) == POINTER_TYPE) TYPE_NEXT_PTR_TO (t) = tt; TYPE_NAME (tt) = DECL_NAME (decl); - TYPE_CONTEXT (tt) = DECL_CONTEXT (decl); + gnat_set_type_context (tt, DECL_CONTEXT (decl)); TYPE_STUB_DECL (tt) = TYPE_STUB_DECL (t); DECL_ORIGINAL_TYPE (decl) = tt; } @@ -623,7 +640,7 @@ gnat_pushdecl (tree decl, Node_Id gnat_node) /* We need a variant for the placeholder machinery to work. */ tree tt = build_variant_type_copy (t); TYPE_NAME (tt) = decl; - TYPE_CONTEXT (tt) = DECL_CONTEXT (decl); + gnat_set_type_context (tt, DECL_CONTEXT (decl)); TREE_USED (tt) = TREE_USED (t); TREE_TYPE (decl) = tt; if (DECL_ORIGINAL_TYPE (TYPE_NAME (t))) @@ -645,7 +662,7 @@ gnat_pushdecl (tree decl, Node_Id gnat_node) if (!(TYPE_NAME (t) && TREE_CODE (TYPE_NAME (t)) == TYPE_DECL)) { TYPE_NAME (t) = decl; - TYPE_CONTEXT (t) = DECL_CONTEXT (decl); + gnat_set_type_context (t, DECL_CONTEXT (decl)); } } } @@ -1692,93 +1709,74 @@ rest_of_record_type_compilation (tree record_type) TYPE_SIZE_UNIT (new_record_type) = size_int (TYPE_ALIGN (record_type) / BITS_PER_UNIT); - /* Now scan all the fields, replacing each field with a new - field corresponding to the new encoding. */ + /* Now scan all the fields, replacing each field with a new field + corresponding to the new encoding. */ for (old_field = TYPE_FIELDS (record_type); old_field; old_field = DECL_CHAIN (old_field)) { tree field_type = TREE_TYPE (old_field); tree field_name = DECL_NAME (old_field); - tree new_field; tree curpos = bit_position (old_field); + tree pos, new_field; bool var = false; unsigned int align = 0; - tree pos; - /* See how the position was modified from the last position. + /* We're going to do some pattern matching below so remove as many + conversions as possible. */ + curpos = remove_conversions (curpos, true); - There are two basic cases we support: a value was added - to the last position or the last position was rounded to - a boundary and they something was added. Check for the - first case first. If not, see if there is any evidence - of rounding. If so, round the last position and try - again. + /* See how the position was modified from the last position. - If this is a union, the position can be taken as zero. */ - - /* Some computations depend on the shape of the position expression, - so strip conversions to make sure it's exposed. */ - curpos = remove_conversions (curpos, true); + There are two basic cases we support: a value was added + to the last position or the last position was rounded to + a boundary and they something was added. Check for the + first case first. If not, see if there is any evidence + of rounding. If so, round the last position and retry. + If this is a union, the position can be taken as zero. */ if (TREE_CODE (new_record_type) == UNION_TYPE) - pos = bitsize_zero_node, align = 0; + pos = bitsize_zero_node; else pos = compute_related_constant (curpos, last_pos); - if (!pos && TREE_CODE (curpos) == MULT_EXPR + if (!pos + && TREE_CODE (curpos) == MULT_EXPR && host_integerp (TREE_OPERAND (curpos, 1), 1)) { tree offset = TREE_OPERAND (curpos, 0); align = tree_low_cst (TREE_OPERAND (curpos, 1), 1); - - /* An offset which is a bitwise AND with a mask increases the - alignment according to the number of trailing zeros. */ - offset = remove_conversions (offset, true); - if (TREE_CODE (offset) == BIT_AND_EXPR - && TREE_CODE (TREE_OPERAND (offset, 1)) == INTEGER_CST) - { - unsigned HOST_WIDE_INT mask - = TREE_INT_CST_LOW (TREE_OPERAND (offset, 1)); - unsigned int i; - - for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++) - { - if (mask & 1) - break; - mask >>= 1; - align *= 2; - } - } - - pos = compute_related_constant (curpos, - round_up (last_pos, align)); + align = scale_by_factor_of (offset, align); + last_pos = round_up (last_pos, align); + pos = compute_related_constant (curpos, last_pos); } - else if (!pos && TREE_CODE (curpos) == PLUS_EXPR - && TREE_CODE (TREE_OPERAND (curpos, 1)) == INTEGER_CST + else if (!pos + && TREE_CODE (curpos) == PLUS_EXPR + && host_integerp (TREE_OPERAND (curpos, 1), 1) && TREE_CODE (TREE_OPERAND (curpos, 0)) == MULT_EXPR - && host_integerp (TREE_OPERAND - (TREE_OPERAND (curpos, 0), 1), - 1)) + && host_integerp + (TREE_OPERAND (TREE_OPERAND (curpos, 0), 1), 1)) { + tree offset = TREE_OPERAND (TREE_OPERAND (curpos, 0), 0); + unsigned HOST_WIDE_INT addend + = tree_low_cst (TREE_OPERAND (curpos, 1), 1); align - = tree_low_cst - (TREE_OPERAND (TREE_OPERAND (curpos, 0), 1), 1); - pos = compute_related_constant (curpos, - round_up (last_pos, align)); + = tree_low_cst (TREE_OPERAND (TREE_OPERAND (curpos, 0), 1), 1); + align = scale_by_factor_of (offset, align); + align = MIN (align, addend & -addend); + last_pos = round_up (last_pos, align); + pos = compute_related_constant (curpos, last_pos); } - else if (potential_alignment_gap (prev_old_field, old_field, - pos)) + else if (potential_alignment_gap (prev_old_field, old_field, pos)) { align = TYPE_ALIGN (field_type); - pos = compute_related_constant (curpos, - round_up (last_pos, align)); + last_pos = round_up (last_pos, align); + pos = compute_related_constant (curpos, last_pos); } /* If we can't compute a position, set it to zero. - ??? We really should abort here, but it's too much work - to get this correct for all cases. */ - + ??? We really should abort here, but it's too much work + to get this correct for all cases. */ if (!pos) pos = bitsize_zero_node; @@ -2553,6 +2551,32 @@ value_factor_p (tree value, HOST_WIDE_INT factor) return false; } +/* Return VALUE scaled by the biggest power-of-2 factor of EXPR. */ + +static unsigned int +scale_by_factor_of (tree expr, unsigned int value) +{ + expr = remove_conversions (expr, true); + + /* An expression which is a bitwise AND with a mask has a power-of-2 factor + corresponding to the number of trailing zeros of the mask. */ + if (TREE_CODE (expr) == BIT_AND_EXPR + && TREE_CODE (TREE_OPERAND (expr, 1)) == INTEGER_CST) + { + unsigned HOST_WIDE_INT mask = TREE_INT_CST_LOW (TREE_OPERAND (expr, 1)); + unsigned int i = 0; + + while ((mask & 1) == 0 && i < HOST_BITS_PER_WIDE_INT) + { + mask >>= 1; + value *= 2; + i++; + } + } + + return value; +} + /* Given two consecutive field decls PREV_FIELD and CURR_FIELD, return true unless we can prove these 2 fields are laid out in such a way that no gap exist between the end of PREV_FIELD and the beginning of CURR_FIELD. OFFSET @@ -4073,33 +4097,25 @@ convert_vms_descriptor32 (tree gnu_type, tree gnu_expr, Entity_Id gnat_subprog) /* Convert GNU_EXPR, a pointer to a VMS descriptor, to GNU_TYPE, a regular pointer or fat pointer type. GNU_EXPR_ALT_TYPE is the alternate (32-bit) - pointer type of GNU_EXPR. BY_REF is true if the result is to be used by - reference. GNAT_SUBPROG is the subprogram to which the VMS descriptor is - passed. */ + pointer type of GNU_EXPR. GNAT_SUBPROG is the subprogram to which the + descriptor is passed. */ tree convert_vms_descriptor (tree gnu_type, tree gnu_expr, tree gnu_expr_alt_type, - bool by_ref, Entity_Id gnat_subprog) + Entity_Id gnat_subprog) { tree desc_type = TREE_TYPE (TREE_TYPE (gnu_expr)); tree desc = build1 (INDIRECT_REF, desc_type, gnu_expr); tree mbo = TYPE_FIELDS (desc_type); const char *mbostr = IDENTIFIER_POINTER (DECL_NAME (mbo)); tree mbmo = DECL_CHAIN (DECL_CHAIN (DECL_CHAIN (mbo))); - tree real_type, is64bit, gnu_expr32, gnu_expr64; - - if (by_ref) - real_type = TREE_TYPE (gnu_type); - else - real_type = gnu_type; + tree is64bit, gnu_expr32, gnu_expr64; /* If the field name is not MBO, it must be 32-bit and no alternate. Otherwise primary must be 64-bit and alternate 32-bit. */ if (strcmp (mbostr, "MBO") != 0) { - tree ret = convert_vms_descriptor32 (real_type, gnu_expr, gnat_subprog); - if (by_ref) - ret = build_unary_op (ADDR_EXPR, gnu_type, ret); + tree ret = convert_vms_descriptor32 (gnu_type, gnu_expr, gnat_subprog); return ret; } @@ -4116,14 +4132,9 @@ convert_vms_descriptor (tree gnu_type, tree gnu_expr, tree gnu_expr_alt_type, integer_minus_one_node)); /* Build the 2 possible end results. */ - gnu_expr64 = convert_vms_descriptor64 (real_type, gnu_expr, gnat_subprog); - if (by_ref) - gnu_expr64 = build_unary_op (ADDR_EXPR, gnu_type, gnu_expr64); + gnu_expr64 = convert_vms_descriptor64 (gnu_type, gnu_expr, gnat_subprog); gnu_expr = fold_convert (gnu_expr_alt_type, gnu_expr); - gnu_expr32 = convert_vms_descriptor32 (real_type, gnu_expr, gnat_subprog); - if (by_ref) - gnu_expr32 = build_unary_op (ADDR_EXPR, gnu_type, gnu_expr32); - + gnu_expr32 = convert_vms_descriptor32 (gnu_type, gnu_expr, gnat_subprog); return build3 (COND_EXPR, gnu_type, is64bit, gnu_expr64, gnu_expr32); } diff --git a/gcc/ada/gcc-interface/utils2.c b/gcc/ada/gcc-interface/utils2.c index 71dd8e5651395..c427247342952 100644 --- a/gcc/ada/gcc-interface/utils2.c +++ b/gcc/ada/gcc-interface/utils2.c @@ -2740,6 +2740,12 @@ gnat_invariant_expr (tree expr) && DECL_INITIAL (expr)) expr = remove_conversions (DECL_INITIAL (expr), false); + /* We are only interested in scalar types at the moment and, even if we may + have gone through padding types in the above loop, we must be back to a + scalar value at this point. */ + if (AGGREGATE_TYPE_P (TREE_TYPE (expr))) + return NULL_TREE; + if (TREE_CONSTANT (expr)) return fold_convert (type, expr); diff --git a/gcc/ada/gsocket.h b/gcc/ada/gsocket.h index e21d7142701f7..1d9235f4ad822 100644 --- a/gcc/ada/gsocket.h +++ b/gcc/ada/gsocket.h @@ -183,6 +183,11 @@ #include #endif +#if defined(__rtems__) +#include +/* Required, for read(), write(), and close() */ +#endif + /* * RTEMS has these .h files but not until you have built and installed RTEMS. * When building a C/C++ toolset, you also build the newlib C library, so the diff --git a/gcc/ada/indepsw-darwin.adb b/gcc/ada/indepsw-darwin.adb new file mode 100644 index 0000000000000..e25e9049200e4 --- /dev/null +++ b/gcc/ada/indepsw-darwin.adb @@ -0,0 +1,67 @@ +------------------------------------------------------------------------------ +-- -- +-- GNAT COMPILER COMPONENTS -- +-- -- +-- I N D E P S W -- +-- -- +-- B o d y -- +-- (Darwin version) -- +-- -- +-- Copyright (C) 2013, Free Software Foundation, Inc. -- +-- -- +-- GNAT is free software; you can redistribute it and/or modify it under -- +-- terms of the GNU General Public License as published by the Free Soft- -- +-- ware Foundation; either version 3, or (at your option) any later ver- -- +-- sion. GNAT is distributed in the hope that it will be useful, but WITH- -- +-- OUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -- +-- or FITNESS FOR A PARTICULAR PURPOSE. -- +-- -- +-- As a special exception under Section 7 of GPL version 3, you are granted -- +-- additional permissions described in the GCC Runtime Library Exception, -- +-- version 3.1, as published by the Free Software Foundation. -- +-- -- +-- You should have received a copy of the GNU General Public License and -- +-- a copy of the GCC Runtime Library Exception along with this program; -- +-- see the files COPYING3 and COPYING.RUNTIME respectively. If not, see -- +-- . -- +-- -- +-- GNAT was originally developed by the GNAT team at New York University. -- +-- Extensive contributions were provided by Ada Core Technologies Inc. -- +-- -- +------------------------------------------------------------------------------ + +-- This is the Darwin version + +package body Indepsw is + + Map_Switch : aliased constant String := "-Wl,-map,"; + + ------------- + -- Convert -- + ------------- + + procedure Convert + (Switch : Switch_Kind; + Argument : String; + To : out String_List_Access) + is + begin + case Switch is + when Map_File => + To := new Argument_List'(1 => new String'(Map_Switch & Argument)); + end case; + end Convert; + + ------------------ + -- Is_Supported -- + ------------------ + + function Is_Supported (Switch : Switch_Kind) return Boolean is + begin + case Switch is + when Map_File => + return True; + end case; + end Is_Supported; + +end Indepsw; diff --git a/gcc/ada/raise-gcc.c b/gcc/ada/raise-gcc.c index 42c5a5c4b45e2..a428642db1ae6 100644 --- a/gcc/ada/raise-gcc.c +++ b/gcc/ada/raise-gcc.c @@ -1019,7 +1019,7 @@ extern void __gnat_notify_unhandled_exception (struct Exception_Occurrence *); #ifdef __USING_SJLJ_EXCEPTIONS__ #define PERSONALITY_FUNCTION __gnat_personality_sj0 -#elif defined(__SEH__) +#elif defined (__SEH__) #define PERSONALITY_FUNCTION __gnat_personality_imp #else #define PERSONALITY_FUNCTION __gnat_personality_v0 @@ -1056,7 +1056,7 @@ typedef int version_arg_t; typedef _Unwind_Action phases_arg_t; #endif -#ifdef __SEH__ +#if defined (__SEH__) && !defined (__USING_SJLJ_EXCEPTIONS__) static #endif _Unwind_Reason_Code @@ -1222,7 +1222,7 @@ __gnat_Unwind_ForcedUnwind (_Unwind_Exception *e, #endif } -#ifdef __SEH__ +#if defined (__SEH__) && !defined (__USING_SJLJ_EXCEPTIONS__) #define STATUS_USER_DEFINED (1U << 29) diff --git a/gcc/ada/s-osinte-rtems.adb b/gcc/ada/s-osinte-rtems.adb index de21785941a7b..9f01128c9188f 100644 --- a/gcc/ada/s-osinte-rtems.adb +++ b/gcc/ada/s-osinte-rtems.adb @@ -22,7 +22,7 @@ -- You should have received a copy of the GNU General Public License and -- -- a copy of the GCC Runtime Library Exception along with this program; -- -- see the files COPYING3 and COPYING.RUNTIME respectively. If not, see -- --- . +-- . -- -- -- -- GNARL was developed by the GNARL team at Florida State University. It is -- -- now maintained by Ada Core Technologies Inc. in cooperation with Florida -- diff --git a/gcc/ada/socket.c b/gcc/ada/socket.c index 18999b394ea55..e65845628a1d0 100644 --- a/gcc/ada/socket.c +++ b/gcc/ada/socket.c @@ -212,7 +212,7 @@ __gnat_gethostbyname (const char *name, struct hostent *rh; int ri; -#if defined(__linux__) || defined(__GLIBC__) +#if defined(__linux__) || defined(__GLIBC__) || defined(__rtems__) (void) gethostbyname_r (name, ret, buf, buflen, &rh, h_errnop); #else rh = gethostbyname_r (name, ret, buf, buflen, h_errnop); diff --git a/gcc/ada/system-linux-alpha.ads b/gcc/ada/system-linux-alpha.ads index 5d845020446f9..044ab3e1c5383 100644 --- a/gcc/ada/system-linux-alpha.ads +++ b/gcc/ada/system-linux-alpha.ads @@ -7,7 +7,7 @@ -- S p e c -- -- (GNU-Linux/alpha Version) -- -- -- --- Copyright (C) 1992-2012, Free Software Foundation, Inc. -- +-- Copyright (C) 1992-2014, Free Software Foundation, Inc. -- -- -- -- This specification is derived from the Ada Reference Manual for use with -- -- GNAT. The copyright notice above, and the license provisions that follow -- @@ -35,9 +35,10 @@ ------------------------------------------------------------------------------ package System is -pragma Pure (System); --- Note that we take advantage of the implementation permission to --- make this unit Pure instead of Preelaborable, see RM 13.7(36) + pragma Pure; + -- Note that we take advantage of the implementation permission to make + -- this unit Pure instead of Preelaborable; see RM 13.7.1(15). In Ada + -- 2005, this is Pure in any case (AI-362). type Name is (SYSTEM_NAME_GNAT); System_Name : constant Name := SYSTEM_NAME_GNAT; @@ -61,6 +62,7 @@ pragma Pure (System); -- Storage-related Declarations type Address is private; + pragma Preelaborable_Initialization (Address); Null_Address : constant Address; Storage_Unit : constant := 8; diff --git a/gcc/ada/system-linux-mips.ads b/gcc/ada/system-linux-mips.ads index 18f449563d4a2..08724650d4d78 100644 --- a/gcc/ada/system-linux-mips.ads +++ b/gcc/ada/system-linux-mips.ads @@ -7,7 +7,7 @@ -- S p e c -- -- (GNU-Linux/MIPS Version) -- -- -- --- Copyright (C) 1992-2012, Free Software Foundation, Inc. -- +-- Copyright (C) 1992-2014, Free Software Foundation, Inc. -- -- -- -- This specification is derived from the Ada Reference Manual for use with -- -- GNAT. The copyright notice above, and the license provisions that follow -- @@ -62,6 +62,7 @@ package System is -- Storage-related Declarations type Address is private; + pragma Preelaborable_Initialization (Address); Null_Address : constant Address; Storage_Unit : constant := 8; diff --git a/gcc/ada/system-linux-mips64el.ads b/gcc/ada/system-linux-mips64el.ads index 85a0f41c3b0a2..5c8cad177497a 100644 --- a/gcc/ada/system-linux-mips64el.ads +++ b/gcc/ada/system-linux-mips64el.ads @@ -7,7 +7,7 @@ -- S p e c -- -- (GNU-Linux/MIPS64EL Version) -- -- -- --- Copyright (C) 1992-2012, Free Software Foundation, Inc. -- +-- Copyright (C) 1992-2014, Free Software Foundation, Inc. -- -- -- -- This specification is derived from the Ada Reference Manual for use with -- -- GNAT. The copyright notice above, and the license provisions that follow -- @@ -62,6 +62,7 @@ package System is -- Storage-related Declarations type Address is private; + pragma Preelaborable_Initialization (Address); Null_Address : constant Address; Storage_Unit : constant := 8; diff --git a/gcc/ada/system-linux-mipsel.ads b/gcc/ada/system-linux-mipsel.ads index c700048b87972..e6d56fb828644 100644 --- a/gcc/ada/system-linux-mipsel.ads +++ b/gcc/ada/system-linux-mipsel.ads @@ -7,7 +7,7 @@ -- S p e c -- -- (GNU-Linux/MIPSEL Version) -- -- -- --- Copyright (C) 1992-2012, Free Software Foundation, Inc. -- +-- Copyright (C) 1992-2014, Free Software Foundation, Inc. -- -- -- -- This specification is derived from the Ada Reference Manual for use with -- -- GNAT. The copyright notice above, and the license provisions that follow -- @@ -62,6 +62,7 @@ package System is -- Storage-related Declarations type Address is private; + pragma Preelaborable_Initialization (Address); Null_Address : constant Address; Storage_Unit : constant := 8; diff --git a/gcc/ada/system-linux-s390.ads b/gcc/ada/system-linux-s390.ads index 28107a0b46422..e240d2e4864f8 100644 --- a/gcc/ada/system-linux-s390.ads +++ b/gcc/ada/system-linux-s390.ads @@ -7,7 +7,7 @@ -- S p e c -- -- (GNU-Linux/s390 Version) -- -- -- --- Copyright (C) 1992-2012, Free Software Foundation, Inc. -- +-- Copyright (C) 1992-2014, Free Software Foundation, Inc. -- -- -- -- This specification is derived from the Ada Reference Manual for use with -- -- GNAT. The copyright notice above, and the license provisions that follow -- @@ -35,9 +35,10 @@ ------------------------------------------------------------------------------ package System is -pragma Pure (System); --- Note that we take advantage of the implementation permission to --- make this unit Pure instead of Preelaborable, see RM 13.7(36) + pragma Pure; + -- Note that we take advantage of the implementation permission to make + -- this unit Pure instead of Preelaborable; see RM 13.7.1(15). In Ada + -- 2005, this is Pure in any case (AI-362). type Name is (SYSTEM_NAME_GNAT); System_Name : constant Name := SYSTEM_NAME_GNAT; @@ -61,6 +62,7 @@ pragma Pure (System); -- Storage-related Declarations type Address is private; + pragma Preelaborable_Initialization (Address); Null_Address : constant Address; Storage_Unit : constant := 8; diff --git a/gcc/ada/system-linux-s390x.ads b/gcc/ada/system-linux-s390x.ads index 135b5a3b174e9..19d2180ffcc43 100644 --- a/gcc/ada/system-linux-s390x.ads +++ b/gcc/ada/system-linux-s390x.ads @@ -7,7 +7,7 @@ -- S p e c -- -- (GNU-Linux/s390x Version) -- -- -- --- Copyright (C) 1992-2012, Free Software Foundation, Inc. -- +-- Copyright (C) 1992-2014, Free Software Foundation, Inc. -- -- -- -- This specification is derived from the Ada Reference Manual for use with -- -- GNAT. The copyright notice above, and the license provisions that follow -- @@ -35,9 +35,10 @@ ------------------------------------------------------------------------------ package System is -pragma Pure (System); --- Note that we take advantage of the implementation permission to --- make this unit Pure instead of Preelaborable, see RM 13.7(36) + pragma Pure; + -- Note that we take advantage of the implementation permission to make + -- this unit Pure instead of Preelaborable; see RM 13.7.1(15). In Ada + -- 2005, this is Pure in any case (AI-362). type Name is (SYSTEM_NAME_GNAT); System_Name : constant Name := SYSTEM_NAME_GNAT; @@ -61,6 +62,7 @@ pragma Pure (System); -- Storage-related Declarations type Address is private; + pragma Preelaborable_Initialization (Address); Null_Address : constant Address; Storage_Unit : constant := 8; diff --git a/gcc/ada/system-linux-sparc.ads b/gcc/ada/system-linux-sparc.ads index ff93463cf8668..6fde138ea5521 100644 --- a/gcc/ada/system-linux-sparc.ads +++ b/gcc/ada/system-linux-sparc.ads @@ -7,7 +7,7 @@ -- S p e c -- -- (GNU/Linux-SPARC Version) -- -- -- --- Copyright (C) 1992-2012, Free Software Foundation, Inc. -- +-- Copyright (C) 1992-2014, Free Software Foundation, Inc. -- -- -- -- This specification is derived from the Ada Reference Manual for use with -- -- GNAT. The copyright notice above, and the license provisions that follow -- @@ -35,9 +35,10 @@ ------------------------------------------------------------------------------ package System is -pragma Pure (System); --- Note that we take advantage of the implementation permission to --- make this unit Pure instead of Preelaborable, see RM 13.7(36) + pragma Pure; + -- Note that we take advantage of the implementation permission to make + -- this unit Pure instead of Preelaborable; see RM 13.7.1(15). In Ada + -- 2005, this is Pure in any case (AI-362). type Name is (SYSTEM_NAME_GNAT); System_Name : constant Name := SYSTEM_NAME_GNAT; @@ -61,6 +62,7 @@ pragma Pure (System); -- Storage-related Declarations type Address is private; + pragma Preelaborable_Initialization (Address); Null_Address : constant Address; Storage_Unit : constant := 8; diff --git a/gcc/ada/system-linux-sparcv9.ads b/gcc/ada/system-linux-sparcv9.ads index 14d89f929b26d..5b7598f3e43a4 100644 --- a/gcc/ada/system-linux-sparcv9.ads +++ b/gcc/ada/system-linux-sparcv9.ads @@ -7,7 +7,7 @@ -- S p e c -- -- (GNU/Linux-SPARCV9 Version) -- -- -- --- Copyright (C) 1992-2011, Free Software Foundation, Inc. -- +-- Copyright (C) 1992-2014, Free Software Foundation, Inc. -- -- -- -- This specification is derived from the Ada Reference Manual for use with -- -- GNAT. The copyright notice above, and the license provisions that follow -- @@ -35,9 +35,10 @@ ------------------------------------------------------------------------------ package System is -pragma Pure (System); --- Note that we take advantage of the implementation permission to --- make this unit Pure instead of Preelaborable, see RM 13.7(36) + pragma Pure; + -- Note that we take advantage of the implementation permission to make + -- this unit Pure instead of Preelaborable; see RM 13.7.1(15). In Ada + -- 2005, this is Pure in any case (AI-362). type Name is (SYSTEM_NAME_GNAT); System_Name : constant Name := SYSTEM_NAME_GNAT; @@ -61,6 +62,7 @@ pragma Pure (System); -- Storage-related Declarations type Address is private; + pragma Preelaborable_Initialization (Address); Null_Address : constant Address; Storage_Unit : constant := 8; diff --git a/gcc/ada/system-rtems.ads b/gcc/ada/system-rtems.ads index 3cab22abfe4a9..50bf7ac6402f8 100644 --- a/gcc/ada/system-rtems.ads +++ b/gcc/ada/system-rtems.ads @@ -7,7 +7,7 @@ -- S p e c -- -- (Compiler Version) -- -- -- --- Copyright (C) 1992-2011 Free Software Foundation, Inc. -- +-- Copyright (C) 1992-2014 Free Software Foundation, Inc. -- -- -- -- This specification is derived from the Ada Reference Manual for use with -- -- GNAT. The copyright notice above, and the license provisions that follow -- @@ -34,9 +34,8 @@ -- -- ------------------------------------------------------------------------------ --- This version of System is a RTEMS version that is used in building --- the compiler. This is based as closely as possible on the generic --- version with the following exceptions: +-- This version is for RTEMS. It is based as closely as possible on the +-- generic version with the following exceptions: -- + priority definitions package System is @@ -67,6 +66,7 @@ package System is -- Storage-related Declarations type Address is private; + pragma Preelaborable_Initialization (Address); Null_Address : constant Address; Storage_Unit : constant := Standard'Storage_Unit; diff --git a/gcc/ada/system-vxworks-arm.ads b/gcc/ada/system-vxworks-arm.ads index ae8ddd5106552..1bc6e898807af 100644 --- a/gcc/ada/system-vxworks-arm.ads +++ b/gcc/ada/system-vxworks-arm.ads @@ -7,7 +7,7 @@ -- S p e c -- -- (VxWorks Version ARM) -- -- -- --- Copyright (C) 1992-2012, Free Software Foundation, Inc. -- +-- Copyright (C) 1992-2014, Free Software Foundation, Inc. -- -- -- -- This specification is derived from the Ada Reference Manual for use with -- -- GNAT. The copyright notice above, and the license provisions that follow -- @@ -35,10 +35,10 @@ ------------------------------------------------------------------------------ package System is -pragma Pure (System); --- Note that we take advantage of the implementation permission to make this --- unit Pure instead of Preelaborable; see RM 13.7.1(15). In Ada 2005, this is --- Pure in any case (AI-362). + pragma Pure; + -- Note that we take advantage of the implementation permission to make + -- this unit Pure instead of Preelaborable; see RM 13.7.1(15). In Ada + -- 2005, this is Pure in any case (AI-362). type Name is (SYSTEM_NAME_GNAT); System_Name : constant Name := SYSTEM_NAME_GNAT; diff --git a/gcc/ada/targparm.ads b/gcc/ada/targparm.ads index 52a6ee4523522..8751f4f4c9479 100644 --- a/gcc/ada/targparm.ads +++ b/gcc/ada/targparm.ads @@ -436,7 +436,7 @@ package Targparm is -- the source program may not contain explicit 64-bit shifts. In addition, -- the code generated for packed arrays will avoid the use of long shifts. - Support_Nondefault_SSO_On_Target : Boolean := False; + Support_Nondefault_SSO_On_Target : Boolean := True; -- If True, the back end supports the non-default Scalar_Storage_Order -- (i.e. allows non-confirming Scalar_Storage_Order attribute definition -- clauses). diff --git a/gcc/ada/uintp.adb b/gcc/ada/uintp.adb index bc014666224fb..7618898af95df 100644 --- a/gcc/ada/uintp.adb +++ b/gcc/ada/uintp.adb @@ -171,22 +171,6 @@ package body Uintp is -- If Discard_Quotient is True, Quotient is set to No_Uint -- If Discard_Remainder is True, Remainder is set to No_Uint - function Vector_To_Uint - (In_Vec : UI_Vector; - Negative : Boolean) return Uint; - -- Functions that calculate values in UI_Vectors, call this function to - -- create and return the Uint value. In_Vec contains the multiple precision - -- (Base) representation of a non-negative value. Leading zeroes are - -- permitted. Negative is set if the desired result is the negative of the - -- given value. The result will be either the appropriate directly - -- represented value, or a table entry in the proper canonical format is - -- created and returned. - -- - -- Note that Init_Operand puts a signed value in the result vector, but - -- Vector_To_Uint is always presented with a non-negative value. The - -- processing of signs is something that is done by the caller before - -- calling Vector_To_Uint. - ------------ -- Direct -- ------------ diff --git a/gcc/ada/uintp.ads b/gcc/ada/uintp.ads index dcf85a07f375f..d76d285270419 100644 --- a/gcc/ada/uintp.ads +++ b/gcc/ada/uintp.ads @@ -90,6 +90,18 @@ package Uintp is Uint_Minus_80 : constant Uint; Uint_Minus_128 : constant Uint; + type UI_Vector is array (Pos range <>) of Int; + -- Vector containing the integer values of a Uint value + + -- Note: An earlier version of this package used pointers of arrays of Ints + -- (dynamically allocated) for the Uint type. The change leads to a few + -- less natural idioms used throughout this code, but eliminates all uses + -- of the heap except for the table package itself. For example, Uint + -- parameters are often converted to UI_Vectors for internal manipulation. + -- This is done by creating the local UI_Vector using the function N_Digits + -- on the Uint to find the size needed for the vector, and then calling + -- Init_Operand to copy the values out of the table into the vector. + ----------------- -- Subprograms -- ----------------- @@ -252,6 +264,22 @@ package Uintp is -- function is used for capacity checks, and it can be one bit off -- without affecting its usage. + function Vector_To_Uint + (In_Vec : UI_Vector; + Negative : Boolean) return Uint; + -- Functions that calculate values in UI_Vectors, call this function to + -- create and return the Uint value. In_Vec contains the multiple precision + -- (Base) representation of a non-negative value. Leading zeroes are + -- permitted. Negative is set if the desired result is the negative of the + -- given value. The result will be either the appropriate directly + -- represented value, or a table entry in the proper canonical format is + -- created and returned. + -- + -- Note that Init_Operand puts a signed value in the result vector, but + -- Vector_To_Uint is always presented with a non-negative value. The + -- processing of signs is something that is done by the caller before + -- calling Vector_To_Uint. + --------------------- -- Output Routines -- --------------------- @@ -494,18 +522,6 @@ private -- UI_Vector is defined for this purpose and some internal subprograms -- used for converting from one to the other are defined. - type UI_Vector is array (Pos range <>) of Int; - -- Vector containing the integer values of a Uint value - - -- Note: An earlier version of this package used pointers of arrays of Ints - -- (dynamically allocated) for the Uint type. The change leads to a few - -- less natural idioms used throughout this code, but eliminates all uses - -- of the heap except for the table package itself. For example, Uint - -- parameters are often converted to UI_Vectors for internal manipulation. - -- This is done by creating the local UI_Vector using the function N_Digits - -- on the Uint to find the size needed for the vector, and then calling - -- Init_Operand to copy the values out of the table into the vector. - type Uint_Entry is record Length : Pos; -- Length of entry in Udigits table in digits (i.e. in words) diff --git a/gcc/alias.c b/gcc/alias.c index 970bdb0ee9a17..7917d8137e720 100644 --- a/gcc/alias.c +++ b/gcc/alias.c @@ -148,7 +148,7 @@ typedef struct alias_set_entry_d *alias_set_entry; static int rtx_equal_for_memref_p (const_rtx, const_rtx); static int memrefs_conflict_p (int, rtx, int, rtx, HOST_WIDE_INT); static void record_set (rtx, const_rtx, void *); -static int base_alias_check (rtx, rtx, enum machine_mode, +static int base_alias_check (rtx, rtx, rtx, rtx, enum machine_mode, enum machine_mode); static rtx find_base_value (rtx); static int mems_in_disjoint_alias_sets_p (const_rtx, const_rtx); @@ -156,7 +156,9 @@ static int insert_subset_children (splay_tree_node, void*); static alias_set_entry get_alias_set_entry (alias_set_type); static bool nonoverlapping_component_refs_p (const_rtx, const_rtx); static tree decl_for_component_ref (tree); -static int write_dependence_p (const_rtx, const_rtx, int); +static int write_dependence_p (const_rtx, + const_rtx, enum machine_mode, rtx, + bool, bool, bool); static void memory_modified_1 (rtx, const_rtx, void *); @@ -378,17 +380,9 @@ get_alias_set_entry (alias_set_type alias_set) static inline int mems_in_disjoint_alias_sets_p (const_rtx mem1, const_rtx mem2) { -/* Perform a basic sanity check. Namely, that there are no alias sets - if we're not using strict aliasing. This helps to catch bugs - whereby someone uses PUT_CODE, but doesn't clear MEM_ALIAS_SET, or - where a MEM is allocated in some way other than by the use of - gen_rtx_MEM, and the MEM_ALIAS_SET is not cleared. If we begin to - use alias sets to indicate that spilled registers cannot alias each - other, we might need to remove this check. */ - gcc_assert (flag_strict_aliasing - || (!MEM_ALIAS_SET (mem1) && !MEM_ALIAS_SET (mem2))); - - return ! alias_sets_conflict_p (MEM_ALIAS_SET (mem1), MEM_ALIAS_SET (mem2)); + return (flag_strict_aliasing + && ! alias_sets_conflict_p (MEM_ALIAS_SET (mem1), + MEM_ALIAS_SET (mem2))); } /* Insert the NODE into the splay tree given by DATA. Used by @@ -1672,34 +1666,30 @@ find_base_term (rtx x) if (tmp1 == pic_offset_table_rtx && CONSTANT_P (tmp2)) return find_base_term (tmp2); - /* If either operand is known to be a pointer, then use it + /* If either operand is known to be a pointer, then prefer it to determine the base term. */ if (REG_P (tmp1) && REG_POINTER (tmp1)) + ; + else if (REG_P (tmp2) && REG_POINTER (tmp2)) { - rtx base = find_base_term (tmp1); - if (base) - return base; + rtx tem = tmp1; + tmp1 = tmp2; + tmp2 = tem; } - if (REG_P (tmp2) && REG_POINTER (tmp2)) - { - rtx base = find_base_term (tmp2); - if (base) - return base; - } - - /* Neither operand was known to be a pointer. Go ahead and find the - base term for both operands. */ - tmp1 = find_base_term (tmp1); - tmp2 = find_base_term (tmp2); - - /* If either base term is named object or a special address + /* Go ahead and find the base term for both operands. If either base + term is from a pointer or is a named object or a special address (like an argument or stack reference), then use it for the base term. */ - if (tmp1 != 0 && known_base_value_p (tmp1)) + tmp1 = find_base_term (tmp1); + if (tmp1 != NULL_RTX + && ((REG_P (tmp1) && REG_POINTER (tmp1)) + || known_base_value_p (tmp1))) return tmp1; - - if (tmp2 != 0 && known_base_value_p (tmp2)) + tmp2 = find_base_term (tmp2); + if (tmp2 != NULL_RTX + && ((REG_P (tmp2) && REG_POINTER (tmp2)) + || known_base_value_p (tmp2))) return tmp2; /* We could not determine which of the two operands was the @@ -1736,12 +1726,9 @@ may_be_sp_based_p (rtx x) objects, 1 if they might be pointers to the same object. */ static int -base_alias_check (rtx x, rtx y, enum machine_mode x_mode, - enum machine_mode y_mode) +base_alias_check (rtx x, rtx x_base, rtx y, rtx y_base, + enum machine_mode x_mode, enum machine_mode y_mode) { - rtx x_base = find_base_term (x); - rtx y_base = find_base_term (y); - /* If the address itself has no known base see if a known equivalent value has one. If either address still has no known base, nothing is known about aliasing. */ @@ -2451,6 +2438,7 @@ static int true_dependence_1 (const_rtx mem, enum machine_mode mem_mode, rtx mem_addr, const_rtx x, rtx x_addr, bool mem_canonicalized) { + rtx true_mem_addr; rtx base; int ret; @@ -2470,17 +2458,9 @@ true_dependence_1 (const_rtx mem, enum machine_mode mem_mode, rtx mem_addr, || MEM_ALIAS_SET (mem) == ALIAS_SET_MEMORY_BARRIER) return 1; - /* Read-only memory is by definition never modified, and therefore can't - conflict with anything. We don't expect to find read-only set on MEM, - but stupid user tricks can produce them, so don't die. */ - if (MEM_READONLY_P (x)) - return 0; - - /* If we have MEMs referring to different address spaces (which can - potentially overlap), we cannot easily tell from the addresses - whether the references overlap. */ - if (MEM_ADDR_SPACE (mem) != MEM_ADDR_SPACE (x)) - return 1; + if (! x_addr) + x_addr = XEXP (x, 0); + x_addr = get_addr (x_addr); if (! mem_addr) { @@ -2488,22 +2468,23 @@ true_dependence_1 (const_rtx mem, enum machine_mode mem_mode, rtx mem_addr, if (mem_mode == VOIDmode) mem_mode = GET_MODE (mem); } + true_mem_addr = get_addr (mem_addr); - if (! x_addr) - { - x_addr = XEXP (x, 0); - if (!((GET_CODE (x_addr) == VALUE - && GET_CODE (mem_addr) != VALUE - && reg_mentioned_p (x_addr, mem_addr)) - || (GET_CODE (x_addr) != VALUE - && GET_CODE (mem_addr) == VALUE - && reg_mentioned_p (mem_addr, x_addr)))) - { - x_addr = get_addr (x_addr); - if (! mem_canonicalized) - mem_addr = get_addr (mem_addr); - } - } + /* Read-only memory is by definition never modified, and therefore can't + conflict with anything. However, don't assume anything when AND + addresses are involved and leave to the code below to determine + dependence. We don't expect to find read-only set on MEM, but + stupid user tricks can produce them, so don't die. */ + if (MEM_READONLY_P (x) + && GET_CODE (x_addr) != AND + && GET_CODE (true_mem_addr) != AND) + return 0; + + /* If we have MEMs referring to different address spaces (which can + potentially overlap), we cannot easily tell from the addresses + whether the references overlap. */ + if (MEM_ADDR_SPACE (mem) != MEM_ADDR_SPACE (x)) + return 1; base = find_base_term (x_addr); if (base && (GET_CODE (base) == LABEL_REF @@ -2511,12 +2492,14 @@ true_dependence_1 (const_rtx mem, enum machine_mode mem_mode, rtx mem_addr, && CONSTANT_POOL_ADDRESS_P (base)))) return 0; - if (! base_alias_check (x_addr, mem_addr, GET_MODE (x), mem_mode)) + rtx mem_base = find_base_term (true_mem_addr); + if (! base_alias_check (x_addr, base, true_mem_addr, mem_base, + GET_MODE (x), mem_mode)) return 0; x_addr = canon_rtx (x_addr); if (!mem_canonicalized) - mem_addr = canon_rtx (mem_addr); + mem_addr = canon_rtx (true_mem_addr); if ((ret = memrefs_conflict_p (GET_MODE_SIZE (mem_mode), mem_addr, SIZE_FOR_MODE (x), x_addr, 0)) != -1) @@ -2558,15 +2541,25 @@ canon_true_dependence (const_rtx mem, enum machine_mode mem_mode, rtx mem_addr, } /* Returns nonzero if a write to X might alias a previous read from - (or, if WRITEP is nonzero, a write to) MEM. */ + (or, if WRITEP is true, a write to) MEM. + If X_CANONCALIZED is true, then X_ADDR is the canonicalized address of X, + and X_MODE the mode for that access. + If MEM_CANONICALIZED is true, MEM is canonicalized. */ static int -write_dependence_p (const_rtx mem, const_rtx x, int writep) +write_dependence_p (const_rtx mem, + const_rtx x, enum machine_mode x_mode, rtx x_addr, + bool mem_canonicalized, bool x_canonicalized, bool writep) { - rtx x_addr, mem_addr; + rtx mem_addr; + rtx true_mem_addr, true_x_addr; rtx base; int ret; + gcc_checking_assert (x_canonicalized + ? (x_addr != NULL_RTX && x_mode != VOIDmode) + : (x_addr == NULL_RTX && x_mode == VOIDmode)); + if (MEM_VOLATILE_P (x) && MEM_VOLATILE_P (mem)) return 1; @@ -2580,8 +2573,20 @@ write_dependence_p (const_rtx mem, const_rtx x, int writep) || MEM_ALIAS_SET (mem) == ALIAS_SET_MEMORY_BARRIER) return 1; - /* A read from read-only memory can't conflict with read-write memory. */ - if (!writep && MEM_READONLY_P (mem)) + if (!x_addr) + x_addr = XEXP (x, 0); + true_x_addr = get_addr (x_addr); + + mem_addr = XEXP (mem, 0); + true_mem_addr = get_addr (mem_addr); + + /* A read from read-only memory can't conflict with read-write memory. + Don't assume anything when AND addresses are involved and leave to + the code below to determine dependence. */ + if (!writep + && MEM_READONLY_P (mem) + && GET_CODE (true_x_addr) != AND + && GET_CODE (true_mem_addr) != AND) return 0; /* If we have MEMs referring to different address spaces (which can @@ -2590,37 +2595,29 @@ write_dependence_p (const_rtx mem, const_rtx x, int writep) if (MEM_ADDR_SPACE (mem) != MEM_ADDR_SPACE (x)) return 1; - x_addr = XEXP (x, 0); - mem_addr = XEXP (mem, 0); - if (!((GET_CODE (x_addr) == VALUE - && GET_CODE (mem_addr) != VALUE - && reg_mentioned_p (x_addr, mem_addr)) - || (GET_CODE (x_addr) != VALUE - && GET_CODE (mem_addr) == VALUE - && reg_mentioned_p (mem_addr, x_addr)))) - { - x_addr = get_addr (x_addr); - mem_addr = get_addr (mem_addr); - } - - if (! writep) - { - base = find_base_term (mem_addr); - if (base && (GET_CODE (base) == LABEL_REF - || (GET_CODE (base) == SYMBOL_REF - && CONSTANT_POOL_ADDRESS_P (base)))) - return 0; - } + base = find_base_term (true_mem_addr); + if (! writep + && base + && (GET_CODE (base) == LABEL_REF + || (GET_CODE (base) == SYMBOL_REF + && CONSTANT_POOL_ADDRESS_P (base)))) + return 0; - if (! base_alias_check (x_addr, mem_addr, GET_MODE (x), - GET_MODE (mem))) + rtx x_base = find_base_term (true_x_addr); + if (! base_alias_check (true_x_addr, x_base, true_mem_addr, base, + GET_MODE (x), GET_MODE (mem))) return 0; - x_addr = canon_rtx (x_addr); - mem_addr = canon_rtx (mem_addr); + if (!x_canonicalized) + { + x_addr = canon_rtx (true_x_addr); + x_mode = GET_MODE (x); + } + if (!mem_canonicalized) + mem_addr = canon_rtx (true_mem_addr); if ((ret = memrefs_conflict_p (SIZE_FOR_MODE (mem), mem_addr, - SIZE_FOR_MODE (x), x_addr, 0)) != -1) + GET_MODE_SIZE (x_mode), x_addr, 0)) != -1) return ret; if (nonoverlapping_memrefs_p (x, mem, false)) @@ -2634,7 +2631,23 @@ write_dependence_p (const_rtx mem, const_rtx x, int writep) int anti_dependence (const_rtx mem, const_rtx x) { - return write_dependence_p (mem, x, /*writep=*/0); + return write_dependence_p (mem, x, VOIDmode, NULL_RTX, + /*mem_canonicalized=*/false, + /*x_canonicalized*/false, /*writep=*/false); +} + +/* Likewise, but we already have a canonicalized MEM, and X_ADDR for X. + Also, consider X in X_MODE (which might be from an enclosing + STRICT_LOW_PART / ZERO_EXTRACT). + If MEM_CANONICALIZED is true, MEM is canonicalized. */ + +int +canon_anti_dependence (const_rtx mem, bool mem_canonicalized, + const_rtx x, enum machine_mode x_mode, rtx x_addr) +{ + return write_dependence_p (mem, x, x_mode, x_addr, + mem_canonicalized, /*x_canonicalized=*/true, + /*writep=*/false); } /* Output dependence: X is written after store in MEM takes place. */ @@ -2642,7 +2655,9 @@ anti_dependence (const_rtx mem, const_rtx x) int output_dependence (const_rtx mem, const_rtx x) { - return write_dependence_p (mem, x, /*writep=*/1); + return write_dependence_p (mem, x, VOIDmode, NULL_RTX, + /*mem_canonicalized=*/false, + /*x_canonicalized*/false, /*writep=*/true); } @@ -2667,10 +2682,20 @@ may_alias_p (const_rtx mem, const_rtx x) || MEM_ALIAS_SET (mem) == ALIAS_SET_MEMORY_BARRIER) return 1; + x_addr = XEXP (x, 0); + x_addr = get_addr (x_addr); + + mem_addr = XEXP (mem, 0); + mem_addr = get_addr (mem_addr); + /* Read-only memory is by definition never modified, and therefore can't - conflict with anything. We don't expect to find read-only set on MEM, - but stupid user tricks can produce them, so don't die. */ - if (MEM_READONLY_P (x)) + conflict with anything. However, don't assume anything when AND + addresses are involved and leave to the code below to determine + dependence. We don't expect to find read-only set on MEM, but + stupid user tricks can produce them, so don't die. */ + if (MEM_READONLY_P (x) + && GET_CODE (x_addr) != AND + && GET_CODE (mem_addr) != AND) return 0; /* If we have MEMs referring to different address spaces (which can @@ -2679,25 +2704,12 @@ may_alias_p (const_rtx mem, const_rtx x) if (MEM_ADDR_SPACE (mem) != MEM_ADDR_SPACE (x)) return 1; - x_addr = XEXP (x, 0); - mem_addr = XEXP (mem, 0); - if (!((GET_CODE (x_addr) == VALUE - && GET_CODE (mem_addr) != VALUE - && reg_mentioned_p (x_addr, mem_addr)) - || (GET_CODE (x_addr) != VALUE - && GET_CODE (mem_addr) == VALUE - && reg_mentioned_p (mem_addr, x_addr)))) - { - x_addr = get_addr (x_addr); - mem_addr = get_addr (mem_addr); - } - - if (! base_alias_check (x_addr, mem_addr, GET_MODE (x), GET_MODE (mem_addr))) + rtx x_base = find_base_term (x_addr); + rtx mem_base = find_base_term (mem_addr); + if (! base_alias_check (x_addr, x_base, mem_addr, mem_base, + GET_MODE (x), GET_MODE (mem_addr))) return 0; - x_addr = canon_rtx (x_addr); - mem_addr = canon_rtx (mem_addr); - if (nonoverlapping_memrefs_p (mem, x, true)) return 0; @@ -2871,16 +2883,13 @@ init_alias_analysis (void) /* Wipe the reg_seen array clean. */ bitmap_clear (reg_seen); - /* Mark all hard registers which may contain an address. - The stack, frame and argument pointers may contain an address. - An argument register which can hold a Pmode value may contain - an address even if it is not in BASE_REGS. - - The address expression is VOIDmode for an argument and - Pmode for other registers. */ - - memcpy (new_reg_base_value, static_reg_base_value, - FIRST_PSEUDO_REGISTER * sizeof (rtx)); + /* Initialize the alias information for this pass. */ + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + if (static_reg_base_value[i]) + { + new_reg_base_value[i] = static_reg_base_value[i]; + bitmap_set_bit (reg_seen, i); + } /* Walk the insns adding values to the new_reg_base_value array. */ for (i = 0; i < rpo_cnt; i++) diff --git a/gcc/asan.c b/gcc/asan.c index 52a2dbc5dfdd9..d68579b2e5ea2 100644 --- a/gcc/asan.c +++ b/gcc/asan.c @@ -1675,7 +1675,7 @@ instrument_mem_region_access (tree base, tree len, access to the last byte of the argument; it uses the result of the call to deduce the offset of that last byte. - Upon completion, iff the call has actullay been instrumented, this + Upon completion, iff the call has actually been instrumented, this function returns TRUE and *ITER points to the statement logically following the built-in strlen function call *ITER was initially pointing to. Otherwise, the function returns FALSE and *ITER @@ -1706,10 +1706,10 @@ instrument_strlen_call (gimple_stmt_iterator *iter) /* Instrument the access to the first byte of str_arg. i.e: _1 = str_arg; instrument (_1); */ + tree cptr_type = build_pointer_type (char_type_node); gimple str_arg_ssa = gimple_build_assign_with_ops (NOP_EXPR, - make_ssa_name (build_pointer_type - (char_type_node), NULL), + make_ssa_name (cptr_type, NULL), str_arg, NULL); gimple_set_location (str_arg_ssa, loc); gimple_stmt_iterator gsi = *iter; @@ -1728,8 +1728,7 @@ instrument_strlen_call (gimple_stmt_iterator *iter) pointer_plus expr: (_1 + len). */ gimple stmt = gimple_build_assign_with_ops (POINTER_PLUS_EXPR, - make_ssa_name (TREE_TYPE (str_arg), - NULL), + make_ssa_name (cptr_type, NULL), gimple_assign_lhs (str_arg_ssa), len); gimple_set_location (stmt, loc); diff --git a/gcc/bb-reorder.c b/gcc/bb-reorder.c index 20c25bd59e5b1..a38d1153acbec 100644 --- a/gcc/bb-reorder.c +++ b/gcc/bb-reorder.c @@ -1685,9 +1685,8 @@ fix_up_fall_thru_edges (void) edge e; edge_iterator ei; - /* Find EDGE_CAN_FALLTHRU edge. */ FOR_EACH_EDGE (e, ei, cur_bb->succs) - if (e->flags & EDGE_CAN_FALLTHRU) + if (e->flags & EDGE_FALLTHRU) { fall_thru = e; break; diff --git a/gcc/builtins.c b/gcc/builtins.c index 68b6a2cd7cf56..c3c3ce37d39a6 100644 --- a/gcc/builtins.c +++ b/gcc/builtins.c @@ -180,7 +180,6 @@ static tree fold_builtin_varargs (location_t, tree, tree, bool); static tree fold_builtin_strpbrk (location_t, tree, tree, tree); static tree fold_builtin_strstr (location_t, tree, tree, tree); static tree fold_builtin_strrchr (location_t, tree, tree, tree); -static tree fold_builtin_strcat (location_t, tree, tree); static tree fold_builtin_strncat (location_t, tree, tree, tree); static tree fold_builtin_strspn (location_t, tree, tree); static tree fold_builtin_strcspn (location_t, tree, tree); @@ -906,9 +905,24 @@ expand_builtin_setjmp_receiver (rtx receiver_label ATTRIBUTE_UNUSED) if (! HAVE_nonlocal_goto) #endif { + /* First adjust our frame pointer to its actual value. It was + previously set to the start of the virtual area corresponding to + the stacked variables when we branched here and now needs to be + adjusted to the actual hardware fp value. + + Assignments to virtual registers are converted by + instantiate_virtual_regs into the corresponding assignment + to the underlying register (fp in this case) that makes + the original assignment true. + So the following insn will actually be decrementing fp by + STARTING_FRAME_OFFSET. */ emit_move_insn (virtual_stack_vars_rtx, hard_frame_pointer_rtx); - /* This might change the hard frame pointer in ways that aren't - apparent to early optimization passes, so force a clobber. */ + + /* Restoring the frame pointer also modifies the hard frame pointer. + Mark it used (so that the previous assignment remains live once + the frame pointer is eliminated) and clobbered (to represent the + implicit update from the assignment). */ + emit_use (hard_frame_pointer_rtx); emit_clobber (hard_frame_pointer_rtx); } @@ -949,8 +963,7 @@ expand_builtin_setjmp_receiver (rtx receiver_label ATTRIBUTE_UNUSED) /* We must not allow the code we just generated to be reordered by scheduling. Specifically, the update of the frame pointer must - happen immediately, not later. Similarly, we must block - (frame-related) register values to be used across this code. */ + happen immediately, not later. */ emit_insn (gen_blockage ()); } @@ -1958,6 +1971,7 @@ expand_builtin_mathfn (tree exp, rtx target, rtx subtarget) tree fndecl = get_callee_fndecl (exp); enum machine_mode mode; bool errno_set = false; + bool try_widening = false; tree arg; if (!validate_arglist (exp, REAL_TYPE, VOID_TYPE)) @@ -1969,6 +1983,7 @@ expand_builtin_mathfn (tree exp, rtx target, rtx subtarget) { CASE_FLT_FN (BUILT_IN_SQRT): errno_set = ! tree_expr_nonnegative_p (arg); + try_widening = true; builtin_optab = sqrt_optab; break; CASE_FLT_FN (BUILT_IN_EXP): @@ -2025,8 +2040,10 @@ expand_builtin_mathfn (tree exp, rtx target, rtx subtarget) if (! flag_errno_math || ! HONOR_NANS (mode)) errno_set = false; - /* Before working hard, check whether the instruction is available. */ - if (optab_handler (builtin_optab, mode) != CODE_FOR_nothing + /* Before working hard, check whether the instruction is available, but try + to widen the mode for specific operations. */ + if ((optab_handler (builtin_optab, mode) != CODE_FOR_nothing + || (try_widening && !excess_precision_type (TREE_TYPE (exp)))) && (!errno_set || !optimize_insn_for_size_p ())) { rtx result = gen_reg_rtx (mode); @@ -5347,7 +5364,7 @@ static rtx expand_builtin_atomic_compare_exchange (enum machine_mode mode, tree exp, rtx target) { - rtx expect, desired, mem, oldval; + rtx expect, desired, mem, oldval, label; enum memmodel success, failure; tree weak; bool is_weak; @@ -5385,14 +5402,26 @@ expand_builtin_atomic_compare_exchange (enum machine_mode mode, tree exp, if (host_integerp (weak, 0) && tree_low_cst (weak, 0) != 0) is_weak = true; - oldval = expect; - if (!expand_atomic_compare_and_swap ((target == const0_rtx ? NULL : &target), - &oldval, mem, oldval, desired, + if (target == const0_rtx) + target = NULL; + + /* Lest the rtl backend create a race condition with an imporoper store + to memory, always create a new pseudo for OLDVAL. */ + oldval = NULL; + + if (!expand_atomic_compare_and_swap (&target, &oldval, mem, expect, desired, is_weak, success, failure)) return NULL_RTX; - if (oldval != expect) - emit_move_insn (expect, oldval); + /* Conditionally store back to EXPECT, lest we create a race condition + with an improper store to memory. */ + /* ??? With a rearrangement of atomics at the gimple level, we can handle + the normal case where EXPECT is totally private, i.e. a register. At + which point the store can be unconditional. */ + label = gen_label_rtx (); + emit_cmp_and_jump_insns (target, const0_rtx, NE, NULL, VOIDmode, 1, label); + emit_move_insn (expect, oldval); + emit_label (label); return target; } @@ -5846,6 +5875,9 @@ expand_builtin (tree exp, rtx target, rtx subtarget, enum machine_mode mode, switch (fcode) { CASE_FLT_FN (BUILT_IN_FABS): + case BUILT_IN_FABSD32: + case BUILT_IN_FABSD64: + case BUILT_IN_FABSD128: target = expand_builtin_fabs (exp, target, subtarget); if (target) return target; @@ -8879,6 +8911,12 @@ fold_builtin_memory_op (location_t loc, tree dest, tree src, if (!POINTER_TYPE_P (TREE_TYPE (src)) || !POINTER_TYPE_P (TREE_TYPE (dest))) return NULL_TREE; + /* In the following try to find a type that is most natural to be + used for the memcpy source and destination and that allows + the most optimization when memcpy is turned into a plain assignment + using that type. In theory we could always use a char[len] type + but that only gains us that the destination and source possibly + no longer will have their address taken. */ /* As we fold (void *)(p + CST) to (void *)p + CST undo this here. */ if (TREE_CODE (src) == POINTER_PLUS_EXPR) { @@ -8914,6 +8952,41 @@ fold_builtin_memory_op (location_t loc, tree dest, tree src, || TREE_ADDRESSABLE (desttype)) return NULL_TREE; + /* Make sure we are not copying using a floating-point mode or + a type whose size possibly does not match its precision. */ + if (FLOAT_MODE_P (TYPE_MODE (desttype)) + || TREE_CODE (desttype) == BOOLEAN_TYPE + || TREE_CODE (desttype) == ENUMERAL_TYPE) + { + /* A more suitable int_mode_for_mode would return a vector + integer mode for a vector float mode or a integer complex + mode for a float complex mode if there isn't a regular + integer mode covering the mode of desttype. */ + enum machine_mode mode = int_mode_for_mode (TYPE_MODE (desttype)); + if (mode == BLKmode) + desttype = NULL_TREE; + else + desttype = build_nonstandard_integer_type (GET_MODE_BITSIZE (mode), + 1); + } + if (FLOAT_MODE_P (TYPE_MODE (srctype)) + || TREE_CODE (srctype) == BOOLEAN_TYPE + || TREE_CODE (srctype) == ENUMERAL_TYPE) + { + enum machine_mode mode = int_mode_for_mode (TYPE_MODE (srctype)); + if (mode == BLKmode) + srctype = NULL_TREE; + else + srctype = build_nonstandard_integer_type (GET_MODE_BITSIZE (mode), + 1); + } + if (!srctype) + srctype = desttype; + if (!desttype) + desttype = srctype; + if (!srctype) + return NULL_TREE; + src_align = get_pointer_alignment (src); dest_align = get_pointer_alignment (dest); if (dest_align < TYPE_ALIGN (desttype) @@ -9694,7 +9767,16 @@ fold_builtin_logb (location_t loc, tree arg, tree rettype) case rvc_inf: /* If arg is Inf or NaN and we're logb, return it. */ if (TREE_CODE (rettype) == REAL_TYPE) - return fold_convert_loc (loc, rettype, arg); + { + /* For logb(-Inf) we have to return +Inf. */ + if (real_isinf (value) && real_isneg (value)) + { + REAL_VALUE_TYPE tem; + real_inf (&tem); + return build_real (rettype, tem); + } + return fold_convert_loc (loc, rettype, arg); + } /* Fall through... */ case rvc_zero: /* Zero may set errno and/or raise an exception for logb, also @@ -10289,6 +10371,9 @@ fold_builtin_1 (location_t loc, tree fndecl, tree arg0, bool ignore) return fold_builtin_strlen (loc, type, arg0); CASE_FLT_FN (BUILT_IN_FABS): + case BUILT_IN_FABSD32: + case BUILT_IN_FABSD64: + case BUILT_IN_FABSD128: return fold_builtin_fabs (loc, arg0, type); case BUILT_IN_ABS: @@ -10757,7 +10842,7 @@ fold_builtin_2 (location_t loc, tree fndecl, tree arg0, tree arg1, bool ignore) return fold_builtin_strstr (loc, arg0, arg1, type); case BUILT_IN_STRCAT: - return fold_builtin_strcat (loc, arg0, arg1); + return fold_builtin_strcat (loc, arg0, arg1, NULL_TREE); case BUILT_IN_STRSPN: return fold_builtin_strspn (loc, arg0, arg1); @@ -11800,8 +11885,9 @@ fold_builtin_strpbrk (location_t loc, tree s1, tree s2, tree type) COMPOUND_EXPR in the chain will contain the tree for the simplified form of the builtin function call. */ -static tree -fold_builtin_strcat (location_t loc ATTRIBUTE_UNUSED, tree dst, tree src) +tree +fold_builtin_strcat (location_t loc ATTRIBUTE_UNUSED, tree dst, tree src, + tree len) { if (!validate_arg (dst, POINTER_TYPE) || !validate_arg (src, POINTER_TYPE)) @@ -11819,22 +11905,17 @@ fold_builtin_strcat (location_t loc ATTRIBUTE_UNUSED, tree dst, tree src) /* See if we can store by pieces into (dst + strlen(dst)). */ tree newdst, call; tree strlen_fn = builtin_decl_implicit (BUILT_IN_STRLEN); - tree strcpy_fn = builtin_decl_implicit (BUILT_IN_STRCPY); + tree memcpy_fn = builtin_decl_implicit (BUILT_IN_MEMCPY); - if (!strlen_fn || !strcpy_fn) + if (!strlen_fn || !memcpy_fn) return NULL_TREE; - /* If we don't have a movstr we don't want to emit an strcpy - call. We have to do that if the length of the source string - isn't computable (in that case we can use memcpy probably - later expanding to a sequence of mov instructions). If we - have movstr instructions we can emit strcpy calls. */ - if (!HAVE_movstr) - { - tree len = c_strlen (src, 1); - if (! len || TREE_SIDE_EFFECTS (len)) - return NULL_TREE; - } + /* If the length of the source string isn't computable don't + split strcat into strlen and memcpy. */ + if (! len) + len = c_strlen (src, 1); + if (! len || TREE_SIDE_EFFECTS (len)) + return NULL_TREE; /* Stabilize the argument list. */ dst = builtin_save_expr (dst); @@ -11846,7 +11927,11 @@ fold_builtin_strcat (location_t loc ATTRIBUTE_UNUSED, tree dst, tree src) newdst = fold_build_pointer_plus_loc (loc, dst, newdst); newdst = builtin_save_expr (newdst); - call = build_call_expr_loc (loc, strcpy_fn, 2, newdst, src); + len = fold_convert_loc (loc, size_type_node, len); + len = size_binop_loc (loc, PLUS_EXPR, len, + build_int_cst (size_type_node, 1)); + + call = build_call_expr_loc (loc, memcpy_fn, 3, newdst, src, len); return build2 (COMPOUND_EXPR, TREE_TYPE (dst), call, dst); } return NULL_TREE; diff --git a/gcc/builtins.def b/gcc/builtins.def index 4f378fad60b59..d5afe0d054efc 100644 --- a/gcc/builtins.def +++ b/gcc/builtins.def @@ -252,6 +252,9 @@ DEF_C99_BUILTIN (BUILT_IN_EXPM1L, "expm1l", BT_FN_LONGDOUBLE_LONGDOUBLE, DEF_LIB_BUILTIN (BUILT_IN_FABS, "fabs", BT_FN_DOUBLE_DOUBLE, ATTR_CONST_NOTHROW_LEAF_LIST) DEF_C99_C90RES_BUILTIN (BUILT_IN_FABSF, "fabsf", BT_FN_FLOAT_FLOAT, ATTR_CONST_NOTHROW_LEAF_LIST) DEF_C99_C90RES_BUILTIN (BUILT_IN_FABSL, "fabsl", BT_FN_LONGDOUBLE_LONGDOUBLE, ATTR_CONST_NOTHROW_LEAF_LIST) +DEF_GCC_BUILTIN (BUILT_IN_FABSD32, "fabsd32", BT_FN_DFLOAT32_DFLOAT32, ATTR_CONST_NOTHROW_LEAF_LIST) +DEF_GCC_BUILTIN (BUILT_IN_FABSD64, "fabsd64", BT_FN_DFLOAT64_DFLOAT64, ATTR_CONST_NOTHROW_LEAF_LIST) +DEF_GCC_BUILTIN (BUILT_IN_FABSD128, "fabsd128", BT_FN_DFLOAT128_DFLOAT128, ATTR_CONST_NOTHROW_LEAF_LIST) DEF_C99_BUILTIN (BUILT_IN_FDIM, "fdim", BT_FN_DOUBLE_DOUBLE_DOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) DEF_C99_BUILTIN (BUILT_IN_FDIMF, "fdimf", BT_FN_FLOAT_FLOAT_FLOAT, ATTR_MATHFN_FPROUNDING_ERRNO) DEF_C99_BUILTIN (BUILT_IN_FDIML, "fdiml", BT_FN_LONGDOUBLE_LONGDOUBLE_LONGDOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) diff --git a/gcc/c-family/ChangeLog b/gcc/c-family/ChangeLog index dd6cb296a4446..900c4cbfbbcc8 100644 --- a/gcc/c-family/ChangeLog +++ b/gcc/c-family/ChangeLog @@ -1,3 +1,128 @@ +2015-06-23 Release Manager + + * GCC 4.8.5 released. + +2015-02-11 Richard Biener + + Backport from mainline + 2014-07-24 Marek Polacek + + PR c/57653 + * c-opts.c (c_finish_options): If -imacros is in effect, return. + +2015-01-20 Marek Polacek + + Backport from mainline + 2014-06-23 Marek Polacek + + PR c/61553 + * c-common.c (get_atomic_generic_size): Don't segfault if the + type doesn't have a size. + +2014-12-19 Release Manager + + * GCC 4.8.4 released. + +2014-05-22 Release Manager + + * GCC 4.8.3 released. + +2014-05-06 Richard Biener + + * c-opts.c (c_common_post_options): For -freestanding, + -fno-hosted and -fno-builtin disable pattern recognition + if not enabled explicitely. + +2014-04-10 Jakub Jelinek + + Backport from mainline + 2014-03-28 Jakub Jelinek + + PR c++/60689 + * c-common.c (add_atomic_size_parameter): When creating new + params vector, push the size argument first. + + 2014-03-22 Jakub Jelinek + + PR debug/60603 + * c-opts.c (c_finish_options): Restore cb_file_change call to + . + + 2014-03-13 Jakub Jelinek + + PR middle-end/36282 + * c-pragma.c (apply_pragma_weak): Only look at + TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl)) if + DECL_ASSEMBLER_NAME_SET_P (decl). + (maybe_apply_pending_pragma_weaks): Exit early if + vec_safe_is_empty (pending_weaks) rather than only when + !pending_weaks. + (maybe_apply_pragma_weak): Likewise. If !DECL_ASSEMBLER_NAME_SET_P, + set assembler name back to NULL afterwards. + +2014-04-07 Dominique d'Humieres + + Backport from mainline + 2013-09-14 Iain Sandoe + + PR target/48094 + * c.opt (fgnu-runtime, fnext-runtime, fobjc-abi-version, + fobjc-gc, freplace-objc-classes): Accept for LTO. + +2014-03-06 Jakub Jelinek + + Backport from mainline + 2014-02-19 Jakub Jelinek + + PR c/37743 + * c-common.c (c_common_nodes_and_builtins): When initializing + c_uint{16,32,64}_type_node, also set corresponding + uint{16,32,64}_type_node to the same value. + + 2014-02-12 Jakub Jelinek + + PR c/60101 + * c-common.c (merge_tlist): If copy is true, call new_tlist, + if false, add ADD itself, rather than vice versa. + (verify_tree): For COND_EXPR, don't call merge_tlist with non-zero + copy. For SAVE_EXPR, only call merge_tlist once. + +2013-11-29 Jakub Jelinek + + PR c/59280 + * c-common.c (get_priority): If TREE_VALUE (args) is IDENTIFIER_NODE, + goto invalid. If it is error_mark_node, don't issue further + diagnostics. + +2013-11-04 Marek Polacek + + Backport from mainline + 2013-11-04 Marek Polacek + + PR c++/58979 + * c-common.c (invalid_indirection_error): Handle RO_ARROW_STAR case. + +2013-10-16 Release Manager + + * GCC 4.8.2 released. + +2013-08-09 Arnaud Charlet + + * c-ada-spec.c (print_ada_declaration): Prevent accessing null asm name + +2013-05-31 Release Manager + + * GCC 4.8.1 released. + +2013-05-14 Jakub Jelinek + + PR c++/57274 + * c-common.c (verify_tree): Don't recurse into SIZEOF_EXPR. + +2013-03-22 Release Manager + + * GCC 4.8.0 released. + 2013-03-09 Richard Sandiford PR middle-end/56524 diff --git a/gcc/c-family/c-ada-spec.c b/gcc/c-family/c-ada-spec.c index 21cbfe94fba66..2d6ce14ca48d0 100644 --- a/gcc/c-family/c-ada-spec.c +++ b/gcc/c-family/c-ada-spec.c @@ -2900,7 +2900,7 @@ print_ada_declaration (pretty_printer *buffer, tree t, tree type, pp_string (buffer, " -- "); dump_sloc (buffer, t); - if (is_abstract) + if (is_abstract || !DECL_ASSEMBLER_NAME (t)) return 1; newline_and_indent (buffer, spc); diff --git a/gcc/c-family/c-common.c b/gcc/c-family/c-common.c index c7cdd0fc7a0bb..f41ec9ca88960 100644 --- a/gcc/c-family/c-common.c +++ b/gcc/c-family/c-common.c @@ -2894,7 +2894,7 @@ merge_tlist (struct tlist **to, struct tlist *add, int copy) } if (!found) { - *end = copy ? add : new_tlist (NULL, add->expr, add->writer); + *end = copy ? new_tlist (NULL, add->expr, add->writer) : add; end = &(*end)->next; *end = 0; } @@ -3032,6 +3032,7 @@ verify_tree (tree x, struct tlist **pbefore_sp, struct tlist **pno_sp, switch (code) { case CONSTRUCTOR: + case SIZEOF_EXPR: return; case COMPOUND_EXPR: @@ -3051,7 +3052,7 @@ verify_tree (tree x, struct tlist **pbefore_sp, struct tlist **pno_sp, verify_tree (TREE_OPERAND (x, 0), &tmp_before, &tmp_list2, NULL_TREE); warn_for_collisions (tmp_list2); merge_tlist (pbefore_sp, tmp_before, 0); - merge_tlist (pbefore_sp, tmp_list2, 1); + merge_tlist (pbefore_sp, tmp_list2, 0); tmp_list3 = tmp_nosp = 0; verify_tree (TREE_OPERAND (x, 1), &tmp_list3, &tmp_nosp, NULL_TREE); @@ -3155,12 +3156,7 @@ verify_tree (tree x, struct tlist **pbefore_sp, struct tlist **pno_sp, warn_for_collisions (tmp_nosp); tmp_list3 = 0; - while (tmp_nosp) - { - struct tlist *t = tmp_nosp; - tmp_nosp = t->next; - merge_tlist (&tmp_list3, t, 0); - } + merge_tlist (&tmp_list3, tmp_nosp, 0); t->cache_before_sp = tmp_before; t->cache_after_sp = tmp_list3; } @@ -5510,13 +5506,13 @@ c_common_nodes_and_builtins (void) uint8_type_node = TREE_TYPE (identifier_global_value (c_get_ident (UINT8_TYPE))); if (UINT16_TYPE) - c_uint16_type_node = + c_uint16_type_node = uint16_type_node = TREE_TYPE (identifier_global_value (c_get_ident (UINT16_TYPE))); if (UINT32_TYPE) - c_uint32_type_node = + c_uint32_type_node = uint32_type_node = TREE_TYPE (identifier_global_value (c_get_ident (UINT32_TYPE))); if (UINT64_TYPE) - c_uint64_type_node = + c_uint64_type_node = uint64_type_node = TREE_TYPE (identifier_global_value (c_get_ident (UINT64_TYPE))); if (INT_LEAST8_TYPE) int_least8_type_node = @@ -6916,6 +6912,10 @@ get_priority (tree args, bool is_destructor) } arg = TREE_VALUE (args); + if (TREE_CODE (arg) == IDENTIFIER_NODE) + goto invalid; + if (arg == error_mark_node) + return DEFAULT_INIT_PRIORITY; arg = default_conversion (arg); if (!host_integerp (arg, /*pos=*/0) || !INTEGRAL_TYPE_P (TREE_TYPE (arg))) @@ -9762,6 +9762,11 @@ invalid_indirection_error (location_t loc, tree type, ref_operator errstring) "invalid type argument of %<->%> (have %qT)", type); break; + case RO_ARROW_STAR: + error_at (loc, + "invalid type argument of %<->*%> (have %qT)", + type); + break; case RO_IMPLICIT_CONVERSION: error_at (loc, "invalid type argument of implicit conversion (have %qT)", @@ -10138,7 +10143,8 @@ get_atomic_generic_size (location_t loc, tree function, function); return 0; } - size = tree_low_cst (TYPE_SIZE_UNIT (TREE_TYPE (type)), 1); + tree type_size = TYPE_SIZE_UNIT (TREE_TYPE (type)); + size = type_size ? tree_low_cst (type_size, 1) : 0; if (size != size_0) { error_at (loc, "size mismatch in argument %d of %qE", x + 1, @@ -10197,6 +10203,7 @@ add_atomic_size_parameter (unsigned n, location_t loc, tree function, len = params->length (); vec_alloc (v, len + 1); + v->quick_push (build_int_cst (size_type_node, n)); for (z = 0; z < len; z++) v->quick_push ((*params)[z]); f = build_function_call_vec (loc, function, v, NULL); diff --git a/gcc/c-family/c-opts.c b/gcc/c-family/c-opts.c index 4b6990a60c19b..30de1e113bee9 100644 --- a/gcc/c-family/c-opts.c +++ b/gcc/c-family/c-opts.c @@ -840,6 +840,12 @@ c_common_post_options (const char **pfilename) if (flag_objc_exceptions && !flag_objc_sjlj_exceptions) flag_exceptions = 1; + /* If -ffreestanding, -fno-hosted or -fno-builtin then disable + pattern recognition. */ + if (!global_options_set.x_flag_tree_loop_distribute_patterns + && flag_no_builtin) + flag_tree_loop_distribute_patterns = 0; + /* -Woverlength-strings is off by default, but is enabled by -Wpedantic. It is never enabled in C++, as the minimum limit is not normative in that standard. */ @@ -1258,17 +1264,18 @@ c_finish_options (void) { size_t i; - { - /* Make sure all of the builtins about to be declared have - BUILTINS_LOCATION has their source_location. */ - source_location builtins_loc = BUILTINS_LOCATION; - cpp_force_token_locations (parse_in, &builtins_loc); + cb_file_change (parse_in, + linemap_add (line_table, LC_RENAME, 0, + _(""), 0)); + /* Make sure all of the builtins about to be declared have + BUILTINS_LOCATION has their source_location. */ + source_location builtins_loc = BUILTINS_LOCATION; + cpp_force_token_locations (parse_in, &builtins_loc); - cpp_init_builtins (parse_in, flag_hosted); - c_cpp_builtins (parse_in); + cpp_init_builtins (parse_in, flag_hosted); + c_cpp_builtins (parse_in); - cpp_stop_forcing_token_locations (parse_in); - } + cpp_stop_forcing_token_locations (parse_in); /* We're about to send user input to cpplib, so make it warn for things that we previously (when we sent it internal definitions) @@ -1340,6 +1347,12 @@ c_finish_options (void) static void push_command_line_include (void) { + /* This can happen if disabled by -imacros for example. + Punt so that we don't set "" as the filename for + the header. */ + if (include_cursor > deferred_count) + return; + if (!done_preinclude) { done_preinclude = true; diff --git a/gcc/c-family/c-pragma.c b/gcc/c-family/c-pragma.c index 7d8a1a6058cb7..cd90433789230 100644 --- a/gcc/c-family/c-pragma.c +++ b/gcc/c-family/c-pragma.c @@ -259,6 +259,7 @@ apply_pragma_weak (tree decl, tree value) if (SUPPORTS_WEAK && DECL_EXTERNAL (decl) && TREE_USED (decl) && !DECL_WEAK (decl) /* Don't complain about a redundant #pragma. */ + && DECL_ASSEMBLER_NAME_SET_P (decl) && TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl))) warning (OPT_Wpragmas, "applying #pragma weak %q+D after first use " "results in unspecified behavior", decl); @@ -276,7 +277,7 @@ maybe_apply_pragma_weak (tree decl) /* Avoid asking for DECL_ASSEMBLER_NAME when it's not needed. */ /* No weak symbols pending, take the short-cut. */ - if (!pending_weaks) + if (vec_safe_is_empty (pending_weaks)) return; /* If it's not visible outside this file, it doesn't matter whether it's weak. */ @@ -288,7 +289,13 @@ maybe_apply_pragma_weak (tree decl) if (TREE_CODE (decl) != FUNCTION_DECL && TREE_CODE (decl) != VAR_DECL) return; - id = DECL_ASSEMBLER_NAME (decl); + if (DECL_ASSEMBLER_NAME_SET_P (decl)) + id = DECL_ASSEMBLER_NAME (decl); + else + { + id = DECL_ASSEMBLER_NAME (decl); + SET_DECL_ASSEMBLER_NAME (decl, NULL_TREE); + } FOR_EACH_VEC_ELT (*pending_weaks, i, pe) if (id == pe->name) @@ -309,7 +316,7 @@ maybe_apply_pending_pragma_weaks (void) pending_weak *pe; symtab_node target; - if (!pending_weaks) + if (vec_safe_is_empty (pending_weaks)) return; FOR_EACH_VEC_ELT (*pending_weaks, i, pe) diff --git a/gcc/c-family/c.opt b/gcc/c-family/c.opt index 10ae84dbb24b9..4da80b0edf558 100644 --- a/gcc/c-family/c.opt +++ b/gcc/c-family/c.opt @@ -933,7 +933,7 @@ C++ ObjC++ Var(flag_no_gnu_keywords, 0) Recognize GNU-defined keywords fgnu-runtime -ObjC ObjC++ Report RejectNegative Var(flag_next_runtime,0) Init(NEXT_OBJC_RUNTIME) +ObjC ObjC++ LTO Report RejectNegative Var(flag_next_runtime,0) Init(NEXT_OBJC_RUNTIME) Generate code for GNU runtime environment fgnu89-inline @@ -1007,7 +1007,7 @@ fnew-abi C++ ObjC++ Ignore Warn(switch %qs is no longer supported) fnext-runtime -ObjC ObjC++ Report RejectNegative Var(flag_next_runtime) +ObjC ObjC++ LTO Report RejectNegative Var(flag_next_runtime) Generate code for NeXT (Apple Mac OS X) runtime environment fnil-receivers @@ -1025,7 +1025,7 @@ C++ ObjC++ Optimization Var(flag_nothrow_opt) Treat a throw() exception specification as noexcept to improve code size fobjc-abi-version= -ObjC ObjC++ Joined Report RejectNegative UInteger Var(flag_objc_abi) +ObjC ObjC++ LTO Joined Report RejectNegative UInteger Var(flag_objc_abi) Specify which ABI to use for Objective-C family code and meta-data generation. ; Generate special '- .cxx_construct' and '- .cxx_destruct' methods @@ -1045,7 +1045,7 @@ ObjC ObjC++ Var(flag_objc_exceptions) Enable Objective-C exception and synchronization syntax fobjc-gc -ObjC ObjC++ Var(flag_objc_gc) +ObjC ObjC++ LTO Var(flag_objc_gc) Enable garbage collection (GC) in Objective-C/Objective-C++ programs fobjc-nilcheck @@ -1105,7 +1105,7 @@ C++ ObjC++ Var(flag_pretty_templates) Init(1) -fno-pretty-templates Do not pretty-print template specializations as the template signature followed by the arguments freplace-objc-classes -ObjC ObjC++ Var(flag_replace_objc_classes) +ObjC ObjC++ LTO Var(flag_replace_objc_classes) Used in Fix-and-Continue mode to indicate that object files may be swapped in at runtime frepo diff --git a/gcc/c/ChangeLog b/gcc/c/ChangeLog index 4c8e455e9d27d..f662d7295f972 100644 --- a/gcc/c/ChangeLog +++ b/gcc/c/ChangeLog @@ -1,3 +1,82 @@ +2015-06-23 Release Manager + + * GCC 4.8.5 released. + +2015-02-01 Jakub Jelinek + + Backported from mainline + 2015-01-27 Jakub Jelinek + + PR c/64766 + * c-typeck.c (store_init_value): Don't overwrite DECL_INITIAL + of FUNCTION_DECLs with error_mark_node. + +2014-12-19 Release Manager + + * GCC 4.8.4 released. + +2014-05-22 Release Manager + + * GCC 4.8.3 released. + +2014-04-10 Jakub Jelinek + + Backport from mainline + 2014-03-28 Jakub Jelinek + + PR c++/60689 + * c-tree.h (c_build_function_call_vec): New prototype. + * c-typeck.c (build_function_call_vec): Don't call + resolve_overloaded_builtin here. + (c_build_function_call_vec): New wrapper function around + build_function_call_vec. Call resolve_overloaded_builtin here. + (convert_lvalue_to_rvalue, build_function_call, build_atomic_assign): + Call c_build_function_call_vec instead of build_function_call_vec. + * c-parser.c (c_parser_postfix_expression_after_primary): Likewise. + * c-decl.c (finish_decl): Likewise. + +2014-01-23 Jakub Jelinek + + PR middle-end/58809 + * c-typeck.c (c_finish_omp_clause): Reject MIN_EXPR, MAX_EXPR, + BIT_AND_EXPR, BIT_IOR_EXPR and BIT_XOR_EXPR on COMPLEX_TYPEs. + +2014-01-22 Marek Polacek + + Backport from mainline + 2014-01-22 Marek Polacek + + PR c/59891 + * c-typeck.c (build_conditional_expr): Call c_fully_fold instead + of remove_c_maybe_const_expr on op1 and op2. + +2013-12-03 Marek Polacek + + Backport from mainline + 2013-12-03 Marek Polacek + + PR c/59351 + * c-decl.c (build_compound_literal): Allow compound literals with + empty initial value. + +2013-11-27 Tom de Vries + Marc Glisse + + PR c++/59032 + * c-typeck.c (build_unary_op): Allow vector increment and decrement. + +2013-10-16 Release Manager + + * GCC 4.8.2 released. + +2013-05-31 Release Manager + + * GCC 4.8.1 released. + +2013-03-22 Release Manager + + * GCC 4.8.0 released. + 2013-02-12 Marek Polacek PR c/44938 diff --git a/gcc/c/c-decl.c b/gcc/c/c-decl.c index d9bbf5c25f9c3..a9108e79001df 100644 --- a/gcc/c/c-decl.c +++ b/gcc/c/c-decl.c @@ -4507,8 +4507,8 @@ finish_decl (tree decl, location_t init_loc, tree init, cleanup = build_unary_op (input_location, ADDR_EXPR, decl, 0); vec_alloc (v, 1); v->quick_push (cleanup); - cleanup = build_function_call_vec (DECL_SOURCE_LOCATION (decl), - cleanup_decl, v, NULL); + cleanup = c_build_function_call_vec (DECL_SOURCE_LOCATION (decl), + cleanup_decl, v, NULL); vec_free (v); /* Don't warn about decl unused; the cleanup uses it. */ @@ -4632,7 +4632,9 @@ build_compound_literal (location_t loc, tree type, tree init, bool non_const) { int failure = complete_array_type (&TREE_TYPE (decl), DECL_INITIAL (decl), true); - gcc_assert (!failure); + /* If complete_array_type returns 3, it means that the + initial value of the compound literal is empty. Allow it. */ + gcc_assert (failure == 0 || failure == 3); type = TREE_TYPE (decl); TREE_TYPE (DECL_INITIAL (decl)) = type; diff --git a/gcc/c/c-parser.c b/gcc/c/c-parser.c index 2ae46220ac14c..215327356cb06 100644 --- a/gcc/c/c-parser.c +++ b/gcc/c/c-parser.c @@ -6904,8 +6904,8 @@ c_parser_postfix_expression_after_primary (c_parser *parser, sizeof_ptr_memacc_comptypes); /* FIXME diagnostics: Ideally we want the FUNCNAME, not the "(" after the FUNCNAME, which is what we have now. */ - expr.value = build_function_call_vec (op_loc, expr.value, exprlist, - origtypes); + expr.value = c_build_function_call_vec (op_loc, expr.value, exprlist, + origtypes); expr.original_code = ERROR_MARK; if (TREE_CODE (expr.value) == INTEGER_CST && TREE_CODE (orig_expr.value) == FUNCTION_DECL diff --git a/gcc/c/c-tree.h b/gcc/c/c-tree.h index d1a871daa683c..1e6e68acb80a4 100644 --- a/gcc/c/c-tree.h +++ b/gcc/c/c-tree.h @@ -640,6 +640,8 @@ extern tree c_finish_omp_task (location_t, tree, tree); extern tree c_finish_omp_clauses (tree); extern tree c_build_va_arg (location_t, tree, tree); extern tree c_finish_transaction (location_t, tree, int); +extern tree c_build_function_call_vec (location_t, tree, vec *, + vec *); /* Set to 0 at beginning of a function definition, set to 1 if a return statement that specifies a return value is seen. */ diff --git a/gcc/c/c-typeck.c b/gcc/c/c-typeck.c index ddb6d39774f95..a608fb6ddc6ff 100644 --- a/gcc/c/c-typeck.c +++ b/gcc/c/c-typeck.c @@ -2666,7 +2666,7 @@ build_function_call (location_t loc, tree function, tree params) vec_alloc (v, list_length (params)); for (; params; params = TREE_CHAIN (params)) v->quick_push (TREE_VALUE (params)); - ret = build_function_call_vec (loc, function, v, NULL); + ret = c_build_function_call_vec (loc, function, v, NULL); vec_free (v); return ret; } @@ -2705,14 +2705,6 @@ build_function_call_vec (location_t loc, tree function, /* Convert anything with function type to a pointer-to-function. */ if (TREE_CODE (function) == FUNCTION_DECL) { - /* Implement type-directed function overloading for builtins. - resolve_overloaded_builtin and targetm.resolve_overloaded_builtin - handle all the type checking. The result is a complete expression - that implements this function call. */ - tem = resolve_overloaded_builtin (loc, function, params); - if (tem) - return tem; - name = DECL_NAME (function); if (flag_tm) @@ -2863,6 +2855,30 @@ build_function_call_vec (location_t loc, tree function, } return require_complete_type (result); } + +/* Like build_function_call_vec, but call also resolve_overloaded_builtin. */ + +tree +c_build_function_call_vec (location_t loc, tree function, + vec *params, + vec *origtypes) +{ + /* Strip NON_LVALUE_EXPRs, etc., since we aren't using as an lvalue. */ + STRIP_TYPE_NOPS (function); + + /* Convert anything with function type to a pointer-to-function. */ + if (TREE_CODE (function) == FUNCTION_DECL) + { + /* Implement type-directed function overloading for builtins. + resolve_overloaded_builtin and targetm.resolve_overloaded_builtin + handle all the type checking. The result is a complete expression + that implements this function call. */ + tree tem = resolve_overloaded_builtin (loc, function, params); + if (tem) + return tem; + } + return build_function_call_vec (loc, function, params, origtypes); +} /* Convert the argument expressions in the vector VALUES to the types in the list TYPELIST. @@ -3629,7 +3645,8 @@ build_unary_op (location_t location, /* Report invalid types. */ if (typecode != POINTER_TYPE && typecode != FIXED_POINT_TYPE - && typecode != INTEGER_TYPE && typecode != REAL_TYPE) + && typecode != INTEGER_TYPE && typecode != REAL_TYPE + && typecode != VECTOR_TYPE) { if (code == PREINCREMENT_EXPR || code == POSTINCREMENT_EXPR) error_at (location, "wrong type argument to increment"); @@ -3694,7 +3711,9 @@ build_unary_op (location_t location, } else { - inc = integer_one_node; + inc = (TREE_CODE (argtype) == VECTOR_TYPE + ? build_one_cst (argtype) + : integer_one_node); inc = convert (argtype, inc); } @@ -4331,8 +4350,10 @@ build_conditional_expr (location_t colon_loc, tree ifexp, bool ifexp_bcp, { if (int_operands) { - op1 = remove_c_maybe_const_expr (op1); - op2 = remove_c_maybe_const_expr (op2); + /* Use c_fully_fold here, since C_MAYBE_CONST_EXPR might be + nested inside of the expression. */ + op1 = c_fully_fold (op1, false, NULL); + op2 = c_fully_fold (op2, false, NULL); } ret = build3 (COND_EXPR, result_type, ifexp, op1, op2); if (int_operands) @@ -5767,7 +5788,8 @@ store_init_value (location_t init_loc, tree decl, tree init, tree origtype) warning (OPT_Wtraditional, "traditional C rejects automatic " "aggregate initialization"); - DECL_INITIAL (decl) = value; + if (value != error_mark_node || TREE_CODE (decl) != FUNCTION_DECL) + DECL_INITIAL (decl) = value; /* ANSI wants warnings about out-of-range constant initializers. */ STRIP_TYPE_NOPS (value); @@ -10618,7 +10640,8 @@ c_finish_omp_clauses (tree clauses) "%qE has invalid type for %", t); remove = true; } - else if (FLOAT_TYPE_P (TREE_TYPE (t))) + else if (FLOAT_TYPE_P (TREE_TYPE (t)) + || TREE_CODE (TREE_TYPE (t)) == COMPLEX_TYPE) { enum tree_code r_code = OMP_CLAUSE_REDUCTION_CODE (c); const char *r_name = NULL; @@ -10628,8 +10651,14 @@ c_finish_omp_clauses (tree clauses) case PLUS_EXPR: case MULT_EXPR: case MINUS_EXPR: + break; case MIN_EXPR: + if (TREE_CODE (TREE_TYPE (t)) == COMPLEX_TYPE) + r_name = "min"; + break; case MAX_EXPR: + if (TREE_CODE (TREE_TYPE (t)) == COMPLEX_TYPE) + r_name = "max"; break; case BIT_AND_EXPR: r_name = "&"; @@ -10641,10 +10670,12 @@ c_finish_omp_clauses (tree clauses) r_name = "|"; break; case TRUTH_ANDIF_EXPR: - r_name = "&&"; + if (FLOAT_TYPE_P (TREE_TYPE (t))) + r_name = "&&"; break; case TRUTH_ORIF_EXPR: - r_name = "||"; + if (FLOAT_TYPE_P (TREE_TYPE (t))) + r_name = "||"; break; default: gcc_unreachable (); diff --git a/gcc/calls.c b/gcc/calls.c index dd034b4009927..bf0ba306b6615 100644 --- a/gcc/calls.c +++ b/gcc/calls.c @@ -983,6 +983,7 @@ store_unaligned_arguments_into_pseudos (struct arg_data *args, int num_actuals) for (i = 0; i < num_actuals; i++) if (args[i].reg != 0 && ! args[i].pass_on_stack + && GET_CODE (args[i].reg) != PARALLEL && args[i].mode == BLKmode && MEM_P (args[i].value) && (MEM_ALIGN (args[i].value) @@ -1327,6 +1328,7 @@ initialize_argument_information (int num_actuals ATTRIBUTE_UNUSED, #else args[i].reg != 0, #endif + reg_parm_stack_space, args[i].pass_on_stack ? 0 : args[i].partial, fndecl, args_size, &args[i].locate); #ifdef BLOCK_REG_PADDING @@ -3171,7 +3173,9 @@ expand_call (tree exp, rtx target, int ignore) group load/store machinery below. */ if (!structure_value_addr && !pcc_struct_value + && TYPE_MODE (rettype) != VOIDmode && TYPE_MODE (rettype) != BLKmode + && REG_P (valreg) && targetm.calls.return_in_msb (rettype)) { if (shift_return_value (TYPE_MODE (rettype), false, valreg)) @@ -3734,7 +3738,8 @@ emit_library_call_value_1 (int retval, rtx orgfun, rtx value, #else argvec[count].reg != 0, #endif - 0, NULL_TREE, &args_size, &argvec[count].locate); + reg_parm_stack_space, 0, + NULL_TREE, &args_size, &argvec[count].locate); if (argvec[count].reg == 0 || argvec[count].partial != 0 || reg_parm_stack_space > 0) @@ -3821,7 +3826,7 @@ emit_library_call_value_1 (int retval, rtx orgfun, rtx value, #else argvec[count].reg != 0, #endif - argvec[count].partial, + reg_parm_stack_space, argvec[count].partial, NULL_TREE, &args_size, &argvec[count].locate); args_size.constant += argvec[count].locate.size.constant; gcc_assert (!argvec[count].locate.size.var); diff --git a/gcc/cfgcleanup.c b/gcc/cfgcleanup.c index 471d293f12ffc..3f930b836c3f3 100644 --- a/gcc/cfgcleanup.c +++ b/gcc/cfgcleanup.c @@ -927,6 +927,24 @@ merge_memattrs (rtx x, rtx y) set_mem_align (y, MEM_ALIGN (x)); } } + if (code == MEM) + { + if (MEM_READONLY_P (x) != MEM_READONLY_P (y)) + { + MEM_READONLY_P (x) = 0; + MEM_READONLY_P (y) = 0; + } + if (MEM_NOTRAP_P (x) != MEM_NOTRAP_P (y)) + { + MEM_NOTRAP_P (x) = 0; + MEM_NOTRAP_P (y) = 0; + } + if (MEM_VOLATILE_P (x) != MEM_VOLATILE_P (y)) + { + MEM_VOLATILE_P (x) = 1; + MEM_VOLATILE_P (y) = 1; + } + } fmt = GET_RTX_FORMAT (code); for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) @@ -1275,7 +1293,6 @@ flow_find_cross_jump (basic_block bb1, basic_block bb2, rtx *f1, rtx *f2, { rtx i1, i2, last1, last2, afterlast1, afterlast2; int ninsns = 0; - rtx p1; enum replace_direction dir, last_dir, afterlast_dir; bool follow_fallthru, did_fallthru; @@ -1303,8 +1320,9 @@ flow_find_cross_jump (basic_block bb1, basic_block bb2, rtx *f1, rtx *f2, || (returnjump_p (i2) && !side_effects_p (PATTERN (i2)))) { last2 = i2; - /* Count everything except for unconditional jump as insn. */ - if (!simplejump_p (i2) && !returnjump_p (i2) && last1) + /* Count everything except for unconditional jump as insn. + Don't count any jumps if dir_p is NULL. */ + if (!simplejump_p (i2) && !returnjump_p (i2) && last1 && dir_p) ninsns++; i2 = PREV_INSN (i2); } @@ -1355,8 +1373,8 @@ flow_find_cross_jump (basic_block bb1, basic_block bb2, rtx *f1, rtx *f2, last1 = i1, last2 = i2; afterlast_dir = last_dir; last_dir = dir; - p1 = PATTERN (i1); - if (!(GET_CODE (p1) == USE || GET_CODE (p1) == CLOBBER)) + if (GET_CODE (PATTERN (i1)) != USE + && GET_CODE (PATTERN (i1)) != CLOBBER) ninsns++; } @@ -1402,7 +1420,8 @@ flow_find_cross_jump (basic_block bb1, basic_block bb2, rtx *f1, rtx *f2, /* Like flow_find_cross_jump, except start looking for a matching sequence from the head of the two blocks. Do not include jumps at the end. If STOP_AFTER is nonzero, stop after finding that many matching - instructions. */ + instructions. If STOP_AFTER is zero, count all INSN_P insns, if it is + non-zero, only count active insns. */ int flow_find_head_matching_sequence (basic_block bb1, basic_block bb2, rtx *f1, @@ -1474,7 +1493,10 @@ flow_find_head_matching_sequence (basic_block bb1, basic_block bb2, rtx *f1, beforelast1 = last1, beforelast2 = last2; last1 = i1, last2 = i2; - ninsns++; + if (!stop_after + || (GET_CODE (PATTERN (i1)) != USE + && GET_CODE (PATTERN (i1)) != CLOBBER)) + ninsns++; } if (i1 == BB_END (bb1) || i2 == BB_END (bb2) diff --git a/gcc/cfgexpand.c b/gcc/cfgexpand.c index 5acc42d73f544..3edfeeea3d0ae 100644 --- a/gcc/cfgexpand.c +++ b/gcc/cfgexpand.c @@ -331,7 +331,7 @@ stack_var_conflict_p (size_t x, size_t y) enter its partition number into bitmap DATA. */ static bool -visit_op (gimple stmt ATTRIBUTE_UNUSED, tree op, void *data) +visit_op (gimple, tree op, tree, void *data) { bitmap active = (bitmap)data; op = get_base_address (op); @@ -351,7 +351,7 @@ visit_op (gimple stmt ATTRIBUTE_UNUSED, tree op, void *data) from bitmap DATA. */ static bool -visit_conflict (gimple stmt ATTRIBUTE_UNUSED, tree op, void *data) +visit_conflict (gimple, tree op, tree, void *data) { bitmap active = (bitmap)data; op = get_base_address (op); @@ -385,7 +385,7 @@ add_scope_conflicts_1 (basic_block bb, bitmap work, bool for_conflict) edge e; edge_iterator ei; gimple_stmt_iterator gsi; - bool (*visit)(gimple, tree, void *); + walk_stmt_load_store_addr_fn visit; bitmap_clear (work); FOR_EACH_EDGE (e, ei, bb->preds) @@ -2111,7 +2111,7 @@ expand_call_stmt (gimple stmt) if (lhs) expand_assignment (lhs, exp, false); else - expand_expr_real_1 (exp, const0_rtx, VOIDmode, EXPAND_NORMAL, NULL); + expand_expr (exp, const0_rtx, VOIDmode, EXPAND_NORMAL); mark_transaction_restart_calls (stmt); } @@ -4707,14 +4707,18 @@ gimple_expand_cfg (void) if (e->insns.r) { rebuild_jump_labels_chain (e->insns.r); - /* Avoid putting insns before parm_birth_insn. */ + /* Put insns after parm birth, but before + NOTE_INSNS_FUNCTION_BEG. */ if (e->src == ENTRY_BLOCK_PTR - && single_succ_p (ENTRY_BLOCK_PTR) - && parm_birth_insn) + && single_succ_p (ENTRY_BLOCK_PTR)) { rtx insns = e->insns.r; e->insns.r = NULL_RTX; - emit_insn_after_noloc (insns, parm_birth_insn, e->dest); + if (NOTE_P (parm_birth_insn) + && NOTE_KIND (parm_birth_insn) == NOTE_INSN_FUNCTION_BEG) + emit_insn_before_noloc (insns, parm_birth_insn, e->dest); + else + emit_insn_after_noloc (insns, parm_birth_insn, e->dest); } else commit_one_edge_insertion (e); diff --git a/gcc/cfgrtl.c b/gcc/cfgrtl.c index ec1ba9ad71c86..1d1c6e7d811e3 100644 --- a/gcc/cfgrtl.c +++ b/gcc/cfgrtl.c @@ -1784,10 +1784,18 @@ commit_one_edge_insertion (edge e) } /* If the source has one successor and the edge is not abnormal, - insert there. Except for the entry block. */ + insert there. Except for the entry block. + Don't do this if the predecessor ends in a jump other than + unconditional simple jump. E.g. for asm goto that points all + its labels at the fallthru basic block, we can't insert instructions + before the asm goto, as the asm goto can have various of side effects, + and can't emit instructions after the asm goto, as it must end + the basic block. */ else if ((e->flags & EDGE_ABNORMAL) == 0 && single_succ_p (e->src) - && e->src != ENTRY_BLOCK_PTR) + && e->src != ENTRY_BLOCK_PTR + && (!JUMP_P (BB_END (e->src)) + || simplejump_p (BB_END (e->src)))) { bb = e->src; diff --git a/gcc/cgraph.c b/gcc/cgraph.c index 79d686b6186f3..fd3aadee45d71 100644 --- a/gcc/cgraph.c +++ b/gcc/cgraph.c @@ -1068,6 +1068,7 @@ cgraph_redirect_edge_call_stmt_to_callee (struct cgraph_edge *e) = gimple_call_copy_skip_args (e->call_stmt, e->callee->clone.combined_args_to_skip); gimple_call_set_fndecl (new_stmt, e->callee->symbol.decl); + gimple_call_set_fntype (new_stmt, gimple_call_fntype (e->call_stmt)); if (gimple_vdef (new_stmt) && TREE_CODE (gimple_vdef (new_stmt)) == SSA_NAME) @@ -2595,4 +2596,47 @@ verify_cgraph (void) FOR_EACH_FUNCTION (node) verify_cgraph_node (node); } + +/* Create external decl node for DECL. + The difference i nbetween cgraph_get_create_node and + cgraph_get_create_real_symbol_node is that cgraph_get_create_node + may return inline clone, while cgraph_get_create_real_symbol_node + will create a new node in this case. + FIXME: This function should be removed once clones are put out of decl + hash. */ + +struct cgraph_node * +cgraph_get_create_real_symbol_node (tree decl) +{ + struct cgraph_node *first_clone = cgraph_get_node (decl); + struct cgraph_node *node; + /* create symbol table node. even if inline clone exists, we can not take + it as a target of non-inlined call. */ + node = cgraph_get_node (decl); + if (node && !node->global.inlined_to) + return node; + + node = cgraph_create_node (decl); + + /* ok, we previously inlined the function, then removed the offline copy and + now we want it back for external call. this can happen when devirtualizing + while inlining function called once that happens after extern inlined and + virtuals are already removed. in this case introduce the external node + and make it available for call. */ + if (first_clone) + { + first_clone->clone_of = node; + node->clones = first_clone; + symtab_prevail_in_asm_name_hash ((symtab_node) node); + symtab_insert_node_to_hashtable ((symtab_node) node); + if (dump_file) + fprintf (dump_file, "Introduced new external node " + "(%s/%i) and turned into root of the clone tree.\n", + xstrdup (cgraph_node_name (node)), node->uid); + } + else if (dump_file) + fprintf (dump_file, "Introduced new external node " + "(%s/%i).\n", xstrdup (cgraph_node_name (node)), node->uid); + return node; +} #include "gt-cgraph.h" diff --git a/gcc/cgraph.h b/gcc/cgraph.h index 5df7fb478b4a6..8ab7ae1810281 100644 --- a/gcc/cgraph.h +++ b/gcc/cgraph.h @@ -575,6 +575,7 @@ struct cgraph_indirect_call_info *cgraph_allocate_init_indirect_info (void); struct cgraph_node * cgraph_create_node (tree); struct cgraph_node * cgraph_create_empty_node (void); struct cgraph_node * cgraph_get_create_node (tree); +struct cgraph_node * cgraph_get_create_real_symbol_node (tree); struct cgraph_node * cgraph_same_body_alias (struct cgraph_node *, tree, tree); struct cgraph_node * cgraph_add_thunk (struct cgraph_node *, tree, tree, bool, HOST_WIDE_INT, HOST_WIDE_INT, tree, tree); diff --git a/gcc/cgraphbuild.c b/gcc/cgraphbuild.c index fb01f24ec076d..8869f524db526 100644 --- a/gcc/cgraphbuild.c +++ b/gcc/cgraphbuild.c @@ -73,7 +73,7 @@ record_reference (tree *tp, int *walk_subtrees, void *data) decl = get_base_var (*tp); if (TREE_CODE (decl) == FUNCTION_DECL) { - struct cgraph_node *node = cgraph_get_create_node (decl); + struct cgraph_node *node = cgraph_get_create_real_symbol_node (decl); if (!ctx->only_vars) cgraph_mark_address_taken_node (node); ipa_record_reference ((symtab_node)ctx->varpool_node, @@ -143,7 +143,7 @@ record_eh_tables (struct cgraph_node *node, struct function *fun) { struct cgraph_node *per_node; - per_node = cgraph_get_create_node (DECL_FUNCTION_PERSONALITY (node->symbol.decl)); + per_node = cgraph_get_create_real_symbol_node (DECL_FUNCTION_PERSONALITY (node->symbol.decl)); ipa_record_reference ((symtab_node)node, (symtab_node)per_node, IPA_REF_ADDR, NULL); cgraph_mark_address_taken_node (per_node); } @@ -218,12 +218,12 @@ compute_call_stmt_bb_frequency (tree decl, basic_block bb) /* Mark address taken in STMT. */ static bool -mark_address (gimple stmt, tree addr, void *data) +mark_address (gimple stmt, tree addr, tree, void *data) { addr = get_base_address (addr); if (TREE_CODE (addr) == FUNCTION_DECL) { - struct cgraph_node *node = cgraph_get_create_node (addr); + struct cgraph_node *node = cgraph_get_create_real_symbol_node (addr); cgraph_mark_address_taken_node (node); ipa_record_reference ((symtab_node)data, (symtab_node)node, @@ -245,14 +245,14 @@ mark_address (gimple stmt, tree addr, void *data) /* Mark load of T. */ static bool -mark_load (gimple stmt, tree t, void *data) +mark_load (gimple stmt, tree t, tree, void *data) { t = get_base_address (t); if (t && TREE_CODE (t) == FUNCTION_DECL) { /* ??? This can happen on platforms with descriptors when these are directly manipulated in the code. Pretend that it's an address. */ - struct cgraph_node *node = cgraph_get_create_node (t); + struct cgraph_node *node = cgraph_get_create_real_symbol_node (t); cgraph_mark_address_taken_node (node); ipa_record_reference ((symtab_node)data, (symtab_node)node, @@ -273,7 +273,7 @@ mark_load (gimple stmt, tree t, void *data) /* Mark store of T. */ static bool -mark_store (gimple stmt, tree t, void *data) +mark_store (gimple stmt, tree t, tree, void *data) { t = get_base_address (t); if (t && TREE_CODE (t) == VAR_DECL @@ -330,7 +330,7 @@ build_cgraph_edges (void) { tree fn = gimple_omp_parallel_child_fn (stmt); ipa_record_reference ((symtab_node)node, - (symtab_node)cgraph_get_create_node (fn), + (symtab_node)cgraph_get_create_real_symbol_node (fn), IPA_REF_ADDR, stmt); } if (gimple_code (stmt) == GIMPLE_OMP_TASK) @@ -338,12 +338,12 @@ build_cgraph_edges (void) tree fn = gimple_omp_task_child_fn (stmt); if (fn) ipa_record_reference ((symtab_node)node, - (symtab_node) cgraph_get_create_node (fn), + (symtab_node) cgraph_get_create_real_symbol_node (fn), IPA_REF_ADDR, stmt); fn = gimple_omp_task_copy_fn (stmt); if (fn) ipa_record_reference ((symtab_node)node, - (symtab_node)cgraph_get_create_node (fn), + (symtab_node)cgraph_get_create_real_symbol_node (fn), IPA_REF_ADDR, stmt); } } diff --git a/gcc/cgraphunit.c b/gcc/cgraphunit.c index 7fa8055878c85..7dd2c1d559506 100644 --- a/gcc/cgraphunit.c +++ b/gcc/cgraphunit.c @@ -1097,7 +1097,7 @@ handle_alias_pairs (void) /* We use local aliases for C++ thunks to force the tailcall to bind locally. This is a hack - to keep it working do the following (which is not strictly correct). */ - && (! TREE_CODE (target_node->symbol.decl) == FUNCTION_DECL + && (TREE_CODE (target_node->symbol.decl) != FUNCTION_DECL || ! DECL_VIRTUAL_P (target_node->symbol.decl)) && ! lookup_attribute ("weakref", DECL_ATTRIBUTES (p->decl))) { diff --git a/gcc/collect2.c b/gcc/collect2.c index 99dd41dc1c542..8284a2e1f7b42 100644 --- a/gcc/collect2.c +++ b/gcc/collect2.c @@ -366,8 +366,8 @@ static void scan_prog_file (const char *, scanpass, scanfilter); /* Delete tempfiles and exit function. */ -void -collect_exit (int status) +static void +collect_atexit (void) { if (c_file != 0 && c_file[0]) maybe_unlink (c_file); @@ -395,13 +395,8 @@ collect_exit (int status) maybe_unlink (lderrout); } - if (status != 0 && output_file != 0 && output_file[0]) - maybe_unlink (output_file); - if (response_file) maybe_unlink (response_file); - - exit (status); } @@ -970,6 +965,9 @@ main (int argc, char **argv) signal (SIGCHLD, SIG_DFL); #endif + if (atexit (collect_atexit) != 0) + fatal_error ("atexit failed"); + /* Unlock the stdio streams. */ unlock_std_streams (); @@ -1110,55 +1108,55 @@ main (int argc, char **argv) if (ld_file_name == 0) #endif #ifdef REAL_LD_FILE_NAME - ld_file_name = find_a_file (&path, REAL_LD_FILE_NAME); + ld_file_name = find_a_file (&path, REAL_LD_FILE_NAME, X_OK); if (ld_file_name == 0) #endif /* Search the (target-specific) compiler dirs for ld'. */ - ld_file_name = find_a_file (&cpath, real_ld_suffix); + ld_file_name = find_a_file (&cpath, real_ld_suffix, X_OK); /* Likewise for `collect-ld'. */ if (ld_file_name == 0) { - ld_file_name = find_a_file (&cpath, collect_ld_suffix); + ld_file_name = find_a_file (&cpath, collect_ld_suffix, X_OK); use_collect_ld = ld_file_name != 0; } /* Search the compiler directories for `ld'. We have protection against recursive calls in find_a_file. */ if (ld_file_name == 0) - ld_file_name = find_a_file (&cpath, ld_suffixes[selected_linker]); + ld_file_name = find_a_file (&cpath, ld_suffixes[selected_linker], X_OK); /* Search the ordinary system bin directories for `ld' (if native linking) or `TARGET-ld' (if cross). */ if (ld_file_name == 0) - ld_file_name = find_a_file (&path, full_ld_suffixes[selected_linker]); + ld_file_name = find_a_file (&path, full_ld_suffixes[selected_linker], X_OK); #ifdef REAL_NM_FILE_NAME - nm_file_name = find_a_file (&path, REAL_NM_FILE_NAME); + nm_file_name = find_a_file (&path, REAL_NM_FILE_NAME, X_OK); if (nm_file_name == 0) #endif - nm_file_name = find_a_file (&cpath, gnm_suffix); + nm_file_name = find_a_file (&cpath, gnm_suffix, X_OK); if (nm_file_name == 0) - nm_file_name = find_a_file (&path, full_gnm_suffix); + nm_file_name = find_a_file (&path, full_gnm_suffix, X_OK); if (nm_file_name == 0) - nm_file_name = find_a_file (&cpath, nm_suffix); + nm_file_name = find_a_file (&cpath, nm_suffix, X_OK); if (nm_file_name == 0) - nm_file_name = find_a_file (&path, full_nm_suffix); + nm_file_name = find_a_file (&path, full_nm_suffix, X_OK); #ifdef LDD_SUFFIX - ldd_file_name = find_a_file (&cpath, ldd_suffix); + ldd_file_name = find_a_file (&cpath, ldd_suffix, X_OK); if (ldd_file_name == 0) - ldd_file_name = find_a_file (&path, full_ldd_suffix); + ldd_file_name = find_a_file (&path, full_ldd_suffix, X_OK); #endif #ifdef REAL_STRIP_FILE_NAME - strip_file_name = find_a_file (&path, REAL_STRIP_FILE_NAME); + strip_file_name = find_a_file (&path, REAL_STRIP_FILE_NAME, X_OK); if (strip_file_name == 0) #endif - strip_file_name = find_a_file (&cpath, gstrip_suffix); + strip_file_name = find_a_file (&cpath, gstrip_suffix, X_OK); if (strip_file_name == 0) - strip_file_name = find_a_file (&path, full_gstrip_suffix); + strip_file_name = find_a_file (&path, full_gstrip_suffix, X_OK); if (strip_file_name == 0) - strip_file_name = find_a_file (&cpath, strip_suffix); + strip_file_name = find_a_file (&cpath, strip_suffix, X_OK); if (strip_file_name == 0) - strip_file_name = find_a_file (&path, full_strip_suffix); + strip_file_name = find_a_file (&path, full_strip_suffix, X_OK); /* Determine the full path name of the C compiler to use. */ c_file_name = getenv ("COLLECT_GCC"); @@ -1171,12 +1169,12 @@ main (int argc, char **argv) #endif } - p = find_a_file (&cpath, c_file_name); + p = find_a_file (&cpath, c_file_name, X_OK); /* Here it should be safe to use the system search path since we should have already qualified the name of the compiler when it is needed. */ if (p == 0) - p = find_a_file (&path, c_file_name); + p = find_a_file (&path, c_file_name, X_OK); if (p) c_file_name = p; @@ -1813,7 +1811,7 @@ collect_wait (const char *prog, struct pex_obj *pex) error ("%s terminated with signal %d [%s]%s", prog, sig, strsignal(sig), WCOREDUMP(status) ? ", core dumped" : ""); - collect_exit (FATAL_EXIT_CODE); + exit (FATAL_EXIT_CODE); } if (WIFEXITED (status)) @@ -1829,7 +1827,7 @@ do_wait (const char *prog, struct pex_obj *pex) if (ret != 0) { error ("%s returned %d exit status", prog, ret); - collect_exit (ret); + exit (ret); } if (response_file) diff --git a/gcc/collect2.h b/gcc/collect2.h index 1765bc438efb8..2385e4a981325 100644 --- a/gcc/collect2.h +++ b/gcc/collect2.h @@ -25,8 +25,6 @@ extern void do_tlink (char **, char **); extern struct pex_obj *collect_execute (const char *, char **, const char *, const char *, int flags); -extern void collect_exit (int) ATTRIBUTE_NORETURN; - extern int collect_wait (const char *, struct pex_obj *); extern void dump_ld_file (const char *, FILE *); diff --git a/gcc/combine.c b/gcc/combine.c index acb742165893f..7c84a3d65592b 100644 --- a/gcc/combine.c +++ b/gcc/combine.c @@ -1527,8 +1527,8 @@ setup_incoming_promotions (rtx first) uns3 = TYPE_UNSIGNED (DECL_ARG_TYPE (arg)); /* The mode and signedness of the argument as it is actually passed, - after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions. */ - mode3 = promote_function_mode (DECL_ARG_TYPE (arg), mode2, &uns3, + see assign_parm_setup_reg in function.c. */ + mode3 = promote_function_mode (TREE_TYPE (arg), mode1, &uns3, TREE_TYPE (cfun->decl), 0); /* The mode of the register in which the argument is being passed. */ @@ -3884,15 +3884,19 @@ try_combine (rtx i3, rtx i2, rtx i1, rtx i0, int *new_direct_jump_p, PATTERN (undobuf.other_insn) = other_pat; - /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they - are still valid. Then add any non-duplicate notes added by - recog_for_combine. */ + /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED, + ensure that they are still valid. Then add any non-duplicate + notes added by recog_for_combine. */ for (note = REG_NOTES (undobuf.other_insn); note; note = next) { next = XEXP (note, 1); - if (REG_NOTE_KIND (note) == REG_UNUSED - && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn))) + if ((REG_NOTE_KIND (note) == REG_DEAD + && !reg_referenced_p (XEXP (note, 0), + PATTERN (undobuf.other_insn))) + ||(REG_NOTE_KIND (note) == REG_UNUSED + && !reg_set_p (XEXP (note, 0), + PATTERN (undobuf.other_insn)))) remove_note (undobuf.other_insn, note); } @@ -5798,8 +5802,15 @@ combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest, return x; } - /* If the code changed, return a whole new comparison. */ - if (new_code != code) + /* If the code changed, return a whole new comparison. + We also need to avoid using SUBST in cases where + simplify_comparison has widened a comparison with a CONST_INT, + since in that case the wider CONST_INT may fail the sanity + checks in do_SUBST. */ + if (new_code != code + || (CONST_INT_P (op1) + && GET_MODE (op0) != GET_MODE (XEXP (x, 0)) + && GET_MODE (op0) != GET_MODE (XEXP (x, 1)))) return gen_rtx_fmt_ee (new_code, mode, op0, op1); /* Otherwise, keep this operation, but maybe change its operands. @@ -7703,8 +7714,24 @@ make_compound_operation (rtx x, enum rtx_code in_code) what it originally did, do this SUBREG as a force_to_mode. */ { rtx inner = SUBREG_REG (x), simplified; - - tem = make_compound_operation (inner, in_code); + enum rtx_code subreg_code = in_code; + + /* If in_code is COMPARE, it isn't always safe to pass it through + to the recursive make_compound_operation call. */ + if (subreg_code == COMPARE + && (!subreg_lowpart_p (x) + || GET_CODE (inner) == SUBREG + /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0) + is (const_int 0), rather than + (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0). */ + || (GET_CODE (inner) == AND + && CONST_INT_P (XEXP (inner, 1)) + && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (inner)) + && exact_log2 (UINTVAL (XEXP (inner, 1))) + >= GET_MODE_BITSIZE (mode)))) + subreg_code = SET; + + tem = make_compound_operation (inner, subreg_code); simplified = simplify_subreg (mode, tem, GET_MODE (inner), SUBREG_BYTE (x)); @@ -7975,7 +8002,7 @@ force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask, if (code == CALL || code == ASM_OPERANDS || code == CLOBBER) return x; - /* We want to perform the operation is its present mode unless we know + /* We want to perform the operation in its present mode unless we know that the operation is valid in MODE, in which case we do the operation in MODE. */ op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x)) @@ -8411,9 +8438,10 @@ force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask, GET_MODE (x), GEN_INT (mask), XEXP (x, 1)); if (temp && CONST_INT_P (temp)) - SUBST (XEXP (x, 0), - force_to_mode (XEXP (x, 0), GET_MODE (x), - INTVAL (temp), next_select)); + x = simplify_gen_binary (code, GET_MODE (x), + force_to_mode (XEXP (x, 0), GET_MODE (x), + INTVAL (temp), next_select), + XEXP (x, 1)); } break; @@ -8481,14 +8509,16 @@ force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask, /* We have no way of knowing if the IF_THEN_ELSE can itself be written in a narrower mode. We play it safe and do not do so. */ - SUBST (XEXP (x, 1), - gen_lowpart_or_truncate (GET_MODE (x), - force_to_mode (XEXP (x, 1), mode, - mask, next_select))); - SUBST (XEXP (x, 2), - gen_lowpart_or_truncate (GET_MODE (x), - force_to_mode (XEXP (x, 2), mode, - mask, next_select))); + op0 = gen_lowpart_or_truncate (GET_MODE (x), + force_to_mode (XEXP (x, 1), mode, + mask, next_select)); + op1 = gen_lowpart_or_truncate (GET_MODE (x), + force_to_mode (XEXP (x, 2), mode, + mask, next_select)); + if (op0 != XEXP (x, 1) || op1 != XEXP (x, 2)) + x = simplify_gen_ternary (IF_THEN_ELSE, GET_MODE (x), + GET_MODE (XEXP (x, 0)), XEXP (x, 0), + op0, op1); break; default: diff --git a/gcc/common.opt b/gcc/common.opt index bdbd3b6cd9ea5..ec4cafc448bfb 100644 --- a/gcc/common.opt +++ b/gcc/common.opt @@ -1226,6 +1226,10 @@ fgnu-tm Common Report Var(flag_tm) Enable support for GNU transactional memory +fgnu-unique +Common Report Var(flag_gnu_unique) Init(1) +Use STB_GNU_UNIQUE if supported by the assembler + floop-flatten Common Ignore Does nothing. Preserved for backward compatibility. diff --git a/gcc/common/config/s390/s390-common.c b/gcc/common/config/s390/s390-common.c index 1ffe93e8a18d7..c2031b74b1f6f 100644 --- a/gcc/common/config/s390/s390-common.c +++ b/gcc/common/config/s390/s390-common.c @@ -42,7 +42,7 @@ EXPORTED_CONST int processor_flags_table[] = /* z196 */ PF_IEEE_FLOAT | PF_ZARCH | PF_LONG_DISPLACEMENT | PF_EXTIMM | PF_DFP | PF_Z10 | PF_Z196, /* zEC12 */ PF_IEEE_FLOAT | PF_ZARCH | PF_LONG_DISPLACEMENT - | PF_EXTIMM | PF_DFP | PF_Z10 | PF_Z196 | PF_ZEC12 + | PF_EXTIMM | PF_DFP | PF_Z10 | PF_Z196 | PF_ZEC12 | PF_TX }; /* Change optimizations to be performed, depending on the diff --git a/gcc/config.gcc b/gcc/config.gcc index 1a0be50f03304..b09a763d525ac 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -420,7 +420,7 @@ picochip-*-*) ;; powerpc*-*-*) cpu_type=rs6000 - extra_headers="ppc-asm.h altivec.h spe.h ppu_intrinsics.h paired.h spu2vmx.h vec_types.h si2vmx.h" + extra_headers="ppc-asm.h altivec.h spe.h ppu_intrinsics.h paired.h spu2vmx.h vec_types.h si2vmx.h htmintrin.h htmxlintrin.h" need_64bit_hwint=yes case x$with_cpu in xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[345678]|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|Xe6500) @@ -452,6 +452,7 @@ s390*-*-*) cpu_type=s390 need_64bit_hwint=yes extra_options="${extra_options} fused-madd.opt" + extra_headers="s390intrin.h htmintrin.h htmxlintrin.h" ;; # Note the 'l'; we need to be able to match e.g. "shle" or "shl". sh[123456789lbe]*-*-* | sh-*-*) @@ -734,6 +735,7 @@ case ${target} in yes) thread_file='rtems' ;; esac extra_options="${extra_options} rtems.opt" + default_use_cxa_atexit=yes use_gcc_stdint=wrap ;; *-*-uclinux*) @@ -1057,7 +1059,6 @@ hppa*64*-*-linux*) tm_file="pa/pa64-start.h ${tm_file} dbxelf.h elfos.h gnu-user.h linux.h \ glibc-stdint.h pa/pa-linux.h pa/pa64-regs.h pa/pa-64.h \ pa/pa64-linux.h" - tmake_file="${tmake_file} pa/t-linux" gas=yes gnu_ld=yes need_64bit_hwint=yes ;; @@ -1760,6 +1761,14 @@ microblaze*-linux*) tmake_file="${tmake_file} microblaze/t-microblaze-linux" ;; microblaze*-*-rtems*) + case $target in + microblazeel-*) + tm_defines="${tm_defines} TARGET_BIG_ENDIAN_DEFAULT=0" + ;; + microblaze-*) + tm_defines="${tm_defines} TARGET_BIG_ENDIAN_DEFAULT=4321" + ;; + esac tm_file="${tm_file} dbxelf.h" tm_file="${tm_file} microblaze/rtems.h rtems.h newlib-stdint.h" c_target_objs="${c_target_objs} microblaze-c.o" @@ -2066,36 +2075,63 @@ powerpc-*-rtems*) extra_options="${extra_options} rs6000/sysv4.opt" tmake_file="rs6000/t-fprules rs6000/t-rtems t-rtems rs6000/t-ppccomm" ;; -powerpc-*-linux* | powerpc64-*-linux*) +powerpc*-*-linux*) tm_file="${tm_file} dbxelf.h elfos.h freebsd-spec.h rs6000/sysv4.h" extra_options="${extra_options} rs6000/sysv4.opt" - tmake_file="rs6000/t-fprules rs6000/t-ppcos ${tmake_file} rs6000/t-ppccomm" - maybe_biarch=yes + tmake_file="${tmake_file} rs6000/t-fprules rs6000/t-ppccomm" case ${target} in - powerpc64-*-linux*spe* | powerpc64-*-linux*paired*) - echo "*** Configuration ${target} not supported" 1>&2 + powerpc*le-*-*) + tm_file="${tm_file} rs6000/sysv4le.h" ;; + esac + case ${target}:${with_cpu} in + powerpc64*: | powerpc64*:native) cpu_is_64bit=yes ;; + esac + maybe_biarch=${cpu_is_64bit} + case ${enable_targets} in + *powerpc64*) maybe_biarch=yes ;; + all) maybe_biarch=yes ;; + esac + case ${target} in + powerpc64*-*-linux*spe* | powerpc64*-*-linux*paired*) + echo "*** Configuration ${target} not supported" 1>&2 exit 1 ;; - powerpc-*-linux*spe* | powerpc-*-linux*paired*) + powerpc*-*-linux*spe* | powerpc*-*-linux*paired*) maybe_biarch= ;; - powerpc64-*-linux*) - test x$with_cpu != x || cpu_is_64bit=yes - maybe_biarch=always - ;; esac - case ${maybe_biarch}:${enable_targets}:${cpu_is_64bit} in - always:* | yes:*powerpc64* | yes:all:* | yes:*:yes) + case ${target}:${enable_targets}:${maybe_biarch} in + powerpc64-* | powerpc-*:*:yes | *:*powerpc64-*:yes | *:all:yes \ + | powerpc64le*:*powerpcle* | powerpc64le*:*powerpc-* \ + | powerpcle-*:*powerpc64le*:yes) if test x$cpu_is_64bit = xyes; then tm_file="${tm_file} rs6000/default64.h" fi tm_file="rs6000/biarch64.h ${tm_file} rs6000/linux64.h glibc-stdint.h" tmake_file="$tmake_file rs6000/t-linux64" + case ${target} in + powerpc*le-*-*) + tmake_file="$tmake_file rs6000/t-linux64le" + case ${enable_targets} in + all | *powerpc64-* | *powerpc-*) + tmake_file="$tmake_file rs6000/t-linux64lebe" ;; + esac ;; + *) + case ${enable_targets} in + all | *powerpc64le-* | *powerpcle-*) + tmake_file="$tmake_file rs6000/t-linux64bele" ;; + esac ;; + esac + extra_options="${extra_options} rs6000/linux64.opt" + ;; + powerpc64*) + tm_file="${tm_file} rs6000/default64.h rs6000/linux64.h glibc-stdint.h" extra_options="${extra_options} rs6000/linux64.opt" + tmake_file="${tmake_file} rs6000/t-linux" ;; *) tm_file="${tm_file} rs6000/linux.h glibc-stdint.h" - tmake_file="$tmake_file rs6000/t-linux" + tmake_file="${tmake_file} rs6000/t-ppcos rs6000/t-linux" ;; esac case ${target} in @@ -2440,7 +2476,7 @@ sparc-*-elf*) ;; sparc-*-rtems*) tm_file="${tm_file} dbxelf.h elfos.h sparc/sysv4.h sparc/sp-elf.h sparc/rtemself.h rtems.h newlib-stdint.h" - tmake_file="sparc/t-sparc sparc/t-elf sparc/t-rtems t-rtems" + tmake_file="sparc/t-sparc sparc/t-rtems t-rtems" ;; sparc-*-linux*) tm_file="${tm_file} dbxelf.h elfos.h sparc/sysv4.h gnu-user.h linux.h glibc-stdint.h sparc/tso.h" @@ -2958,11 +2994,21 @@ if test x$with_cpu = x ; then with_cpu=8540 fi ;; - sparc-leon*-*) - with_cpu=v8; - ;; sparc*-*-*) - with_cpu="`echo ${target} | sed 's/-.*$//'`" + case ${target} in + *-leon-*) + with_cpu=leon + ;; + *-leon[3-9]*) + with_cpu=leon3 + ;; + *-leon[3-9]v7*) + with_cpu=leon3v7 + ;; + *) + with_cpu="`echo ${target} | sed 's/-.*$//'`" + ;; + esac ;; esac @@ -3117,6 +3163,11 @@ case "${target}" in ${srcdir}/config/aarch64/$def | \ sed -e 's/^[^,]*,[ ]*//' | \ sed -e 's/,.*$//'` + # Extract the architecture flags from aarch64-arches.def + ext_mask=`grep "^$pattern(\"$base_val\"," \ + ${srcdir}/config/aarch64/$def | \ + sed -e 's/)$//' | \ + sed -e 's/^.*,//'` else base_id=`grep "^$pattern(\"$base_val\"," \ ${srcdir}/config/aarch64/$def | \ @@ -3489,7 +3540,7 @@ case "${target}" in ;; powerpc*-*-* | rs6000-*-*) - supported_defaults="cpu cpu_32 cpu_64 float tune tune_32 tune_64" + supported_defaults="abi cpu cpu_32 cpu_64 float tune tune_32 tune_64" for which in cpu cpu_32 cpu_64 tune tune_32 tune_64; do eval "val=\$with_$which" @@ -3526,6 +3577,16 @@ case "${target}" in ;; esac done + + case "$with_abi" in + "" | elfv1 | elfv2 ) + #OK + ;; + *) + echo "Unknown ABI used in --with-abi=$with_abi" + exit 1 + ;; + esac ;; s390*-*-*) @@ -3582,7 +3643,7 @@ case "${target}" in case ${val} in "" | sparc | sparcv9 | sparc64 \ | v7 | cypress \ - | v8 | supersparc | hypersparc | leon \ + | v8 | supersparc | hypersparc | leon | leon3 | leon3v7 \ | sparclite | f930 | f934 | sparclite86x \ | sparclet | tsc701 \ | v9 | ultrasparc | ultrasparc3 | niagara | niagara2 \ @@ -3656,10 +3717,8 @@ esac target_cpu_default2= case ${target} in aarch64*-*-*) - if test x$target_cpu_cname = x + if test x"$target_cpu_cname" != x then - target_cpu_default2=TARGET_CPU_generic - else target_cpu_default2=$target_cpu_cname fi ;; @@ -3740,15 +3799,6 @@ case ${target} in cxx_target_objs="${cxx_target_objs} sh-c.o" ;; - sparc-leon*-*) - if test x$with_tune = x ; then - with_tune=leon; - fi - - # The SPARC port checks this value at compile-time. - target_cpu_default2="TARGET_CPU_$with_cpu" - ;; - sparc*-*-*) # Some standard aliases. case x$with_cpu in @@ -3760,6 +3810,17 @@ case ${target} in ;; esac + if test x$with_tune = x ; then + case ${target} in + *-leon-*) + with_tune=leon + ;; + *-leon[3-9]*) + with_tune=leon3 + ;; + esac + fi + # The SPARC port checks this value at compile-time. target_cpu_default2="TARGET_CPU_$with_cpu" ;; diff --git a/gcc/config.in b/gcc/config.in index d80fb9f6e1137..8e8976265c4a1 100644 --- a/gcc/config.in +++ b/gcc/config.in @@ -363,6 +363,12 @@ #endif +/* Define if your assembler supports the 'ud2' mnemonic. */ +#ifndef USED_FOR_TARGET +#undef HAVE_AS_IX86_UD2 +#endif + + /* Define if your assembler supports the lituse_jsrdirect relocation. */ #ifndef USED_FOR_TARGET #undef HAVE_AS_JSRDIRECT_RELOCS @@ -375,6 +381,12 @@ #endif +/* Define if your assembler supports LEON instructions. */ +#ifndef USED_FOR_TARGET +#undef HAVE_AS_LEON +#endif + + /* Define if the assembler won't complain about a line such as # 0 "" 2. */ #ifndef USED_FOR_TARGET #undef HAVE_AS_LINE_ZERO @@ -1163,6 +1175,12 @@ #endif +/* Define if isl_schedule_constraints_compute_schedule exists. */ +#ifndef USED_FOR_TARGET +#undef HAVE_ISL_SCHED_CONSTRAINTS_COMPUTE_SCHEDULE +#endif + + /* Define to 1 if you have the `kill' function. */ #ifndef USED_FOR_TARGET #undef HAVE_KILL @@ -1228,7 +1246,7 @@ #endif -/* Define if your AIX linker supports a large TOC. */ +/* Define if your PowerPC64 linker supports a large TOC. */ #ifndef USED_FOR_TARGET #undef HAVE_LD_LARGE_TOC #endif @@ -1278,12 +1296,6 @@ #endif -/* Define to 1 if you have the header file. */ -#ifndef USED_FOR_TARGET -#undef HAVE_LIBINTL_H -#endif - - /* Define to 1 if you have the header file. */ #ifndef USED_FOR_TARGET #undef HAVE_LIMITS_H diff --git a/gcc/config/aarch64/aarch64-builtins.c b/gcc/config/aarch64/aarch64-builtins.c index 1ea55a83eb86f..b2901dbcab2d3 100644 --- a/gcc/config/aarch64/aarch64-builtins.c +++ b/gcc/config/aarch64/aarch64-builtins.c @@ -1154,6 +1154,7 @@ aarch64_simd_expand_builtin (int fcode, tree exp, rtx target) return aarch64_simd_expand_args (target, icode, 1, exp, SIMD_ARG_COPY_TO_REG, SIMD_ARG_STOP); + case AARCH64_SIMD_STORE1: case AARCH64_SIMD_STORESTRUCT: return aarch64_simd_expand_args (target, icode, 0, exp, SIMD_ARG_COPY_TO_REG, diff --git a/gcc/config/aarch64/aarch64-elf-raw.h b/gcc/config/aarch64/aarch64-elf-raw.h index 1cd0155fc6333..9515d112d2eff 100644 --- a/gcc/config/aarch64/aarch64-elf-raw.h +++ b/gcc/config/aarch64/aarch64-elf-raw.h @@ -25,8 +25,17 @@ #define STARTFILE_SPEC " crti%O%s crtbegin%O%s crt0%O%s" #define ENDFILE_SPEC " crtend%O%s crtn%O%s" +#ifdef TARGET_FIX_ERR_A53_835769_DEFAULT +#define CA53_ERR_835769_SPEC \ + " %{!mno-fix-cortex-a53-835769:--fix-cortex-a53-835769}" +#else +#define CA53_ERR_835769_SPEC \ + " %{mfix-cortex-a53-835769:--fix-cortex-a53-835769}" +#endif + #ifndef LINK_SPEC -#define LINK_SPEC "%{mbig-endian:-EB} %{mlittle-endian:-EL} -X" +#define LINK_SPEC "%{mbig-endian:-EB} %{mlittle-endian:-EL} -X" \ + CA53_ERR_835769_SPEC #endif #endif /* GCC_AARCH64_ELF_RAW_H */ diff --git a/gcc/config/aarch64/aarch64-linux.h b/gcc/config/aarch64/aarch64-linux.h index e914ed27f1f63..a012baed28410 100644 --- a/gcc/config/aarch64/aarch64-linux.h +++ b/gcc/config/aarch64/aarch64-linux.h @@ -23,6 +23,8 @@ #define GLIBC_DYNAMIC_LINKER "/lib/ld-linux-aarch64.so.1" +#define CPP_SPEC "%{pthread:-D_REENTRANT}" + #define LINUX_TARGET_LINK_SPEC "%{h*} \ %{static:-Bstatic} \ %{shared:-shared} \ @@ -32,7 +34,16 @@ -X \ %{mbig-endian:-EB} %{mlittle-endian:-EL}" -#define LINK_SPEC LINUX_TARGET_LINK_SPEC +#ifdef TARGET_FIX_ERR_A53_835769_DEFAULT +#define CA53_ERR_835769_SPEC \ + " %{!mno-fix-cortex-a53-835769:--fix-cortex-a53-835769}" +#else +#define CA53_ERR_835769_SPEC \ + " %{mfix-cortex-a53-835769:--fix-cortex-a53-835769}" +#endif + +#define LINK_SPEC LINUX_TARGET_LINK_SPEC \ + CA53_ERR_835769_SPEC #define TARGET_OS_CPP_BUILTINS() \ do \ @@ -41,4 +52,6 @@ } \ while (0) +#define TARGET_ASM_FILE_END file_end_indicate_exec_stack + #endif /* GCC_AARCH64_LINUX_H */ diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h index 5d0072f9da7c3..07ff7031b356f 100644 --- a/gcc/config/aarch64/aarch64-protos.h +++ b/gcc/config/aarch64/aarch64-protos.h @@ -247,6 +247,8 @@ aarch64_builtin_vectorized_function (tree fndecl, extern void aarch64_split_combinev16qi (rtx operands[3]); extern void aarch64_expand_vec_perm (rtx target, rtx op0, rtx op1, rtx sel); +extern bool aarch64_madd_needs_nop (rtx); +extern void aarch64_final_prescan_insn (rtx); extern bool aarch64_expand_vec_perm_const (rtx target, rtx op0, rtx op1, rtx sel); diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def index a6a5e12c7a5b3..ed73c15d7e9a1 100644 --- a/gcc/config/aarch64/aarch64-simd-builtins.def +++ b/gcc/config/aarch64/aarch64-simd-builtins.def @@ -217,8 +217,8 @@ BUILTIN_VSDQ_I_DI (BINOP, cmle) BUILTIN_VSDQ_I_DI (BINOP, cmlt) /* Implemented by aarch64_cm. */ - BUILTIN_VSDQ_I_DI (BINOP, cmhs) - BUILTIN_VSDQ_I_DI (BINOP, cmhi) + BUILTIN_VSDQ_I_DI (BINOP, cmgeu) + BUILTIN_VSDQ_I_DI (BINOP, cmgtu) BUILTIN_VSDQ_I_DI (BINOP, cmtst) /* Implemented by aarch64_. */ @@ -256,3 +256,10 @@ BUILTIN_VALL (BINOP, uzp2) BUILTIN_VALL (BINOP, trn1) BUILTIN_VALL (BINOP, trn2) + + /* Implemented by aarch64_ld1. */ + BUILTIN_VALL (LOAD1, ld1) + + /* Implemented by aarch64_st1. */ + BUILTIN_VALL (STORE1, st1) + diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 0f0009505d888..481222cf5287c 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -21,7 +21,7 @@ ; Main data types used by the insntructions -(define_attr "simd_mode" "unknown,none,V8QI,V16QI,V4HI,V8HI,V2SI,V4SI,V2DI,V2SF,V4SF,V2DF,OI,CI,XI,DI,DF,SI,HI,QI" +(define_attr "simd_mode" "unknown,none,V8QI,V16QI,V4HI,V8HI,V2SI,V4SI,V2DI,V2SF,V4SF,V2DF,OI,CI,XI,DI,DF,SI,SF,HI,QI" (const_string "unknown")) @@ -1548,12 +1548,12 @@ case LTU: case GEU: - emit_insn (gen_aarch64_cmhs (mask, operands[4], operands[5])); + emit_insn (gen_aarch64_cmgeu (mask, operands[4], operands[5])); break; case LEU: case GTU: - emit_insn (gen_aarch64_cmhi (mask, operands[4], operands[5])); + emit_insn (gen_aarch64_cmgtu (mask, operands[4], operands[5])); break; case NE: @@ -1586,6 +1586,7 @@ "TARGET_SIMD" { int inverse = 0; + int use_zero_form = 0; int swap_bsl_operands = 0; rtx mask = gen_reg_rtx (mode); rtx tmp = gen_reg_rtx (mode); @@ -1596,12 +1597,16 @@ switch (GET_CODE (operands[3])) { case GE: + case GT: case LE: + case LT: case EQ: - if (!REG_P (operands[5]) - && (operands[5] != CONST0_RTX (mode))) - operands[5] = force_reg (mode, operands[5]); - break; + if (operands[5] == CONST0_RTX (mode)) + { + use_zero_form = 1; + break; + } + /* Fall through. */ default: if (!REG_P (operands[5])) operands[5] = force_reg (mode, operands[5]); @@ -1652,7 +1657,26 @@ a GT b -> a GT b a LE b -> b GE a a LT b -> b GT a - a EQ b -> a EQ b */ + a EQ b -> a EQ b + Note that there also exist direct comparison against 0 forms, + so catch those as a special case. */ + if (use_zero_form) + { + inverse = 0; + switch (GET_CODE (operands[3])) + { + case LT: + base_comparison = gen_aarch64_cmlt; + break; + case LE: + base_comparison = gen_aarch64_cmle; + break; + default: + /* Do nothing, other zero form cases already have the correct + base_comparison. */ + break; + } + } if (!inverse) emit_insn (base_comparison (mask, operands[4], operands[5])); @@ -3010,48 +3034,181 @@ ) -;; cm(eq|ge|le|lt|gt) +;; cm(eq|ge|gt|lt|le) +;; Note, we have constraints for Dz and Z as different expanders +;; have different ideas of what should be passed to this pattern. -(define_insn "aarch64_cm" +(define_insn "aarch64_cm" [(set (match_operand: 0 "register_operand" "=w,w") - (unspec: - [(match_operand:VSDQ_I_DI 1 "register_operand" "w,w") - (match_operand:VSDQ_I_DI 2 "aarch64_simd_reg_or_zero" "w,Z")] - VCMP_S))] + (neg: + (COMPARISONS: + (match_operand:VDQ 1 "register_operand" "w,w") + (match_operand:VDQ 2 "aarch64_simd_reg_or_zero" "w,ZDz") + )))] "TARGET_SIMD" "@ - cm\t%0, %1, %2 - cm\t%0, %1, #0" + cm\t%0, %, % + cm\t%0, %1, #0" [(set_attr "simd_type" "simd_cmp") (set_attr "simd_mode" "")] ) -;; cm(hs|hi|tst) +(define_insn_and_split "aarch64_cmdi" + [(set (match_operand:DI 0 "register_operand" "=w,w,r") + (neg:DI + (COMPARISONS:DI + (match_operand:DI 1 "register_operand" "w,w,r") + (match_operand:DI 2 "aarch64_simd_reg_or_zero" "w,ZDz,r") + )))] + "TARGET_SIMD" + "@ + cm\t%d0, %d, %d + cm\t%d0, %d1, #0 + #" + "reload_completed + /* We need to prevent the split from + happening in the 'w' constraint cases. */ + && GP_REGNUM_P (REGNO (operands[0])) + && GP_REGNUM_P (REGNO (operands[1]))" + [(set (reg:CC CC_REGNUM) + (compare:CC + (match_dup 1) + (match_dup 2))) + (set (match_dup 0) + (neg:DI + (COMPARISONS:DI + (match_operand 3 "cc_register" "") + (const_int 0))))] + { + enum machine_mode mode = SELECT_CC_MODE (, operands[1], operands[2]); + rtx cc_reg = aarch64_gen_compare_reg (, operands[1], operands[2]); + rtx comparison = gen_rtx_ (mode, operands[1], operands[2]); + emit_insn (gen_cstoredi_neg (operands[0], comparison, cc_reg)); + DONE; + } + [(set_attr "simd_type" "simd_cmp") + (set_attr "simd_mode" "DI")] +) + +;; cm(hs|hi) -(define_insn "aarch64_cm" +(define_insn "aarch64_cm" [(set (match_operand: 0 "register_operand" "=w") - (unspec: - [(match_operand:VSDQ_I_DI 1 "register_operand" "w") - (match_operand:VSDQ_I_DI 2 "register_operand" "w")] - VCMP_U))] + (neg: + (UCOMPARISONS: + (match_operand:VDQ 1 "register_operand" "w") + (match_operand:VDQ 2 "register_operand" "w") + )))] "TARGET_SIMD" - "cm\t%0, %1, %2" + "cm\t%0, %, %" + [(set_attr "simd_type" "simd_cmp") + (set_attr "simd_mode" "")] +) + +(define_insn_and_split "aarch64_cmdi" + [(set (match_operand:DI 0 "register_operand" "=w,r") + (neg:DI + (UCOMPARISONS:DI + (match_operand:DI 1 "register_operand" "w,r") + (match_operand:DI 2 "aarch64_simd_reg_or_zero" "w,r") + )))] + "TARGET_SIMD" + "@ + cm\t%d0, %d, %d + #" + "reload_completed + /* We need to prevent the split from + happening in the 'w' constraint cases. */ + && GP_REGNUM_P (REGNO (operands[0])) + && GP_REGNUM_P (REGNO (operands[1]))" + [(set (reg:CC CC_REGNUM) + (compare:CC + (match_dup 1) + (match_dup 2))) + (set (match_dup 0) + (neg:DI + (UCOMPARISONS:DI + (match_operand 3 "cc_register" "") + (const_int 0))))] + { + enum machine_mode mode = SELECT_CC_MODE (, operands[1], operands[2]); + rtx cc_reg = aarch64_gen_compare_reg (, operands[1], operands[2]); + rtx comparison = gen_rtx_ (mode, operands[1], operands[2]); + emit_insn (gen_cstoredi_neg (operands[0], comparison, cc_reg)); + DONE; + } + [(set_attr "simd_type" "simd_cmp") + (set_attr "simd_mode" "DI")] +) + +;; cmtst + +(define_insn "aarch64_cmtst" + [(set (match_operand: 0 "register_operand" "=w") + (neg: + (ne: + (and:VDQ + (match_operand:VDQ 1 "register_operand" "w") + (match_operand:VDQ 2 "register_operand" "w")) + (vec_duplicate: (const_int 0)))))] + "TARGET_SIMD" + "cmtst\t%0, %1, %2" [(set_attr "simd_type" "simd_cmp") (set_attr "simd_mode" "")] ) -;; fcm(eq|ge|le|lt|gt) +(define_insn_and_split "aarch64_cmtstdi" + [(set (match_operand:DI 0 "register_operand" "=w,r") + (neg:DI + (ne:DI + (and:DI + (match_operand:DI 1 "register_operand" "w,r") + (match_operand:DI 2 "register_operand" "w,r")) + (const_int 0))))] + "TARGET_SIMD" + "@ + cmtst\t%d0, %d1, %d2 + #" + "reload_completed + /* We need to prevent the split from + happening in the 'w' constraint cases. */ + && GP_REGNUM_P (REGNO (operands[0])) + && GP_REGNUM_P (REGNO (operands[1]))" + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ + (and:DI (match_dup 1) + (match_dup 2)) + (const_int 0))) + (set (match_dup 0) + (neg:DI + (ne:DI + (match_operand 3 "cc_register" "") + (const_int 0))))] + { + rtx and_tree = gen_rtx_AND (DImode, operands[1], operands[2]); + enum machine_mode mode = SELECT_CC_MODE (NE, and_tree, const0_rtx); + rtx cc_reg = aarch64_gen_compare_reg (NE, and_tree, const0_rtx); + rtx comparison = gen_rtx_NE (mode, and_tree, const0_rtx); + emit_insn (gen_cstoredi_neg (operands[0], comparison, cc_reg)); + DONE; + } + [(set_attr "simd_type" "simd_cmp") + (set_attr "simd_mode" "DI")] +) + +;; fcm(eq|ge|gt|le|lt) -(define_insn "aarch64_cm" +(define_insn "aarch64_cm" [(set (match_operand: 0 "register_operand" "=w,w") - (unspec: - [(match_operand:VDQF 1 "register_operand" "w,w") - (match_operand:VDQF 2 "aarch64_simd_reg_or_zero" "w,Dz")] - VCMP_S))] + (neg: + (COMPARISONS: + (match_operand:VALLF 1 "register_operand" "w,w") + (match_operand:VALLF 2 "aarch64_simd_reg_or_zero" "w,YDz") + )))] "TARGET_SIMD" "@ - fcm\t%0, %1, %2 - fcm\t%0, %1, 0" + fcm\t%0, %, % + fcm\t%0, %1, 0" [(set_attr "simd_type" "simd_fcmp") (set_attr "simd_mode" "")] ) @@ -3433,6 +3590,17 @@ DONE; }) +(define_expand "aarch64_ld1" + [(match_operand:VALL 0 "register_operand") + (match_operand:DI 1 "register_operand")] + "TARGET_SIMD" +{ + enum machine_mode mode = mode; + rtx mem = gen_rtx_MEM (mode, operands[1]); + emit_move_insn (operands[0], mem); + DONE; +}) + (define_expand "aarch64_ld" [(match_operand:VSTRUCT 0 "register_operand" "=w") (match_operand:DI 1 "register_operand" "r") @@ -3649,6 +3817,17 @@ DONE; }) +(define_expand "aarch64_st1" + [(match_operand:DI 0 "register_operand") + (match_operand:VALL 1 "register_operand")] + "TARGET_SIMD" +{ + enum machine_mode mode = mode; + rtx mem = gen_rtx_MEM (mode, operands[0]); + emit_move_insn (mem, operands[1]); + DONE; +}) + ;; Expander for builtins to insert vector registers into large ;; opaque integer modes. diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index ce572f912d2b3..c262792890f6c 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -1201,6 +1201,7 @@ aarch64_layout_arg (cumulative_args_t pcum_v, enum machine_mode mode, CUMULATIVE_ARGS *pcum = get_cumulative_args (pcum_v); int ncrn, nvrn, nregs; bool allocate_ncrn, allocate_nvrn; + HOST_WIDE_INT size; /* We need to do this once per argument. */ if (pcum->aapcs_arg_processed) @@ -1208,6 +1209,11 @@ aarch64_layout_arg (cumulative_args_t pcum_v, enum machine_mode mode, pcum->aapcs_arg_processed = true; + /* Size in bytes, rounded to the nearest multiple of 8 bytes. */ + size + = AARCH64_ROUND_UP (type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode), + UNITS_PER_WORD); + allocate_ncrn = (type) ? !(FLOAT_TYPE_P (type)) : !FLOAT_MODE_P (mode); allocate_nvrn = aarch64_vfp_is_call_candidate (pcum_v, mode, @@ -1258,9 +1264,7 @@ aarch64_layout_arg (cumulative_args_t pcum_v, enum machine_mode mode, } ncrn = pcum->aapcs_ncrn; - nregs = ((type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode)) - + UNITS_PER_WORD - 1) / UNITS_PER_WORD; - + nregs = size / UNITS_PER_WORD; /* C6 - C9. though the sign and zero extension semantics are handled elsewhere. This is the case where the argument fits @@ -1309,13 +1313,12 @@ aarch64_layout_arg (cumulative_args_t pcum_v, enum machine_mode mode, pcum->aapcs_nextncrn = NUM_ARG_REGS; /* The argument is passed on stack; record the needed number of words for - this argument (we can re-use NREGS) and align the total size if - necessary. */ + this argument and align the total size if necessary. */ on_stack: - pcum->aapcs_stack_words = nregs; + pcum->aapcs_stack_words = size / UNITS_PER_WORD; if (aarch64_function_arg_alignment (mode, type) == 16 * BITS_PER_UNIT) pcum->aapcs_stack_size = AARCH64_ROUND_UP (pcum->aapcs_stack_size, - 16 / UNITS_PER_WORD) + 1; + 16 / UNITS_PER_WORD); return; } @@ -2274,7 +2277,7 @@ aarch64_build_constant (int regnum, HOST_WIDE_INT val) if (ncount < zcount) { emit_move_insn (gen_rtx_REG (Pmode, regnum), - GEN_INT ((~val) & 0xffff)); + GEN_INT (val | ~(HOST_WIDE_INT) 0xffff)); tval = 0xffff; } else @@ -2926,9 +2929,10 @@ aarch64_classify_address (struct aarch64_address_info *info, case CONST: case SYMBOL_REF: case LABEL_REF: - /* load literal: pc-relative constant pool entry. */ + /* load literal: pc-relative constant pool entry. Only supported + for SI mode or larger. */ info->type = ADDRESS_SYMBOLIC; - if (outer_code != PARALLEL) + if (outer_code != PARALLEL && GET_MODE_SIZE (mode) >= 4) { rtx sym, addend; @@ -3365,6 +3369,16 @@ aarch64_print_operand (FILE *f, rtx x, char code) REGNO (x) - V0_REGNUM + (code - 'S')); break; + case 'X': + /* Print integer constant in hex. */ + if (GET_CODE (x) != CONST_INT) + { + output_operand_lossage ("invalid operand for '%%%c'", code); + return; + } + asm_fprintf (f, "0x%wx", UINTVAL (x)); + break; + case 'w': case 'x': /* Print a general register name or the zero register (32-bit or @@ -3870,14 +3884,21 @@ aarch64_can_eliminate (const int from, const int to) } else { - /* If we decided that we didn't need a frame pointer but then used - LR in the function, then we do need a frame pointer after all, so - prevent this elimination to ensure a frame pointer is used. */ + /* If we decided that we didn't need a leaf frame pointer but then used + LR in the function, then we'll want a frame pointer after all, so + prevent this elimination to ensure a frame pointer is used. + NOTE: the original value of flag_omit_frame_pointer gets trashed + IFF flag_omit_leaf_frame_pointer is true, so we check the value + of faked_omit_frame_pointer here (which is true when we always + wish to keep non-leaf frame pointers but only wish to keep leaf frame + pointers when LR is clobbered). */ if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM - && df_regs_ever_live_p (LR_REGNUM)) + && df_regs_ever_live_p (LR_REGNUM) + && faked_omit_frame_pointer) return false; } + return true; } @@ -4550,9 +4571,11 @@ aarch64_address_cost (rtx x ATTRIBUTE_UNUSED, } static int -aarch64_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED, - reg_class_t from, reg_class_t to) +aarch64_register_move_cost (enum machine_mode mode, + reg_class_t from_i, reg_class_t to_i) { + enum reg_class from = (enum reg_class) from_i; + enum reg_class to = (enum reg_class) to_i; const struct cpu_regmove_cost *regmove_cost = aarch64_tune_params->regmove_cost; @@ -4568,8 +4591,7 @@ aarch64_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED, secondary reload. A general register is used as a scratch to move the upper DI value and the lower DI value is moved directly, hence the cost is the sum of three moves. */ - - if (! TARGET_SIMD && GET_MODE_SIZE (from) == 128 && GET_MODE_SIZE (to) == 128) + if (! TARGET_SIMD && GET_MODE_SIZE (mode) == 128) return regmove_cost->GP2FP + regmove_cost->FP2GP + regmove_cost->FP2FP; return regmove_cost->FP2FP; @@ -4826,6 +4848,15 @@ aarch64_override_options (void) aarch64_tune = selected_tune->core; aarch64_tune_params = selected_tune->tune; + if (aarch64_fix_a53_err835769 == 2) + { +#ifdef TARGET_FIX_ERR_A53_835769_DEFAULT + aarch64_fix_a53_err835769 = 1; +#else + aarch64_fix_a53_err835769 = 0; +#endif + } + aarch64_override_options_after_change (); } @@ -6018,6 +6049,135 @@ aarch64_mangle_type (const_tree type) return NULL; } + +/* Return true iff X is a MEM rtx. */ + +static int +is_mem_p (rtx *x, void *data ATTRIBUTE_UNUSED) +{ + return MEM_P (*x); +} + + +/* Return true if mem_insn contains a MEM RTX somewhere in it. */ + +static bool +has_memory_op (rtx mem_insn) +{ + rtx pattern = PATTERN (mem_insn); + return for_each_rtx (&pattern, is_mem_p, NULL); +} + + +/* Find the first rtx before insn that will generate an assembly + instruction. */ + +static rtx +aarch64_prev_real_insn (rtx insn) +{ + if (!insn) + return NULL; + + do + { + insn = prev_real_insn (insn); + } + while (insn && recog_memoized (insn) < 0); + + return insn; +} + +/* Return true iff t1 is the v8type of a multiply-accumulate instruction. */ + +static bool +is_madd_op (enum attr_v8type t1) +{ + return t1 == V8TYPE_MADD + || t1 == V8TYPE_MADDL; +} + + +/* Check if there is a register dependency between a load and the insn + for which we hold recog_data. */ + +static bool +dep_between_memop_and_curr (rtx memop) +{ + rtx load_reg; + int opno; + + gcc_assert (GET_CODE (memop) == SET); + + if (!REG_P (SET_DEST (memop))) + return false; + + load_reg = SET_DEST (memop); + for (opno = 1; opno < recog_data.n_operands; opno++) + { + rtx operand = recog_data.operand[opno]; + if (REG_P (operand) + && reg_overlap_mentioned_p (load_reg, operand)) + return true; + + } + return false; +} + + + +/* When working around the Cortex-A53 erratum 835769, + given rtx_insn INSN, return true if it is a 64-bit multiply-accumulate + instruction and has a preceding memory instruction such that a NOP + should be inserted between them. */ + +bool +aarch64_madd_needs_nop (rtx insn) +{ + enum attr_v8type attr_type; + rtx prev; + rtx body; + + if (!aarch64_fix_a53_err835769) + return false; + + if (recog_memoized (insn) < 0) + return false; + + attr_type = get_attr_v8type (insn); + if (!is_madd_op (attr_type)) + return false; + + prev = aarch64_prev_real_insn (insn); + /* aarch64_prev_real_insn can call recog_memoized on insns other than INSN. + Restore recog state to INSN to avoid state corruption. */ + extract_constrain_insn_cached (insn); + + if (!prev || !has_memory_op (prev)) + return false; + + body = single_set (prev); + + /* If the previous insn is a memory op and there is no dependency between + it and the madd, emit a nop between them. If we know it's a memop but + body is NULL, return true to be safe. */ + if (GET_MODE (recog_data.operand[0]) == DImode + && (!body || !dep_between_memop_and_curr (body))) + return true; + + return false; + +} + +/* Implement FINAL_PRESCAN_INSN. */ + +void +aarch64_final_prescan_insn (rtx insn) +{ + if (aarch64_madd_needs_nop (insn)) + fprintf (asm_out_file, "\tnop // between mem op and mult-accumulate\n"); +} + + /* Return the equivalent letter for size. */ static unsigned char sizetochar (int size) @@ -7048,13 +7208,31 @@ aarch64_split_atomic_op (enum rtx_code code, rtx old_out, rtx new_out, rtx mem, aarch64_emit_unlikely_jump (gen_rtx_SET (VOIDmode, pc_rtx, x)); } +static void +aarch64_print_extension (void) +{ + const struct aarch64_option_extension *opt = NULL; + + for (opt = all_extensions; opt->name != NULL; opt++) + if ((aarch64_isa_flags & opt->flags_on) == opt->flags_on) + asm_fprintf (asm_out_file, "+%s", opt->name); + + asm_fprintf (asm_out_file, "\n"); +} + static void aarch64_start_file (void) { if (selected_arch) - asm_fprintf (asm_out_file, "\t.arch %s\n", selected_arch->name); + { + asm_fprintf (asm_out_file, "\t.arch %s", selected_arch->name); + aarch64_print_extension (); + } else if (selected_cpu) - asm_fprintf (asm_out_file, "\t.cpu %s\n", selected_cpu->name); + { + asm_fprintf (asm_out_file, "\t.cpu %s", selected_cpu->name); + aarch64_print_extension (); + } default_file_start(); } diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h index c3efd2a887f57..1a8b993467bec 100644 --- a/gcc/config/aarch64/aarch64.h +++ b/gcc/config/aarch64/aarch64.h @@ -73,9 +73,9 @@ #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN) /* AdvSIMD is supported in the default configuration, unless disabled by - -mgeneral-regs-only. */ -#define TARGET_SIMD !TARGET_GENERAL_REGS_ONLY -#define TARGET_FLOAT !TARGET_GENERAL_REGS_ONLY + -mgeneral-regs-only or the +nosimd extension. */ +#define TARGET_SIMD (!TARGET_GENERAL_REGS_ONLY && AARCH64_ISA_SIMD) +#define TARGET_FLOAT (!TARGET_GENERAL_REGS_ONLY && AARCH64_ISA_FP) #define UNITS_PER_WORD 8 @@ -465,6 +465,18 @@ enum target_cpus (TARGET_CPU_generic | (AARCH64_CPU_DEFAULT_FLAGS << 6)) #endif +/* If inserting NOP before a mult-accumulate insn remember to adjust the + length so that conditional branching code is updated appropriately. */ +#define ADJUST_INSN_LENGTH(insn, length) \ + do \ + { \ + if (aarch64_madd_needs_nop (insn)) \ + length += 4; \ + } while (0) + +#define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ + aarch64_final_prescan_insn (INSN); \ + /* The processor for which instructions should be scheduled. */ extern enum aarch64_processor aarch64_tune; diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 76a51259728c3..f5c0761d4f1ba 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -834,7 +834,8 @@ movi\\t%d0, %1" [(set_attr "v8type" "move,move,move,alu,load1,store1,adr,adr,fmov,fmov,fmov,fmov") (set_attr "mode" "DI") - (set_attr "fp" "*,*,*,*,*,*,*,*,yes,yes,yes,yes")] + (set_attr "fp" "*,*,*,*,*,*,*,*,yes,yes,yes,*") + (set_attr "simd" "*,*,*,*,*,*,*,*,*,*,*,yes")] ) (define_insn "insv_imm" @@ -844,8 +845,8 @@ (match_operand:GPI 2 "const_int_operand" "n"))] "INTVAL (operands[1]) < GET_MODE_BITSIZE (mode) && INTVAL (operands[1]) % 16 == 0 - && INTVAL (operands[2]) <= 0xffff" - "movk\\t%0, %2, lsl %1" + && UINTVAL (operands[2]) <= 0xffff" + "movk\\t%0, %X2, lsl %1" [(set_attr "v8type" "movk") (set_attr "mode" "")] ) @@ -1312,7 +1313,7 @@ ) (define_insn "*add__" - [(set (match_operand:GPI 0 "register_operand" "=rk") + [(set (match_operand:GPI 0 "register_operand" "=r") (plus:GPI (ASHIFT:GPI (match_operand:GPI 1 "register_operand" "r") (match_operand:QI 2 "aarch64_shift_imm_" "n")) (match_operand:GPI 3 "register_operand" "r")))] @@ -1324,7 +1325,7 @@ ;; zero_extend version of above (define_insn "*add__si_uxtw" - [(set (match_operand:DI 0 "register_operand" "=rk") + [(set (match_operand:DI 0 "register_operand" "=r") (zero_extend:DI (plus:SI (ASHIFT:SI (match_operand:SI 1 "register_operand" "r") (match_operand:QI 2 "aarch64_shift_imm_si" "n")) @@ -1336,7 +1337,7 @@ ) (define_insn "*add_mul_imm_" - [(set (match_operand:GPI 0 "register_operand" "=rk") + [(set (match_operand:GPI 0 "register_operand" "=r") (plus:GPI (mult:GPI (match_operand:GPI 1 "register_operand" "r") (match_operand:QI 2 "aarch64_pwr_2_" "n")) (match_operand:GPI 3 "register_operand" "r")))] @@ -1659,7 +1660,7 @@ ) (define_insn "*sub__" - [(set (match_operand:GPI 0 "register_operand" "=rk") + [(set (match_operand:GPI 0 "register_operand" "=r") (minus:GPI (match_operand:GPI 3 "register_operand" "r") (ASHIFT:GPI (match_operand:GPI 1 "register_operand" "r") @@ -1672,7 +1673,7 @@ ;; zero_extend version of above (define_insn "*sub__si_uxtw" - [(set (match_operand:DI 0 "register_operand" "=rk") + [(set (match_operand:DI 0 "register_operand" "=r") (zero_extend:DI (minus:SI (match_operand:SI 3 "register_operand" "r") (ASHIFT:SI @@ -1685,7 +1686,7 @@ ) (define_insn "*sub_mul_imm_" - [(set (match_operand:GPI 0 "register_operand" "=rk") + [(set (match_operand:GPI 0 "register_operand" "=r") (minus:GPI (match_operand:GPI 3 "register_operand" "r") (mult:GPI (match_operand:GPI 1 "register_operand" "r") @@ -1698,7 +1699,7 @@ ;; zero_extend version of above (define_insn "*sub_mul_imm_si_uxtw" - [(set (match_operand:DI 0 "register_operand" "=rk") + [(set (match_operand:DI 0 "register_operand" "=r") (zero_extend:DI (minus:SI (match_operand:SI 3 "register_operand" "r") (mult:SI @@ -2210,7 +2211,7 @@ (set_attr "mode" "SI")] ) -(define_insn "*cstore_neg" +(define_insn "cstore_neg" [(set (match_operand:ALLI 0 "register_operand" "=r") (neg:ALLI (match_operator:ALLI 1 "aarch64_comparison_operator" [(match_operand 2 "cc_register" "") (const_int 0)])))] @@ -2611,6 +2612,8 @@ DONE; } } + else + FAIL; } ) @@ -2680,16 +2683,6 @@ (set_attr "mode" "SI")] ) -(define_insn "*ashl3_insn" - [(set (match_operand:SHORT 0 "register_operand" "=r") - (ashift:SHORT (match_operand:SHORT 1 "register_operand" "r") - (match_operand:QI 2 "aarch64_reg_or_shift_imm_si" "rUss")))] - "" - "lsl\\t%0, %1, %2" - [(set_attr "v8type" "shift") - (set_attr "mode" "")] -) - (define_insn "*3_insn" [(set (match_operand:SHORT 0 "register_operand" "=r") (ASHIFT:SHORT (match_operand:SHORT 1 "register_operand" "r") @@ -3291,6 +3284,7 @@ (unspec:DI [(match_operand:DI 0 "aarch64_valid_symref" "S")] UNSPEC_TLSDESC)) (clobber (reg:DI LR_REGNUM)) + (clobber (reg:CC CC_REGNUM)) (clobber (match_scratch:DI 1 "=r"))] "TARGET_TLS_DESC" "adrp\\tx0, %A0\;ldr\\t%1, [x0, #%L0]\;add\\tx0, x0, %L0\;.tlsdesccall\\t%0\;blr\\t%1" diff --git a/gcc/config/aarch64/aarch64.opt b/gcc/config/aarch64/aarch64.opt index 35182489d79c8..f7c70bf8f086b 100644 --- a/gcc/config/aarch64/aarch64.opt +++ b/gcc/config/aarch64/aarch64.opt @@ -67,6 +67,10 @@ mgeneral-regs-only Target Report RejectNegative Mask(GENERAL_REGS_ONLY) Generate code which uses only the general registers +mfix-cortex-a53-835769 +Target Report Var(aarch64_fix_a53_err835769) Init(2) +Workaround for ARM Cortex-A53 Erratum number 835769 + mlittle-endian Target Report RejectNegative InverseMask(BIG_END) Assume target CPU is configured as little endian diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h index ca474033e1d02..385e5c616009e 100644 --- a/gcc/config/aarch64/arm_neon.h +++ b/gcc/config/aarch64/arm_neon.h @@ -8390,10 +8390,10 @@ __extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) vld1_dup_f32 (const float32_t * a) { float32x2_t result; - __asm__ ("ld1r {%0.2s},[%1]" - : "=w"(result) - : "r"(a) - : "memory"); + __asm__ ("ld1r {%0.2s}, %1" + : "=w"(result) + : "Utv"(*a) + : /* No clobbers */); return result; } @@ -8401,10 +8401,10 @@ __extension__ static __inline float64x1_t __attribute__ ((__always_inline__)) vld1_dup_f64 (const float64_t * a) { float64x1_t result; - __asm__ ("ld1 {%0.1d},[%1]" - : "=w"(result) - : "r"(a) - : "memory"); + __asm__ ("ld1r {%0.1d}, %1" + : "=w"(result) + : "Utv"(*a) + : /* No clobbers */); return result; } @@ -8412,10 +8412,10 @@ __extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) vld1_dup_p8 (const poly8_t * a) { poly8x8_t result; - __asm__ ("ld1r {%0.8b},[%1]" - : "=w"(result) - : "r"(a) - : "memory"); + __asm__ ("ld1r {%0.8b}, %1" + : "=w"(result) + : "Utv"(*a) + : /* No clobbers */); return result; } @@ -8423,10 +8423,10 @@ __extension__ static __inline poly16x4_t __attribute__ ((__always_inline__)) vld1_dup_p16 (const poly16_t * a) { poly16x4_t result; - __asm__ ("ld1r {%0.4h},[%1]" - : "=w"(result) - : "r"(a) - : "memory"); + __asm__ ("ld1r {%0.4h}, %1" + : "=w"(result) + : "Utv"(*a) + : /* No clobbers */); return result; } @@ -8434,10 +8434,10 @@ __extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) vld1_dup_s8 (const int8_t * a) { int8x8_t result; - __asm__ ("ld1r {%0.8b},[%1]" - : "=w"(result) - : "r"(a) - : "memory"); + __asm__ ("ld1r {%0.8b}, %1" + : "=w"(result) + : "Utv"(*a) + : /* No clobbers */); return result; } @@ -8445,10 +8445,10 @@ __extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) vld1_dup_s16 (const int16_t * a) { int16x4_t result; - __asm__ ("ld1r {%0.4h},[%1]" - : "=w"(result) - : "r"(a) - : "memory"); + __asm__ ("ld1r {%0.4h}, %1" + : "=w"(result) + : "Utv"(*a) + : /* No clobbers */); return result; } @@ -8456,10 +8456,10 @@ __extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) vld1_dup_s32 (const int32_t * a) { int32x2_t result; - __asm__ ("ld1r {%0.2s},[%1]" - : "=w"(result) - : "r"(a) - : "memory"); + __asm__ ("ld1r {%0.2s}, %1" + : "=w"(result) + : "Utv"(*a) + : /* No clobbers */); return result; } @@ -8467,10 +8467,10 @@ __extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) vld1_dup_s64 (const int64_t * a) { int64x1_t result; - __asm__ ("ld1 {%0.1d},[%1]" - : "=w"(result) - : "r"(a) - : "memory"); + __asm__ ("ld1r {%0.1d}, %1" + : "=w"(result) + : "Utv"(*a) + : /* No clobbers */); return result; } @@ -8478,10 +8478,10 @@ __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) vld1_dup_u8 (const uint8_t * a) { uint8x8_t result; - __asm__ ("ld1r {%0.8b},[%1]" - : "=w"(result) - : "r"(a) - : "memory"); + __asm__ ("ld1r {%0.8b}, %1" + : "=w"(result) + : "Utv"(*a) + : /* No clobbers */); return result; } @@ -8489,10 +8489,10 @@ __extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) vld1_dup_u16 (const uint16_t * a) { uint16x4_t result; - __asm__ ("ld1r {%0.4h},[%1]" - : "=w"(result) - : "r"(a) - : "memory"); + __asm__ ("ld1r {%0.4h}, %1" + : "=w"(result) + : "Utv"(*a) + : /* No clobbers */); return result; } @@ -8500,10 +8500,10 @@ __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) vld1_dup_u32 (const uint32_t * a) { uint32x2_t result; - __asm__ ("ld1r {%0.2s},[%1]" - : "=w"(result) - : "r"(a) - : "memory"); + __asm__ ("ld1r {%0.2s}, %1" + : "=w"(result) + : "Utv"(*a) + : /* No clobbers */); return result; } @@ -8511,32 +8511,10 @@ __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) vld1_dup_u64 (const uint64_t * a) { uint64x1_t result; - __asm__ ("ld1 {%0.1d},[%1]" - : "=w"(result) - : "r"(a) - : "memory"); - return result; -} - -__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) -vld1_f32 (const float32_t * a) -{ - float32x2_t result; - __asm__ ("ld1 {%0.2s},[%1]" - : "=w"(result) - : "r"(a) - : "memory"); - return result; -} - -__extension__ static __inline float64x1_t __attribute__ ((__always_inline__)) -vld1_f64 (const float64_t * a) -{ - float64x1_t result; - __asm__ ("ld1 {%0.1d},[%1]" - : "=w"(result) - : "r"(a) - : "memory"); + __asm__ ("ld1r {%0.1d}, %1" + : "=w"(result) + : "Utv"(*a) + : /* No clobbers */); return result; } @@ -8546,9 +8524,9 @@ vld1_f64 (const float64_t * a) float32x2_t b_ = (b); \ const float32_t * a_ = (a); \ float32x2_t result; \ - __asm__ ("ld1 {%0.s}[%3],[%1]" \ + __asm__ ("ld1 {%0.s}[%1], %2" \ : "=w"(result) \ - : "r"(a_), "0"(b_), "i"(c) \ + : "i" (c), "Utv"(*a_), "0"(b_) \ : /* No clobbers */); \ result; \ }) @@ -8559,9 +8537,9 @@ vld1_f64 (const float64_t * a) float64x1_t b_ = (b); \ const float64_t * a_ = (a); \ float64x1_t result; \ - __asm__ ("ld1 {%0.d}[%3],[%1]" \ + __asm__ ("ld1 {%0.d}[%1], %2" \ : "=w"(result) \ - : "r"(a_), "0"(b_), "i"(c) \ + : "i" (c), "Utv"(*a_), "0"(b_) \ : /* No clobbers */); \ result; \ }) @@ -8572,9 +8550,9 @@ vld1_f64 (const float64_t * a) poly8x8_t b_ = (b); \ const poly8_t * a_ = (a); \ poly8x8_t result; \ - __asm__ ("ld1 {%0.b}[%3],[%1]" \ + __asm__ ("ld1 {%0.b}[%1], %2" \ : "=w"(result) \ - : "r"(a_), "0"(b_), "i"(c) \ + : "i" (c), "Utv"(*a_), "0"(b_) \ : /* No clobbers */); \ result; \ }) @@ -8585,9 +8563,9 @@ vld1_f64 (const float64_t * a) poly16x4_t b_ = (b); \ const poly16_t * a_ = (a); \ poly16x4_t result; \ - __asm__ ("ld1 {%0.h}[%3],[%1]" \ + __asm__ ("ld1 {%0.h}[%1], %2" \ : "=w"(result) \ - : "r"(a_), "0"(b_), "i"(c) \ + : "i" (c), "Utv"(*a_), "0"(b_) \ : /* No clobbers */); \ result; \ }) @@ -8598,9 +8576,9 @@ vld1_f64 (const float64_t * a) int8x8_t b_ = (b); \ const int8_t * a_ = (a); \ int8x8_t result; \ - __asm__ ("ld1 {%0.b}[%3],[%1]" \ + __asm__ ("ld1 {%0.b}[%1], %2" \ : "=w"(result) \ - : "r"(a_), "0"(b_), "i"(c) \ + : "i" (c), "Utv"(*a_), "0"(b_) \ : /* No clobbers */); \ result; \ }) @@ -8611,9 +8589,9 @@ vld1_f64 (const float64_t * a) int16x4_t b_ = (b); \ const int16_t * a_ = (a); \ int16x4_t result; \ - __asm__ ("ld1 {%0.h}[%3],[%1]" \ + __asm__ ("ld1 {%0.h}[%1], %2" \ : "=w"(result) \ - : "r"(a_), "0"(b_), "i"(c) \ + : "i" (c), "Utv"(*a_), "0"(b_) \ : /* No clobbers */); \ result; \ }) @@ -8624,9 +8602,9 @@ vld1_f64 (const float64_t * a) int32x2_t b_ = (b); \ const int32_t * a_ = (a); \ int32x2_t result; \ - __asm__ ("ld1 {%0.s}[%3],[%1]" \ + __asm__ ("ld1 {%0.s}[%1], %2" \ : "=w"(result) \ - : "r"(a_), "0"(b_), "i"(c) \ + : "i" (c), "Utv"(*a_), "0"(b_) \ : /* No clobbers */); \ result; \ }) @@ -8637,9 +8615,9 @@ vld1_f64 (const float64_t * a) int64x1_t b_ = (b); \ const int64_t * a_ = (a); \ int64x1_t result; \ - __asm__ ("ld1 {%0.d}[%3],[%1]" \ + __asm__ ("ld1 {%0.d}[%1], %2" \ : "=w"(result) \ - : "r"(a_), "0"(b_), "i"(c) \ + : "i" (c), "Utv"(*a_), "0"(b_) \ : /* No clobbers */); \ result; \ }) @@ -8650,9 +8628,9 @@ vld1_f64 (const float64_t * a) uint8x8_t b_ = (b); \ const uint8_t * a_ = (a); \ uint8x8_t result; \ - __asm__ ("ld1 {%0.b}[%3],[%1]" \ + __asm__ ("ld1 {%0.b}[%1], %2" \ : "=w"(result) \ - : "r"(a_), "0"(b_), "i"(c) \ + : "i" (c), "Utv"(*a_), "0"(b_) \ : /* No clobbers */); \ result; \ }) @@ -8663,9 +8641,9 @@ vld1_f64 (const float64_t * a) uint16x4_t b_ = (b); \ const uint16_t * a_ = (a); \ uint16x4_t result; \ - __asm__ ("ld1 {%0.h}[%3],[%1]" \ + __asm__ ("ld1 {%0.h}[%1], %2" \ : "=w"(result) \ - : "r"(a_), "0"(b_), "i"(c) \ + : "i" (c), "Utv"(*a_), "0"(b_) \ : /* No clobbers */); \ result; \ }) @@ -8676,9 +8654,9 @@ vld1_f64 (const float64_t * a) uint32x2_t b_ = (b); \ const uint32_t * a_ = (a); \ uint32x2_t result; \ - __asm__ ("ld1 {%0.s}[%3],[%1]" \ + __asm__ ("ld1 {%0.s}[%1], %2" \ : "=w"(result) \ - : "r"(a_), "0"(b_), "i"(c) \ + : "i" (c), "Utv"(*a_), "0"(b_) \ : /* No clobbers */); \ result; \ }) @@ -8689,131 +8667,21 @@ vld1_f64 (const float64_t * a) uint64x1_t b_ = (b); \ const uint64_t * a_ = (a); \ uint64x1_t result; \ - __asm__ ("ld1 {%0.d}[%3],[%1]" \ + __asm__ ("ld1 {%0.d}[%1], %2" \ : "=w"(result) \ - : "r"(a_), "0"(b_), "i"(c) \ + : "i" (c), "Utv"(*a_), "0"(b_) \ : /* No clobbers */); \ result; \ }) -__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) -vld1_p8 (const poly8_t * a) -{ - poly8x8_t result; - __asm__ ("ld1 {%0.8b}, [%1]" - : "=w"(result) - : "r"(a) - : /* No clobbers */); - return result; -} - -__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__)) -vld1_p16 (const poly16_t * a) -{ - poly16x4_t result; - __asm__ ("ld1 {%0.4h}, [%1]" - : "=w"(result) - : "r"(a) - : /* No clobbers */); - return result; -} - -__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -vld1_s8 (const int8_t * a) -{ - int8x8_t result; - __asm__ ("ld1 {%0.8b},[%1]" - : "=w"(result) - : "r"(a) - : "memory"); - return result; -} - -__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -vld1_s16 (const int16_t * a) -{ - int16x4_t result; - __asm__ ("ld1 {%0.4h},[%1]" - : "=w"(result) - : "r"(a) - : "memory"); - return result; -} - -__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -vld1_s32 (const int32_t * a) -{ - int32x2_t result; - __asm__ ("ld1 {%0.2s},[%1]" - : "=w"(result) - : "r"(a) - : "memory"); - return result; -} - -__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -vld1_s64 (const int64_t * a) -{ - int64x1_t result; - __asm__ ("ld1 {%0.1d},[%1]" - : "=w"(result) - : "r"(a) - : "memory"); - return result; -} - -__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -vld1_u8 (const uint8_t * a) -{ - uint8x8_t result; - __asm__ ("ld1 {%0.8b},[%1]" - : "=w"(result) - : "r"(a) - : "memory"); - return result; -} - -__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -vld1_u16 (const uint16_t * a) -{ - uint16x4_t result; - __asm__ ("ld1 {%0.4h},[%1]" - : "=w"(result) - : "r"(a) - : "memory"); - return result; -} - -__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -vld1_u32 (const uint32_t * a) -{ - uint32x2_t result; - __asm__ ("ld1 {%0.2s},[%1]" - : "=w"(result) - : "r"(a) - : "memory"); - return result; -} - -__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) -vld1_u64 (const uint64_t * a) -{ - uint64x1_t result; - __asm__ ("ld1 {%0.1d},[%1]" - : "=w"(result) - : "r"(a) - : "memory"); - return result; -} - __extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) vld1q_dup_f32 (const float32_t * a) { float32x4_t result; - __asm__ ("ld1r {%0.4s},[%1]" - : "=w"(result) - : "r"(a) - : "memory"); + __asm__ ("ld1r {%0.4s}, %1" + : "=w"(result) + : "Utv"(*a) + : /* No clobbers */); return result; } @@ -8821,10 +8689,10 @@ __extension__ static __inline float64x2_t __attribute__ ((__always_inline__)) vld1q_dup_f64 (const float64_t * a) { float64x2_t result; - __asm__ ("ld1r {%0.2d},[%1]" - : "=w"(result) - : "r"(a) - : "memory"); + __asm__ ("ld1r {%0.2d}, %1" + : "=w"(result) + : "Utv"(*a) + : /* No clobbers */); return result; } @@ -8832,10 +8700,10 @@ __extension__ static __inline poly8x16_t __attribute__ ((__always_inline__)) vld1q_dup_p8 (const poly8_t * a) { poly8x16_t result; - __asm__ ("ld1r {%0.16b},[%1]" - : "=w"(result) - : "r"(a) - : "memory"); + __asm__ ("ld1r {%0.16b}, %1" + : "=w"(result) + : "Utv"(*a) + : /* No clobbers */); return result; } @@ -8843,10 +8711,10 @@ __extension__ static __inline poly16x8_t __attribute__ ((__always_inline__)) vld1q_dup_p16 (const poly16_t * a) { poly16x8_t result; - __asm__ ("ld1r {%0.8h},[%1]" - : "=w"(result) - : "r"(a) - : "memory"); + __asm__ ("ld1r {%0.8h}, %1" + : "=w"(result) + : "Utv"(*a) + : /* No clobbers */); return result; } @@ -8854,10 +8722,10 @@ __extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) vld1q_dup_s8 (const int8_t * a) { int8x16_t result; - __asm__ ("ld1r {%0.16b},[%1]" - : "=w"(result) - : "r"(a) - : "memory"); + __asm__ ("ld1r {%0.16b}, %1" + : "=w"(result) + : "Utv"(*a) + : /* No clobbers */); return result; } @@ -8865,10 +8733,10 @@ __extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) vld1q_dup_s16 (const int16_t * a) { int16x8_t result; - __asm__ ("ld1r {%0.8h},[%1]" - : "=w"(result) - : "r"(a) - : "memory"); + __asm__ ("ld1r {%0.8h}, %1" + : "=w"(result) + : "Utv"(*a) + : /* No clobbers */); return result; } @@ -8876,10 +8744,10 @@ __extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) vld1q_dup_s32 (const int32_t * a) { int32x4_t result; - __asm__ ("ld1r {%0.4s},[%1]" - : "=w"(result) - : "r"(a) - : "memory"); + __asm__ ("ld1r {%0.4s}, %1" + : "=w"(result) + : "Utv"(*a) + : /* No clobbers */); return result; } @@ -8887,10 +8755,10 @@ __extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) vld1q_dup_s64 (const int64_t * a) { int64x2_t result; - __asm__ ("ld1r {%0.2d},[%1]" - : "=w"(result) - : "r"(a) - : "memory"); + __asm__ ("ld1r {%0.2d}, %1" + : "=w"(result) + : "Utv"(*a) + : /* No clobbers */); return result; } @@ -8898,10 +8766,10 @@ __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) vld1q_dup_u8 (const uint8_t * a) { uint8x16_t result; - __asm__ ("ld1r {%0.16b},[%1]" - : "=w"(result) - : "r"(a) - : "memory"); + __asm__ ("ld1r {%0.16b}, %1" + : "=w"(result) + : "Utv"(*a) + : /* No clobbers */); return result; } @@ -8909,10 +8777,10 @@ __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) vld1q_dup_u16 (const uint16_t * a) { uint16x8_t result; - __asm__ ("ld1r {%0.8h},[%1]" - : "=w"(result) - : "r"(a) - : "memory"); + __asm__ ("ld1r {%0.8h}, %1" + : "=w"(result) + : "Utv"(*a) + : /* No clobbers */); return result; } @@ -8920,10 +8788,10 @@ __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) vld1q_dup_u32 (const uint32_t * a) { uint32x4_t result; - __asm__ ("ld1r {%0.4s},[%1]" - : "=w"(result) - : "r"(a) - : "memory"); + __asm__ ("ld1r {%0.4s}, %1" + : "=w"(result) + : "Utv"(*a) + : /* No clobbers */); return result; } @@ -8931,32 +8799,10 @@ __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) vld1q_dup_u64 (const uint64_t * a) { uint64x2_t result; - __asm__ ("ld1r {%0.2d},[%1]" - : "=w"(result) - : "r"(a) - : "memory"); - return result; -} - -__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -vld1q_f32 (const float32_t * a) -{ - float32x4_t result; - __asm__ ("ld1 {%0.4s},[%1]" - : "=w"(result) - : "r"(a) - : "memory"); - return result; -} - -__extension__ static __inline float64x2_t __attribute__ ((__always_inline__)) -vld1q_f64 (const float64_t * a) -{ - float64x2_t result; - __asm__ ("ld1 {%0.2d},[%1]" - : "=w"(result) - : "r"(a) - : "memory"); + __asm__ ("ld1r {%0.2d}, %1" + : "=w"(result) + : "Utv"(*a) + : /* No clobbers */); return result; } @@ -8966,9 +8812,9 @@ vld1q_f64 (const float64_t * a) float32x4_t b_ = (b); \ const float32_t * a_ = (a); \ float32x4_t result; \ - __asm__ ("ld1 {%0.s}[%3],[%1]" \ + __asm__ ("ld1 {%0.s}[%1], %2" \ : "=w"(result) \ - : "r"(a_), "0"(b_), "i"(c) \ + : "i"(c), "Utv"(*a_), "0"(b_) \ : /* No clobbers */); \ result; \ }) @@ -8979,9 +8825,9 @@ vld1q_f64 (const float64_t * a) float64x2_t b_ = (b); \ const float64_t * a_ = (a); \ float64x2_t result; \ - __asm__ ("ld1 {%0.d}[%3],[%1]" \ + __asm__ ("ld1 {%0.d}[%1], %2" \ : "=w"(result) \ - : "r"(a_), "0"(b_), "i"(c) \ + : "i"(c), "Utv"(*a_), "0"(b_) \ : /* No clobbers */); \ result; \ }) @@ -8992,9 +8838,9 @@ vld1q_f64 (const float64_t * a) poly8x16_t b_ = (b); \ const poly8_t * a_ = (a); \ poly8x16_t result; \ - __asm__ ("ld1 {%0.b}[%3],[%1]" \ + __asm__ ("ld1 {%0.b}[%1], %2" \ : "=w"(result) \ - : "r"(a_), "0"(b_), "i"(c) \ + : "i"(c), "Utv"(*a_), "0"(b_) \ : /* No clobbers */); \ result; \ }) @@ -9005,9 +8851,9 @@ vld1q_f64 (const float64_t * a) poly16x8_t b_ = (b); \ const poly16_t * a_ = (a); \ poly16x8_t result; \ - __asm__ ("ld1 {%0.h}[%3],[%1]" \ + __asm__ ("ld1 {%0.h}[%1], %2" \ : "=w"(result) \ - : "r"(a_), "0"(b_), "i"(c) \ + : "i"(c), "Utv"(*a_), "0"(b_) \ : /* No clobbers */); \ result; \ }) @@ -9018,9 +8864,9 @@ vld1q_f64 (const float64_t * a) int8x16_t b_ = (b); \ const int8_t * a_ = (a); \ int8x16_t result; \ - __asm__ ("ld1 {%0.b}[%3],[%1]" \ + __asm__ ("ld1 {%0.b}[%1], %2" \ : "=w"(result) \ - : "r"(a_), "0"(b_), "i"(c) \ + : "i"(c), "Utv"(*a_), "0"(b_) \ : /* No clobbers */); \ result; \ }) @@ -9031,9 +8877,9 @@ vld1q_f64 (const float64_t * a) int16x8_t b_ = (b); \ const int16_t * a_ = (a); \ int16x8_t result; \ - __asm__ ("ld1 {%0.h}[%3],[%1]" \ + __asm__ ("ld1 {%0.h}[%1], %2" \ : "=w"(result) \ - : "r"(a_), "0"(b_), "i"(c) \ + : "i"(c), "Utv"(*a_), "0"(b_) \ : /* No clobbers */); \ result; \ }) @@ -9044,9 +8890,9 @@ vld1q_f64 (const float64_t * a) int32x4_t b_ = (b); \ const int32_t * a_ = (a); \ int32x4_t result; \ - __asm__ ("ld1 {%0.s}[%3],[%1]" \ + __asm__ ("ld1 {%0.s}[%1], %2" \ : "=w"(result) \ - : "r"(a_), "0"(b_), "i"(c) \ + : "i"(c), "Utv"(*a_), "0"(b_) \ : /* No clobbers */); \ result; \ }) @@ -9057,9 +8903,9 @@ vld1q_f64 (const float64_t * a) int64x2_t b_ = (b); \ const int64_t * a_ = (a); \ int64x2_t result; \ - __asm__ ("ld1 {%0.d}[%3],[%1]" \ + __asm__ ("ld1 {%0.d}[%1], %2" \ : "=w"(result) \ - : "r"(a_), "0"(b_), "i"(c) \ + : "i"(c), "Utv"(*a_), "0"(b_) \ : /* No clobbers */); \ result; \ }) @@ -9070,9 +8916,9 @@ vld1q_f64 (const float64_t * a) uint8x16_t b_ = (b); \ const uint8_t * a_ = (a); \ uint8x16_t result; \ - __asm__ ("ld1 {%0.b}[%3],[%1]" \ + __asm__ ("ld1 {%0.b}[%1], %2" \ : "=w"(result) \ - : "r"(a_), "0"(b_), "i"(c) \ + : "i"(c), "Utv"(*a_), "0"(b_) \ : /* No clobbers */); \ result; \ }) @@ -9083,9 +8929,9 @@ vld1q_f64 (const float64_t * a) uint16x8_t b_ = (b); \ const uint16_t * a_ = (a); \ uint16x8_t result; \ - __asm__ ("ld1 {%0.h}[%3],[%1]" \ + __asm__ ("ld1 {%0.h}[%1], %2" \ : "=w"(result) \ - : "r"(a_), "0"(b_), "i"(c) \ + : "i"(c), "Utv"(*a_), "0"(b_) \ : /* No clobbers */); \ result; \ }) @@ -9096,9 +8942,9 @@ vld1q_f64 (const float64_t * a) uint32x4_t b_ = (b); \ const uint32_t * a_ = (a); \ uint32x4_t result; \ - __asm__ ("ld1 {%0.s}[%3],[%1]" \ + __asm__ ("ld1 {%0.s}[%1], %2" \ : "=w"(result) \ - : "r"(a_), "0"(b_), "i"(c) \ + : "i"(c), "Utv"(*a_), "0"(b_) \ : /* No clobbers */); \ result; \ }) @@ -9109,123 +8955,13 @@ vld1q_f64 (const float64_t * a) uint64x2_t b_ = (b); \ const uint64_t * a_ = (a); \ uint64x2_t result; \ - __asm__ ("ld1 {%0.d}[%3],[%1]" \ + __asm__ ("ld1 {%0.d}[%1], %2" \ : "=w"(result) \ - : "r"(a_), "0"(b_), "i"(c) \ + : "i"(c), "Utv"(*a_), "0"(b_) \ : /* No clobbers */); \ result; \ }) -__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__)) -vld1q_p8 (const poly8_t * a) -{ - poly8x16_t result; - __asm__ ("ld1 {%0.16b},[%1]" - : "=w"(result) - : "r"(a) - : "memory"); - return result; -} - -__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__)) -vld1q_p16 (const poly16_t * a) -{ - poly16x8_t result; - __asm__ ("ld1 {%0.8h},[%1]" - : "=w"(result) - : "r"(a) - : "memory"); - return result; -} - -__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -vld1q_s8 (const int8_t * a) -{ - int8x16_t result; - __asm__ ("ld1 {%0.16b},[%1]" - : "=w"(result) - : "r"(a) - : "memory"); - return result; -} - -__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) -vld1q_s16 (const int16_t * a) -{ - int16x8_t result; - __asm__ ("ld1 {%0.8h},[%1]" - : "=w"(result) - : "r"(a) - : "memory"); - return result; -} - -__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) -vld1q_s32 (const int32_t * a) -{ - int32x4_t result; - __asm__ ("ld1 {%0.4s},[%1]" - : "=w"(result) - : "r"(a) - : "memory"); - return result; -} - -__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) -vld1q_s64 (const int64_t * a) -{ - int64x2_t result; - __asm__ ("ld1 {%0.2d},[%1]" - : "=w"(result) - : "r"(a) - : "memory"); - return result; -} - -__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -vld1q_u8 (const uint8_t * a) -{ - uint8x16_t result; - __asm__ ("ld1 {%0.16b},[%1]" - : "=w"(result) - : "r"(a) - : "memory"); - return result; -} - -__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) -vld1q_u16 (const uint16_t * a) -{ - uint16x8_t result; - __asm__ ("ld1 {%0.8h},[%1]" - : "=w"(result) - : "r"(a) - : "memory"); - return result; -} - -__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) -vld1q_u32 (const uint32_t * a) -{ - uint32x4_t result; - __asm__ ("ld1 {%0.4s},[%1]" - : "=w"(result) - : "r"(a) - : "memory"); - return result; -} - -__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) -vld1q_u64 (const uint64_t * a) -{ - uint64x2_t result; - __asm__ ("ld1 {%0.2d},[%1]" - : "=w"(result) - : "r"(a) - : "memory"); - return result; -} - __extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) vmaxnm_f32 (float32x2_t a, float32x2_t b) { @@ -14079,7 +13815,7 @@ vqdmulh_n_s16 (int16x4_t a, int16_t b) int16x4_t result; __asm__ ("sqdmulh %0.4h,%1.4h,%2.h[0]" : "=w"(result) - : "w"(a), "w"(b) + : "w"(a), "x"(b) : /* No clobbers */); return result; } @@ -14101,7 +13837,7 @@ vqdmulhq_n_s16 (int16x8_t a, int16_t b) int16x8_t result; __asm__ ("sqdmulh %0.8h,%1.8h,%2.h[0]" : "=w"(result) - : "w"(a), "w"(b) + : "w"(a), "x"(b) : /* No clobbers */); return result; } @@ -16285,24 +16021,6 @@ vrsubhn_u64 (uint64x2_t a, uint64x2_t b) result; \ }) -__extension__ static __inline void __attribute__ ((__always_inline__)) -vst1_f32 (float32_t * a, float32x2_t b) -{ - __asm__ ("st1 {%1.2s},[%0]" - : - : "r"(a), "w"(b) - : "memory"); -} - -__extension__ static __inline void __attribute__ ((__always_inline__)) -vst1_f64 (float64_t * a, float64x1_t b) -{ - __asm__ ("st1 {%1.1d},[%0]" - : - : "r"(a), "w"(b) - : "memory"); -} - #define vst1_lane_f32(a, b, c) \ __extension__ \ ({ \ @@ -16419,129 +16137,22 @@ vst1_f64 (float64_t * a, float64x1_t b) uint32x2_t b_ = (b); \ uint32_t * a_ = (a); \ __asm__ ("st1 {%1.s}[%2],[%0]" \ - : \ - : "r"(a_), "w"(b_), "i"(c) \ - : "memory"); \ - }) - -#define vst1_lane_u64(a, b, c) \ - __extension__ \ - ({ \ - uint64x1_t b_ = (b); \ - uint64_t * a_ = (a); \ - __asm__ ("st1 {%1.d}[%2],[%0]" \ - : \ - : "r"(a_), "w"(b_), "i"(c) \ - : "memory"); \ - }) - -__extension__ static __inline void __attribute__ ((__always_inline__)) -vst1_p8 (poly8_t * a, poly8x8_t b) -{ - __asm__ ("st1 {%1.8b},[%0]" - : - : "r"(a), "w"(b) - : "memory"); -} - -__extension__ static __inline void __attribute__ ((__always_inline__)) -vst1_p16 (poly16_t * a, poly16x4_t b) -{ - __asm__ ("st1 {%1.4h},[%0]" - : - : "r"(a), "w"(b) - : "memory"); -} - -__extension__ static __inline void __attribute__ ((__always_inline__)) -vst1_s8 (int8_t * a, int8x8_t b) -{ - __asm__ ("st1 {%1.8b},[%0]" - : - : "r"(a), "w"(b) - : "memory"); -} - -__extension__ static __inline void __attribute__ ((__always_inline__)) -vst1_s16 (int16_t * a, int16x4_t b) -{ - __asm__ ("st1 {%1.4h},[%0]" - : - : "r"(a), "w"(b) - : "memory"); -} - -__extension__ static __inline void __attribute__ ((__always_inline__)) -vst1_s32 (int32_t * a, int32x2_t b) -{ - __asm__ ("st1 {%1.2s},[%0]" - : - : "r"(a), "w"(b) - : "memory"); -} - -__extension__ static __inline void __attribute__ ((__always_inline__)) -vst1_s64 (int64_t * a, int64x1_t b) -{ - __asm__ ("st1 {%1.1d},[%0]" - : - : "r"(a), "w"(b) - : "memory"); -} - -__extension__ static __inline void __attribute__ ((__always_inline__)) -vst1_u8 (uint8_t * a, uint8x8_t b) -{ - __asm__ ("st1 {%1.8b},[%0]" - : - : "r"(a), "w"(b) - : "memory"); -} - -__extension__ static __inline void __attribute__ ((__always_inline__)) -vst1_u16 (uint16_t * a, uint16x4_t b) -{ - __asm__ ("st1 {%1.4h},[%0]" - : - : "r"(a), "w"(b) - : "memory"); -} - -__extension__ static __inline void __attribute__ ((__always_inline__)) -vst1_u32 (uint32_t * a, uint32x2_t b) -{ - __asm__ ("st1 {%1.2s},[%0]" - : - : "r"(a), "w"(b) - : "memory"); -} - -__extension__ static __inline void __attribute__ ((__always_inline__)) -vst1_u64 (uint64_t * a, uint64x1_t b) -{ - __asm__ ("st1 {%1.1d},[%0]" - : - : "r"(a), "w"(b) - : "memory"); -} + : \ + : "r"(a_), "w"(b_), "i"(c) \ + : "memory"); \ + }) -__extension__ static __inline void __attribute__ ((__always_inline__)) -vst1q_f32 (float32_t * a, float32x4_t b) -{ - __asm__ ("st1 {%1.4s},[%0]" - : - : "r"(a), "w"(b) - : "memory"); -} +#define vst1_lane_u64(a, b, c) \ + __extension__ \ + ({ \ + uint64x1_t b_ = (b); \ + uint64_t * a_ = (a); \ + __asm__ ("st1 {%1.d}[%2],[%0]" \ + : \ + : "r"(a_), "w"(b_), "i"(c) \ + : "memory"); \ + }) -__extension__ static __inline void __attribute__ ((__always_inline__)) -vst1q_f64 (float64_t * a, float64x2_t b) -{ - __asm__ ("st1 {%1.2d},[%0]" - : - : "r"(a), "w"(b) - : "memory"); -} #define vst1q_lane_f32(a, b, c) \ __extension__ \ @@ -16675,96 +16286,6 @@ vst1q_f64 (float64_t * a, float64x2_t b) : "memory"); \ }) -__extension__ static __inline void __attribute__ ((__always_inline__)) -vst1q_p8 (poly8_t * a, poly8x16_t b) -{ - __asm__ ("st1 {%1.16b},[%0]" - : - : "r"(a), "w"(b) - : "memory"); -} - -__extension__ static __inline void __attribute__ ((__always_inline__)) -vst1q_p16 (poly16_t * a, poly16x8_t b) -{ - __asm__ ("st1 {%1.8h},[%0]" - : - : "r"(a), "w"(b) - : "memory"); -} - -__extension__ static __inline void __attribute__ ((__always_inline__)) -vst1q_s8 (int8_t * a, int8x16_t b) -{ - __asm__ ("st1 {%1.16b},[%0]" - : - : "r"(a), "w"(b) - : "memory"); -} - -__extension__ static __inline void __attribute__ ((__always_inline__)) -vst1q_s16 (int16_t * a, int16x8_t b) -{ - __asm__ ("st1 {%1.8h},[%0]" - : - : "r"(a), "w"(b) - : "memory"); -} - -__extension__ static __inline void __attribute__ ((__always_inline__)) -vst1q_s32 (int32_t * a, int32x4_t b) -{ - __asm__ ("st1 {%1.4s},[%0]" - : - : "r"(a), "w"(b) - : "memory"); -} - -__extension__ static __inline void __attribute__ ((__always_inline__)) -vst1q_s64 (int64_t * a, int64x2_t b) -{ - __asm__ ("st1 {%1.2d},[%0]" - : - : "r"(a), "w"(b) - : "memory"); -} - -__extension__ static __inline void __attribute__ ((__always_inline__)) -vst1q_u8 (uint8_t * a, uint8x16_t b) -{ - __asm__ ("st1 {%1.16b},[%0]" - : - : "r"(a), "w"(b) - : "memory"); -} - -__extension__ static __inline void __attribute__ ((__always_inline__)) -vst1q_u16 (uint16_t * a, uint16x8_t b) -{ - __asm__ ("st1 {%1.8h},[%0]" - : - : "r"(a), "w"(b) - : "memory"); -} - -__extension__ static __inline void __attribute__ ((__always_inline__)) -vst1q_u32 (uint32_t * a, uint32x4_t b) -{ - __asm__ ("st1 {%1.4s},[%0]" - : - : "r"(a), "w"(b) - : "memory"); -} - -__extension__ static __inline void __attribute__ ((__always_inline__)) -vst1q_u64 (uint64_t * a, uint64x2_t b) -{ - __asm__ ("st1 {%1.2d},[%0]" - : - : "r"(a), "w"(b) - : "memory"); -} - __extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) vsubhn_high_s16 (int8x8_t a, int16x8_t b, int16x8_t c) { @@ -19669,7 +19190,7 @@ vtbx1_s8 (int8x8_t r, int8x8_t tab, int8x8_t idx) "cmhs %0.8b, %3.8b, %0.8b\n\t" "tbl %1.8b, {%2.16b}, %3.8b\n\t" "bsl %0.8b, %4.8b, %1.8b\n\t" - : "+w"(result), "=w"(tmp1) + : "+w"(result), "=&w"(tmp1) : "w"(temp), "w"(idx), "w"(r) : /* No clobbers */); return result; @@ -19685,7 +19206,7 @@ vtbx1_u8 (uint8x8_t r, uint8x8_t tab, uint8x8_t idx) "cmhs %0.8b, %3.8b, %0.8b\n\t" "tbl %1.8b, {%2.16b}, %3.8b\n\t" "bsl %0.8b, %4.8b, %1.8b\n\t" - : "+w"(result), "=w"(tmp1) + : "+w"(result), "=&w"(tmp1) : "w"(temp), "w"(idx), "w"(r) : /* No clobbers */); return result; @@ -19701,7 +19222,7 @@ vtbx1_p8 (poly8x8_t r, poly8x8_t tab, uint8x8_t idx) "cmhs %0.8b, %3.8b, %0.8b\n\t" "tbl %1.8b, {%2.16b}, %3.8b\n\t" "bsl %0.8b, %4.8b, %1.8b\n\t" - : "+w"(result), "=w"(tmp1) + : "+w"(result), "=&w"(tmp1) : "w"(temp), "w"(idx), "w"(r) : /* No clobbers */); return result; @@ -19756,7 +19277,7 @@ vtbx3_s8 (int8x8_t r, int8x8x3_t tab, int8x8_t idx) "cmhs %0.8b, %3.8b, %0.8b\n\t" "tbl %1.8b, {v16.16b - v17.16b}, %3.8b\n\t" "bsl %0.8b, %4.8b, %1.8b\n\t" - : "+w"(result), "=w"(tmp1) + : "+w"(result), "=&w"(tmp1) : "Q"(temp), "w"(idx), "w"(r) : "v16", "v17", "memory"); return result; @@ -19775,7 +19296,7 @@ vtbx3_u8 (uint8x8_t r, uint8x8x3_t tab, uint8x8_t idx) "cmhs %0.8b, %3.8b, %0.8b\n\t" "tbl %1.8b, {v16.16b - v17.16b}, %3.8b\n\t" "bsl %0.8b, %4.8b, %1.8b\n\t" - : "+w"(result), "=w"(tmp1) + : "+w"(result), "=&w"(tmp1) : "Q"(temp), "w"(idx), "w"(r) : "v16", "v17", "memory"); return result; @@ -19794,7 +19315,7 @@ vtbx3_p8 (poly8x8_t r, poly8x8x3_t tab, uint8x8_t idx) "cmhs %0.8b, %3.8b, %0.8b\n\t" "tbl %1.8b, {v16.16b - v17.16b}, %3.8b\n\t" "bsl %0.8b, %4.8b, %1.8b\n\t" - : "+w"(result), "=w"(tmp1) + : "+w"(result), "=&w"(tmp1) : "Q"(temp), "w"(idx), "w"(r) : "v16", "v17", "memory"); return result; @@ -20030,28 +19551,28 @@ vcge_s64 (int64x1_t __a, int64x1_t __b) __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) vcge_u8 (uint8x8_t __a, uint8x8_t __b) { - return (uint8x8_t) __builtin_aarch64_cmhsv8qi ((int8x8_t) __a, + return (uint8x8_t) __builtin_aarch64_cmgeuv8qi ((int8x8_t) __a, (int8x8_t) __b); } __extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) vcge_u16 (uint16x4_t __a, uint16x4_t __b) { - return (uint16x4_t) __builtin_aarch64_cmhsv4hi ((int16x4_t) __a, + return (uint16x4_t) __builtin_aarch64_cmgeuv4hi ((int16x4_t) __a, (int16x4_t) __b); } __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) vcge_u32 (uint32x2_t __a, uint32x2_t __b) { - return (uint32x2_t) __builtin_aarch64_cmhsv2si ((int32x2_t) __a, + return (uint32x2_t) __builtin_aarch64_cmgeuv2si ((int32x2_t) __a, (int32x2_t) __b); } __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) vcge_u64 (uint64x1_t __a, uint64x1_t __b) { - return (uint64x1_t) __builtin_aarch64_cmhsdi ((int64x1_t) __a, + return (uint64x1_t) __builtin_aarch64_cmgeudi ((int64x1_t) __a, (int64x1_t) __b); } @@ -20082,28 +19603,28 @@ vcgeq_s64 (int64x2_t __a, int64x2_t __b) __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) vcgeq_u8 (uint8x16_t __a, uint8x16_t __b) { - return (uint8x16_t) __builtin_aarch64_cmhsv16qi ((int8x16_t) __a, + return (uint8x16_t) __builtin_aarch64_cmgeuv16qi ((int8x16_t) __a, (int8x16_t) __b); } __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) vcgeq_u16 (uint16x8_t __a, uint16x8_t __b) { - return (uint16x8_t) __builtin_aarch64_cmhsv8hi ((int16x8_t) __a, + return (uint16x8_t) __builtin_aarch64_cmgeuv8hi ((int16x8_t) __a, (int16x8_t) __b); } __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) vcgeq_u32 (uint32x4_t __a, uint32x4_t __b) { - return (uint32x4_t) __builtin_aarch64_cmhsv4si ((int32x4_t) __a, + return (uint32x4_t) __builtin_aarch64_cmgeuv4si ((int32x4_t) __a, (int32x4_t) __b); } __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) vcgeq_u64 (uint64x2_t __a, uint64x2_t __b) { - return (uint64x2_t) __builtin_aarch64_cmhsv2di ((int64x2_t) __a, + return (uint64x2_t) __builtin_aarch64_cmgeuv2di ((int64x2_t) __a, (int64x2_t) __b); } @@ -20116,7 +19637,7 @@ vcged_s64 (int64x1_t __a, int64x1_t __b) __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) vcged_u64 (uint64x1_t __a, uint64x1_t __b) { - return (uint64x1_t) __builtin_aarch64_cmhsdi ((int64x1_t) __a, + return (uint64x1_t) __builtin_aarch64_cmgeudi ((int64x1_t) __a, (int64x1_t) __b); } @@ -20155,28 +19676,28 @@ vcgt_s64 (int64x1_t __a, int64x1_t __b) __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) vcgt_u8 (uint8x8_t __a, uint8x8_t __b) { - return (uint8x8_t) __builtin_aarch64_cmhiv8qi ((int8x8_t) __a, + return (uint8x8_t) __builtin_aarch64_cmgtuv8qi ((int8x8_t) __a, (int8x8_t) __b); } __extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) vcgt_u16 (uint16x4_t __a, uint16x4_t __b) { - return (uint16x4_t) __builtin_aarch64_cmhiv4hi ((int16x4_t) __a, + return (uint16x4_t) __builtin_aarch64_cmgtuv4hi ((int16x4_t) __a, (int16x4_t) __b); } __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) vcgt_u32 (uint32x2_t __a, uint32x2_t __b) { - return (uint32x2_t) __builtin_aarch64_cmhiv2si ((int32x2_t) __a, + return (uint32x2_t) __builtin_aarch64_cmgtuv2si ((int32x2_t) __a, (int32x2_t) __b); } __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) vcgt_u64 (uint64x1_t __a, uint64x1_t __b) { - return (uint64x1_t) __builtin_aarch64_cmhidi ((int64x1_t) __a, + return (uint64x1_t) __builtin_aarch64_cmgtudi ((int64x1_t) __a, (int64x1_t) __b); } @@ -20207,28 +19728,28 @@ vcgtq_s64 (int64x2_t __a, int64x2_t __b) __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) vcgtq_u8 (uint8x16_t __a, uint8x16_t __b) { - return (uint8x16_t) __builtin_aarch64_cmhiv16qi ((int8x16_t) __a, + return (uint8x16_t) __builtin_aarch64_cmgtuv16qi ((int8x16_t) __a, (int8x16_t) __b); } __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) vcgtq_u16 (uint16x8_t __a, uint16x8_t __b) { - return (uint16x8_t) __builtin_aarch64_cmhiv8hi ((int16x8_t) __a, + return (uint16x8_t) __builtin_aarch64_cmgtuv8hi ((int16x8_t) __a, (int16x8_t) __b); } __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) vcgtq_u32 (uint32x4_t __a, uint32x4_t __b) { - return (uint32x4_t) __builtin_aarch64_cmhiv4si ((int32x4_t) __a, + return (uint32x4_t) __builtin_aarch64_cmgtuv4si ((int32x4_t) __a, (int32x4_t) __b); } __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) vcgtq_u64 (uint64x2_t __a, uint64x2_t __b) { - return (uint64x2_t) __builtin_aarch64_cmhiv2di ((int64x2_t) __a, + return (uint64x2_t) __builtin_aarch64_cmgtuv2di ((int64x2_t) __a, (int64x2_t) __b); } @@ -20241,7 +19762,7 @@ vcgtd_s64 (int64x1_t __a, int64x1_t __b) __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) vcgtd_u64 (uint64x1_t __a, uint64x1_t __b) { - return (uint64x1_t) __builtin_aarch64_cmhidi ((int64x1_t) __a, + return (uint64x1_t) __builtin_aarch64_cmgtudi ((int64x1_t) __a, (int64x1_t) __b); } @@ -20280,28 +19801,28 @@ vcle_s64 (int64x1_t __a, int64x1_t __b) __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) vcle_u8 (uint8x8_t __a, uint8x8_t __b) { - return (uint8x8_t) __builtin_aarch64_cmhsv8qi ((int8x8_t) __b, + return (uint8x8_t) __builtin_aarch64_cmgeuv8qi ((int8x8_t) __b, (int8x8_t) __a); } __extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) vcle_u16 (uint16x4_t __a, uint16x4_t __b) { - return (uint16x4_t) __builtin_aarch64_cmhsv4hi ((int16x4_t) __b, + return (uint16x4_t) __builtin_aarch64_cmgeuv4hi ((int16x4_t) __b, (int16x4_t) __a); } __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) vcle_u32 (uint32x2_t __a, uint32x2_t __b) { - return (uint32x2_t) __builtin_aarch64_cmhsv2si ((int32x2_t) __b, + return (uint32x2_t) __builtin_aarch64_cmgeuv2si ((int32x2_t) __b, (int32x2_t) __a); } __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) vcle_u64 (uint64x1_t __a, uint64x1_t __b) { - return (uint64x1_t) __builtin_aarch64_cmhsdi ((int64x1_t) __b, + return (uint64x1_t) __builtin_aarch64_cmgeudi ((int64x1_t) __b, (int64x1_t) __a); } @@ -20332,28 +19853,28 @@ vcleq_s64 (int64x2_t __a, int64x2_t __b) __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) vcleq_u8 (uint8x16_t __a, uint8x16_t __b) { - return (uint8x16_t) __builtin_aarch64_cmhsv16qi ((int8x16_t) __b, + return (uint8x16_t) __builtin_aarch64_cmgeuv16qi ((int8x16_t) __b, (int8x16_t) __a); } __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) vcleq_u16 (uint16x8_t __a, uint16x8_t __b) { - return (uint16x8_t) __builtin_aarch64_cmhsv8hi ((int16x8_t) __b, + return (uint16x8_t) __builtin_aarch64_cmgeuv8hi ((int16x8_t) __b, (int16x8_t) __a); } __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) vcleq_u32 (uint32x4_t __a, uint32x4_t __b) { - return (uint32x4_t) __builtin_aarch64_cmhsv4si ((int32x4_t) __b, + return (uint32x4_t) __builtin_aarch64_cmgeuv4si ((int32x4_t) __b, (int32x4_t) __a); } __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) vcleq_u64 (uint64x2_t __a, uint64x2_t __b) { - return (uint64x2_t) __builtin_aarch64_cmhsv2di ((int64x2_t) __b, + return (uint64x2_t) __builtin_aarch64_cmgeuv2di ((int64x2_t) __b, (int64x2_t) __a); } @@ -20398,28 +19919,28 @@ vclt_s64 (int64x1_t __a, int64x1_t __b) __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) vclt_u8 (uint8x8_t __a, uint8x8_t __b) { - return (uint8x8_t) __builtin_aarch64_cmhiv8qi ((int8x8_t) __b, + return (uint8x8_t) __builtin_aarch64_cmgtuv8qi ((int8x8_t) __b, (int8x8_t) __a); } __extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) vclt_u16 (uint16x4_t __a, uint16x4_t __b) { - return (uint16x4_t) __builtin_aarch64_cmhiv4hi ((int16x4_t) __b, + return (uint16x4_t) __builtin_aarch64_cmgtuv4hi ((int16x4_t) __b, (int16x4_t) __a); } __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) vclt_u32 (uint32x2_t __a, uint32x2_t __b) { - return (uint32x2_t) __builtin_aarch64_cmhiv2si ((int32x2_t) __b, + return (uint32x2_t) __builtin_aarch64_cmgtuv2si ((int32x2_t) __b, (int32x2_t) __a); } __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) vclt_u64 (uint64x1_t __a, uint64x1_t __b) { - return (uint64x1_t) __builtin_aarch64_cmhidi ((int64x1_t) __b, + return (uint64x1_t) __builtin_aarch64_cmgtudi ((int64x1_t) __b, (int64x1_t) __a); } @@ -20450,28 +19971,28 @@ vcltq_s64 (int64x2_t __a, int64x2_t __b) __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) vcltq_u8 (uint8x16_t __a, uint8x16_t __b) { - return (uint8x16_t) __builtin_aarch64_cmhiv16qi ((int8x16_t) __b, + return (uint8x16_t) __builtin_aarch64_cmgtuv16qi ((int8x16_t) __b, (int8x16_t) __a); } __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) vcltq_u16 (uint16x8_t __a, uint16x8_t __b) { - return (uint16x8_t) __builtin_aarch64_cmhiv8hi ((int16x8_t) __b, + return (uint16x8_t) __builtin_aarch64_cmgtuv8hi ((int16x8_t) __b, (int16x8_t) __a); } __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) vcltq_u32 (uint32x4_t __a, uint32x4_t __b) { - return (uint32x4_t) __builtin_aarch64_cmhiv4si ((int32x4_t) __b, + return (uint32x4_t) __builtin_aarch64_cmgtuv4si ((int32x4_t) __b, (int32x4_t) __a); } __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) vcltq_u64 (uint64x2_t __a, uint64x2_t __b) { - return (uint64x2_t) __builtin_aarch64_cmhiv2di ((int64x2_t) __b, + return (uint64x2_t) __builtin_aarch64_cmgtuv2di ((int64x2_t) __b, (int64x2_t) __a); } @@ -20537,6 +20058,165 @@ vdupd_lane_u64 (uint64x2_t a, int const b) return (uint64x1_t) __builtin_aarch64_dup_lanedi ((int64x2_t) a, b); } +/* vld1 */ + +__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) +vld1_f32 (const float32_t *a) +{ + return __builtin_aarch64_ld1v2sf ((const __builtin_aarch64_simd_sf *) a); +} + +__extension__ static __inline float64x1_t __attribute__ ((__always_inline__)) +vld1_f64 (const float64_t *a) +{ + return *a; +} + +__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) +vld1_p8 (const poly8_t *a) +{ + return (poly8x8_t) + __builtin_aarch64_ld1v8qi ((const __builtin_aarch64_simd_qi *) a); +} + +__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__)) +vld1_p16 (const poly16_t *a) +{ + return (poly16x4_t) + __builtin_aarch64_ld1v4hi ((const __builtin_aarch64_simd_hi *) a); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +vld1_s8 (const int8_t *a) +{ + return __builtin_aarch64_ld1v8qi ((const __builtin_aarch64_simd_qi *) a); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vld1_s16 (const int16_t *a) +{ + return __builtin_aarch64_ld1v4hi ((const __builtin_aarch64_simd_hi *) a); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vld1_s32 (const int32_t *a) +{ + return __builtin_aarch64_ld1v2si ((const __builtin_aarch64_simd_si *) a); +} + +__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) +vld1_s64 (const int64_t *a) +{ + return *a; +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +vld1_u8 (const uint8_t *a) +{ + return (uint8x8_t) + __builtin_aarch64_ld1v8qi ((const __builtin_aarch64_simd_qi *) a); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vld1_u16 (const uint16_t *a) +{ + return (uint16x4_t) + __builtin_aarch64_ld1v4hi ((const __builtin_aarch64_simd_hi *) a); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +vld1_u32 (const uint32_t *a) +{ + return (uint32x2_t) + __builtin_aarch64_ld1v2si ((const __builtin_aarch64_simd_si *) a); +} + +__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) +vld1_u64 (const uint64_t *a) +{ + return *a; +} + +/* vld1q */ + +__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) +vld1q_f32 (const float32_t *a) +{ + return __builtin_aarch64_ld1v4sf ((const __builtin_aarch64_simd_sf *) a); +} + +__extension__ static __inline float64x2_t __attribute__ ((__always_inline__)) +vld1q_f64 (const float64_t *a) +{ + return __builtin_aarch64_ld1v2df ((const __builtin_aarch64_simd_df *) a); +} + +__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__)) +vld1q_p8 (const poly8_t *a) +{ + return (poly8x16_t) + __builtin_aarch64_ld1v16qi ((const __builtin_aarch64_simd_qi *) a); +} + +__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__)) +vld1q_p16 (const poly16_t *a) +{ + return (poly16x8_t) + __builtin_aarch64_ld1v8hi ((const __builtin_aarch64_simd_hi *) a); +} + +__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) +vld1q_s8 (const int8_t *a) +{ + return __builtin_aarch64_ld1v16qi ((const __builtin_aarch64_simd_qi *) a); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vld1q_s16 (const int16_t *a) +{ + return __builtin_aarch64_ld1v8hi ((const __builtin_aarch64_simd_hi *) a); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vld1q_s32 (const int32_t *a) +{ + return __builtin_aarch64_ld1v4si ((const __builtin_aarch64_simd_si *) a); +} + +__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) +vld1q_s64 (const int64_t *a) +{ + return __builtin_aarch64_ld1v2di ((const __builtin_aarch64_simd_di *) a); +} + +__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) +vld1q_u8 (const uint8_t *a) +{ + return (uint8x16_t) + __builtin_aarch64_ld1v16qi ((const __builtin_aarch64_simd_qi *) a); +} + +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vld1q_u16 (const uint16_t *a) +{ + return (uint16x8_t) + __builtin_aarch64_ld1v8hi ((const __builtin_aarch64_simd_hi *) a); +} + +__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +vld1q_u32 (const uint32_t *a) +{ + return (uint32x4_t) + __builtin_aarch64_ld1v4si ((const __builtin_aarch64_simd_si *) a); +} + +__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) +vld1q_u64 (const uint64_t *a) +{ + return (uint64x2_t) + __builtin_aarch64_ld1v2di ((const __builtin_aarch64_simd_di *) a); +} + /* vldn */ __extension__ static __inline int64x1x2_t __attribute__ ((__always_inline__)) @@ -24307,6 +23987,165 @@ vsrid_n_u64 (uint64x1_t __a, uint64x1_t __b, const int __c) return (uint64x1_t) __builtin_aarch64_usri_ndi (__a, __b, __c); } +/* vst1 */ + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst1_f32 (float32_t *a, float32x2_t b) +{ + __builtin_aarch64_st1v2sf ((__builtin_aarch64_simd_sf *) a, b); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst1_f64 (float64_t *a, float64x1_t b) +{ + *a = b; +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst1_p8 (poly8_t *a, poly8x8_t b) +{ + __builtin_aarch64_st1v8qi ((__builtin_aarch64_simd_qi *) a, + (int8x8_t) b); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst1_p16 (poly16_t *a, poly16x4_t b) +{ + __builtin_aarch64_st1v4hi ((__builtin_aarch64_simd_hi *) a, + (int16x4_t) b); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst1_s8 (int8_t *a, int8x8_t b) +{ + __builtin_aarch64_st1v8qi ((__builtin_aarch64_simd_qi *) a, b); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst1_s16 (int16_t *a, int16x4_t b) +{ + __builtin_aarch64_st1v4hi ((__builtin_aarch64_simd_hi *) a, b); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst1_s32 (int32_t *a, int32x2_t b) +{ + __builtin_aarch64_st1v2si ((__builtin_aarch64_simd_si *) a, b); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst1_s64 (int64_t *a, int64x1_t b) +{ + *a = b; +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst1_u8 (uint8_t *a, uint8x8_t b) +{ + __builtin_aarch64_st1v8qi ((__builtin_aarch64_simd_qi *) a, + (int8x8_t) b); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst1_u16 (uint16_t *a, uint16x4_t b) +{ + __builtin_aarch64_st1v4hi ((__builtin_aarch64_simd_hi *) a, + (int16x4_t) b); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst1_u32 (uint32_t *a, uint32x2_t b) +{ + __builtin_aarch64_st1v2si ((__builtin_aarch64_simd_si *) a, + (int32x2_t) b); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst1_u64 (uint64_t *a, uint64x1_t b) +{ + *a = b; +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst1q_f32 (float32_t *a, float32x4_t b) +{ + __builtin_aarch64_st1v4sf ((__builtin_aarch64_simd_sf *) a, b); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst1q_f64 (float64_t *a, float64x2_t b) +{ + __builtin_aarch64_st1v2df ((__builtin_aarch64_simd_df *) a, b); +} + +/* vst1q */ + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst1q_p8 (poly8_t *a, poly8x16_t b) +{ + __builtin_aarch64_st1v16qi ((__builtin_aarch64_simd_qi *) a, + (int8x16_t) b); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst1q_p16 (poly16_t *a, poly16x8_t b) +{ + __builtin_aarch64_st1v8hi ((__builtin_aarch64_simd_hi *) a, + (int16x8_t) b); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst1q_s8 (int8_t *a, int8x16_t b) +{ + __builtin_aarch64_st1v16qi ((__builtin_aarch64_simd_qi *) a, b); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst1q_s16 (int16_t *a, int16x8_t b) +{ + __builtin_aarch64_st1v8hi ((__builtin_aarch64_simd_hi *) a, b); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst1q_s32 (int32_t *a, int32x4_t b) +{ + __builtin_aarch64_st1v4si ((__builtin_aarch64_simd_si *) a, b); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst1q_s64 (int64_t *a, int64x2_t b) +{ + __builtin_aarch64_st1v2di ((__builtin_aarch64_simd_di *) a, b); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst1q_u8 (uint8_t *a, uint8x16_t b) +{ + __builtin_aarch64_st1v16qi ((__builtin_aarch64_simd_qi *) a, + (int8x16_t) b); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst1q_u16 (uint16_t *a, uint16x8_t b) +{ + __builtin_aarch64_st1v8hi ((__builtin_aarch64_simd_hi *) a, + (int16x8_t) b); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst1q_u32 (uint32_t *a, uint32x4_t b) +{ + __builtin_aarch64_st1v4si ((__builtin_aarch64_simd_si *) a, + (int32x4_t) b); +} + +__extension__ static __inline void __attribute__ ((__always_inline__)) +vst1q_u64 (uint64_t *a, uint64x2_t b) +{ + __builtin_aarch64_st1v2di ((__builtin_aarch64_simd_di *) a, + (int64x2_t) b); +} + /* vstn */ __extension__ static __inline void diff --git a/gcc/config/aarch64/atomics.md b/gcc/config/aarch64/atomics.md index e576166c900d5..fe09dea1d01b3 100644 --- a/gcc/config/aarch64/atomics.md +++ b/gcc/config/aarch64/atomics.md @@ -119,7 +119,7 @@ [(set (match_operand:ALLI 0 "aarch64_sync_memory_operand" "+Q") (unspec_volatile:ALLI [(atomic_op:ALLI (match_dup 0) - (match_operand:ALLI 1 "" "rn")) + (match_operand:ALLI 1 "" "r")) (match_operand:SI 2 "const_int_operand")] ;; model UNSPECV_ATOMIC_OP)) (clobber (reg:CC CC_REGNUM)) @@ -141,7 +141,7 @@ (unspec_volatile:ALLI [(not:ALLI (and:ALLI (match_dup 0) - (match_operand:ALLI 1 "aarch64_logical_operand" "rn"))) + (match_operand:ALLI 1 "aarch64_logical_operand" "r"))) (match_operand:SI 2 "const_int_operand")] ;; model UNSPECV_ATOMIC_OP)) (clobber (reg:CC CC_REGNUM)) @@ -164,7 +164,7 @@ (set (match_dup 1) (unspec_volatile:ALLI [(atomic_op:ALLI (match_dup 1) - (match_operand:ALLI 2 "" "rn")) + (match_operand:ALLI 2 "" "r")) (match_operand:SI 3 "const_int_operand")] ;; model UNSPECV_ATOMIC_OP)) (clobber (reg:CC CC_REGNUM)) @@ -188,7 +188,7 @@ (unspec_volatile:ALLI [(not:ALLI (and:ALLI (match_dup 1) - (match_operand:ALLI 2 "aarch64_logical_operand" "rn"))) + (match_operand:ALLI 2 "aarch64_logical_operand" "r"))) (match_operand:SI 3 "const_int_operand")] ;; model UNSPECV_ATOMIC_OP)) (clobber (reg:CC CC_REGNUM)) @@ -209,7 +209,7 @@ [(set (match_operand:ALLI 0 "register_operand" "=&r") (atomic_op:ALLI (match_operand:ALLI 1 "aarch64_sync_memory_operand" "+Q") - (match_operand:ALLI 2 "" "rn"))) + (match_operand:ALLI 2 "" "r"))) (set (match_dup 1) (unspec_volatile:ALLI [(match_dup 1) (match_dup 2) @@ -233,7 +233,7 @@ (not:ALLI (and:ALLI (match_operand:ALLI 1 "aarch64_sync_memory_operand" "+Q") - (match_operand:ALLI 2 "aarch64_logical_operand" "rn")))) + (match_operand:ALLI 2 "aarch64_logical_operand" "r")))) (set (match_dup 1) (unspec_volatile:ALLI [(match_dup 1) (match_dup 2) diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index ce81ac5ce875d..f283850fab278 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -83,6 +83,9 @@ ;; Vector Float modes. (define_mode_iterator VDQF [V2SF V4SF V2DF]) +;; All Float modes. +(define_mode_iterator VALLF [V2SF V4SF V2DF SF DF]) + ;; Vector Float modes with 2 elements. (define_mode_iterator V2F [V2SF V2DF]) @@ -213,13 +216,6 @@ UNSPEC_URSHL ; Used in aarch64-simd.md. UNSPEC_SQRSHL ; Used in aarch64-simd.md. UNSPEC_UQRSHL ; Used in aarch64-simd.md. - UNSPEC_CMEQ ; Used in aarch64-simd.md. - UNSPEC_CMLE ; Used in aarch64-simd.md. - UNSPEC_CMLT ; Used in aarch64-simd.md. - UNSPEC_CMGE ; Used in aarch64-simd.md. - UNSPEC_CMGT ; Used in aarch64-simd.md. - UNSPEC_CMHS ; Used in aarch64-simd.md. - UNSPEC_CMHI ; Used in aarch64-simd.md. UNSPEC_SSLI ; Used in aarch64-simd.md. UNSPEC_USLI ; Used in aarch64-simd.md. UNSPEC_SSRI ; Used in aarch64-simd.md. @@ -227,7 +223,6 @@ UNSPEC_SSHLL ; Used in aarch64-simd.md. UNSPEC_USHLL ; Used in aarch64-simd.md. UNSPEC_ADDP ; Used in aarch64-simd.md. - UNSPEC_CMTST ; Used in aarch64-simd.md. UNSPEC_FMAX ; Used in aarch64-simd.md. UNSPEC_FMIN ; Used in aarch64-simd.md. UNSPEC_BSL ; Used in aarch64-simd.md. @@ -251,6 +246,7 @@ ;; For scalar usage of vector/FP registers (define_mode_attr v [(QI "b") (HI "h") (SI "s") (DI "d") + (SF "s") (DF "d") (V8QI "") (V16QI "") (V4HI "") (V8HI "") (V2SI "") (V4SI "") @@ -288,6 +284,9 @@ ;; Attribute to describe constants acceptable in logical operations (define_mode_attr lconst [(SI "K") (DI "L")]) +;; Attribute to describe constants acceptable in atomic logical operations +(define_mode_attr lconst_atomic [(QI "K") (HI "K") (SI "K") (DI "L")]) + ;; Map a mode to a specific constraint character. (define_mode_attr cmode [(QI "q") (HI "h") (SI "s") (DI "d")]) @@ -305,7 +304,8 @@ (V4SF ".4s") (V2DF ".2d") (DI "") (SI "") (HI "") (QI "") - (TI "")]) + (TI "") (SF "") + (DF "")]) ;; Register suffix narrowed modes for VQN. (define_mode_attr Vmntype [(V8HI ".8b") (V4SI ".4h") @@ -444,7 +444,8 @@ (V2SI "V2SI") (V4SI "V4SI") (DI "DI") (V2DI "V2DI") (V2SF "V2SI") (V4SF "V4SI") - (V2DF "V2DI")]) + (V2DF "V2DI") (DF "DI") + (SF "SI")]) ;; Lower case mode of results of comparison operations. (define_mode_attr v_cmp_result [(V8QI "v8qi") (V16QI "v16qi") @@ -452,7 +453,8 @@ (V2SI "v2si") (V4SI "v4si") (DI "di") (V2DI "v2di") (V2SF "v2si") (V4SF "v4si") - (V2DF "v2di")]) + (V2DF "v2di") (DF "di") + (SF "si")]) ;; Vm for lane instructions is restricted to FP_LO_REGS. (define_mode_attr vwx [(V4HI "x") (V8HI "x") (HI "x") @@ -543,6 +545,12 @@ ;; Code iterator for signed variants of vector saturating binary ops. (define_code_iterator SBINQOPS [ss_plus ss_minus]) +;; Comparison operators for CM. +(define_code_iterator COMPARISONS [lt le eq ge gt]) + +;; Unsigned comparison operators. +(define_code_iterator UCOMPARISONS [ltu leu geu gtu]) + ;; ------------------------------------------------------------------- ;; Code Attributes ;; ------------------------------------------------------------------- @@ -571,7 +579,28 @@ (eq "eq") (ne "ne") (lt "lt") - (ge "ge")]) + (ge "ge") + (le "le") + (gt "gt") + (ltu "ltu") + (leu "leu") + (geu "geu") + (gtu "gtu")]) + +;; For comparison operators we use the FCM* and CM* instructions. +;; As there are no CMLE or CMLT instructions which act on 3 vector +;; operands, we must use CMGE or CMGT and swap the order of the +;; source operands. + +(define_code_attr n_optab [(lt "gt") (le "ge") (eq "eq") (ge "ge") (gt "gt") + (ltu "hi") (leu "hs") (geu "hs") (gtu "hi")]) +(define_code_attr cmp_1 [(lt "2") (le "2") (eq "1") (ge "1") (gt "1") + (ltu "2") (leu "2") (geu "1") (gtu "1")]) +(define_code_attr cmp_2 [(lt "1") (le "1") (eq "2") (ge "2") (gt "2") + (ltu "1") (leu "1") (geu "2") (gtu "2")]) + +(define_code_attr CMP [(lt "LT") (le "LE") (eq "EQ") (ge "GE") (gt "GT") + (ltu "LTU") (leu "LEU") (geu "GEU") (gtu "GTU")]) ;; Optab prefix for sign/zero-extending operations (define_code_attr su_optab [(sign_extend "") (zero_extend "u") @@ -680,11 +709,6 @@ UNSPEC_SQSHRN UNSPEC_UQSHRN UNSPEC_SQRSHRN UNSPEC_UQRSHRN]) -(define_int_iterator VCMP_S [UNSPEC_CMEQ UNSPEC_CMGE UNSPEC_CMGT - UNSPEC_CMLE UNSPEC_CMLT]) - -(define_int_iterator VCMP_U [UNSPEC_CMHS UNSPEC_CMHI UNSPEC_CMTST]) - (define_int_iterator PERMUTE [UNSPEC_ZIP1 UNSPEC_ZIP2 UNSPEC_TRN1 UNSPEC_TRN2 UNSPEC_UZP1 UNSPEC_UZP2]) @@ -768,12 +792,6 @@ (UNSPEC_RADDHN2 "add") (UNSPEC_RSUBHN2 "sub")]) -(define_int_attr cmp [(UNSPEC_CMGE "ge") (UNSPEC_CMGT "gt") - (UNSPEC_CMLE "le") (UNSPEC_CMLT "lt") - (UNSPEC_CMEQ "eq") - (UNSPEC_CMHS "hs") (UNSPEC_CMHI "hi") - (UNSPEC_CMTST "tst")]) - (define_int_attr offsetlr [(UNSPEC_SSLI "1") (UNSPEC_USLI "1") (UNSPEC_SSRI "0") (UNSPEC_USRI "0")]) diff --git a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicates.md index 8f80b20281137..8514e8f8fbdda 100644 --- a/gcc/config/aarch64/predicates.md +++ b/gcc/config/aarch64/predicates.md @@ -31,6 +31,11 @@ (ior (match_operand 0 "register_operand") (match_test "op == const0_rtx")))) +(define_predicate "aarch64_reg_or_fp_zero" + (and (match_code "reg,subreg,const_double") + (ior (match_operand 0 "register_operand") + (match_test "aarch64_float_const_zero_rtx_p (op)")))) + (define_predicate "aarch64_reg_zero_or_m1_or_1" (and (match_code "reg,subreg,const_int") (ior (match_operand 0 "register_operand") diff --git a/gcc/config/alpha/alpha.c b/gcc/config/alpha/alpha.c index 6926055f2068a..2874b8454a9b6 100644 --- a/gcc/config/alpha/alpha.c +++ b/gcc/config/alpha/alpha.c @@ -1372,8 +1372,7 @@ get_aligned_mem (rtx ref, rtx *paligned_mem, rtx *pbitnum) gcc_assert (MEM_P (ref)); - if (reload_in_progress - && ! memory_address_p (GET_MODE (ref), XEXP (ref, 0))) + if (reload_in_progress) { base = find_replacement (&XEXP (ref, 0)); gcc_assert (memory_address_p (GET_MODE (ref), base)); @@ -1418,11 +1417,9 @@ get_unaligned_address (rtx ref) gcc_assert (MEM_P (ref)); - if (reload_in_progress - && ! memory_address_p (GET_MODE (ref), XEXP (ref, 0))) + if (reload_in_progress) { base = find_replacement (&XEXP (ref, 0)); - gcc_assert (memory_address_p (GET_MODE (ref), base)); } else @@ -2659,6 +2656,7 @@ alpha_emit_conditional_move (rtx cmp, enum machine_mode mode) cmp_mode = cmp_mode == DImode ? DFmode : DImode; op0 = gen_lowpart (cmp_mode, tem); op1 = CONST0_RTX (cmp_mode); + cmp = gen_rtx_fmt_ee (code, VOIDmode, op0, op1); local_fast_math = 1; } @@ -2700,12 +2698,12 @@ alpha_emit_conditional_move (rtx cmp, enum machine_mode mode) break; case GE: case GT: case GEU: case GTU: - /* These must be swapped. */ - if (op1 != CONST0_RTX (cmp_mode)) - { - code = swap_condition (code); - tem = op0, op0 = op1, op1 = tem; - } + /* These normally need swapping, but for integer zero we have + special patterns that recognize swapped operands. */ + if (cmp_mode == DImode && op1 == const0_rtx) + break; + code = swap_condition (code); + tem = op0, op0 = op1, op1 = tem; break; default: @@ -3067,12 +3065,9 @@ alpha_emit_xfloating_compare (enum rtx_code *pcode, rtx op0, rtx op1) operands[1] = op1; out = gen_reg_rtx (DImode); - /* What's actually returned is -1,0,1, not a proper boolean value, - so use an EXPR_LIST as with a generic libcall instead of a - comparison type expression. */ - note = gen_rtx_EXPR_LIST (VOIDmode, op1, NULL_RTX); - note = gen_rtx_EXPR_LIST (VOIDmode, op0, note); - note = gen_rtx_EXPR_LIST (VOIDmode, func, note); + /* What's actually returned is -1,0,1, not a proper boolean value. */ + note = gen_rtx_fmt_ee (cmp_code, VOIDmode, op0, op1); + note = gen_rtx_UNSPEC (DImode, gen_rtvec (1, note), UNSPEC_XFLT_COMPARE); alpha_emit_xfloating_libcall (func, out, operands, 2, note); return out; @@ -8660,6 +8655,11 @@ alpha_handle_trap_shadows (void) } break; + case BARRIER: + /* __builtin_unreachable can expand to no code at all, + leaving (barrier) RTXes in the instruction stream. */ + goto close_shadow_notrapb; + case JUMP_INSN: case CALL_INSN: case CODE_LABEL: @@ -8675,6 +8675,7 @@ alpha_handle_trap_shadows (void) n = emit_insn_before (gen_trapb (), i); PUT_MODE (n, TImode); PUT_MODE (i, TImode); + close_shadow_notrapb: trap_pending = 0; shadow.used.i = 0; shadow.used.fp = 0; diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md index 439752780a0b6..a3b185c4cb6fa 100644 --- a/gcc/config/alpha/alpha.md +++ b/gcc/config/alpha/alpha.md @@ -23,6 +23,7 @@ ;; Uses of UNSPEC in this file: (define_c_enum "unspec" [ + UNSPEC_XFLT_COMPARE UNSPEC_ARG_HOME UNSPEC_LDGP1 UNSPEC_INSXH @@ -4495,8 +4496,8 @@ (define_insn_and_split "reload_out_aligned" [(set (match_operand:I12MODE 0 "memory_operand" "=m") (match_operand:I12MODE 1 "register_operand" "r")) - (clobber (match_operand:SI 2 "register_operand" "=r")) - (clobber (match_operand:SI 3 "register_operand" "=r"))] + (clobber (match_operand:SI 2 "register_operand" "=&r")) + (clobber (match_operand:SI 3 "register_operand" "=&r"))] "!TARGET_BWX && (reload_in_progress || reload_completed)" "#" "!TARGET_BWX && reload_completed" @@ -5983,16 +5984,38 @@ [(set_attr "type" "jsr") (set_attr "length" "*,*,8")]) -(define_insn_and_split "call_value_osf_tlsgd" +(define_int_iterator TLS_CALL + [UNSPEC_TLSGD_CALL + UNSPEC_TLSLDM_CALL]) + +(define_int_attr tls + [(UNSPEC_TLSGD_CALL "tlsgd") + (UNSPEC_TLSLDM_CALL "tlsldm")]) + +(define_insn "call_value_osf_" [(set (match_operand 0) (call (mem:DI (match_operand:DI 1 "symbolic_operand")) (const_int 0))) - (unspec [(match_operand:DI 2 "const_int_operand")] UNSPEC_TLSGD_CALL) + (unspec [(match_operand:DI 2 "const_int_operand")] TLS_CALL) (use (reg:DI 29)) (clobber (reg:DI 26))] "HAVE_AS_TLS" - "#" - "&& reload_completed" + "ldq $27,%1($29)\t\t!literal!%2\;jsr $26,($27),%1\t\t!lituse_!%2\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*" + [(set_attr "type" "jsr") + (set_attr "length" "16")]) + +;; We must use peep2 instead of a split because we need accurate life +;; information for $gp. +(define_peephole2 + [(parallel + [(set (match_operand 0) + (call (mem:DI (match_operand:DI 1 "symbolic_operand")) + (const_int 0))) + (unspec [(match_operand:DI 2 "const_int_operand")] TLS_CALL) + (use (reg:DI 29)) + (clobber (reg:DI 26))])] + "HAVE_AS_TLS && reload_completed + && peep2_regno_dead_p (1, 29)" [(set (match_dup 3) (unspec:DI [(match_dup 5) (match_dup 1) @@ -6000,10 +6023,9 @@ (parallel [(set (match_dup 0) (call (mem:DI (match_dup 3)) (const_int 0))) - (set (match_dup 5) - (unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP1)) + (use (match_dup 5)) (use (match_dup 1)) - (use (unspec [(match_dup 2)] UNSPEC_TLSGD_CALL)) + (use (unspec [(match_dup 2)] TLS_CALL)) (clobber (reg:DI 26))]) (set (match_dup 5) (unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP2))] @@ -6011,19 +6033,18 @@ operands[3] = gen_rtx_REG (Pmode, 27); operands[4] = GEN_INT (alpha_next_sequence_number++); operands[5] = pic_offset_table_rtx; -} - [(set_attr "type" "multi")]) +}) -(define_insn_and_split "call_value_osf_tlsldm" - [(set (match_operand 0) - (call (mem:DI (match_operand:DI 1 "symbolic_operand")) - (const_int 0))) - (unspec [(match_operand:DI 2 "const_int_operand")] UNSPEC_TLSLDM_CALL) - (use (reg:DI 29)) - (clobber (reg:DI 26))] - "HAVE_AS_TLS" - "#" - "&& reload_completed" +(define_peephole2 + [(parallel + [(set (match_operand 0) + (call (mem:DI (match_operand:DI 1 "symbolic_operand")) + (const_int 0))) + (unspec [(match_operand:DI 2 "const_int_operand")] TLS_CALL) + (use (reg:DI 29)) + (clobber (reg:DI 26))])] + "HAVE_AS_TLS && reload_completed + && !peep2_regno_dead_p (1, 29)" [(set (match_dup 3) (unspec:DI [(match_dup 5) (match_dup 1) @@ -6034,7 +6055,7 @@ (set (match_dup 5) (unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP1)) (use (match_dup 1)) - (use (unspec [(match_dup 2)] UNSPEC_TLSLDM_CALL)) + (use (unspec [(match_dup 2)] TLS_CALL)) (clobber (reg:DI 26))]) (set (match_dup 5) (unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP2))] @@ -6042,8 +6063,7 @@ operands[3] = gen_rtx_REG (Pmode, 27); operands[4] = GEN_INT (alpha_next_sequence_number++); operands[5] = pic_offset_table_rtx; -} - [(set_attr "type" "multi")]) +}) (define_insn "*call_value_osf_1" [(set (match_operand 0) diff --git a/gcc/config/alpha/elf.h b/gcc/config/alpha/elf.h index ee44105f725e8..9ed2441da1ac7 100644 --- a/gcc/config/alpha/elf.h +++ b/gcc/config/alpha/elf.h @@ -126,6 +126,10 @@ do { \ "%{Ofast|ffast-math|funsafe-math-optimizations:crtfastmath.o%s} \ %{shared|pie:crtendS.o%s;:crtend.o%s} crtn.o%s" +/* This variable should be set to 'true' if the target ABI requires + unwinding tables even when exceptions are not used. */ +#define TARGET_UNWIND_TABLES_DEFAULT true + /* Select a format to encode pointers in exception handling data. CODE is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is true if the symbol may be affected by dynamic relocations. diff --git a/gcc/config/arm/arm-ldmstm.ml b/gcc/config/arm/arm-ldmstm.ml index 2bc9702bee2d5..0f637d3fe392a 100644 --- a/gcc/config/arm/arm-ldmstm.ml +++ b/gcc/config/arm/arm-ldmstm.ml @@ -67,10 +67,13 @@ let destreg nregs first op_type thumb = Printf.sprintf ("(match_operand:SI %d \"s_register_operand\" \"%s%s\")") (nregs + 1) (inout_constr op_type) (constr thumb) +let reg_predicate thumb = + if thumb then "low_register_operand" else "arm_hard_general_register_operand" + let write_ldm_set thumb nregs offset opnr first = let indent = " " in Printf.printf "%s" (if first then " [" else indent); - Printf.printf "(set (match_operand:SI %d \"arm_hard_register_operand\" \"\")\n" opnr; + Printf.printf "(set (match_operand:SI %d \"%s\" \"\")\n" opnr (reg_predicate thumb); Printf.printf "%s (mem:SI " indent; begin if offset != 0 then Printf.printf "(plus:SI " end; Printf.printf "%s" (destreg nregs first IN thumb); @@ -84,7 +87,7 @@ let write_stm_set thumb nregs offset opnr first = begin if offset != 0 then Printf.printf "(plus:SI " end; Printf.printf "%s" (destreg nregs first IN thumb); begin if offset != 0 then Printf.printf " (const_int %d))" offset end; - Printf.printf ")\n%s (match_operand:SI %d \"arm_hard_register_operand\" \"\"))" indent opnr + Printf.printf ")\n%s (match_operand:SI %d \"%s\" \"\"))" indent opnr (reg_predicate thumb) let write_ldm_peep_set extra_indent nregs opnr first = let indent = " " ^ extra_indent in diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h index ffa00c0f7b74c..685af30a4c56f 100644 --- a/gcc/config/arm/arm-protos.h +++ b/gcc/config/arm/arm-protos.h @@ -55,6 +55,7 @@ extern int arm_split_constant (RTX_CODE, enum machine_mode, rtx, extern int legitimate_pic_operand_p (rtx); extern rtx legitimize_pic_address (rtx, enum machine_mode, rtx); extern rtx legitimize_tls_address (rtx, rtx); +extern bool arm_legitimate_address_p (enum machine_mode, rtx, bool); extern int arm_legitimate_address_outer_p (enum machine_mode, rtx, RTX_CODE, int); extern int thumb_legitimate_offset_p (enum machine_mode, HOST_WIDE_INT); extern bool arm_legitimize_reload_address (rtx *, enum machine_mode, int, int, @@ -286,4 +287,6 @@ extern bool arm_autoinc_modes_ok_p (enum machine_mode, enum arm_auto_incmodes); extern void arm_emit_eabi_attribute (const char *, int, int); +extern bool arm_is_constant_pool_ref (rtx); + #endif /* ! GCC_ARM_PROTOS_H */ diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index ca367608c96c8..a699951a13201 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -82,7 +82,6 @@ static rtx arm_legitimize_address (rtx, rtx, enum machine_mode); static reg_class_t arm_preferred_reload_class (rtx, reg_class_t); static rtx thumb_legitimize_address (rtx, rtx, enum machine_mode); inline static int thumb1_index_register_rtx_p (rtx, int); -static bool arm_legitimate_address_p (enum machine_mode, rtx, bool); static int thumb_far_jump_used_p (void); static bool thumb_force_lr_save (void); static unsigned arm_size_return_regs (void); @@ -230,7 +229,6 @@ static tree arm_gimplify_va_arg_expr (tree, tree, gimple_seq *, gimple_seq *); static void arm_option_override (void); static unsigned HOST_WIDE_INT arm_shift_truncation_mask (enum machine_mode); static bool arm_cannot_copy_insn_p (rtx); -static bool arm_tls_symbol_p (rtx x); static int arm_issue_rate (void); static void arm_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED; static bool arm_output_addr_const_extra (FILE *, rtx); @@ -4459,7 +4457,9 @@ aapcs_vfp_allocate (CUMULATIVE_ARGS *pcum, enum machine_mode mode, if (((pcum->aapcs_vfp_regs_free >> regno) & mask) == mask) { pcum->aapcs_vfp_reg_alloc = mask << regno; - if (mode == BLKmode || (mode == TImode && !TARGET_NEON)) + if (mode == BLKmode + || (mode == TImode && ! TARGET_NEON) + || ! arm_hard_regno_mode_ok (FIRST_VFP_REGNUM + regno, mode)) { int i; int rcount = pcum->aapcs_vfp_rcount; @@ -5423,7 +5423,8 @@ require_pic_register (void) if (!crtl->uses_pic_offset_table) { gcc_assert (can_create_pseudo_p ()); - if (arm_pic_register != INVALID_REGNUM) + if (arm_pic_register != INVALID_REGNUM + && !(TARGET_THUMB1 && arm_pic_register > LAST_LO_REGNUM)) { if (!cfun->machine->pic_reg) cfun->machine->pic_reg = gen_rtx_REG (Pmode, arm_pic_register); @@ -5449,7 +5450,12 @@ require_pic_register (void) crtl->uses_pic_offset_table = 1; start_sequence (); - arm_load_pic_register (0UL); + if (TARGET_THUMB1 && arm_pic_register != INVALID_REGNUM + && arm_pic_register > LAST_LO_REGNUM) + emit_move_insn (cfun->machine->pic_reg, + gen_rtx_REG (Pmode, arm_pic_register)); + else + arm_load_pic_register (0UL); seq = get_insns (); end_sequence (); @@ -5707,6 +5713,14 @@ arm_load_pic_register (unsigned long saved_regs ATTRIBUTE_UNUSED) emit_insn (gen_movsi (pic_offset_table_rtx, pic_tmp)); emit_insn (gen_pic_add_dot_plus_four (pic_reg, pic_reg, labelno)); } + else if (arm_pic_register != INVALID_REGNUM + && arm_pic_register > LAST_LO_REGNUM + && REGNO (pic_reg) <= LAST_LO_REGNUM) + { + emit_insn (gen_pic_load_addr_unified (pic_reg, pic_rtx, labelno)); + emit_move_insn (gen_rtx_REG (Pmode, arm_pic_register), pic_reg); + emit_use (gen_rtx_REG (Pmode, arm_pic_register)); + } else emit_insn (gen_pic_load_addr_unified (pic_reg, pic_rtx, labelno)); } @@ -6571,6 +6585,32 @@ legitimize_tls_address (rtx x, rtx reg) rtx arm_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode) { + if (arm_tls_referenced_p (x)) + { + rtx addend = NULL; + + if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS) + { + addend = XEXP (XEXP (x, 0), 1); + x = XEXP (XEXP (x, 0), 0); + } + + if (GET_CODE (x) != SYMBOL_REF) + return x; + + gcc_assert (SYMBOL_REF_TLS_MODEL (x) != 0); + + x = legitimize_tls_address (x, NULL_RTX); + + if (addend) + { + x = gen_rtx_PLUS (SImode, x, addend); + orig_x = x; + } + else + return x; + } + if (!TARGET_ARM) { /* TODO: legitimize_address for Thumb2. */ @@ -6579,9 +6619,6 @@ arm_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode) return thumb_legitimize_address (x, orig_x, mode); } - if (arm_tls_symbol_p (x)) - return legitimize_tls_address (x, NULL_RTX); - if (GET_CODE (x) == PLUS) { rtx xop0 = XEXP (x, 0); @@ -6693,9 +6730,6 @@ arm_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode) rtx thumb_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode) { - if (arm_tls_symbol_p (x)) - return legitimize_tls_address (x, NULL_RTX); - if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)) && (INTVAL (XEXP (x, 1)) >= 32 * GET_MODE_SIZE (mode) @@ -6986,20 +7020,6 @@ thumb_legitimize_reload_address (rtx *x_p, /* Test for various thread-local symbols. */ -/* Return TRUE if X is a thread-local symbol. */ - -static bool -arm_tls_symbol_p (rtx x) -{ - if (! TARGET_HAVE_TLS) - return false; - - if (GET_CODE (x) != SYMBOL_REF) - return false; - - return SYMBOL_REF_TLS_MODEL (x) != 0; -} - /* Helper for arm_tls_referenced_p. */ static int @@ -7094,7 +7114,7 @@ static inline int thumb1_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer) { enum machine_mode mode = GET_MODE (x); - int total; + int total, words; switch (code) { @@ -7102,6 +7122,8 @@ thumb1_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer) case ASHIFTRT: case LSHIFTRT: case ROTATERT: + return (mode == SImode) ? COSTS_N_INSNS (1) : COSTS_N_INSNS (2); + case PLUS: case MINUS: case COMPARE: @@ -7125,7 +7147,10 @@ thumb1_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer) return COSTS_N_INSNS (1) + 16; case SET: - return (COSTS_N_INSNS (1) + /* A SET doesn't have a mode, so let's look at the SET_DEST to get + the mode. */ + words = ARM_NUM_INTS (GET_MODE_SIZE (GET_MODE (SET_DEST (x)))); + return (COSTS_N_INSNS (words) + 4 * ((MEM_P (SET_SRC (x))) + MEM_P (SET_DEST (x)))); @@ -7822,6 +7847,7 @@ static inline int thumb1_size_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer) { enum machine_mode mode = GET_MODE (x); + int words; switch (code) { @@ -7829,8 +7855,19 @@ thumb1_size_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer) case ASHIFTRT: case LSHIFTRT: case ROTATERT: + return (mode == SImode) ? COSTS_N_INSNS (1) : COSTS_N_INSNS (2); + case PLUS: case MINUS: + /* Thumb-1 needs two instructions to fulfill shiftadd/shiftsub0/shiftsub1 + defined by RTL expansion, especially for the expansion of + multiplication. */ + if ((GET_CODE (XEXP (x, 0)) == MULT + && power_of_two_operand (XEXP (XEXP (x,0),1), SImode)) + || (GET_CODE (XEXP (x, 1)) == MULT + && power_of_two_operand (XEXP (XEXP (x, 1), 1), SImode))) + return COSTS_N_INSNS (2); + /* On purpose fall through for normal RTX. */ case COMPARE: case NEG: case NOT: @@ -7847,7 +7884,10 @@ thumb1_size_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer) return COSTS_N_INSNS (1); case SET: - return (COSTS_N_INSNS (1) + /* A SET doesn't have a mode, so let's look at the SET_DEST to get + the mode. */ + words = ARM_NUM_INTS (GET_MODE_SIZE (GET_MODE (SET_DEST (x)))); + return (COSTS_N_INSNS (words) + 4 * ((MEM_P (SET_SRC (x))) + MEM_P (SET_DEST (x)))); @@ -10707,6 +10747,13 @@ load_multiple_sequence (rtx *operands, int nops, int *regs, int *saved_order, || (i != nops - 1 && unsorted_regs[i] == base_reg)) return 0; + /* Don't allow SP to be loaded unless it is also the base + register. It guarantees that SP is reset correctly when + an LDM instruction is interrupted. Otherwise, we might + end up with a corrupt stack. */ + if (unsorted_regs[i] == SP_REGNUM && base_reg != SP_REGNUM) + return 0; + unsorted_offsets[i] = INTVAL (offset); if (i == 0 || unsorted_offsets[i] < unsorted_offsets[order[0]]) order[0] = i; @@ -13290,7 +13337,7 @@ dump_minipool (rtx scan) fputc ('\n', dump_file); } - switch (mp->fix_size) + switch (GET_MODE_SIZE (mp->mode)) { #ifdef HAVE_consttable_1 case 1: @@ -15579,6 +15626,14 @@ output_ascii_pseudo_op (FILE *stream, const unsigned char *p, int len) fputs ("\"\n", stream); } +/* Whether a register is callee saved or not. This is necessary because high + registers are marked as caller saved when optimizing for size on Thumb-1 + targets despite being callee saved in order to avoid using them. */ +#define callee_saved_reg_p(reg) \ + (!call_used_regs[reg] \ + || (TARGET_THUMB1 && optimize_size \ + && reg >= FIRST_HI_REGNUM && reg <= LAST_HI_REGNUM)) + /* Compute the register save mask for registers 0 through 12 inclusive. This code is used by arm_compute_save_reg_mask. */ @@ -15639,7 +15694,7 @@ arm_compute_save_reg0_reg12_mask (void) /* In the normal case we only need to save those registers which are call saved and which are used by this function. */ for (reg = 0; reg <= 11; reg++) - if (df_regs_ever_live_p (reg) && ! call_used_regs[reg]) + if (df_regs_ever_live_p (reg) && callee_saved_reg_p (reg)) save_reg_mask |= (1 << reg); /* Handle the frame pointer as a special case. */ @@ -15793,7 +15848,7 @@ thumb1_compute_save_reg_mask (void) mask = 0; for (reg = 0; reg < 12; reg ++) - if (df_regs_ever_live_p (reg) && !call_used_regs[reg]) + if (df_regs_ever_live_p (reg) && callee_saved_reg_p (reg)) mask |= 1 << reg; if (flag_pic @@ -15826,7 +15881,7 @@ thumb1_compute_save_reg_mask (void) if (reg * UNITS_PER_WORD <= (unsigned) arm_size_return_regs ()) reg = LAST_LO_REGNUM; - if (! call_used_regs[reg]) + if (callee_saved_reg_p (reg)) mask |= 1 << reg; } @@ -17446,7 +17501,8 @@ arm_expand_prologue (void) } } - if (current_tune->prefer_ldrd_strd + if (TARGET_LDRD + && current_tune->prefer_ldrd_strd && !optimize_function_for_size_p (cfun)) { if (TARGET_THUMB2) @@ -17975,7 +18031,7 @@ arm_print_operand (FILE *stream, rtx x, int code) "wC12", "wC13", "wC14", "wC15" }; - fprintf (stream, wc_reg_names [INTVAL (x)]); + fputs (wc_reg_names [INTVAL (x)], stream); } return; @@ -21249,7 +21305,11 @@ arm_expand_neon_args (rtx target, int icode, int have_retval, type_mode); } - op[argc] = expand_normal (arg[argc]); + /* Use EXPAND_MEMORY for NEON_ARG_MEMORY to ensure a MEM_P + be returned. */ + op[argc] = expand_expr (arg[argc], NULL_RTX, VOIDmode, + (thisarg == NEON_ARG_MEMORY + ? EXPAND_MEMORY : EXPAND_NORMAL)); switch (thisarg) { @@ -21268,6 +21328,9 @@ arm_expand_neon_args (rtx target, int icode, int have_retval, break; case NEON_ARG_MEMORY: + /* Check if expand failed. */ + if (op[argc] == const0_rtx) + return 0; gcc_assert (MEM_P (op[argc])); PUT_MODE (op[argc], mode[argc]); /* ??? arm_neon.h uses the same built-in functions for signed @@ -23525,6 +23588,7 @@ arm_expand_epilogue_apcs_frame (bool really_return) num_regs = bit_count (saved_regs_mask); if ((offsets->outgoing_args != (1 + num_regs)) || cfun->calls_alloca) { + emit_insn (gen_blockage ()); /* Unwind the stack to just below the saved registers. */ emit_insn (gen_addsi3 (stack_pointer_rtx, hard_frame_pointer_rtx, @@ -23553,8 +23617,8 @@ arm_expand_epilogue_apcs_frame (bool really_return) if (crtl->calls_eh_return) emit_insn (gen_addsi3 (stack_pointer_rtx, - stack_pointer_rtx, - GEN_INT (ARM_EH_STACKADJ_REGNUM))); + stack_pointer_rtx, + gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM))); if (IS_STACKALIGN (func_type)) /* Restore the original stack pointer. Before prologue, the stack was @@ -23584,7 +23648,8 @@ arm_expand_epilogue (bool really_return) if (IS_NAKED (func_type) || (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN)) { - emit_jump_insn (simple_return_rtx); + if (really_return) + emit_jump_insn (simple_return_rtx); return; } @@ -23759,7 +23824,8 @@ arm_expand_epilogue (bool really_return) } else { - if (current_tune->prefer_ldrd_strd + if (TARGET_LDRD + && current_tune->prefer_ldrd_strd && !optimize_function_for_size_p (cfun)) { if (TARGET_THUMB2) @@ -24417,9 +24483,13 @@ arm_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED, fputs (":\n", file); if (flag_pic) { - /* Output ".word .LTHUNKn-7-.LTHUNKPCn". */ + /* Output ".word .LTHUNKn-[3,7]-.LTHUNKPCn". */ rtx tem = XEXP (DECL_RTL (function), 0); - tem = gen_rtx_PLUS (GET_MODE (tem), tem, GEN_INT (-7)); + /* For TARGET_THUMB1_ONLY the thunk is in Thumb mode, so the PC + pipeline offset is four rather than eight. Adjust the offset + accordingly. */ + tem = plus_constant (GET_MODE (tem), tem, + TARGET_THUMB1_ONLY ? -3 : -7); tem = gen_rtx_MINUS (GET_MODE (tem), tem, gen_rtx_SYMBOL_REF (Pmode, @@ -27403,4 +27473,13 @@ arm_validize_comparison (rtx *comparison, rtx * op1, rtx * op2) } +/* return TRUE if x is a reference to a value in a constant pool */ +extern bool +arm_is_constant_pool_ref (rtx x) +{ + return (MEM_P (x) + && GET_CODE (XEXP (x, 0)) == SYMBOL_REF + && CONSTANT_POOL_ADDRESS_P (XEXP (x, 0))); +} + #include "gt-arm.h" diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index 6d336e89ee952..d86eef7d7d281 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -63,8 +63,8 @@ extern char arm_arch_name[]; builtin_define_with_int_value ( \ "__ARM_SIZEOF_MINIMAL_ENUM", \ flag_short_enums ? 1 : 4); \ - builtin_define_with_int_value ( \ - "__ARM_SIZEOF_WCHAR_T", WCHAR_TYPE_SIZE); \ + builtin_define_type_sizeof ("__ARM_SIZEOF_WCHAR_T", \ + wchar_type_node); \ if (TARGET_ARM_ARCH_PROFILE) \ builtin_define_with_int_value ( \ "__ARM_ARCH_PROFILE", TARGET_ARM_ARCH_PROFILE); \ @@ -1166,7 +1166,9 @@ enum reg_class "IWMMXT_GR_REGS", \ "CC_REG", \ "VFPCC_REG", \ - "ALL_REGS", \ + "SFP_REG", \ + "AFP_REG", \ + "ALL_REGS" \ } /* Define which registers fit in which classes. @@ -1211,11 +1213,15 @@ enum reg_class VFPv2. In big-endian mode, modes greater than word size (i.e. DFmode) are stored in VFP registers in little-endian order. We can't describe that accurately to - GCC, so avoid taking subregs of such values. */ -#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ - (TARGET_VFP && TARGET_BIG_END \ - && (GET_MODE_SIZE (FROM) > UNITS_PER_WORD \ - || GET_MODE_SIZE (TO) > UNITS_PER_WORD) \ + GCC, so avoid taking subregs of such values. + The only exception is going from a 128-bit to a 64-bit type. In that case + the data layout happens to be consistent for big-endian, so we explicitly allow + that case. */ +#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ + (TARGET_VFP && TARGET_BIG_END \ + && !(GET_MODE_SIZE (FROM) == 16 && GET_MODE_SIZE (TO) == 8) \ + && (GET_MODE_SIZE (FROM) > UNITS_PER_WORD \ + || GET_MODE_SIZE (TO) > UNITS_PER_WORD) \ && reg_classes_intersect_p (VFP_REGS, (CLASS))) /* The class value for index registers, and the one for base regs. */ @@ -2076,9 +2082,10 @@ extern int making_const_table; ? reverse_condition_maybe_unordered (code) \ : reverse_condition (code)) -/* The arm5 clz instruction returns 32. */ -#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1) -#define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1) +#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ + ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE)) +#define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ + ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE)) #define CC_STATUS_INIT \ do { cfun->machine->thumb1_cc_insn = NULL_RTX; } while (0) @@ -2137,14 +2144,9 @@ extern int making_const_table; #undef ASM_OUTPUT_BEFORE_CASE_LABEL #define ASM_OUTPUT_BEFORE_CASE_LABEL(FILE, PREFIX, NUM, TABLE) /* Empty. */ -/* Make sure subsequent insns are aligned after a TBB. */ -#define ASM_OUTPUT_CASE_END(FILE, NUM, JUMPTABLE) \ - do \ - { \ - if (GET_MODE (PATTERN (JUMPTABLE)) == QImode) \ - ASM_OUTPUT_ALIGN (FILE, 1); \ - } \ - while (0) +#define LABEL_ALIGN_AFTER_BARRIER(LABEL) \ + (GET_CODE (PATTERN (prev_active_insn (LABEL))) == ADDR_DIFF_VEC \ + ? 1 : 0) #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \ do \ diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index f3c59f37c8596..64b56b2fe6857 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -92,9 +92,11 @@ ; This can be "a" for ARM, "t" for either of the Thumbs, "32" for ; TARGET_32BIT, "t1" or "t2" to specify a specific Thumb mode. "v6" ; for ARM or Thumb-2 with arm_arch6, and nov6 for ARM without -; arm_arch6. This attribute is used to compute attribute "enabled", -; use type "any" to enable an alternative in all cases. -(define_attr "arch" "any,a,t,32,t1,t2,v6,nov6,onlya8,neon_onlya8,nota8,neon_nota8,iwmmxt,iwmmxt2" +; arm_arch6. "v6t2" for Thumb-2 with arm_arch6. This attribute is +; used to compute attribute "enabled", use type "any" to enable an +; alternative in all cases. + +(define_attr "arch" "any,a,t,32,t1,t2,v6,nov6,v6t2,onlya8,neon_onlya8,nota8,neon_nota8,iwmmxt,iwmmxt2" (const_string "any")) (define_attr "arch_enabled" "no,yes" @@ -129,6 +131,10 @@ (match_test "TARGET_32BIT && !arm_arch6")) (const_string "yes") + (and (eq_attr "arch" "v6t2") + (match_test "TARGET_32BIT && arm_arch6 && arm_arch_thumb2")) + (const_string "yes") + (and (eq_attr "arch" "onlya8") (eq_attr "tune" "cortexa8")) (const_string "yes") @@ -4047,7 +4053,7 @@ (define_insn "unaligned_loadhis" [(set (match_operand:SI 0 "s_register_operand" "=l,r") (sign_extend:SI - (unspec:HI [(match_operand:HI 1 "memory_operand" "Uw,m")] + (unspec:HI [(match_operand:HI 1 "memory_operand" "Uw,Uh")] UNSPEC_UNALIGNED_LOAD)))] "unaligned_access && TARGET_32BIT" "ldr%(sh%)\t%0, %1\t@ unaligned" @@ -4655,7 +4661,7 @@ (define_insn "*arm_zero_extendhisi2_v6" [(set (match_operand:SI 0 "s_register_operand" "=r,r") - (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))] + (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,Uh")))] "TARGET_ARM && arm_arch6" "@ uxth%?\\t%0, %1 @@ -4748,7 +4754,7 @@ (define_insn "*arm_zero_extendqisi2_v6" [(set (match_operand:SI 0 "s_register_operand" "=r,r") - (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))] + (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,Uh")))] "TARGET_ARM && arm_arch6" "@ uxtb%(%)\\t%0, %1 @@ -4980,30 +4986,26 @@ (define_insn "*arm_extendhisi2" [(set (match_operand:SI 0 "s_register_operand" "=r,r") - (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))] + (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,Uh")))] "TARGET_ARM && arm_arch4 && !arm_arch6" "@ # ldr%(sh%)\\t%0, %1" [(set_attr "length" "8,4") (set_attr "type" "alu_shift,load_byte") - (set_attr "predicable" "yes") - (set_attr "pool_range" "*,256") - (set_attr "neg_pool_range" "*,244")] + (set_attr "predicable" "yes")] ) ;; ??? Check Thumb-2 pool range (define_insn "*arm_extendhisi2_v6" [(set (match_operand:SI 0 "s_register_operand" "=r,r") - (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))] + (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,Uh")))] "TARGET_32BIT && arm_arch6" "@ sxth%?\\t%0, %1 ldr%(sh%)\\t%0, %1" [(set_attr "type" "simple_alu_shift,load_byte") - (set_attr "predicable" "yes") - (set_attr "pool_range" "*,256") - (set_attr "neg_pool_range" "*,244")] + (set_attr "predicable" "yes")] ) (define_insn "*arm_extendhisi2addsi" @@ -5045,9 +5047,7 @@ "TARGET_ARM && arm_arch4" "ldr%(sb%)\\t%0, %1" [(set_attr "type" "load_byte") - (set_attr "predicable" "yes") - (set_attr "pool_range" "256") - (set_attr "neg_pool_range" "244")] + (set_attr "predicable" "yes")] ) (define_expand "extendqisi2" @@ -5087,9 +5087,7 @@ ldr%(sb%)\\t%0, %1" [(set_attr "length" "8,4") (set_attr "type" "alu_shift,load_byte") - (set_attr "predicable" "yes") - (set_attr "pool_range" "*,256") - (set_attr "neg_pool_range" "*,244")] + (set_attr "predicable" "yes")] ) (define_insn "*arm_extendqisi_v6" @@ -5101,9 +5099,7 @@ sxtb%?\\t%0, %1 ldr%(sb%)\\t%0, %1" [(set_attr "type" "simple_alu_shift,load_byte") - (set_attr "predicable" "yes") - (set_attr "pool_range" "*,256") - (set_attr "neg_pool_range" "*,244")] + (set_attr "predicable" "yes")] ) (define_insn "*arm_extendqisi2addsi" @@ -6292,8 +6288,8 @@ ;; Pattern to recognize insn generated default case above (define_insn "*movhi_insn_arch4" - [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r") - (match_operand:HI 1 "general_operand" "rI,K,r,mi"))] + [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m,r") + (match_operand:HI 1 "general_operand" "rI,K,n,r,mi"))] "TARGET_ARM && arm_arch4 && (register_operand (operands[0], HImode) @@ -6301,17 +6297,20 @@ "@ mov%?\\t%0, %1\\t%@ movhi mvn%?\\t%0, #%B1\\t%@ movhi + movw%?\\t%0, %L1\\t%@ movhi str%(h%)\\t%1, %0\\t%@ movhi ldr%(h%)\\t%0, %1\\t%@ movhi" [(set_attr "predicable" "yes") - (set_attr "insn" "mov,mvn,*,*") - (set_attr "pool_range" "*,*,*,256") - (set_attr "neg_pool_range" "*,*,*,244") + (set_attr "insn" "mov,mvn,mov,*,*") + (set_attr "pool_range" "*,*,*,*,256") + (set_attr "neg_pool_range" "*,*,*,*,244") + (set_attr "arch" "*,*,v6t2,*,*") (set_attr_alternative "type" [(if_then_else (match_operand 1 "const_int_operand" "") (const_string "simple_alu_imm" ) (const_string "*")) (const_string "simple_alu_imm") + (const_string "simple_alu_imm") (const_string "store1") (const_string "load1")])] ) @@ -7630,12 +7629,13 @@ (define_insn "*arm_cmpdi_unsigned" [(set (reg:CC_CZ CC_REGNUM) - (compare:CC_CZ (match_operand:DI 0 "s_register_operand" "r") - (match_operand:DI 1 "arm_di_operand" "rDi")))] + (compare:CC_CZ (match_operand:DI 0 "s_register_operand" "r,r") + (match_operand:DI 1 "arm_di_operand" "rDi,rDi")))] "TARGET_32BIT" "cmp\\t%R0, %R1\;it eq\;cmpeq\\t%Q0, %Q1" [(set_attr "conds" "set") - (set_attr "length" "8")] + (set_attr "arch" "a,t2") + (set_attr "length" "8,10")] ) (define_insn "*arm_cmpdi_zero" @@ -11036,7 +11036,7 @@ [(set (match_operand:SI 1 "s_register_operand" "+rk") (plus:SI (match_dup 1) (match_operand:SI 2 "const_int_operand" "I"))) - (set (match_operand:DF 3 "arm_hard_register_operand" "") + (set (match_operand:DF 3 "vfp_hard_register_operand" "") (mem:DF (match_dup 1)))])] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" "* @@ -11096,7 +11096,7 @@ (define_insn "consttable_1" [(unspec_volatile [(match_operand 0 "" "")] VUNSPEC_POOL_1)] - "TARGET_THUMB1" + "TARGET_EITHER" "* making_const_table = TRUE; assemble_integer (operands[0], 1, BITS_PER_WORD, 1); @@ -11108,14 +11108,23 @@ (define_insn "consttable_2" [(unspec_volatile [(match_operand 0 "" "")] VUNSPEC_POOL_2)] - "TARGET_THUMB1" + "TARGET_EITHER" "* - making_const_table = TRUE; - gcc_assert (GET_MODE_CLASS (GET_MODE (operands[0])) != MODE_FLOAT); - assemble_integer (operands[0], 2, BITS_PER_WORD, 1); - assemble_zeros (2); - return \"\"; - " + { + rtx x = operands[0]; + making_const_table = TRUE; + switch (GET_MODE_CLASS (GET_MODE (x))) + { + case MODE_FLOAT: + arm_emit_fp16_const (x); + break; + default: + assemble_integer (operands[0], 2, BITS_PER_WORD, 1); + assemble_zeros (2); + break; + } + return \"\"; + }" [(set_attr "length" "4")] ) @@ -11129,15 +11138,12 @@ switch (GET_MODE_CLASS (GET_MODE (x))) { case MODE_FLOAT: - if (GET_MODE (x) == HFmode) - arm_emit_fp16_const (x); - else - { - REAL_VALUE_TYPE r; - REAL_VALUE_FROM_CONST_DOUBLE (r, x); - assemble_real (r, GET_MODE (x), BITS_PER_WORD); - } - break; + { + REAL_VALUE_TYPE r; + REAL_VALUE_FROM_CONST_DOUBLE (r, x); + assemble_real (r, GET_MODE (x), BITS_PER_WORD); + break; + } default: /* XXX: Sometimes gcc does something really dumb and ends up with a HIGH in a constant pool entry, usually because it's trying to @@ -11270,7 +11276,9 @@ (match_operand:SI 1 "" "") (match_operand:SI 2 "" ""))] "TARGET_32BIT && arm_arch5e" - "pld\\t%a0") + "pld\\t%a0" + [(set_attr "type" "load1")] +) ;; General predication pattern diff --git a/gcc/config/arm/constraints.md b/gcc/config/arm/constraints.md index 775f8afd7f308..639439165c05f 100644 --- a/gcc/config/arm/constraints.md +++ b/gcc/config/arm/constraints.md @@ -36,7 +36,7 @@ ;; in Thumb-2 state: Pj, PJ, Ps, Pt, Pu, Pv, Pw, Px, Py ;; The following memory constraints have been used: -;; in ARM/Thumb-2 state: Q, Ut, Uv, Uy, Un, Um, Us +;; in ARM/Thumb-2 state: Q, Uh, Ut, Uv, Uy, Un, Um, Us ;; in ARM state: Uq ;; in Thumb state: Uu, Uw @@ -310,6 +310,12 @@ An address valid for loading/storing register exclusive" (match_operand 0 "mem_noofs_operand")) +(define_memory_constraint "Uh" + "@internal + An address suitable for byte and half-word loads which does not point inside a constant pool" + (and (match_code "mem") + (match_test "arm_legitimate_address_p (GET_MODE (op), XEXP (op, 0), false) && !arm_is_constant_pool_ref (op)"))) + (define_memory_constraint "Ut" "@internal In ARM/Thumb-2 state an address valid for loading/storing opaque structure @@ -356,7 +362,8 @@ (and (match_code "mem") (match_test "TARGET_ARM && arm_legitimate_address_outer_p (GET_MODE (op), XEXP (op, 0), - SIGN_EXTEND, 0)"))) + SIGN_EXTEND, 0) + && !arm_is_constant_pool_ref (op)"))) (define_memory_constraint "Q" "@internal diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md index 252f18b40a8a1..df82c061fab2b 100644 --- a/gcc/config/arm/iterators.md +++ b/gcc/config/arm/iterators.md @@ -314,6 +314,12 @@ (V2SF "V2SI") (V4SF "V4SI") (DI "DI") (V2DI "V2DI")]) +(define_mode_attr v_cmp_result [(V8QI "v8qi") (V16QI "v16qi") + (V4HI "v4hi") (V8HI "v8hi") + (V2SI "v2si") (V4SI "v4si") + (DI "di") (V2DI "v2di") + (V2SF "v2si") (V4SF "v4si")]) + ;; Get element type from double-width mode, for operations where we ;; don't care about signedness. (define_mode_attr V_if_elem [(V8QI "i8") (V16QI "i8") @@ -487,6 +493,10 @@ (UNSPEC_VRINTA "no") (UNSPEC_VRINTM "no") (UNSPEC_VRINTR "yes") (UNSPEC_VRINTX "yes")]) +(define_int_attr vrint_conds [(UNSPEC_VRINTZ "nocond") (UNSPEC_VRINTP "unconditional") + (UNSPEC_VRINTA "unconditional") (UNSPEC_VRINTM "unconditional") + (UNSPEC_VRINTR "nocond") (UNSPEC_VRINTX "nocond")]) + (define_int_attr nvrint_variant [(UNSPEC_NVRINTZ "z") (UNSPEC_NVRINTP "p") (UNSPEC_NVRINTA "a") (UNSPEC_NVRINTM "m") (UNSPEC_NVRINTX "x") (UNSPEC_NVRINTN "n")]) diff --git a/gcc/config/arm/ldmstm.md b/gcc/config/arm/ldmstm.md index 8ebdfc8176107..ed206b00c3358 100644 --- a/gcc/config/arm/ldmstm.md +++ b/gcc/config/arm/ldmstm.md @@ -23,15 +23,15 @@ (define_insn "*ldm4_ia" [(match_parallel 0 "load_multiple_operation" - [(set (match_operand:SI 1 "arm_hard_register_operand" "") + [(set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (match_operand:SI 5 "s_register_operand" "rk"))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 4)))) - (set (match_operand:SI 3 "arm_hard_register_operand" "") + (set (match_operand:SI 3 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 8)))) - (set (match_operand:SI 4 "arm_hard_register_operand" "") + (set (match_operand:SI 4 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 12))))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" @@ -41,15 +41,15 @@ (define_insn "*thumb_ldm4_ia" [(match_parallel 0 "load_multiple_operation" - [(set (match_operand:SI 1 "arm_hard_register_operand" "") + [(set (match_operand:SI 1 "low_register_operand" "") (mem:SI (match_operand:SI 5 "s_register_operand" "l"))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "low_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 4)))) - (set (match_operand:SI 3 "arm_hard_register_operand" "") + (set (match_operand:SI 3 "low_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 8)))) - (set (match_operand:SI 4 "arm_hard_register_operand" "") + (set (match_operand:SI 4 "low_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 12))))])] "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4" @@ -60,15 +60,15 @@ [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 5 "s_register_operand" "+&rk") (plus:SI (match_dup 5) (const_int 16))) - (set (match_operand:SI 1 "arm_hard_register_operand" "") + (set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (match_dup 5))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 4)))) - (set (match_operand:SI 3 "arm_hard_register_operand" "") + (set (match_operand:SI 3 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 8)))) - (set (match_operand:SI 4 "arm_hard_register_operand" "") + (set (match_operand:SI 4 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 12))))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 5" @@ -80,15 +80,15 @@ [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 5 "s_register_operand" "+&l") (plus:SI (match_dup 5) (const_int 16))) - (set (match_operand:SI 1 "arm_hard_register_operand" "") + (set (match_operand:SI 1 "low_register_operand" "") (mem:SI (match_dup 5))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "low_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 4)))) - (set (match_operand:SI 3 "arm_hard_register_operand" "") + (set (match_operand:SI 3 "low_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 8)))) - (set (match_operand:SI 4 "arm_hard_register_operand" "") + (set (match_operand:SI 4 "low_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 12))))])] "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 5" @@ -98,13 +98,13 @@ (define_insn "*stm4_ia" [(match_parallel 0 "store_multiple_operation" [(set (mem:SI (match_operand:SI 5 "s_register_operand" "rk")) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int 4))) - (match_operand:SI 2 "arm_hard_register_operand" "")) + (match_operand:SI 2 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int 8))) - (match_operand:SI 3 "arm_hard_register_operand" "")) + (match_operand:SI 3 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int 12))) - (match_operand:SI 4 "arm_hard_register_operand" ""))])] + (match_operand:SI 4 "arm_hard_general_register_operand" ""))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" "stm%(ia%)\t%5, {%1, %2, %3, %4}" [(set_attr "type" "store4") @@ -115,13 +115,13 @@ [(set (match_operand:SI 5 "s_register_operand" "+&rk") (plus:SI (match_dup 5) (const_int 16))) (set (mem:SI (match_dup 5)) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int 4))) - (match_operand:SI 2 "arm_hard_register_operand" "")) + (match_operand:SI 2 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int 8))) - (match_operand:SI 3 "arm_hard_register_operand" "")) + (match_operand:SI 3 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int 12))) - (match_operand:SI 4 "arm_hard_register_operand" ""))])] + (match_operand:SI 4 "arm_hard_general_register_operand" ""))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 5" "stm%(ia%)\t%5!, {%1, %2, %3, %4}" [(set_attr "type" "store4") @@ -132,29 +132,29 @@ [(set (match_operand:SI 5 "s_register_operand" "+&l") (plus:SI (match_dup 5) (const_int 16))) (set (mem:SI (match_dup 5)) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "low_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int 4))) - (match_operand:SI 2 "arm_hard_register_operand" "")) + (match_operand:SI 2 "low_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int 8))) - (match_operand:SI 3 "arm_hard_register_operand" "")) + (match_operand:SI 3 "low_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int 12))) - (match_operand:SI 4 "arm_hard_register_operand" ""))])] + (match_operand:SI 4 "low_register_operand" ""))])] "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 5" "stm%(ia%)\t%5!, {%1, %2, %3, %4}" [(set_attr "type" "store4")]) (define_insn "*ldm4_ib" [(match_parallel 0 "load_multiple_operation" - [(set (match_operand:SI 1 "arm_hard_register_operand" "") + [(set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk") (const_int 4)))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 8)))) - (set (match_operand:SI 3 "arm_hard_register_operand" "") + (set (match_operand:SI 3 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 12)))) - (set (match_operand:SI 4 "arm_hard_register_operand" "") + (set (match_operand:SI 4 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 16))))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 4" @@ -166,16 +166,16 @@ [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 5 "s_register_operand" "+&rk") (plus:SI (match_dup 5) (const_int 16))) - (set (match_operand:SI 1 "arm_hard_register_operand" "") + (set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 4)))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 8)))) - (set (match_operand:SI 3 "arm_hard_register_operand" "") + (set (match_operand:SI 3 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 12)))) - (set (match_operand:SI 4 "arm_hard_register_operand" "") + (set (match_operand:SI 4 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 16))))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 5" @@ -186,13 +186,13 @@ (define_insn "*stm4_ib" [(match_parallel 0 "store_multiple_operation" [(set (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk") (const_int 4))) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int 8))) - (match_operand:SI 2 "arm_hard_register_operand" "")) + (match_operand:SI 2 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int 12))) - (match_operand:SI 3 "arm_hard_register_operand" "")) + (match_operand:SI 3 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int 16))) - (match_operand:SI 4 "arm_hard_register_operand" ""))])] + (match_operand:SI 4 "arm_hard_general_register_operand" ""))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 4" "stm%(ib%)\t%5, {%1, %2, %3, %4}" [(set_attr "type" "store4") @@ -203,13 +203,13 @@ [(set (match_operand:SI 5 "s_register_operand" "+&rk") (plus:SI (match_dup 5) (const_int 16))) (set (mem:SI (plus:SI (match_dup 5) (const_int 4))) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int 8))) - (match_operand:SI 2 "arm_hard_register_operand" "")) + (match_operand:SI 2 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int 12))) - (match_operand:SI 3 "arm_hard_register_operand" "")) + (match_operand:SI 3 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int 16))) - (match_operand:SI 4 "arm_hard_register_operand" ""))])] + (match_operand:SI 4 "arm_hard_general_register_operand" ""))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 5" "stm%(ib%)\t%5!, {%1, %2, %3, %4}" [(set_attr "type" "store4") @@ -217,16 +217,16 @@ (define_insn "*ldm4_da" [(match_parallel 0 "load_multiple_operation" - [(set (match_operand:SI 1 "arm_hard_register_operand" "") + [(set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk") (const_int -12)))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int -8)))) - (set (match_operand:SI 3 "arm_hard_register_operand" "") + (set (match_operand:SI 3 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int -4)))) - (set (match_operand:SI 4 "arm_hard_register_operand" "") + (set (match_operand:SI 4 "arm_hard_general_register_operand" "") (mem:SI (match_dup 5)))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 4" "ldm%(da%)\t%5, {%1, %2, %3, %4}" @@ -237,16 +237,16 @@ [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 5 "s_register_operand" "+&rk") (plus:SI (match_dup 5) (const_int -16))) - (set (match_operand:SI 1 "arm_hard_register_operand" "") + (set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int -12)))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int -8)))) - (set (match_operand:SI 3 "arm_hard_register_operand" "") + (set (match_operand:SI 3 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int -4)))) - (set (match_operand:SI 4 "arm_hard_register_operand" "") + (set (match_operand:SI 4 "arm_hard_general_register_operand" "") (mem:SI (match_dup 5)))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 5" "ldm%(da%)\t%5!, {%1, %2, %3, %4}" @@ -256,13 +256,13 @@ (define_insn "*stm4_da" [(match_parallel 0 "store_multiple_operation" [(set (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk") (const_int -12))) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int -8))) - (match_operand:SI 2 "arm_hard_register_operand" "")) + (match_operand:SI 2 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int -4))) - (match_operand:SI 3 "arm_hard_register_operand" "")) + (match_operand:SI 3 "arm_hard_general_register_operand" "")) (set (mem:SI (match_dup 5)) - (match_operand:SI 4 "arm_hard_register_operand" ""))])] + (match_operand:SI 4 "arm_hard_general_register_operand" ""))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 4" "stm%(da%)\t%5, {%1, %2, %3, %4}" [(set_attr "type" "store4") @@ -273,13 +273,13 @@ [(set (match_operand:SI 5 "s_register_operand" "+&rk") (plus:SI (match_dup 5) (const_int -16))) (set (mem:SI (plus:SI (match_dup 5) (const_int -12))) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int -8))) - (match_operand:SI 2 "arm_hard_register_operand" "")) + (match_operand:SI 2 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int -4))) - (match_operand:SI 3 "arm_hard_register_operand" "")) + (match_operand:SI 3 "arm_hard_general_register_operand" "")) (set (mem:SI (match_dup 5)) - (match_operand:SI 4 "arm_hard_register_operand" ""))])] + (match_operand:SI 4 "arm_hard_general_register_operand" ""))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 5" "stm%(da%)\t%5!, {%1, %2, %3, %4}" [(set_attr "type" "store4") @@ -287,16 +287,16 @@ (define_insn "*ldm4_db" [(match_parallel 0 "load_multiple_operation" - [(set (match_operand:SI 1 "arm_hard_register_operand" "") + [(set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk") (const_int -16)))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int -12)))) - (set (match_operand:SI 3 "arm_hard_register_operand" "") + (set (match_operand:SI 3 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int -8)))) - (set (match_operand:SI 4 "arm_hard_register_operand" "") + (set (match_operand:SI 4 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int -4))))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" @@ -308,16 +308,16 @@ [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 5 "s_register_operand" "+&rk") (plus:SI (match_dup 5) (const_int -16))) - (set (match_operand:SI 1 "arm_hard_register_operand" "") + (set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int -16)))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int -12)))) - (set (match_operand:SI 3 "arm_hard_register_operand" "") + (set (match_operand:SI 3 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int -8)))) - (set (match_operand:SI 4 "arm_hard_register_operand" "") + (set (match_operand:SI 4 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int -4))))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 5" @@ -328,13 +328,13 @@ (define_insn "*stm4_db" [(match_parallel 0 "store_multiple_operation" [(set (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk") (const_int -16))) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int -12))) - (match_operand:SI 2 "arm_hard_register_operand" "")) + (match_operand:SI 2 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int -8))) - (match_operand:SI 3 "arm_hard_register_operand" "")) + (match_operand:SI 3 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int -4))) - (match_operand:SI 4 "arm_hard_register_operand" ""))])] + (match_operand:SI 4 "arm_hard_general_register_operand" ""))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" "stm%(db%)\t%5, {%1, %2, %3, %4}" [(set_attr "type" "store4") @@ -345,13 +345,13 @@ [(set (match_operand:SI 5 "s_register_operand" "+&rk") (plus:SI (match_dup 5) (const_int -16))) (set (mem:SI (plus:SI (match_dup 5) (const_int -16))) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int -12))) - (match_operand:SI 2 "arm_hard_register_operand" "")) + (match_operand:SI 2 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int -8))) - (match_operand:SI 3 "arm_hard_register_operand" "")) + (match_operand:SI 3 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int -4))) - (match_operand:SI 4 "arm_hard_register_operand" ""))])] + (match_operand:SI 4 "arm_hard_general_register_operand" ""))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 5" "stm%(db%)\t%5!, {%1, %2, %3, %4}" [(set_attr "type" "store4") @@ -466,12 +466,12 @@ (define_insn "*ldm3_ia" [(match_parallel 0 "load_multiple_operation" - [(set (match_operand:SI 1 "arm_hard_register_operand" "") + [(set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (match_operand:SI 4 "s_register_operand" "rk"))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int 4)))) - (set (match_operand:SI 3 "arm_hard_register_operand" "") + (set (match_operand:SI 3 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int 8))))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" @@ -481,12 +481,12 @@ (define_insn "*thumb_ldm3_ia" [(match_parallel 0 "load_multiple_operation" - [(set (match_operand:SI 1 "arm_hard_register_operand" "") + [(set (match_operand:SI 1 "low_register_operand" "") (mem:SI (match_operand:SI 4 "s_register_operand" "l"))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "low_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int 4)))) - (set (match_operand:SI 3 "arm_hard_register_operand" "") + (set (match_operand:SI 3 "low_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int 8))))])] "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 3" @@ -497,12 +497,12 @@ [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 4 "s_register_operand" "+&rk") (plus:SI (match_dup 4) (const_int 12))) - (set (match_operand:SI 1 "arm_hard_register_operand" "") + (set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (match_dup 4))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int 4)))) - (set (match_operand:SI 3 "arm_hard_register_operand" "") + (set (match_operand:SI 3 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int 8))))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" @@ -514,12 +514,12 @@ [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 4 "s_register_operand" "+&l") (plus:SI (match_dup 4) (const_int 12))) - (set (match_operand:SI 1 "arm_hard_register_operand" "") + (set (match_operand:SI 1 "low_register_operand" "") (mem:SI (match_dup 4))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "low_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int 4)))) - (set (match_operand:SI 3 "arm_hard_register_operand" "") + (set (match_operand:SI 3 "low_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int 8))))])] "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4" @@ -529,11 +529,11 @@ (define_insn "*stm3_ia" [(match_parallel 0 "store_multiple_operation" [(set (mem:SI (match_operand:SI 4 "s_register_operand" "rk")) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int 4))) - (match_operand:SI 2 "arm_hard_register_operand" "")) + (match_operand:SI 2 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int 8))) - (match_operand:SI 3 "arm_hard_register_operand" ""))])] + (match_operand:SI 3 "arm_hard_general_register_operand" ""))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" "stm%(ia%)\t%4, {%1, %2, %3}" [(set_attr "type" "store3") @@ -544,11 +544,11 @@ [(set (match_operand:SI 4 "s_register_operand" "+&rk") (plus:SI (match_dup 4) (const_int 12))) (set (mem:SI (match_dup 4)) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int 4))) - (match_operand:SI 2 "arm_hard_register_operand" "")) + (match_operand:SI 2 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int 8))) - (match_operand:SI 3 "arm_hard_register_operand" ""))])] + (match_operand:SI 3 "arm_hard_general_register_operand" ""))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" "stm%(ia%)\t%4!, {%1, %2, %3}" [(set_attr "type" "store3") @@ -559,24 +559,24 @@ [(set (match_operand:SI 4 "s_register_operand" "+&l") (plus:SI (match_dup 4) (const_int 12))) (set (mem:SI (match_dup 4)) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "low_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int 4))) - (match_operand:SI 2 "arm_hard_register_operand" "")) + (match_operand:SI 2 "low_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int 8))) - (match_operand:SI 3 "arm_hard_register_operand" ""))])] + (match_operand:SI 3 "low_register_operand" ""))])] "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4" "stm%(ia%)\t%4!, {%1, %2, %3}" [(set_attr "type" "store3")]) (define_insn "*ldm3_ib" [(match_parallel 0 "load_multiple_operation" - [(set (match_operand:SI 1 "arm_hard_register_operand" "") + [(set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk") (const_int 4)))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int 8)))) - (set (match_operand:SI 3 "arm_hard_register_operand" "") + (set (match_operand:SI 3 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int 12))))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 3" @@ -588,13 +588,13 @@ [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 4 "s_register_operand" "+&rk") (plus:SI (match_dup 4) (const_int 12))) - (set (match_operand:SI 1 "arm_hard_register_operand" "") + (set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int 4)))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int 8)))) - (set (match_operand:SI 3 "arm_hard_register_operand" "") + (set (match_operand:SI 3 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int 12))))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 4" @@ -605,11 +605,11 @@ (define_insn "*stm3_ib" [(match_parallel 0 "store_multiple_operation" [(set (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk") (const_int 4))) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int 8))) - (match_operand:SI 2 "arm_hard_register_operand" "")) + (match_operand:SI 2 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int 12))) - (match_operand:SI 3 "arm_hard_register_operand" ""))])] + (match_operand:SI 3 "arm_hard_general_register_operand" ""))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 3" "stm%(ib%)\t%4, {%1, %2, %3}" [(set_attr "type" "store3") @@ -620,11 +620,11 @@ [(set (match_operand:SI 4 "s_register_operand" "+&rk") (plus:SI (match_dup 4) (const_int 12))) (set (mem:SI (plus:SI (match_dup 4) (const_int 4))) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int 8))) - (match_operand:SI 2 "arm_hard_register_operand" "")) + (match_operand:SI 2 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int 12))) - (match_operand:SI 3 "arm_hard_register_operand" ""))])] + (match_operand:SI 3 "arm_hard_general_register_operand" ""))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 4" "stm%(ib%)\t%4!, {%1, %2, %3}" [(set_attr "type" "store3") @@ -632,13 +632,13 @@ (define_insn "*ldm3_da" [(match_parallel 0 "load_multiple_operation" - [(set (match_operand:SI 1 "arm_hard_register_operand" "") + [(set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk") (const_int -8)))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int -4)))) - (set (match_operand:SI 3 "arm_hard_register_operand" "") + (set (match_operand:SI 3 "arm_hard_general_register_operand" "") (mem:SI (match_dup 4)))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 3" "ldm%(da%)\t%4, {%1, %2, %3}" @@ -649,13 +649,13 @@ [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 4 "s_register_operand" "+&rk") (plus:SI (match_dup 4) (const_int -12))) - (set (match_operand:SI 1 "arm_hard_register_operand" "") + (set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int -8)))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int -4)))) - (set (match_operand:SI 3 "arm_hard_register_operand" "") + (set (match_operand:SI 3 "arm_hard_general_register_operand" "") (mem:SI (match_dup 4)))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 4" "ldm%(da%)\t%4!, {%1, %2, %3}" @@ -665,11 +665,11 @@ (define_insn "*stm3_da" [(match_parallel 0 "store_multiple_operation" [(set (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk") (const_int -8))) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int -4))) - (match_operand:SI 2 "arm_hard_register_operand" "")) + (match_operand:SI 2 "arm_hard_general_register_operand" "")) (set (mem:SI (match_dup 4)) - (match_operand:SI 3 "arm_hard_register_operand" ""))])] + (match_operand:SI 3 "arm_hard_general_register_operand" ""))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 3" "stm%(da%)\t%4, {%1, %2, %3}" [(set_attr "type" "store3") @@ -680,11 +680,11 @@ [(set (match_operand:SI 4 "s_register_operand" "+&rk") (plus:SI (match_dup 4) (const_int -12))) (set (mem:SI (plus:SI (match_dup 4) (const_int -8))) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int -4))) - (match_operand:SI 2 "arm_hard_register_operand" "")) + (match_operand:SI 2 "arm_hard_general_register_operand" "")) (set (mem:SI (match_dup 4)) - (match_operand:SI 3 "arm_hard_register_operand" ""))])] + (match_operand:SI 3 "arm_hard_general_register_operand" ""))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 4" "stm%(da%)\t%4!, {%1, %2, %3}" [(set_attr "type" "store3") @@ -692,13 +692,13 @@ (define_insn "*ldm3_db" [(match_parallel 0 "load_multiple_operation" - [(set (match_operand:SI 1 "arm_hard_register_operand" "") + [(set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk") (const_int -12)))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int -8)))) - (set (match_operand:SI 3 "arm_hard_register_operand" "") + (set (match_operand:SI 3 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int -4))))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" @@ -710,13 +710,13 @@ [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 4 "s_register_operand" "+&rk") (plus:SI (match_dup 4) (const_int -12))) - (set (match_operand:SI 1 "arm_hard_register_operand" "") + (set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int -12)))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int -8)))) - (set (match_operand:SI 3 "arm_hard_register_operand" "") + (set (match_operand:SI 3 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int -4))))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" @@ -727,11 +727,11 @@ (define_insn "*stm3_db" [(match_parallel 0 "store_multiple_operation" [(set (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk") (const_int -12))) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int -8))) - (match_operand:SI 2 "arm_hard_register_operand" "")) + (match_operand:SI 2 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int -4))) - (match_operand:SI 3 "arm_hard_register_operand" ""))])] + (match_operand:SI 3 "arm_hard_general_register_operand" ""))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" "stm%(db%)\t%4, {%1, %2, %3}" [(set_attr "type" "store3") @@ -742,11 +742,11 @@ [(set (match_operand:SI 4 "s_register_operand" "+&rk") (plus:SI (match_dup 4) (const_int -12))) (set (mem:SI (plus:SI (match_dup 4) (const_int -12))) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int -8))) - (match_operand:SI 2 "arm_hard_register_operand" "")) + (match_operand:SI 2 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int -4))) - (match_operand:SI 3 "arm_hard_register_operand" ""))])] + (match_operand:SI 3 "arm_hard_general_register_operand" ""))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" "stm%(db%)\t%4!, {%1, %2, %3}" [(set_attr "type" "store3") @@ -847,9 +847,9 @@ (define_insn "*ldm2_ia" [(match_parallel 0 "load_multiple_operation" - [(set (match_operand:SI 1 "arm_hard_register_operand" "") + [(set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (match_operand:SI 3 "s_register_operand" "rk"))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 3) (const_int 4))))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 2" @@ -859,9 +859,9 @@ (define_insn "*thumb_ldm2_ia" [(match_parallel 0 "load_multiple_operation" - [(set (match_operand:SI 1 "arm_hard_register_operand" "") + [(set (match_operand:SI 1 "low_register_operand" "") (mem:SI (match_operand:SI 3 "s_register_operand" "l"))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "low_register_operand" "") (mem:SI (plus:SI (match_dup 3) (const_int 4))))])] "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 2" @@ -872,9 +872,9 @@ [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 3 "s_register_operand" "+&rk") (plus:SI (match_dup 3) (const_int 8))) - (set (match_operand:SI 1 "arm_hard_register_operand" "") + (set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (match_dup 3))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 3) (const_int 4))))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" @@ -886,9 +886,9 @@ [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 3 "s_register_operand" "+&l") (plus:SI (match_dup 3) (const_int 8))) - (set (match_operand:SI 1 "arm_hard_register_operand" "") + (set (match_operand:SI 1 "low_register_operand" "") (mem:SI (match_dup 3))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "low_register_operand" "") (mem:SI (plus:SI (match_dup 3) (const_int 4))))])] "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 3" @@ -898,9 +898,9 @@ (define_insn "*stm2_ia" [(match_parallel 0 "store_multiple_operation" [(set (mem:SI (match_operand:SI 3 "s_register_operand" "rk")) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 3) (const_int 4))) - (match_operand:SI 2 "arm_hard_register_operand" ""))])] + (match_operand:SI 2 "arm_hard_general_register_operand" ""))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 2" "stm%(ia%)\t%3, {%1, %2}" [(set_attr "type" "store2") @@ -911,9 +911,9 @@ [(set (match_operand:SI 3 "s_register_operand" "+&rk") (plus:SI (match_dup 3) (const_int 8))) (set (mem:SI (match_dup 3)) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 3) (const_int 4))) - (match_operand:SI 2 "arm_hard_register_operand" ""))])] + (match_operand:SI 2 "arm_hard_general_register_operand" ""))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" "stm%(ia%)\t%3!, {%1, %2}" [(set_attr "type" "store2") @@ -924,19 +924,19 @@ [(set (match_operand:SI 3 "s_register_operand" "+&l") (plus:SI (match_dup 3) (const_int 8))) (set (mem:SI (match_dup 3)) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "low_register_operand" "")) (set (mem:SI (plus:SI (match_dup 3) (const_int 4))) - (match_operand:SI 2 "arm_hard_register_operand" ""))])] + (match_operand:SI 2 "low_register_operand" ""))])] "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 3" "stm%(ia%)\t%3!, {%1, %2}" [(set_attr "type" "store2")]) (define_insn "*ldm2_ib" [(match_parallel 0 "load_multiple_operation" - [(set (match_operand:SI 1 "arm_hard_register_operand" "") + [(set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk") (const_int 4)))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 3) (const_int 8))))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 2" @@ -948,10 +948,10 @@ [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 3 "s_register_operand" "+&rk") (plus:SI (match_dup 3) (const_int 8))) - (set (match_operand:SI 1 "arm_hard_register_operand" "") + (set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 3) (const_int 4)))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 3) (const_int 8))))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 3" @@ -962,9 +962,9 @@ (define_insn "*stm2_ib" [(match_parallel 0 "store_multiple_operation" [(set (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk") (const_int 4))) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 3) (const_int 8))) - (match_operand:SI 2 "arm_hard_register_operand" ""))])] + (match_operand:SI 2 "arm_hard_general_register_operand" ""))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 2" "stm%(ib%)\t%3, {%1, %2}" [(set_attr "type" "store2") @@ -975,9 +975,9 @@ [(set (match_operand:SI 3 "s_register_operand" "+&rk") (plus:SI (match_dup 3) (const_int 8))) (set (mem:SI (plus:SI (match_dup 3) (const_int 4))) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 3) (const_int 8))) - (match_operand:SI 2 "arm_hard_register_operand" ""))])] + (match_operand:SI 2 "arm_hard_general_register_operand" ""))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 3" "stm%(ib%)\t%3!, {%1, %2}" [(set_attr "type" "store2") @@ -985,10 +985,10 @@ (define_insn "*ldm2_da" [(match_parallel 0 "load_multiple_operation" - [(set (match_operand:SI 1 "arm_hard_register_operand" "") + [(set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk") (const_int -4)))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (match_dup 3)))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 2" "ldm%(da%)\t%3, {%1, %2}" @@ -999,10 +999,10 @@ [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 3 "s_register_operand" "+&rk") (plus:SI (match_dup 3) (const_int -8))) - (set (match_operand:SI 1 "arm_hard_register_operand" "") + (set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 3) (const_int -4)))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (match_dup 3)))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 3" "ldm%(da%)\t%3!, {%1, %2}" @@ -1012,9 +1012,9 @@ (define_insn "*stm2_da" [(match_parallel 0 "store_multiple_operation" [(set (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk") (const_int -4))) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (match_dup 3)) - (match_operand:SI 2 "arm_hard_register_operand" ""))])] + (match_operand:SI 2 "arm_hard_general_register_operand" ""))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 2" "stm%(da%)\t%3, {%1, %2}" [(set_attr "type" "store2") @@ -1025,9 +1025,9 @@ [(set (match_operand:SI 3 "s_register_operand" "+&rk") (plus:SI (match_dup 3) (const_int -8))) (set (mem:SI (plus:SI (match_dup 3) (const_int -4))) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (match_dup 3)) - (match_operand:SI 2 "arm_hard_register_operand" ""))])] + (match_operand:SI 2 "arm_hard_general_register_operand" ""))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 3" "stm%(da%)\t%3!, {%1, %2}" [(set_attr "type" "store2") @@ -1035,10 +1035,10 @@ (define_insn "*ldm2_db" [(match_parallel 0 "load_multiple_operation" - [(set (match_operand:SI 1 "arm_hard_register_operand" "") + [(set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk") (const_int -8)))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 3) (const_int -4))))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 2" @@ -1050,10 +1050,10 @@ [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 3 "s_register_operand" "+&rk") (plus:SI (match_dup 3) (const_int -8))) - (set (match_operand:SI 1 "arm_hard_register_operand" "") + (set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 3) (const_int -8)))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 3) (const_int -4))))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" @@ -1064,9 +1064,9 @@ (define_insn "*stm2_db" [(match_parallel 0 "store_multiple_operation" [(set (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk") (const_int -8))) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 3) (const_int -4))) - (match_operand:SI 2 "arm_hard_register_operand" ""))])] + (match_operand:SI 2 "arm_hard_general_register_operand" ""))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 2" "stm%(db%)\t%3, {%1, %2}" [(set_attr "type" "store2") @@ -1077,9 +1077,9 @@ [(set (match_operand:SI 3 "s_register_operand" "+&rk") (plus:SI (match_dup 3) (const_int -8))) (set (mem:SI (plus:SI (match_dup 3) (const_int -8))) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 3) (const_int -4))) - (match_operand:SI 2 "arm_hard_register_operand" ""))])] + (match_operand:SI 2 "arm_hard_general_register_operand" ""))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" "stm%(db%)\t%3!, {%1, %2}" [(set_attr "type" "store2") diff --git a/gcc/config/arm/linux-elf.h b/gcc/config/arm/linux-elf.h index 488efa4ba15f6..81884234489ff 100644 --- a/gcc/config/arm/linux-elf.h +++ b/gcc/config/arm/linux-elf.h @@ -65,7 +65,7 @@ %{symbolic:-Bsymbolic} \ %{!static: \ %{rdynamic:-export-dynamic} \ - -dynamic-linker " GNU_USER_DYNAMIC_LINKER "} \ + %{!shared:-dynamic-linker " GNU_USER_DYNAMIC_LINKER "}} \ -X \ %{mbig-endian:-EB} %{mlittle-endian:-EL}" \ SUBTARGET_EXTRA_LINK_SPEC diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index 79b3f667c1727..86a5932d7b02c 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -244,7 +244,7 @@ [(set (match_operand:VDQX 0 "neon_struct_or_register_operand") (unspec:VDQX [(match_operand:VDQX 1 "neon_struct_or_register_operand")] UNSPEC_MISALIGNED_ACCESS))] - "TARGET_NEON && !BYTES_BIG_ENDIAN" + "TARGET_NEON && !BYTES_BIG_ENDIAN && unaligned_access" { /* This pattern is not permitted to fail during expansion: if both arguments are non-registers (e.g. memory := constant, which can be created by the @@ -258,7 +258,7 @@ [(set (match_operand:VDX 0 "neon_struct_operand" "=Um") (unspec:VDX [(match_operand:VDX 1 "s_register_operand" " w")] UNSPEC_MISALIGNED_ACCESS))] - "TARGET_NEON && !BYTES_BIG_ENDIAN" + "TARGET_NEON && !BYTES_BIG_ENDIAN && unaligned_access" "vst1.\t{%P1}, %A0" [(set_attr "neon_type" "neon_vst1_1_2_regs_vst2_2_regs")]) @@ -266,7 +266,7 @@ [(set (match_operand:VDX 0 "s_register_operand" "=w") (unspec:VDX [(match_operand:VDX 1 "neon_struct_operand" " Um")] UNSPEC_MISALIGNED_ACCESS))] - "TARGET_NEON && !BYTES_BIG_ENDIAN" + "TARGET_NEON && !BYTES_BIG_ENDIAN && unaligned_access" "vld1.\t{%P0}, %A1" [(set_attr "neon_type" "neon_vld1_1_2_regs")]) @@ -274,7 +274,7 @@ [(set (match_operand:VQX 0 "neon_struct_operand" "=Um") (unspec:VQX [(match_operand:VQX 1 "s_register_operand" " w")] UNSPEC_MISALIGNED_ACCESS))] - "TARGET_NEON && !BYTES_BIG_ENDIAN" + "TARGET_NEON && !BYTES_BIG_ENDIAN && unaligned_access" "vst1.\t{%q1}, %A0" [(set_attr "neon_type" "neon_vst1_1_2_regs_vst2_2_regs")]) @@ -282,7 +282,7 @@ [(set (match_operand:VQX 0 "s_register_operand" "=w") (unspec:VQX [(match_operand:VQX 1 "neon_struct_operand" " Um")] UNSPEC_MISALIGNED_ACCESS))] - "TARGET_NEON && !BYTES_BIG_ENDIAN" + "TARGET_NEON && !BYTES_BIG_ENDIAN && unaligned_access" "vld1.\t{%q0}, %A1" [(set_attr "neon_type" "neon_vld1_1_2_regs")]) @@ -1721,80 +1721,168 @@ (define_expand "vcond" [(set (match_operand:VDQW 0 "s_register_operand" "") (if_then_else:VDQW - (match_operator 3 "arm_comparison_operator" + (match_operator 3 "comparison_operator" [(match_operand:VDQW 4 "s_register_operand" "") (match_operand:VDQW 5 "nonmemory_operand" "")]) (match_operand:VDQW 1 "s_register_operand" "") (match_operand:VDQW 2 "s_register_operand" "")))] "TARGET_NEON && (! || flag_unsafe_math_optimizations)" { - rtx mask; - int inverse = 0, immediate_zero = 0; - /* See the description of "magic" bits in the 'T' case of - arm_print_operand. */ HOST_WIDE_INT magic_word = (mode == V2SFmode || mode == V4SFmode) ? 3 : 1; rtx magic_rtx = GEN_INT (magic_word); - - mask = gen_reg_rtx (mode); - - if (operands[5] == CONST0_RTX (mode)) - immediate_zero = 1; - else if (!REG_P (operands[5])) - operands[5] = force_reg (mode, operands[5]); - + int inverse = 0; + int use_zero_form = 0; + int swap_bsl_operands = 0; + rtx mask = gen_reg_rtx (mode); + rtx tmp = gen_reg_rtx (mode); + + rtx (*base_comparison) (rtx, rtx, rtx, rtx); + rtx (*complimentary_comparison) (rtx, rtx, rtx, rtx); + switch (GET_CODE (operands[3])) { case GE: - emit_insn (gen_neon_vcge (mask, operands[4], operands[5], - magic_rtx)); + case GT: + case LE: + case LT: + case EQ: + if (operands[5] == CONST0_RTX (mode)) + { + use_zero_form = 1; + break; + } + /* Fall through. */ + default: + if (!REG_P (operands[5])) + operands[5] = force_reg (mode, operands[5]); + } + + switch (GET_CODE (operands[3])) + { + case LT: + case UNLT: + inverse = 1; + /* Fall through. */ + case GE: + case UNGE: + case ORDERED: + case UNORDERED: + base_comparison = gen_neon_vcge; + complimentary_comparison = gen_neon_vcgt; break; - + case LE: + case UNLE: + inverse = 1; + /* Fall through. */ case GT: - emit_insn (gen_neon_vcgt (mask, operands[4], operands[5], - magic_rtx)); + case UNGT: + base_comparison = gen_neon_vcgt; + complimentary_comparison = gen_neon_vcge; break; - case EQ: - emit_insn (gen_neon_vceq (mask, operands[4], operands[5], - magic_rtx)); + case NE: + case UNEQ: + base_comparison = gen_neon_vceq; + complimentary_comparison = gen_neon_vceq; break; - + default: + gcc_unreachable (); + } + + switch (GET_CODE (operands[3])) + { + case LT: case LE: - if (immediate_zero) - emit_insn (gen_neon_vcle (mask, operands[4], operands[5], - magic_rtx)); + case GT: + case GE: + case EQ: + /* The easy case. Here we emit one of vcge, vcgt or vceq. + As a LT b <=> b GE a && a LE b <=> b GT a. Our transformations are: + a GE b -> a GE b + a GT b -> a GT b + a LE b -> b GE a + a LT b -> b GT a + a EQ b -> a EQ b + Note that there also exist direct comparison against 0 forms, + so catch those as a special case. */ + if (use_zero_form) + { + inverse = 0; + switch (GET_CODE (operands[3])) + { + case LT: + base_comparison = gen_neon_vclt; + break; + case LE: + base_comparison = gen_neon_vcle; + break; + default: + /* Do nothing, other zero form cases already have the correct + base_comparison. */ + break; + } + } + + if (!inverse) + emit_insn (base_comparison (mask, operands[4], operands[5], magic_rtx)); else - emit_insn (gen_neon_vcge (mask, operands[5], operands[4], - magic_rtx)); + emit_insn (complimentary_comparison (mask, operands[5], operands[4], magic_rtx)); break; - - case LT: - if (immediate_zero) - emit_insn (gen_neon_vclt (mask, operands[4], operands[5], - magic_rtx)); + case UNLT: + case UNLE: + case UNGT: + case UNGE: + case NE: + /* Vector compare returns false for lanes which are unordered, so if we use + the inverse of the comparison we actually want to emit, then + swap the operands to BSL, we will end up with the correct result. + Note that a NE NaN and NaN NE b are true for all a, b. + + Our transformations are: + a GE b -> !(b GT a) + a GT b -> !(b GE a) + a LE b -> !(a GT b) + a LT b -> !(a GE b) + a NE b -> !(a EQ b) */ + + if (inverse) + emit_insn (base_comparison (mask, operands[4], operands[5], magic_rtx)); else - emit_insn (gen_neon_vcgt (mask, operands[5], operands[4], - magic_rtx)); + emit_insn (complimentary_comparison (mask, operands[5], operands[4], magic_rtx)); + + swap_bsl_operands = 1; break; - - case NE: - emit_insn (gen_neon_vceq (mask, operands[4], operands[5], - magic_rtx)); - inverse = 1; + case UNEQ: + /* We check (a > b || b > a). combining these comparisons give us + true iff !(a != b && a ORDERED b), swapping the operands to BSL + will then give us (a == b || a UNORDERED b) as intended. */ + + emit_insn (gen_neon_vcgt (mask, operands[4], operands[5], magic_rtx)); + emit_insn (gen_neon_vcgt (tmp, operands[5], operands[4], magic_rtx)); + emit_insn (gen_ior3 (mask, mask, tmp)); + swap_bsl_operands = 1; + break; + case UNORDERED: + /* Operands are ORDERED iff (a > b || b >= a). + Swapping the operands to BSL will give the UNORDERED case. */ + swap_bsl_operands = 1; + /* Fall through. */ + case ORDERED: + emit_insn (gen_neon_vcgt (tmp, operands[4], operands[5], magic_rtx)); + emit_insn (gen_neon_vcge (mask, operands[5], operands[4], magic_rtx)); + emit_insn (gen_ior3 (mask, mask, tmp)); break; - default: gcc_unreachable (); } - - if (inverse) + + if (swap_bsl_operands) emit_insn (gen_neon_vbsl (operands[0], mask, operands[2], operands[1])); else emit_insn (gen_neon_vbsl (operands[0], mask, operands[1], operands[2])); - DONE; }) diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md index f493d8284a67b..238f9fd7e434d 100644 --- a/gcc/config/arm/predicates.md +++ b/gcc/config/arm/predicates.md @@ -31,11 +31,11 @@ || REGNO_REG_CLASS (REGNO (op)) != NO_REGS)); }) -;; Any hard register. -(define_predicate "arm_hard_register_operand" +;; Any general register. +(define_predicate "arm_hard_general_register_operand" (match_code "reg") { - return REGNO (op) < FIRST_PSEUDO_REGISTER; + return REGNO (op) <= LAST_ARM_REGNUM; }) ;; A low register. @@ -76,6 +76,12 @@ && REGNO_REG_CLASS (REGNO (op)) == VFP_REGS))); }) +(define_predicate "vfp_hard_register_operand" + (match_code "reg") +{ + return (IS_VFP_REGNUM (REGNO (op))); +}) + (define_predicate "zero_operand" (and (match_code "const_int,const_double,const_vector") (match_test "op == CONST0_RTX (mode)"))) diff --git a/gcc/config/arm/t-rtems-eabi b/gcc/config/arm/t-rtems-eabi index f0e714a9bc5e4..92c4dcb128864 100644 --- a/gcc/config/arm/t-rtems-eabi +++ b/gcc/config/arm/t-rtems-eabi @@ -1,8 +1,167 @@ # Custom RTEMS EABI multilibs -MULTILIB_OPTIONS = mthumb march=armv6-m/march=armv7/march=armv7-m -MULTILIB_DIRNAMES = thumb armv6-m armv7 armv7-m -MULTILIB_EXCEPTIONS = march=armv6-m march=armv7 march=armv7-m -MULTILIB_MATCHES = -MULTILIB_EXCLUSIONS = -MULTILIB_OSDIRNAMES = +MULTILIB_OPTIONS = mbig-endian mthumb march=armv6-m/march=armv7-a/march=armv7-r/march=armv7-m mfpu=neon/mfpu=vfpv3-d16/mfpu=fpv4-sp-d16 mfloat-abi=hard +MULTILIB_DIRNAMES = eb thumb armv6-m armv7-a armv7-r armv7-m neon vfpv3-d16 fpv4-sp-d16 hard + +# Enumeration of multilibs + +MULTILIB_EXCEPTIONS = +MULTILIB_EXCEPTIONS += mbig-endian/mthumb/march=armv6-m/mfpu=neon/mfloat-abi=hard +MULTILIB_EXCEPTIONS += mbig-endian/mthumb/march=armv6-m/mfpu=neon +MULTILIB_EXCEPTIONS += mbig-endian/mthumb/march=armv6-m/mfpu=vfpv3-d16/mfloat-abi=hard +MULTILIB_EXCEPTIONS += mbig-endian/mthumb/march=armv6-m/mfpu=vfpv3-d16 +MULTILIB_EXCEPTIONS += mbig-endian/mthumb/march=armv6-m/mfpu=fpv4-sp-d16/mfloat-abi=hard +MULTILIB_EXCEPTIONS += mbig-endian/mthumb/march=armv6-m/mfpu=fpv4-sp-d16 +MULTILIB_EXCEPTIONS += mbig-endian/mthumb/march=armv6-m/mfloat-abi=hard +MULTILIB_EXCEPTIONS += mbig-endian/mthumb/march=armv6-m +MULTILIB_EXCEPTIONS += mbig-endian/mthumb/march=armv7-a/mfpu=neon/mfloat-abi=hard +MULTILIB_EXCEPTIONS += mbig-endian/mthumb/march=armv7-a/mfpu=neon +MULTILIB_EXCEPTIONS += mbig-endian/mthumb/march=armv7-a/mfpu=vfpv3-d16/mfloat-abi=hard +MULTILIB_EXCEPTIONS += mbig-endian/mthumb/march=armv7-a/mfpu=vfpv3-d16 +MULTILIB_EXCEPTIONS += mbig-endian/mthumb/march=armv7-a/mfpu=fpv4-sp-d16/mfloat-abi=hard +MULTILIB_EXCEPTIONS += mbig-endian/mthumb/march=armv7-a/mfpu=fpv4-sp-d16 +MULTILIB_EXCEPTIONS += mbig-endian/mthumb/march=armv7-a/mfloat-abi=hard +MULTILIB_EXCEPTIONS += mbig-endian/mthumb/march=armv7-a +MULTILIB_EXCEPTIONS += mbig-endian/mthumb/march=armv7-r/mfpu=neon/mfloat-abi=hard +MULTILIB_EXCEPTIONS += mbig-endian/mthumb/march=armv7-r/mfpu=neon +# MULTILIB_EXCEPTIONS += mbig-endian/mthumb/march=armv7-r/mfpu=vfpv3-d16/mfloat-abi=hard +MULTILIB_EXCEPTIONS += mbig-endian/mthumb/march=armv7-r/mfpu=vfpv3-d16 +MULTILIB_EXCEPTIONS += mbig-endian/mthumb/march=armv7-r/mfpu=fpv4-sp-d16/mfloat-abi=hard +MULTILIB_EXCEPTIONS += mbig-endian/mthumb/march=armv7-r/mfpu=fpv4-sp-d16 +MULTILIB_EXCEPTIONS += mbig-endian/mthumb/march=armv7-r/mfloat-abi=hard +# MULTILIB_EXCEPTIONS += mbig-endian/mthumb/march=armv7-r +MULTILIB_EXCEPTIONS += mbig-endian/mthumb/march=armv7-m/mfpu=neon/mfloat-abi=hard +MULTILIB_EXCEPTIONS += mbig-endian/mthumb/march=armv7-m/mfpu=neon +MULTILIB_EXCEPTIONS += mbig-endian/mthumb/march=armv7-m/mfpu=vfpv3-d16/mfloat-abi=hard +MULTILIB_EXCEPTIONS += mbig-endian/mthumb/march=armv7-m/mfpu=vfpv3-d16 +MULTILIB_EXCEPTIONS += mbig-endian/mthumb/march=armv7-m/mfpu=fpv4-sp-d16/mfloat-abi=hard +MULTILIB_EXCEPTIONS += mbig-endian/mthumb/march=armv7-m/mfpu=fpv4-sp-d16 +MULTILIB_EXCEPTIONS += mbig-endian/mthumb/march=armv7-m/mfloat-abi=hard +MULTILIB_EXCEPTIONS += mbig-endian/mthumb/march=armv7-m +MULTILIB_EXCEPTIONS += mbig-endian/mthumb/mfpu=neon/mfloat-abi=hard +MULTILIB_EXCEPTIONS += mbig-endian/mthumb/mfpu=neon +MULTILIB_EXCEPTIONS += mbig-endian/mthumb/mfpu=vfpv3-d16/mfloat-abi=hard +MULTILIB_EXCEPTIONS += mbig-endian/mthumb/mfpu=vfpv3-d16 +MULTILIB_EXCEPTIONS += mbig-endian/mthumb/mfpu=fpv4-sp-d16/mfloat-abi=hard +MULTILIB_EXCEPTIONS += mbig-endian/mthumb/mfpu=fpv4-sp-d16 +MULTILIB_EXCEPTIONS += mbig-endian/mthumb/mfloat-abi=hard +MULTILIB_EXCEPTIONS += mbig-endian/mthumb +MULTILIB_EXCEPTIONS += mbig-endian/march=armv6-m/mfpu=neon/mfloat-abi=hard +MULTILIB_EXCEPTIONS += mbig-endian/march=armv6-m/mfpu=neon +MULTILIB_EXCEPTIONS += mbig-endian/march=armv6-m/mfpu=vfpv3-d16/mfloat-abi=hard +MULTILIB_EXCEPTIONS += mbig-endian/march=armv6-m/mfpu=vfpv3-d16 +MULTILIB_EXCEPTIONS += mbig-endian/march=armv6-m/mfpu=fpv4-sp-d16/mfloat-abi=hard +MULTILIB_EXCEPTIONS += mbig-endian/march=armv6-m/mfpu=fpv4-sp-d16 +MULTILIB_EXCEPTIONS += mbig-endian/march=armv6-m/mfloat-abi=hard +MULTILIB_EXCEPTIONS += mbig-endian/march=armv6-m +MULTILIB_EXCEPTIONS += mbig-endian/march=armv7-a/mfpu=neon/mfloat-abi=hard +MULTILIB_EXCEPTIONS += mbig-endian/march=armv7-a/mfpu=neon +MULTILIB_EXCEPTIONS += mbig-endian/march=armv7-a/mfpu=vfpv3-d16/mfloat-abi=hard +MULTILIB_EXCEPTIONS += mbig-endian/march=armv7-a/mfpu=vfpv3-d16 +MULTILIB_EXCEPTIONS += mbig-endian/march=armv7-a/mfpu=fpv4-sp-d16/mfloat-abi=hard +MULTILIB_EXCEPTIONS += mbig-endian/march=armv7-a/mfpu=fpv4-sp-d16 +MULTILIB_EXCEPTIONS += mbig-endian/march=armv7-a/mfloat-abi=hard +MULTILIB_EXCEPTIONS += mbig-endian/march=armv7-a +MULTILIB_EXCEPTIONS += mbig-endian/march=armv7-r/mfpu=neon/mfloat-abi=hard +MULTILIB_EXCEPTIONS += mbig-endian/march=armv7-r/mfpu=neon +MULTILIB_EXCEPTIONS += mbig-endian/march=armv7-r/mfpu=vfpv3-d16/mfloat-abi=hard +MULTILIB_EXCEPTIONS += mbig-endian/march=armv7-r/mfpu=vfpv3-d16 +MULTILIB_EXCEPTIONS += mbig-endian/march=armv7-r/mfpu=fpv4-sp-d16/mfloat-abi=hard +MULTILIB_EXCEPTIONS += mbig-endian/march=armv7-r/mfpu=fpv4-sp-d16 +MULTILIB_EXCEPTIONS += mbig-endian/march=armv7-r/mfloat-abi=hard +MULTILIB_EXCEPTIONS += mbig-endian/march=armv7-r +MULTILIB_EXCEPTIONS += mbig-endian/march=armv7-m/mfpu=neon/mfloat-abi=hard +MULTILIB_EXCEPTIONS += mbig-endian/march=armv7-m/mfpu=neon +MULTILIB_EXCEPTIONS += mbig-endian/march=armv7-m/mfpu=vfpv3-d16/mfloat-abi=hard +MULTILIB_EXCEPTIONS += mbig-endian/march=armv7-m/mfpu=vfpv3-d16 +MULTILIB_EXCEPTIONS += mbig-endian/march=armv7-m/mfpu=fpv4-sp-d16/mfloat-abi=hard +MULTILIB_EXCEPTIONS += mbig-endian/march=armv7-m/mfpu=fpv4-sp-d16 +MULTILIB_EXCEPTIONS += mbig-endian/march=armv7-m/mfloat-abi=hard +MULTILIB_EXCEPTIONS += mbig-endian/march=armv7-m +MULTILIB_EXCEPTIONS += mbig-endian/mfpu=neon/mfloat-abi=hard +MULTILIB_EXCEPTIONS += mbig-endian/mfpu=neon +MULTILIB_EXCEPTIONS += mbig-endian/mfpu=vfpv3-d16/mfloat-abi=hard +MULTILIB_EXCEPTIONS += mbig-endian/mfpu=vfpv3-d16 +MULTILIB_EXCEPTIONS += mbig-endian/mfpu=fpv4-sp-d16/mfloat-abi=hard +MULTILIB_EXCEPTIONS += mbig-endian/mfpu=fpv4-sp-d16 +MULTILIB_EXCEPTIONS += mbig-endian/mfloat-abi=hard +MULTILIB_EXCEPTIONS += mbig-endian +MULTILIB_EXCEPTIONS += mthumb/march=armv6-m/mfpu=neon/mfloat-abi=hard +MULTILIB_EXCEPTIONS += mthumb/march=armv6-m/mfpu=neon +MULTILIB_EXCEPTIONS += mthumb/march=armv6-m/mfpu=vfpv3-d16/mfloat-abi=hard +MULTILIB_EXCEPTIONS += mthumb/march=armv6-m/mfpu=vfpv3-d16 +MULTILIB_EXCEPTIONS += mthumb/march=armv6-m/mfpu=fpv4-sp-d16/mfloat-abi=hard +MULTILIB_EXCEPTIONS += mthumb/march=armv6-m/mfpu=fpv4-sp-d16 +MULTILIB_EXCEPTIONS += mthumb/march=armv6-m/mfloat-abi=hard +# MULTILIB_EXCEPTIONS += mthumb/march=armv6-m +# MULTILIB_EXCEPTIONS += mthumb/march=armv7-a/mfpu=neon/mfloat-abi=hard +MULTILIB_EXCEPTIONS += mthumb/march=armv7-a/mfpu=neon +MULTILIB_EXCEPTIONS += mthumb/march=armv7-a/mfpu=vfpv3-d16/mfloat-abi=hard +MULTILIB_EXCEPTIONS += mthumb/march=armv7-a/mfpu=vfpv3-d16 +MULTILIB_EXCEPTIONS += mthumb/march=armv7-a/mfpu=fpv4-sp-d16/mfloat-abi=hard +MULTILIB_EXCEPTIONS += mthumb/march=armv7-a/mfpu=fpv4-sp-d16 +MULTILIB_EXCEPTIONS += mthumb/march=armv7-a/mfloat-abi=hard +# MULTILIB_EXCEPTIONS += mthumb/march=armv7-a +MULTILIB_EXCEPTIONS += mthumb/march=armv7-r/mfpu=neon/mfloat-abi=hard +MULTILIB_EXCEPTIONS += mthumb/march=armv7-r/mfpu=neon +# MULTILIB_EXCEPTIONS += mthumb/march=armv7-r/mfpu=vfpv3-d16/mfloat-abi=hard +MULTILIB_EXCEPTIONS += mthumb/march=armv7-r/mfpu=vfpv3-d16 +MULTILIB_EXCEPTIONS += mthumb/march=armv7-r/mfpu=fpv4-sp-d16/mfloat-abi=hard +MULTILIB_EXCEPTIONS += mthumb/march=armv7-r/mfpu=fpv4-sp-d16 +MULTILIB_EXCEPTIONS += mthumb/march=armv7-r/mfloat-abi=hard +# MULTILIB_EXCEPTIONS += mthumb/march=armv7-r +MULTILIB_EXCEPTIONS += mthumb/march=armv7-m/mfpu=neon/mfloat-abi=hard +MULTILIB_EXCEPTIONS += mthumb/march=armv7-m/mfpu=neon +MULTILIB_EXCEPTIONS += mthumb/march=armv7-m/mfpu=vfpv3-d16/mfloat-abi=hard +MULTILIB_EXCEPTIONS += mthumb/march=armv7-m/mfpu=vfpv3-d16 +# MULTILIB_EXCEPTIONS += mthumb/march=armv7-m/mfpu=fpv4-sp-d16/mfloat-abi=hard +MULTILIB_EXCEPTIONS += mthumb/march=armv7-m/mfpu=fpv4-sp-d16 +MULTILIB_EXCEPTIONS += mthumb/march=armv7-m/mfloat-abi=hard +# MULTILIB_EXCEPTIONS += mthumb/march=armv7-m +MULTILIB_EXCEPTIONS += mthumb/mfpu=neon/mfloat-abi=hard +MULTILIB_EXCEPTIONS += mthumb/mfpu=neon +MULTILIB_EXCEPTIONS += mthumb/mfpu=vfpv3-d16/mfloat-abi=hard +MULTILIB_EXCEPTIONS += mthumb/mfpu=vfpv3-d16 +MULTILIB_EXCEPTIONS += mthumb/mfpu=fpv4-sp-d16/mfloat-abi=hard +MULTILIB_EXCEPTIONS += mthumb/mfpu=fpv4-sp-d16 +MULTILIB_EXCEPTIONS += mthumb/mfloat-abi=hard +# MULTILIB_EXCEPTIONS += mthumb +MULTILIB_EXCEPTIONS += march=armv6-m/mfpu=neon/mfloat-abi=hard +MULTILIB_EXCEPTIONS += march=armv6-m/mfpu=neon +MULTILIB_EXCEPTIONS += march=armv6-m/mfpu=vfpv3-d16/mfloat-abi=hard +MULTILIB_EXCEPTIONS += march=armv6-m/mfpu=vfpv3-d16 +MULTILIB_EXCEPTIONS += march=armv6-m/mfpu=fpv4-sp-d16/mfloat-abi=hard +MULTILIB_EXCEPTIONS += march=armv6-m/mfpu=fpv4-sp-d16 +MULTILIB_EXCEPTIONS += march=armv6-m/mfloat-abi=hard +MULTILIB_EXCEPTIONS += march=armv6-m +MULTILIB_EXCEPTIONS += march=armv7-a/mfpu=neon/mfloat-abi=hard +MULTILIB_EXCEPTIONS += march=armv7-a/mfpu=neon +MULTILIB_EXCEPTIONS += march=armv7-a/mfpu=vfpv3-d16/mfloat-abi=hard +MULTILIB_EXCEPTIONS += march=armv7-a/mfpu=vfpv3-d16 +MULTILIB_EXCEPTIONS += march=armv7-a/mfpu=fpv4-sp-d16/mfloat-abi=hard +MULTILIB_EXCEPTIONS += march=armv7-a/mfpu=fpv4-sp-d16 +MULTILIB_EXCEPTIONS += march=armv7-a/mfloat-abi=hard +MULTILIB_EXCEPTIONS += march=armv7-a +MULTILIB_EXCEPTIONS += march=armv7-r/mfpu=neon/mfloat-abi=hard +MULTILIB_EXCEPTIONS += march=armv7-r/mfpu=neon +MULTILIB_EXCEPTIONS += march=armv7-r/mfpu=vfpv3-d16/mfloat-abi=hard +MULTILIB_EXCEPTIONS += march=armv7-r/mfpu=vfpv3-d16 +MULTILIB_EXCEPTIONS += march=armv7-r/mfpu=fpv4-sp-d16/mfloat-abi=hard +MULTILIB_EXCEPTIONS += march=armv7-r/mfpu=fpv4-sp-d16 +MULTILIB_EXCEPTIONS += march=armv7-r/mfloat-abi=hard +MULTILIB_EXCEPTIONS += march=armv7-r +MULTILIB_EXCEPTIONS += march=armv7-m/mfpu=neon/mfloat-abi=hard +MULTILIB_EXCEPTIONS += march=armv7-m/mfpu=neon +MULTILIB_EXCEPTIONS += march=armv7-m/mfpu=vfpv3-d16/mfloat-abi=hard +MULTILIB_EXCEPTIONS += march=armv7-m/mfpu=vfpv3-d16 +MULTILIB_EXCEPTIONS += march=armv7-m/mfpu=fpv4-sp-d16/mfloat-abi=hard +MULTILIB_EXCEPTIONS += march=armv7-m/mfpu=fpv4-sp-d16 +MULTILIB_EXCEPTIONS += march=armv7-m/mfloat-abi=hard +MULTILIB_EXCEPTIONS += march=armv7-m +MULTILIB_EXCEPTIONS += mfpu=neon/mfloat-abi=hard +MULTILIB_EXCEPTIONS += mfpu=neon +MULTILIB_EXCEPTIONS += mfpu=vfpv3-d16/mfloat-abi=hard +MULTILIB_EXCEPTIONS += mfpu=vfpv3-d16 +MULTILIB_EXCEPTIONS += mfpu=fpv4-sp-d16/mfloat-abi=hard +MULTILIB_EXCEPTIONS += mfpu=fpv4-sp-d16 +MULTILIB_EXCEPTIONS += mfloat-abi=hard diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md index 923624ffc6f27..13e151f5ad81b 100644 --- a/gcc/config/arm/vfp.md +++ b/gcc/config/arm/vfp.md @@ -1207,18 +1207,18 @@ (set_attr "type" "fcmpd")] ) -;; Fixed point to floating point conversions. +;; Fixed point to floating point conversions. (define_code_iterator FCVT [unsigned_float float]) (define_code_attr FCVTI32typename [(unsigned_float "u32") (float "s32")]) (define_insn "*combine_vcvt_f32_" [(set (match_operand:SF 0 "s_register_operand" "=t") (mult:SF (FCVT:SF (match_operand:SI 1 "s_register_operand" "0")) - (match_operand 2 + (match_operand 2 "const_double_vcvt_power_of_two_reciprocal" "Dt")))] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP3 && !flag_rounding_math" - "vcvt.f32.\\t%0, %1, %v2" - [(set_attr "predicable" "no") + "vcvt%?.f32.\\t%0, %1, %v2" + [(set_attr "predicable" "yes") (set_attr "type" "f_cvt")] ) @@ -1227,15 +1227,16 @@ (define_insn "*combine_vcvt_f64_" [(set (match_operand:DF 0 "s_register_operand" "=x,x,w") (mult:DF (FCVT:DF (match_operand:SI 1 "s_register_operand" "r,t,r")) - (match_operand 2 + (match_operand 2 "const_double_vcvt_power_of_two_reciprocal" "Dt,Dt,Dt")))] - "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP3 && !flag_rounding_math + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP3 && !flag_rounding_math && !TARGET_VFP_SINGLE" "@ - vmov.f32\\t%0, %1\;vcvt.f64.\\t%P0, %P0, %v2 - vmov.f32\\t%0, %1\;vcvt.f64.\\t%P0, %P0, %v2 - vmov.f64\\t%P0, %1, %1\;vcvt.f64.\\t%P0, %P0, %v2" - [(set_attr "predicable" "no") + vmov%?.f32\\t%0, %1\;vcvt%?.f64.\\t%P0, %P0, %v2 + vmov%?.f32\\t%0, %1\;vcvt%?.f64.\\t%P0, %P0, %v2 + vmov%?.f64\\t%P0, %1, %1\;vcvt%?.f64.\\t%P0, %P0, %v2" + [(set_attr "predicable" "yes") + (set_attr "ce_count" "2") (set_attr "type" "f_cvt") (set_attr "length" "8")] ) @@ -1263,6 +1264,7 @@ "TARGET_HARD_FLOAT && TARGET_FPU_ARMV8 " "vrint%?.\\t%0, %1" [(set_attr "predicable" "") + (set_attr "conds" "") (set_attr "type" "f_rint")] ) @@ -1279,7 +1281,8 @@ (match_operand:SDF 2 "register_operand" "")))] "TARGET_HARD_FLOAT && TARGET_FPU_ARMV8 " "vmaxnm.\\t%0, %1, %2" - [(set_attr "type" "f_minmax")] + [(set_attr "type" "f_minmax") + (set_attr "conds" "unconditional")] ) (define_insn "smin3" @@ -1288,7 +1291,8 @@ (match_operand:SDF 2 "register_operand" "")))] "TARGET_HARD_FLOAT && TARGET_FPU_ARMV8 " "vminnm.\\t%0, %1, %2" - [(set_attr "type" "f_minmax")] + [(set_attr "type" "f_minmax") + (set_attr "conds" "unconditional")] ) ;; Unimplemented insns: diff --git a/gcc/config/avr/avr-fixed.md b/gcc/config/avr/avr-fixed.md index 7d9b525ef6cfc..5bda9c2fa7a2b 100644 --- a/gcc/config/avr/avr-fixed.md +++ b/gcc/config/avr/avr-fixed.md @@ -430,8 +430,8 @@ } // Input and output of the libgcc function - const unsigned int regno_in[] = { -1, 22, 22, -1, 18 }; - const unsigned int regno_out[] = { -1, 24, 24, -1, 22 }; + const unsigned int regno_in[] = { -1U, 22, 22, -1U, 18 }; + const unsigned int regno_out[] = { -1U, 24, 24, -1U, 22 }; operands[3] = gen_rtx_REG (mode, regno_out[(size_t) GET_MODE_SIZE (mode)]); operands[4] = gen_rtx_REG (mode, regno_in[(size_t) GET_MODE_SIZE (mode)]); @@ -447,49 +447,18 @@ ;; "roundqq3_const" "rounduqq3_const" ;; "roundhq3_const" "rounduhq3_const" "roundha3_const" "rounduha3_const" ;; "roundsq3_const" "roundusq3_const" "roundsa3_const" "roundusa3_const" -(define_expand "round3_const" - [(parallel [(match_operand:ALL124QA 0 "register_operand" "") - (match_operand:ALL124QA 1 "register_operand" "") - (match_operand:HI 2 "const_int_operand" "")])] +(define_insn "round3_const" + [(set (match_operand:ALL124QA 0 "register_operand" "=d") + (unspec:ALL124QA [(match_operand:ALL124QA 1 "register_operand" "0") + (match_operand:HI 2 "const_int_operand" "n") + (const_int 0)] + UNSPEC_ROUND))] "" { - // The rounding point RP is $2. The smallest fractional - // bit that is not cleared by the rounding is 2^(-RP). - - enum machine_mode imode = int_mode_for_mode (mode); - int fbit = (int) GET_MODE_FBIT (mode); - - // Add-Saturate 1/2 * 2^(-RP) - - double_int i_add = double_int_zero.set_bit (fbit-1 - INTVAL (operands[2])); - rtx x_add = const_fixed_from_double_int (i_add, mode); - - if (SIGNED_FIXED_POINT_MODE_P (mode)) - emit_move_insn (operands[0], - gen_rtx_SS_PLUS (mode, operands[1], x_add)); - else - emit_move_insn (operands[0], - gen_rtx_US_PLUS (mode, operands[1], x_add)); - - // Keep all bits from RP and higher: ... 2^(-RP) - // Clear all bits from RP+1 and lower: 2^(-RP-1) ... - // Rounding point ^^^^^^^ - // Added above ^^^^^^^^^ - - rtx xreg = simplify_gen_subreg (imode, operands[0], mode, 0); - rtx xmask = immed_double_int_const (-i_add - i_add, imode); - - if (SImode == imode) - emit_insn (gen_andsi3 (xreg, xreg, xmask)); - else if (HImode == imode) - emit_insn (gen_andhi3 (xreg, xreg, xmask)); - else if (QImode == imode) - emit_insn (gen_andqi3 (xreg, xreg, xmask)); - else - gcc_unreachable(); - - DONE; - }) + return avr_out_round (insn, operands); + } + [(set_attr "cc" "clobber") + (set_attr "adjust_len" "round")]) ;; "*roundqq3.libgcc" "*rounduqq3.libgcc" diff --git a/gcc/config/avr/avr-mcus.def b/gcc/config/avr/avr-mcus.def index 2a730ac7a197c..f277d3687b9ad 100644 --- a/gcc/config/avr/avr-mcus.def +++ b/gcc/config/avr/avr-mcus.def @@ -168,7 +168,6 @@ AVR_MCU ("atmega169", ARCH_AVR5, "__AVR_ATmega169__", 0, 0, 0 AVR_MCU ("atmega169a", ARCH_AVR5, "__AVR_ATmega169A__", 0, 0, 0x0100, 1, "m169a") AVR_MCU ("atmega169p", ARCH_AVR5, "__AVR_ATmega169P__", 0, 0, 0x0100, 1, "m169p") AVR_MCU ("atmega169pa", ARCH_AVR5, "__AVR_ATmega169PA__", 0, 0, 0x0100, 1, "m169pa") -AVR_MCU ("atmega16hva", ARCH_AVR5, "__AVR_ATmega16HVA__", 0, 0, 0x0100, 1, "m16hva") AVR_MCU ("atmega16hvb", ARCH_AVR5, "__AVR_ATmega16HVB__", 0, 0, 0x0100, 1, "m16hvb") AVR_MCU ("atmega16hvbrevb", ARCH_AVR5, "__AVR_ATmega16HVBREVB__", 0, 0, 0x0100, 1, "m16hvbrevb") AVR_MCU ("atmega16m1", ARCH_AVR5, "__AVR_ATmega16M1__", 0, 0, 0x0100, 1, "m16m1") @@ -176,7 +175,6 @@ AVR_MCU ("atmega16u4", ARCH_AVR5, "__AVR_ATmega16U4__", 0, 0, 0 AVR_MCU ("atmega26hvg", ARCH_AVR5, "__AVR_ATmega26HVG__", 0, 0, 0x0100, 1, "m26hvg") AVR_MCU ("atmega32a", ARCH_AVR5, "__AVR_ATmega32A__", 0, 0, 0x0060, 1, "m32a") AVR_MCU ("atmega32", ARCH_AVR5, "__AVR_ATmega32__", 0, 0, 0x0060, 1, "m32") -AVR_MCU ("atmega32a", ARCH_AVR5, "__AVR_ATmega32A__", 0, 0, 0x0060, 1, "m32a") AVR_MCU ("atmega323", ARCH_AVR5, "__AVR_ATmega323__", 0, 0, 0x0060, 1, "m323") AVR_MCU ("atmega324a", ARCH_AVR5, "__AVR_ATmega324A__", 0, 0, 0x0100, 1, "m324a") AVR_MCU ("atmega324p", ARCH_AVR5, "__AVR_ATmega324P__", 0, 0, 0x0100, 1, "m324p") @@ -222,7 +220,6 @@ AVR_MCU ("atmega649p", ARCH_AVR5, "__AVR_ATmega649P__", 0, 0, 0 AVR_MCU ("atmega6490", ARCH_AVR5, "__AVR_ATmega6490__", 0, 0, 0x0100, 1, "m6490") AVR_MCU ("atmega16hva", ARCH_AVR5, "__AVR_ATmega16HVA__", 0, 0, 0x0100, 1, "m16hva") AVR_MCU ("atmega16hva2", ARCH_AVR5, "__AVR_ATmega16HVA2__", 0, 0, 0x0100, 1, "m16hva2") -AVR_MCU ("atmega16hvb", ARCH_AVR5, "__AVR_ATmega16HVB__", 0, 0, 0x0100, 1, "m16hvb") AVR_MCU ("atmega32hvb", ARCH_AVR5, "__AVR_ATmega32HVB__", 0, 0, 0x0100, 1, "m32hvb") AVR_MCU ("atmega6490a", ARCH_AVR5, "__AVR_ATmega6490A__", 0, 0, 0x0100, 1, "m6490a") AVR_MCU ("atmega6490p", ARCH_AVR5, "__AVR_ATmega6490P__", 0, 0, 0x0100, 1, "m6490p") @@ -231,23 +228,13 @@ AVR_MCU ("atmega64m1", ARCH_AVR5, "__AVR_ATmega64M1__", 0, 0, 0 AVR_MCU ("atmega64hve", ARCH_AVR5, "__AVR_ATmega64HVE__", 0, 0, 0x0100, 1, "m64hve") AVR_MCU ("atmega64rfa2", ARCH_AVR5, "__AVR_ATmega64RFA2__", 0, 0, 0x0200, 1, "m64rfa2") AVR_MCU ("atmega64rfr2", ARCH_AVR5, "__AVR_ATmega64RFR2__", 0, 0, 0x0200, 1, "m64rfr2") -AVR_MCU ("atmega32hvb", ARCH_AVR5, "__AVR_ATmega32HVB__", 0, 0, 0x0100, 1, "m32hvb") AVR_MCU ("atmega32hvbrevb", ARCH_AVR5, "__AVR_ATmega32HVBREVB__", 0, 0, 0x0100, 1, "m32hvbrevb") -AVR_MCU ("atmega16hva2", ARCH_AVR5, "__AVR_ATmega16HVA2__", 0, 0, 0x0100, 1, "m16hva2") AVR_MCU ("atmega48hvf", ARCH_AVR5, "__AVR_ATmega48HVF__", 0, 0, 0x0100, 1, "m48hvf") AVR_MCU ("at90can32", ARCH_AVR5, "__AVR_AT90CAN32__", 0, 0, 0x0100, 1, "can32") AVR_MCU ("at90can64", ARCH_AVR5, "__AVR_AT90CAN64__", 0, 0, 0x0100, 1, "can64") AVR_MCU ("at90pwm161", ARCH_AVR5, "__AVR_AT90PWM161__", 0, 0, 0x0100, 1, "90pwm161") AVR_MCU ("at90pwm216", ARCH_AVR5, "__AVR_AT90PWM216__", 0, 0, 0x0100, 1, "90pwm216") AVR_MCU ("at90pwm316", ARCH_AVR5, "__AVR_AT90PWM316__", 0, 0, 0x0100, 1, "90pwm316") -AVR_MCU ("atmega32c1", ARCH_AVR5, "__AVR_ATmega32C1__", 0, 0, 0x0100, 1, "m32c1") -AVR_MCU ("atmega64c1", ARCH_AVR5, "__AVR_ATmega64C1__", 0, 0, 0x0100, 1, "m64c1") -AVR_MCU ("atmega16m1", ARCH_AVR5, "__AVR_ATmega16M1__", 0, 0, 0x0100, 1, "m16m1") -AVR_MCU ("atmega32m1", ARCH_AVR5, "__AVR_ATmega32M1__", 0, 0, 0x0100, 1, "m32m1") -AVR_MCU ("atmega64m1", ARCH_AVR5, "__AVR_ATmega64M1__", 0, 0, 0x0100, 1, "m64m1") -AVR_MCU ("atmega16u4", ARCH_AVR5, "__AVR_ATmega16U4__", 0, 0, 0x0100, 1, "m16u4") -AVR_MCU ("atmega32u4", ARCH_AVR5, "__AVR_ATmega32U4__", 0, 0, 0x0100, 1, "m32u4") -AVR_MCU ("atmega32u6", ARCH_AVR5, "__AVR_ATmega32U6__", 0, 0, 0x0100, 1, "m32u6") AVR_MCU ("at90scr100", ARCH_AVR5, "__AVR_AT90SCR100__", 0, 0, 0x0100, 1, "90scr100") AVR_MCU ("at90usb646", ARCH_AVR5, "__AVR_AT90USB646__", 0, 0, 0x0100, 1, "usb646") AVR_MCU ("at90usb647", ARCH_AVR5, "__AVR_AT90USB647__", 0, 0, 0x0100, 1, "usb647") diff --git a/gcc/config/avr/avr-protos.h b/gcc/config/avr/avr-protos.h index 5246d063799f7..21ad26a6f3420 100644 --- a/gcc/config/avr/avr-protos.h +++ b/gcc/config/avr/avr-protos.h @@ -86,7 +86,8 @@ extern int avr_starting_frame_offset (void); extern void avr_output_addr_vec_elt (FILE *stream, int value); extern const char *avr_out_sbxx_branch (rtx insn, rtx operands[]); extern const char* avr_out_bitop (rtx, rtx*, int*); -extern const char* avr_out_plus (rtx, rtx*, int* =NULL, int* =NULL); +extern const char* avr_out_plus (rtx, rtx*, int* =NULL, int* =NULL, bool =true); +extern const char* avr_out_round (rtx, rtx*, int* =NULL); extern const char* avr_out_addto_sp (rtx*, int*); extern const char* avr_out_xload (rtx, rtx*, int*); extern const char* avr_out_movmem (rtx, rtx*, int*); diff --git a/gcc/config/avr/avr-tables.opt b/gcc/config/avr/avr-tables.opt index 1a451bda4b670..b101e00e7e90c 100644 --- a/gcc/config/avr/avr-tables.opt +++ b/gcc/config/avr/avr-tables.opt @@ -330,479 +330,440 @@ EnumValue Enum(avr_mcu) String(atmega169pa) Value(101) EnumValue -Enum(avr_mcu) String(atmega16hva) Value(102) +Enum(avr_mcu) String(atmega16hvb) Value(102) EnumValue -Enum(avr_mcu) String(atmega16hvb) Value(103) +Enum(avr_mcu) String(atmega16hvbrevb) Value(103) EnumValue -Enum(avr_mcu) String(atmega16hvbrevb) Value(104) +Enum(avr_mcu) String(atmega16m1) Value(104) EnumValue -Enum(avr_mcu) String(atmega16m1) Value(105) +Enum(avr_mcu) String(atmega16u4) Value(105) EnumValue -Enum(avr_mcu) String(atmega16u4) Value(106) +Enum(avr_mcu) String(atmega26hvg) Value(106) EnumValue -Enum(avr_mcu) String(atmega26hvg) Value(107) +Enum(avr_mcu) String(atmega32a) Value(107) EnumValue -Enum(avr_mcu) String(atmega32a) Value(108) +Enum(avr_mcu) String(atmega32) Value(108) EnumValue -Enum(avr_mcu) String(atmega32) Value(109) +Enum(avr_mcu) String(atmega323) Value(109) EnumValue -Enum(avr_mcu) String(atmega32a) Value(110) +Enum(avr_mcu) String(atmega324a) Value(110) EnumValue -Enum(avr_mcu) String(atmega323) Value(111) +Enum(avr_mcu) String(atmega324p) Value(111) EnumValue -Enum(avr_mcu) String(atmega324a) Value(112) +Enum(avr_mcu) String(atmega324pa) Value(112) EnumValue -Enum(avr_mcu) String(atmega324p) Value(113) +Enum(avr_mcu) String(atmega325) Value(113) EnumValue -Enum(avr_mcu) String(atmega324pa) Value(114) +Enum(avr_mcu) String(atmega325a) Value(114) EnumValue -Enum(avr_mcu) String(atmega325) Value(115) +Enum(avr_mcu) String(atmega325p) Value(115) EnumValue -Enum(avr_mcu) String(atmega325a) Value(116) +Enum(avr_mcu) String(atmega3250) Value(116) EnumValue -Enum(avr_mcu) String(atmega325p) Value(117) +Enum(avr_mcu) String(atmega3250a) Value(117) EnumValue -Enum(avr_mcu) String(atmega3250) Value(118) +Enum(avr_mcu) String(atmega3250p) Value(118) EnumValue -Enum(avr_mcu) String(atmega3250a) Value(119) +Enum(avr_mcu) String(atmega3250pa) Value(119) EnumValue -Enum(avr_mcu) String(atmega3250p) Value(120) +Enum(avr_mcu) String(atmega328) Value(120) EnumValue -Enum(avr_mcu) String(atmega3250pa) Value(121) +Enum(avr_mcu) String(atmega328p) Value(121) EnumValue -Enum(avr_mcu) String(atmega328) Value(122) +Enum(avr_mcu) String(atmega329) Value(122) EnumValue -Enum(avr_mcu) String(atmega328p) Value(123) +Enum(avr_mcu) String(atmega329a) Value(123) EnumValue -Enum(avr_mcu) String(atmega329) Value(124) +Enum(avr_mcu) String(atmega329p) Value(124) EnumValue -Enum(avr_mcu) String(atmega329a) Value(125) +Enum(avr_mcu) String(atmega329pa) Value(125) EnumValue -Enum(avr_mcu) String(atmega329p) Value(126) +Enum(avr_mcu) String(atmega3290) Value(126) EnumValue -Enum(avr_mcu) String(atmega329pa) Value(127) +Enum(avr_mcu) String(atmega3290a) Value(127) EnumValue -Enum(avr_mcu) String(atmega3290) Value(128) +Enum(avr_mcu) String(atmega3290p) Value(128) EnumValue -Enum(avr_mcu) String(atmega3290a) Value(129) +Enum(avr_mcu) String(atmega3290pa) Value(129) EnumValue -Enum(avr_mcu) String(atmega3290p) Value(130) +Enum(avr_mcu) String(atmega32c1) Value(130) EnumValue -Enum(avr_mcu) String(atmega3290pa) Value(131) +Enum(avr_mcu) String(atmega32m1) Value(131) EnumValue -Enum(avr_mcu) String(atmega32c1) Value(132) +Enum(avr_mcu) String(atmega32u4) Value(132) EnumValue -Enum(avr_mcu) String(atmega32m1) Value(133) +Enum(avr_mcu) String(atmega32u6) Value(133) EnumValue -Enum(avr_mcu) String(atmega32u4) Value(134) +Enum(avr_mcu) String(atmega406) Value(134) EnumValue -Enum(avr_mcu) String(atmega32u6) Value(135) +Enum(avr_mcu) String(atmega64) Value(135) EnumValue -Enum(avr_mcu) String(atmega406) Value(136) +Enum(avr_mcu) String(atmega64a) Value(136) EnumValue -Enum(avr_mcu) String(atmega64) Value(137) +Enum(avr_mcu) String(atmega640) Value(137) EnumValue -Enum(avr_mcu) String(atmega64a) Value(138) +Enum(avr_mcu) String(atmega644) Value(138) EnumValue -Enum(avr_mcu) String(atmega640) Value(139) +Enum(avr_mcu) String(atmega644a) Value(139) EnumValue -Enum(avr_mcu) String(atmega644) Value(140) +Enum(avr_mcu) String(atmega644p) Value(140) EnumValue -Enum(avr_mcu) String(atmega644a) Value(141) +Enum(avr_mcu) String(atmega644pa) Value(141) EnumValue -Enum(avr_mcu) String(atmega644p) Value(142) +Enum(avr_mcu) String(atmega645) Value(142) EnumValue -Enum(avr_mcu) String(atmega644pa) Value(143) +Enum(avr_mcu) String(atmega645a) Value(143) EnumValue -Enum(avr_mcu) String(atmega645) Value(144) +Enum(avr_mcu) String(atmega645p) Value(144) EnumValue -Enum(avr_mcu) String(atmega645a) Value(145) +Enum(avr_mcu) String(atmega6450) Value(145) EnumValue -Enum(avr_mcu) String(atmega645p) Value(146) +Enum(avr_mcu) String(atmega6450a) Value(146) EnumValue -Enum(avr_mcu) String(atmega6450) Value(147) +Enum(avr_mcu) String(atmega6450p) Value(147) EnumValue -Enum(avr_mcu) String(atmega6450a) Value(148) +Enum(avr_mcu) String(atmega649) Value(148) EnumValue -Enum(avr_mcu) String(atmega6450p) Value(149) +Enum(avr_mcu) String(atmega649a) Value(149) EnumValue -Enum(avr_mcu) String(atmega649) Value(150) +Enum(avr_mcu) String(atmega649p) Value(150) EnumValue -Enum(avr_mcu) String(atmega649a) Value(151) +Enum(avr_mcu) String(atmega6490) Value(151) EnumValue -Enum(avr_mcu) String(atmega649p) Value(152) +Enum(avr_mcu) String(atmega16hva) Value(152) EnumValue -Enum(avr_mcu) String(atmega6490) Value(153) +Enum(avr_mcu) String(atmega16hva2) Value(153) EnumValue -Enum(avr_mcu) String(atmega16hva) Value(154) +Enum(avr_mcu) String(atmega32hvb) Value(154) EnumValue -Enum(avr_mcu) String(atmega16hva2) Value(155) +Enum(avr_mcu) String(atmega6490a) Value(155) EnumValue -Enum(avr_mcu) String(atmega16hvb) Value(156) +Enum(avr_mcu) String(atmega6490p) Value(156) EnumValue -Enum(avr_mcu) String(atmega32hvb) Value(157) +Enum(avr_mcu) String(atmega64c1) Value(157) EnumValue -Enum(avr_mcu) String(atmega6490a) Value(158) +Enum(avr_mcu) String(atmega64m1) Value(158) EnumValue -Enum(avr_mcu) String(atmega6490p) Value(159) +Enum(avr_mcu) String(atmega64hve) Value(159) EnumValue -Enum(avr_mcu) String(atmega64c1) Value(160) +Enum(avr_mcu) String(atmega64rfa2) Value(160) EnumValue -Enum(avr_mcu) String(atmega64m1) Value(161) +Enum(avr_mcu) String(atmega64rfr2) Value(161) EnumValue -Enum(avr_mcu) String(atmega64hve) Value(162) +Enum(avr_mcu) String(atmega32hvbrevb) Value(162) EnumValue -Enum(avr_mcu) String(atmega64rfa2) Value(163) +Enum(avr_mcu) String(atmega48hvf) Value(163) EnumValue -Enum(avr_mcu) String(atmega64rfr2) Value(164) +Enum(avr_mcu) String(at90can32) Value(164) EnumValue -Enum(avr_mcu) String(atmega32hvb) Value(165) +Enum(avr_mcu) String(at90can64) Value(165) EnumValue -Enum(avr_mcu) String(atmega32hvbrevb) Value(166) +Enum(avr_mcu) String(at90pwm161) Value(166) EnumValue -Enum(avr_mcu) String(atmega16hva2) Value(167) +Enum(avr_mcu) String(at90pwm216) Value(167) EnumValue -Enum(avr_mcu) String(atmega48hvf) Value(168) +Enum(avr_mcu) String(at90pwm316) Value(168) EnumValue -Enum(avr_mcu) String(at90can32) Value(169) +Enum(avr_mcu) String(at90scr100) Value(169) EnumValue -Enum(avr_mcu) String(at90can64) Value(170) +Enum(avr_mcu) String(at90usb646) Value(170) EnumValue -Enum(avr_mcu) String(at90pwm161) Value(171) +Enum(avr_mcu) String(at90usb647) Value(171) EnumValue -Enum(avr_mcu) String(at90pwm216) Value(172) +Enum(avr_mcu) String(at94k) Value(172) EnumValue -Enum(avr_mcu) String(at90pwm316) Value(173) +Enum(avr_mcu) String(m3000) Value(173) EnumValue -Enum(avr_mcu) String(atmega32c1) Value(174) +Enum(avr_mcu) String(avr51) Value(174) EnumValue -Enum(avr_mcu) String(atmega64c1) Value(175) +Enum(avr_mcu) String(atmega128) Value(175) EnumValue -Enum(avr_mcu) String(atmega16m1) Value(176) +Enum(avr_mcu) String(atmega128a) Value(176) EnumValue -Enum(avr_mcu) String(atmega32m1) Value(177) +Enum(avr_mcu) String(atmega1280) Value(177) EnumValue -Enum(avr_mcu) String(atmega64m1) Value(178) +Enum(avr_mcu) String(atmega1281) Value(178) EnumValue -Enum(avr_mcu) String(atmega16u4) Value(179) +Enum(avr_mcu) String(atmega1284) Value(179) EnumValue -Enum(avr_mcu) String(atmega32u4) Value(180) +Enum(avr_mcu) String(atmega1284p) Value(180) EnumValue -Enum(avr_mcu) String(atmega32u6) Value(181) +Enum(avr_mcu) String(atmega128rfa1) Value(181) EnumValue -Enum(avr_mcu) String(at90scr100) Value(182) +Enum(avr_mcu) String(at90can128) Value(182) EnumValue -Enum(avr_mcu) String(at90usb646) Value(183) +Enum(avr_mcu) String(at90usb1286) Value(183) EnumValue -Enum(avr_mcu) String(at90usb647) Value(184) +Enum(avr_mcu) String(at90usb1287) Value(184) EnumValue -Enum(avr_mcu) String(at94k) Value(185) +Enum(avr_mcu) String(avr6) Value(185) EnumValue -Enum(avr_mcu) String(m3000) Value(186) +Enum(avr_mcu) String(atmega2560) Value(186) EnumValue -Enum(avr_mcu) String(avr51) Value(187) +Enum(avr_mcu) String(atmega2561) Value(187) EnumValue -Enum(avr_mcu) String(atmega128) Value(188) +Enum(avr_mcu) String(avrxmega2) Value(188) EnumValue -Enum(avr_mcu) String(atmega128a) Value(189) +Enum(avr_mcu) String(atxmega16a4) Value(189) EnumValue -Enum(avr_mcu) String(atmega1280) Value(190) +Enum(avr_mcu) String(atxmega16d4) Value(190) EnumValue -Enum(avr_mcu) String(atmega1281) Value(191) +Enum(avr_mcu) String(atxmega16x1) Value(191) EnumValue -Enum(avr_mcu) String(atmega1284) Value(192) +Enum(avr_mcu) String(atxmega32a4) Value(192) EnumValue -Enum(avr_mcu) String(atmega1284p) Value(193) +Enum(avr_mcu) String(atxmega32d4) Value(193) EnumValue -Enum(avr_mcu) String(atmega128rfa1) Value(194) +Enum(avr_mcu) String(atxmega32x1) Value(194) EnumValue -Enum(avr_mcu) String(at90can128) Value(195) +Enum(avr_mcu) String(atmxt112sl) Value(195) EnumValue -Enum(avr_mcu) String(at90usb1286) Value(196) +Enum(avr_mcu) String(atmxt224) Value(196) EnumValue -Enum(avr_mcu) String(at90usb1287) Value(197) +Enum(avr_mcu) String(atmxt224e) Value(197) EnumValue -Enum(avr_mcu) String(avr6) Value(198) +Enum(avr_mcu) String(atmxt336s) Value(198) EnumValue -Enum(avr_mcu) String(atmega2560) Value(199) +Enum(avr_mcu) String(atxmega16a4u) Value(199) EnumValue -Enum(avr_mcu) String(atmega2561) Value(200) +Enum(avr_mcu) String(atxmega16c4) Value(200) EnumValue -Enum(avr_mcu) String(avrxmega2) Value(201) +Enum(avr_mcu) String(atxmega32a4u) Value(201) EnumValue -Enum(avr_mcu) String(atxmega16a4) Value(202) +Enum(avr_mcu) String(atxmega32c4) Value(202) EnumValue -Enum(avr_mcu) String(atxmega16d4) Value(203) +Enum(avr_mcu) String(atxmega32e5) Value(203) EnumValue -Enum(avr_mcu) String(atxmega16x1) Value(204) +Enum(avr_mcu) String(avrxmega4) Value(204) EnumValue -Enum(avr_mcu) String(atxmega32a4) Value(205) +Enum(avr_mcu) String(atxmega64a3) Value(205) EnumValue -Enum(avr_mcu) String(atxmega32d4) Value(206) +Enum(avr_mcu) String(atxmega64d3) Value(206) EnumValue -Enum(avr_mcu) String(atxmega32x1) Value(207) +Enum(avr_mcu) String(atxmega64a3u) Value(207) EnumValue -Enum(avr_mcu) String(atmxt112sl) Value(208) +Enum(avr_mcu) String(atxmega64a4u) Value(208) EnumValue -Enum(avr_mcu) String(atmxt224) Value(209) +Enum(avr_mcu) String(atxmega64b1) Value(209) EnumValue -Enum(avr_mcu) String(atmxt224e) Value(210) +Enum(avr_mcu) String(atxmega64b3) Value(210) EnumValue -Enum(avr_mcu) String(atmxt336s) Value(211) +Enum(avr_mcu) String(atxmega64c3) Value(211) EnumValue -Enum(avr_mcu) String(atxmega16a4u) Value(212) +Enum(avr_mcu) String(atxmega64d4) Value(212) EnumValue -Enum(avr_mcu) String(atxmega16c4) Value(213) +Enum(avr_mcu) String(avrxmega5) Value(213) EnumValue -Enum(avr_mcu) String(atxmega32a4u) Value(214) +Enum(avr_mcu) String(atxmega64a1) Value(214) EnumValue -Enum(avr_mcu) String(atxmega32c4) Value(215) +Enum(avr_mcu) String(atxmega64a1u) Value(215) EnumValue -Enum(avr_mcu) String(atxmega32e5) Value(216) +Enum(avr_mcu) String(avrxmega6) Value(216) EnumValue -Enum(avr_mcu) String(avrxmega4) Value(217) +Enum(avr_mcu) String(atxmega128a3) Value(217) EnumValue -Enum(avr_mcu) String(atxmega64a3) Value(218) +Enum(avr_mcu) String(atxmega128d3) Value(218) EnumValue -Enum(avr_mcu) String(atxmega64d3) Value(219) +Enum(avr_mcu) String(atxmega192a3) Value(219) EnumValue -Enum(avr_mcu) String(atxmega64a3u) Value(220) +Enum(avr_mcu) String(atxmega192d3) Value(220) EnumValue -Enum(avr_mcu) String(atxmega64a4u) Value(221) +Enum(avr_mcu) String(atxmega256a3) Value(221) EnumValue -Enum(avr_mcu) String(atxmega64b1) Value(222) +Enum(avr_mcu) String(atxmega256a3b) Value(222) EnumValue -Enum(avr_mcu) String(atxmega64b3) Value(223) +Enum(avr_mcu) String(atxmega256a3bu) Value(223) EnumValue -Enum(avr_mcu) String(atxmega64c3) Value(224) +Enum(avr_mcu) String(atxmega256d3) Value(224) EnumValue -Enum(avr_mcu) String(atxmega64d4) Value(225) +Enum(avr_mcu) String(atxmega128a3u) Value(225) EnumValue -Enum(avr_mcu) String(avrxmega5) Value(226) +Enum(avr_mcu) String(atxmega128b1) Value(226) EnumValue -Enum(avr_mcu) String(atxmega64a1) Value(227) +Enum(avr_mcu) String(atxmega128b3) Value(227) EnumValue -Enum(avr_mcu) String(atxmega64a1u) Value(228) +Enum(avr_mcu) String(atxmega128c3) Value(228) EnumValue -Enum(avr_mcu) String(avrxmega6) Value(229) +Enum(avr_mcu) String(atxmega128d4) Value(229) EnumValue -Enum(avr_mcu) String(atxmega128a3) Value(230) +Enum(avr_mcu) String(atmxt540s) Value(230) EnumValue -Enum(avr_mcu) String(atxmega128d3) Value(231) +Enum(avr_mcu) String(atmxt540sreva) Value(231) EnumValue -Enum(avr_mcu) String(atxmega192a3) Value(232) +Enum(avr_mcu) String(atxmega192a3u) Value(232) EnumValue -Enum(avr_mcu) String(atxmega192d3) Value(233) +Enum(avr_mcu) String(atxmega192c3) Value(233) EnumValue -Enum(avr_mcu) String(atxmega256a3) Value(234) +Enum(avr_mcu) String(atxmega256a3u) Value(234) EnumValue -Enum(avr_mcu) String(atxmega256a3b) Value(235) +Enum(avr_mcu) String(atxmega256c3) Value(235) EnumValue -Enum(avr_mcu) String(atxmega256a3bu) Value(236) +Enum(avr_mcu) String(atxmega384c3) Value(236) EnumValue -Enum(avr_mcu) String(atxmega256d3) Value(237) +Enum(avr_mcu) String(atxmega384d3) Value(237) EnumValue -Enum(avr_mcu) String(atxmega128a3u) Value(238) +Enum(avr_mcu) String(avrxmega7) Value(238) EnumValue -Enum(avr_mcu) String(atxmega128b1) Value(239) +Enum(avr_mcu) String(atxmega128a1) Value(239) EnumValue -Enum(avr_mcu) String(atxmega128b3) Value(240) +Enum(avr_mcu) String(atxmega128a1u) Value(240) EnumValue -Enum(avr_mcu) String(atxmega128c3) Value(241) +Enum(avr_mcu) String(atxmega128a4u) Value(241) EnumValue -Enum(avr_mcu) String(atxmega128d4) Value(242) +Enum(avr_mcu) String(avr1) Value(242) EnumValue -Enum(avr_mcu) String(atmxt540s) Value(243) +Enum(avr_mcu) String(at90s1200) Value(243) EnumValue -Enum(avr_mcu) String(atmxt540sreva) Value(244) +Enum(avr_mcu) String(attiny11) Value(244) EnumValue -Enum(avr_mcu) String(atxmega192a3u) Value(245) +Enum(avr_mcu) String(attiny12) Value(245) EnumValue -Enum(avr_mcu) String(atxmega192c3) Value(246) +Enum(avr_mcu) String(attiny15) Value(246) EnumValue -Enum(avr_mcu) String(atxmega256a3u) Value(247) - -EnumValue -Enum(avr_mcu) String(atxmega256c3) Value(248) - -EnumValue -Enum(avr_mcu) String(atxmega384c3) Value(249) - -EnumValue -Enum(avr_mcu) String(atxmega384d3) Value(250) - -EnumValue -Enum(avr_mcu) String(avrxmega7) Value(251) - -EnumValue -Enum(avr_mcu) String(atxmega128a1) Value(252) - -EnumValue -Enum(avr_mcu) String(atxmega128a1u) Value(253) - -EnumValue -Enum(avr_mcu) String(atxmega128a4u) Value(254) - -EnumValue -Enum(avr_mcu) String(avr1) Value(255) - -EnumValue -Enum(avr_mcu) String(at90s1200) Value(256) - -EnumValue -Enum(avr_mcu) String(attiny11) Value(257) - -EnumValue -Enum(avr_mcu) String(attiny12) Value(258) - -EnumValue -Enum(avr_mcu) String(attiny15) Value(259) - -EnumValue -Enum(avr_mcu) String(attiny28) Value(260) +Enum(avr_mcu) String(attiny28) Value(247) diff --git a/gcc/config/avr/avr.c b/gcc/config/avr/avr.c index c916d6bcf2376..597adc55147fe 100644 --- a/gcc/config/avr/avr.c +++ b/gcc/config/avr/avr.c @@ -584,7 +584,16 @@ avr_set_current_function (tree decl) { tree args = TYPE_ARG_TYPES (TREE_TYPE (decl)); tree ret = TREE_TYPE (TREE_TYPE (decl)); - const char *name = IDENTIFIER_POINTER (DECL_NAME (decl)); + const char *name; + + name = DECL_ASSEMBLER_NAME_SET_P (decl) + ? IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl)) + : IDENTIFIER_POINTER (DECL_NAME (decl)); + + /* Skip a leading '*' that might still prefix the assembler name, + e.g. in non-LTO runs. */ + + name = default_strip_name_encoding (name); /* Silently ignore 'signal' if 'interrupt' is present. AVR-LibC startet using this when it switched from SIGNAL and INTERRUPT to ISR. */ @@ -1112,7 +1121,7 @@ avr_prologue_setup_frame (HOST_WIDE_INT size, HARD_REG_SET set) leaf function and thus X has already been saved. */ int irq_state = -1; - HOST_WIDE_INT size_cfa = size; + HOST_WIDE_INT size_cfa = size, neg_size; rtx fp_plus_insns, fp, my_fp; gcc_assert (frame_pointer_needed @@ -1151,6 +1160,7 @@ avr_prologue_setup_frame (HOST_WIDE_INT size, HARD_REG_SET set) } size = trunc_int_for_mode (size, GET_MODE (my_fp)); + neg_size = trunc_int_for_mode (-size, GET_MODE (my_fp)); /************ Method 1: Adjust frame pointer ************/ @@ -1171,7 +1181,8 @@ avr_prologue_setup_frame (HOST_WIDE_INT size, HARD_REG_SET set) } insn = emit_move_insn (my_fp, plus_constant (GET_MODE (my_fp), - my_fp, -size)); + my_fp, neg_size)); + if (frame_pointer_needed) { RTX_FRAME_RELATED_P (insn) = 1; @@ -2332,6 +2343,12 @@ avr_notice_update_cc (rtx body ATTRIBUTE_UNUSED, rtx insn) } break; + case CC_SET_VZN: + /* Insn like INC, DEC, NEG that set Z,N,V. We currently don't make use + of this combination, cf. also PR61055. */ + CC_STATUS_INIT; + break; + case CC_SET_CZN: /* Insn sets the Z,N,C flags of CC to recog_operand[0]. The V flag may or may not be known but that's ok because @@ -3970,7 +3987,7 @@ avr_out_store_psi (rtx insn, rtx *op, int *plen) "std Y+61,%A1" CR_TAB "std Y+62,%B1" CR_TAB "std Y+63,%C1" CR_TAB - "sbiw r28,%o0-60", op, plen, -5); + "sbiw r28,%o0-61", op, plen, -5); return avr_asm_len ("subi r28,lo8(-%o0)" CR_TAB "sbci r29,hi8(-%o0)" CR_TAB @@ -6225,11 +6242,14 @@ lshrsi3_out (rtx insn, rtx operands[], int *len) the subtrahend in the original insn, provided it is a compile time constant. In all other cases, SIGN is 0. - Return "". */ + If OUT_LABEL is true, print the final 0: label which is needed for + saturated addition / subtraction. The only case where OUT_LABEL = false + is useful is for saturated addition / subtraction performed during + fixed-point rounding, cf. `avr_out_round'. */ static void avr_out_plus_1 (rtx *xop, int *plen, enum rtx_code code, int *pcc, - enum rtx_code code_sat = UNKNOWN, int sign = 0) + enum rtx_code code_sat, int sign, bool out_label) { /* MODE of the operation. */ enum machine_mode mode = GET_MODE (xop[0]); @@ -6264,7 +6284,7 @@ avr_out_plus_1 (rtx *xop, int *plen, enum rtx_code code, int *pcc, if (REG_P (xop[2])) { - *pcc = MINUS == code ? (int) CC_SET_CZN : (int) CC_SET_N; + *pcc = MINUS == code ? (int) CC_SET_CZN : (int) CC_CLOBBER; for (i = 0; i < n_bytes; i++) { @@ -6373,7 +6393,7 @@ avr_out_plus_1 (rtx *xop, int *plen, enum rtx_code code, int *pcc, op, plen, 1); if (n_bytes == 2 && PLUS == code) - *pcc = CC_SET_ZN; + *pcc = CC_SET_CZN; } i++; @@ -6396,6 +6416,7 @@ avr_out_plus_1 (rtx *xop, int *plen, enum rtx_code code, int *pcc, { avr_asm_len ((code == PLUS) ^ (val8 == 1) ? "dec %0" : "inc %0", op, plen, 1); + *pcc = CC_CLOBBER; break; } @@ -6668,7 +6689,8 @@ avr_out_plus_1 (rtx *xop, int *plen, enum rtx_code code, int *pcc, "mov %r0+5,%0", xop, plen, 4); } - avr_asm_len ("0:", op, plen, 0); + if (out_label) + avr_asm_len ("0:", op, plen, 0); } @@ -6706,8 +6728,8 @@ avr_out_plus_symbol (rtx *xop, enum rtx_code code, int *plen, int *pcc) /* Prepare operands of addition/subtraction to be used with avr_out_plus_1. - INSN is a single_set insn with a binary operation as SET_SRC that is - one of: PLUS, SS_PLUS, US_PLUS, MINUS, SS_MINUS, US_MINUS. + INSN is a single_set insn or an insn pattern with a binary operation as + SET_SRC that is one of: PLUS, SS_PLUS, US_PLUS, MINUS, SS_MINUS, US_MINUS. XOP are the operands of INSN. In the case of 64-bit operations with constant XOP[] has just one element: The summand/subtrahend in XOP[0]. @@ -6722,19 +6744,22 @@ avr_out_plus_symbol (rtx *xop, enum rtx_code code, int *plen, int *pcc) PLEN and PCC default to NULL. + OUT_LABEL defaults to TRUE. For a description, see AVR_OUT_PLUS_1. + Return "" */ const char* -avr_out_plus (rtx insn, rtx *xop, int *plen, int *pcc) +avr_out_plus (rtx insn, rtx *xop, int *plen, int *pcc, bool out_label) { int cc_plus, cc_minus, cc_dummy; int len_plus, len_minus; rtx op[4]; - rtx xdest = SET_DEST (single_set (insn)); + rtx xpattern = INSN_P (insn) ? single_set (insn) : insn; + rtx xdest = SET_DEST (xpattern); enum machine_mode mode = GET_MODE (xdest); enum machine_mode imode = int_mode_for_mode (mode); int n_bytes = GET_MODE_SIZE (mode); - enum rtx_code code_sat = GET_CODE (SET_SRC (single_set (insn))); + enum rtx_code code_sat = GET_CODE (SET_SRC (xpattern)); enum rtx_code code = (PLUS == code_sat || SS_PLUS == code_sat || US_PLUS == code_sat ? PLUS : MINUS); @@ -6749,7 +6774,7 @@ avr_out_plus (rtx insn, rtx *xop, int *plen, int *pcc) if (n_bytes <= 4 && REG_P (xop[2])) { - avr_out_plus_1 (xop, plen, code, pcc, code_sat); + avr_out_plus_1 (xop, plen, code, pcc, code_sat, 0, out_label); return ""; } @@ -6776,7 +6801,8 @@ avr_out_plus (rtx insn, rtx *xop, int *plen, int *pcc) /* Saturations and 64-bit operations don't have a clobber operand. For the other cases, the caller will provide a proper XOP[3]. */ - op[3] = PARALLEL == GET_CODE (PATTERN (insn)) ? xop[3] : NULL_RTX; + xpattern = INSN_P (insn) ? PATTERN (insn) : insn; + op[3] = PARALLEL == GET_CODE (xpattern) ? xop[3] : NULL_RTX; /* Saturation will need the sign of the original operand. */ @@ -6791,8 +6817,8 @@ avr_out_plus (rtx insn, rtx *xop, int *plen, int *pcc) /* Work out the shortest sequence. */ - avr_out_plus_1 (op, &len_minus, MINUS, &cc_plus, code_sat, sign); - avr_out_plus_1 (op, &len_plus, PLUS, &cc_minus, code_sat, sign); + avr_out_plus_1 (op, &len_minus, MINUS, &cc_minus, code_sat, sign, out_label); + avr_out_plus_1 (op, &len_plus, PLUS, &cc_plus, code_sat, sign, out_label); if (plen) { @@ -6800,9 +6826,9 @@ avr_out_plus (rtx insn, rtx *xop, int *plen, int *pcc) *pcc = (len_minus <= len_plus) ? cc_minus : cc_plus; } else if (len_minus <= len_plus) - avr_out_plus_1 (op, NULL, MINUS, pcc, code_sat, sign); + avr_out_plus_1 (op, NULL, MINUS, pcc, code_sat, sign, out_label); else - avr_out_plus_1 (op, NULL, PLUS, pcc, code_sat, sign); + avr_out_plus_1 (op, NULL, PLUS, pcc, code_sat, sign, out_label); return ""; } @@ -6816,13 +6842,15 @@ avr_out_plus (rtx insn, rtx *xop, int *plen, int *pcc) and return "". If PLEN == NULL, print assembler instructions to perform the operation; otherwise, set *PLEN to the length of the instruction sequence (in words) printed with PLEN == NULL. XOP[3] is either an 8-bit clobber - register or SCRATCH if no clobber register is needed for the operation. */ + register or SCRATCH if no clobber register is needed for the operation. + INSN is an INSN_P or a pattern of an insn. */ const char* avr_out_bitop (rtx insn, rtx *xop, int *plen) { /* CODE and MODE of the operation. */ - enum rtx_code code = GET_CODE (SET_SRC (single_set (insn))); + rtx xpattern = INSN_P (insn) ? single_set (insn) : insn; + enum rtx_code code = GET_CODE (SET_SRC (xpattern)); enum machine_mode mode = GET_MODE (xop[0]); /* Number of bytes to operate on. */ @@ -7325,6 +7353,67 @@ avr_out_fract (rtx insn, rtx operands[], bool intsigned, int *plen) } +/* Output fixed-point rounding. XOP[0] = XOP[1] is the operand to round. + XOP[2] is the rounding point, a CONST_INT. The function prints the + instruction sequence if PLEN = NULL and computes the length in words + of the sequence if PLEN != NULL. Most of this function deals with + preparing operands for calls to `avr_out_plus' and `avr_out_bitop'. */ + +const char* +avr_out_round (rtx insn ATTRIBUTE_UNUSED, rtx *xop, int *plen) +{ + enum machine_mode mode = GET_MODE (xop[0]); + enum machine_mode imode = int_mode_for_mode (mode); + // The smallest fractional bit not cleared by the rounding is 2^(-RP). + int fbit = (int) GET_MODE_FBIT (mode); + double_int i_add = double_int_zero.set_bit (fbit-1 - INTVAL (xop[2])); + // Lengths of PLUS and AND parts. + int len_add = 0, *plen_add = plen ? &len_add : NULL; + int len_and = 0, *plen_and = plen ? &len_and : NULL; + + // Add-Saturate 1/2 * 2^(-RP). Don't print the label "0:" when printing + // the saturated addition so that we can emit the "rjmp 1f" before the + // "0:" below. + + rtx xadd = const_fixed_from_double_int (i_add, mode); + rtx xpattern, xsrc, op[4]; + + xsrc = SIGNED_FIXED_POINT_MODE_P (mode) + ? gen_rtx_SS_PLUS (mode, xop[1], xadd) + : gen_rtx_US_PLUS (mode, xop[1], xadd); + xpattern = gen_rtx_SET (VOIDmode, xop[0], xsrc); + + op[0] = xop[0]; + op[1] = xop[1]; + op[2] = xadd; + avr_out_plus (xpattern, op, plen_add, NULL, false /* Don't print "0:" */); + + avr_asm_len ("rjmp 1f" CR_TAB + "0:", NULL, plen_add, 1); + + // Keep all bits from RP and higher: ... 2^(-RP) + // Clear all bits from RP+1 and lower: 2^(-RP-1) ... + // Rounding point ^^^^^^^ + // Added above ^^^^^^^^^ + rtx xreg = simplify_gen_subreg (imode, xop[0], mode, 0); + rtx xmask = immed_double_int_const (-i_add - i_add, imode); + + xpattern = gen_rtx_SET (VOIDmode, xreg, gen_rtx_AND (imode, xreg, xmask)); + + op[0] = xreg; + op[1] = xreg; + op[2] = xmask; + op[3] = gen_rtx_SCRATCH (QImode); + avr_out_bitop (xpattern, op, plen_and); + avr_asm_len ("1:", NULL, plen, 0); + + if (plen) + *plen = len_add + len_and; + + return ""; +} + + /* Create RTL split patterns for byte sized rotate expressions. This produces a series of move instructions and considers overlap situations. Overlapping non-HImode operands need a scratch register. */ @@ -7489,7 +7578,8 @@ avr_adjust_insn_length (rtx insn, int len) It is easier to state this in an insn attribute "adjust_len" than to clutter up code here... */ - if (-1 == recog_memoized (insn)) + if (!NONDEBUG_INSN_P (insn) + || -1 == recog_memoized (insn)) { return len; } @@ -7533,6 +7623,7 @@ avr_adjust_insn_length (rtx insn, int len) case ADJUST_LEN_SFRACT: avr_out_fract (insn, op, true, &len); break; case ADJUST_LEN_UFRACT: avr_out_fract (insn, op, false, &len); break; + case ADJUST_LEN_ROUND: avr_out_round (insn, op, &len); break; case ADJUST_LEN_TSTHI: avr_out_tsthi (insn, op, &len); break; case ADJUST_LEN_TSTPSI: avr_out_tstpsi (insn, op, &len); break; diff --git a/gcc/config/avr/avr.h b/gcc/config/avr/avr.h index f223a6148ee17..57e47bf5a525b 100644 --- a/gcc/config/avr/avr.h +++ b/gcc/config/avr/avr.h @@ -250,18 +250,18 @@ enum reg_class { #define REG_CLASS_CONTENTS { \ {0x00000000,0x00000000}, /* NO_REGS */ \ {0x00000001,0x00000000}, /* R0_REG */ \ - {3 << REG_X,0x00000000}, /* POINTER_X_REGS, r26 - r27 */ \ - {3 << REG_Y,0x00000000}, /* POINTER_Y_REGS, r28 - r29 */ \ - {3 << REG_Z,0x00000000}, /* POINTER_Z_REGS, r30 - r31 */ \ + {3u << REG_X,0x00000000}, /* POINTER_X_REGS, r26 - r27 */ \ + {3u << REG_Y,0x00000000}, /* POINTER_Y_REGS, r28 - r29 */ \ + {3u << REG_Z,0x00000000}, /* POINTER_Z_REGS, r30 - r31 */ \ {0x00000000,0x00000003}, /* STACK_REG, STACK */ \ - {(3 << REG_Y) | (3 << REG_Z), \ + {(3u << REG_Y) | (3u << REG_Z), \ 0x00000000}, /* BASE_POINTER_REGS, r28 - r31 */ \ - {(3 << REG_X) | (3 << REG_Y) | (3 << REG_Z), \ + {(3u << REG_X) | (3u << REG_Y) | (3u << REG_Z), \ 0x00000000}, /* POINTER_REGS, r26 - r31 */ \ - {(3 << REG_X) | (3 << REG_Y) | (3 << REG_Z) | (3 << REG_W), \ + {(3u << REG_X) | (3u << REG_Y) | (3u << REG_Z) | (3u << REG_W), \ 0x00000000}, /* ADDW_REGS, r24 - r31 */ \ {0x00ff0000,0x00000000}, /* SIMPLE_LD_REGS r16 - r23 */ \ - {(3 << REG_X)|(3 << REG_Y)|(3 << REG_Z)|(3 << REG_W)|(0xff << 16), \ + {(3u << REG_X)|(3u << REG_Y)|(3u << REG_Z)|(3u << REG_W)|(0xffu << 16),\ 0x00000000}, /* LD_REGS, r16 - r31 */ \ {0x0000ffff,0x00000000}, /* NO_LD_REGS r0 - r15 */ \ {0xffffffff,0x00000000}, /* GENERAL_REGS, r0 - r31 */ \ diff --git a/gcc/config/avr/avr.md b/gcc/config/avr/avr.md index e9f5d038f1f4b..5a38e798886c5 100644 --- a/gcc/config/avr/avr.md +++ b/gcc/config/avr/avr.md @@ -89,7 +89,7 @@ (include "constraints.md") ;; Condition code settings. -(define_attr "cc" "none,set_czn,set_zn,set_n,compare,clobber, +(define_attr "cc" "none,set_czn,set_zn,set_vzn,set_n,compare,clobber, plus,ldi" (const_string "none")) @@ -140,7 +140,7 @@ "out_bitop, plus, addto_sp, tsthi, tstpsi, tstsi, compare, compare64, call, mov8, mov16, mov24, mov32, reload_in16, reload_in24, reload_in32, - ufract, sfract, + ufract, sfract, round, xload, lpm, movmem, ashlqi, ashrqi, lshrqi, ashlhi, ashrhi, lshrhi, @@ -351,6 +351,13 @@ push __zero_reg__" [(set_attr "length" "1,1")]) +(define_insn "pushhi1_insn" + [(set (mem:HI (post_dec:HI (reg:HI REG_SP))) + (match_operand:HI 0 "register_operand" "r"))] + "" + "push %B0\;push %A0" + [(set_attr "length" "2")]) + ;; All modes for a multi-byte push. We must include complex modes here too, ;; lest emit_single_push_insn "helpfully" create the auto-inc itself. (define_mode_iterator MPUSH @@ -366,8 +373,42 @@ [(match_operand:MPUSH 0 "" "")] "" { - int i; - for (i = GET_MODE_SIZE (mode) - 1; i >= 0; --i) + if (MEM_P (operands[0]) + && !ADDR_SPACE_GENERIC_P (MEM_ADDR_SPACE (operands[0]))) + { + // Avoid (subreg (mem)) for non-generic address spaces. Because + // of the poor addressing capabilities of these spaces it's better to + // load them in one chunk. And it avoids PR61443. + + operands[0] = copy_to_mode_reg (mode, operands[0]); + } + else if (REG_P (operands[0]) + && IN_RANGE (REGNO (operands[0]), FIRST_VIRTUAL_REGISTER, + LAST_VIRTUAL_REGISTER)) + { + // Byte-wise pushing of virtual regs might result in something like + // + // (set (mem:QI (post_dec:HI (reg:HI 32 SP))) + // (subreg:QI (plus:HI (reg:HI 28) + // (const_int 17)) 0)) + // + // after elimination. This cannot be handled by reload, cf. PR64452. + // Reload virtuals in one chunk. That way it's possible to reload + // above situation and finally + // + // (set (reg:HI **) + // (const_int 17)) + // (set (reg:HI **) + // (plus:HI (reg:HI **) + // (reg:HI 28))) + // (set (mem:HI (post_dec:HI (reg:HI 32 SP)) + // (reg:HI **))) + + emit_insn (gen_pushhi1_insn (operands[0])); + DONE; + } + + for (int i = GET_MODE_SIZE (mode) - 1; i >= 0; --i) { rtx part = simplify_gen_subreg (QImode, operands[0], mode, i); if (part != const0_rtx) @@ -1097,7 +1138,7 @@ inc %0\;inc %0 dec %0\;dec %0" [(set_attr "length" "1,1,1,1,2,2") - (set_attr "cc" "set_czn,set_czn,set_zn,set_zn,set_zn,set_zn")]) + (set_attr "cc" "set_czn,set_czn,set_vzn,set_vzn,set_vzn,set_vzn")]) ;; "addhi3" ;; "addhq3" "adduhq3" @@ -1368,7 +1409,7 @@ dec %0\;dec %0 inc %0\;inc %0" [(set_attr "length" "1,1,1,1,2,2") - (set_attr "cc" "set_czn,set_czn,set_zn,set_zn,set_zn,set_zn")]) + (set_attr "cc" "set_czn,set_czn,set_vzn,set_vzn,set_vzn,set_vzn")]) ;; "subhi3" ;; "subhq3" "subuhq3" @@ -3991,7 +4032,7 @@ "" "neg %0" [(set_attr "length" "1") - (set_attr "cc" "set_zn")]) + (set_attr "cc" "set_vzn")]) (define_insn "*negqihi2" [(set (match_operand:HI 0 "register_operand" "=r") diff --git a/gcc/config/avr/avr.opt b/gcc/config/avr/avr.opt index 6b2e755eeb2ca..4b990775b7fca 100644 --- a/gcc/config/avr/avr.opt +++ b/gcc/config/avr/avr.opt @@ -77,4 +77,4 @@ The device has no SPH special function register. This option will be overridden Waddr-space-convert Warning C Report Var(avr_warn_addr_space_convert) Init(0) -Warn if the address space of an address is change. +Warn if the address space of an address is changed. diff --git a/gcc/config/avr/gen-avr-mmcu-texi.c b/gcc/config/avr/gen-avr-mmcu-texi.c index 55335f98dd953..e69cd419e4e6e 100644 --- a/gcc/config/avr/gen-avr-mmcu-texi.c +++ b/gcc/config/avr/gen-avr-mmcu-texi.c @@ -68,6 +68,7 @@ comparator (const void *va, const void *vb) static void print_mcus (size_t n_mcus) { + int duplicate = 0; size_t i; if (!n_mcus) @@ -78,7 +79,20 @@ print_mcus (size_t n_mcus) printf ("@*@var{mcu}@tie{}="); for (i = 0; i < n_mcus; i++) - printf (" @code{%s}%s", mcu_name[i], i == n_mcus-1 ? ".\n\n" : ","); + { + printf (" @code{%s}%s", mcu_name[i], i == n_mcus-1 ? ".\n\n" : ","); + + if (i && !strcmp (mcu_name[i], mcu_name[i-1])) + { + /* Sanity-check: Fail on devices that are present more than once. */ + + duplicate = 1; + fprintf (stderr, "error: duplicate device: %s\n", mcu_name[i]); + } + } + + if (duplicate) + exit (1); } int main (void) diff --git a/gcc/config/avr/t-multilib b/gcc/config/avr/t-multilib index 6b1db60927185..d3fb28cd6ab77 100644 --- a/gcc/config/avr/t-multilib +++ b/gcc/config/avr/t-multilib @@ -135,7 +135,6 @@ MULTILIB_MATCHES = \ mmcu?avr5=mmcu?atmega169a \ mmcu?avr5=mmcu?atmega169p \ mmcu?avr5=mmcu?atmega169pa \ - mmcu?avr5=mmcu?atmega16hva \ mmcu?avr5=mmcu?atmega16hvb \ mmcu?avr5=mmcu?atmega16hvbrevb \ mmcu?avr5=mmcu?atmega16m1 \ @@ -143,7 +142,6 @@ MULTILIB_MATCHES = \ mmcu?avr5=mmcu?atmega26hvg \ mmcu?avr5=mmcu?atmega32a \ mmcu?avr5=mmcu?atmega32 \ - mmcu?avr5=mmcu?atmega32a \ mmcu?avr5=mmcu?atmega323 \ mmcu?avr5=mmcu?atmega324a \ mmcu?avr5=mmcu?atmega324p \ @@ -189,7 +187,6 @@ MULTILIB_MATCHES = \ mmcu?avr5=mmcu?atmega6490 \ mmcu?avr5=mmcu?atmega16hva \ mmcu?avr5=mmcu?atmega16hva2 \ - mmcu?avr5=mmcu?atmega16hvb \ mmcu?avr5=mmcu?atmega32hvb \ mmcu?avr5=mmcu?atmega6490a \ mmcu?avr5=mmcu?atmega6490p \ @@ -198,23 +195,13 @@ MULTILIB_MATCHES = \ mmcu?avr5=mmcu?atmega64hve \ mmcu?avr5=mmcu?atmega64rfa2 \ mmcu?avr5=mmcu?atmega64rfr2 \ - mmcu?avr5=mmcu?atmega32hvb \ mmcu?avr5=mmcu?atmega32hvbrevb \ - mmcu?avr5=mmcu?atmega16hva2 \ mmcu?avr5=mmcu?atmega48hvf \ mmcu?avr5=mmcu?at90can32 \ mmcu?avr5=mmcu?at90can64 \ mmcu?avr5=mmcu?at90pwm161 \ mmcu?avr5=mmcu?at90pwm216 \ mmcu?avr5=mmcu?at90pwm316 \ - mmcu?avr5=mmcu?atmega32c1 \ - mmcu?avr5=mmcu?atmega64c1 \ - mmcu?avr5=mmcu?atmega16m1 \ - mmcu?avr5=mmcu?atmega32m1 \ - mmcu?avr5=mmcu?atmega64m1 \ - mmcu?avr5=mmcu?atmega16u4 \ - mmcu?avr5=mmcu?atmega32u4 \ - mmcu?avr5=mmcu?atmega32u6 \ mmcu?avr5=mmcu?at90scr100 \ mmcu?avr5=mmcu?at90usb646 \ mmcu?avr5=mmcu?at90usb647 \ diff --git a/gcc/config/cris/cris.md b/gcc/config/cris/cris.md index 8a7f0bfdd7060..b3e9f0494b809 100644 --- a/gcc/config/cris/cris.md +++ b/gcc/config/cris/cris.md @@ -758,7 +758,7 @@ (match_operand:SI 1 "const_int_operand" "")) (match_operand:SI 2 "register_operand" ""))]) (match_operand 3 "register_operand" "")) - (set (match_operand:SI 4 "register_operand" "") + (set (match_operand:SI 4 "cris_nonsp_register_operand" "") (plus:SI (mult:SI (match_dup 0) (match_dup 1)) (match_dup 2)))])] @@ -859,7 +859,7 @@ (match_operand:SI 0 "cris_bdap_operand" "") (match_operand:SI 1 "cris_bdap_operand" ""))]) (match_operand 2 "register_operand" "")) - (set (match_operand:SI 3 "register_operand" "") + (set (match_operand:SI 3 "cris_nonsp_register_operand" "") (plus:SI (match_dup 0) (match_dup 1)))])] "reload_completed && reg_overlap_mentioned_p (operands[3], operands[2])" [(set (match_dup 4) (match_dup 2)) @@ -3960,7 +3960,7 @@ ;; up. (define_split - [(set (match_operand 0 "register_operand" "") + [(set (match_operand 0 "cris_nonsp_register_operand" "") (match_operator 4 "cris_operand_extend_operator" [(match_operand 1 "register_operand" "") @@ -3990,7 +3990,7 @@ ;; Call this op-extend-split-rx=rz (define_split - [(set (match_operand 0 "register_operand" "") + [(set (match_operand 0 "cris_nonsp_register_operand" "") (match_operator 4 "cris_plus_or_bound_operator" [(match_operand 1 "register_operand" "") @@ -4018,7 +4018,7 @@ ;; Call this op-extend-split-swapped (define_split - [(set (match_operand 0 "register_operand" "") + [(set (match_operand 0 "cris_nonsp_register_operand" "") (match_operator 4 "cris_plus_or_bound_operator" [(match_operator @@ -4044,7 +4044,7 @@ ;; bound. Call this op-extend-split-swapped-rx=rz. (define_split - [(set (match_operand 0 "register_operand" "") + [(set (match_operand 0 "cris_nonsp_register_operand" "") (match_operator 4 "cris_plus_or_bound_operator" [(match_operator @@ -4075,7 +4075,7 @@ ;; Call this op-extend. (define_split - [(set (match_operand 0 "register_operand" "") + [(set (match_operand 0 "cris_nonsp_register_operand" "") (match_operator 3 "cris_orthogonal_operator" [(match_operand 1 "register_operand" "") @@ -4099,7 +4099,7 @@ ;; Call this op-split-rx=rz (define_split - [(set (match_operand 0 "register_operand" "") + [(set (match_operand 0 "cris_nonsp_register_operand" "") (match_operator 3 "cris_commutative_orth_op" [(match_operand 2 "memory_operand" "") @@ -4123,7 +4123,7 @@ ;; Call this op-split-swapped. (define_split - [(set (match_operand 0 "register_operand" "") + [(set (match_operand 0 "cris_nonsp_register_operand" "") (match_operator 3 "cris_commutative_orth_op" [(match_operand 1 "register_operand" "") @@ -4146,7 +4146,7 @@ ;; Call this op-split-swapped-rx=rz. (define_split - [(set (match_operand 0 "register_operand" "") + [(set (match_operand 0 "cris_nonsp_register_operand" "") (match_operator 3 "cris_orthogonal_operator" [(match_operand 2 "memory_operand" "") @@ -4555,10 +4555,11 @@ ;; We're not allowed to generate copies of registers with different mode ;; until after reload; copying pseudos upsets reload. CVS as of ;; 2001-08-24, unwind-dw2-fde.c, _Unwind_Find_FDE ICE in -;; cselib_invalidate_regno. +;; cselib_invalidate_regno. Also, don't do this for the stack-pointer, +;; as we don't want it set temporarily to an invalid value. (define_split ; indir_to_reg_split - [(set (match_operand 0 "register_operand" "") + [(set (match_operand 0 "cris_nonsp_register_operand" "") (match_operand 1 "indirect_operand" ""))] "reload_completed && REG_P (operands[0]) @@ -4574,7 +4575,7 @@ ;; As the above, but MOVS and MOVU. (define_split - [(set (match_operand 0 "register_operand" "") + [(set (match_operand 0 "cris_nonsp_register_operand" "") (match_operator 4 "cris_extend_operator" [(match_operand 1 "indirect_operand" "")]))] diff --git a/gcc/config/cris/predicates.md b/gcc/config/cris/predicates.md index 040482ba9d1a0..2acd02f8ad9cf 100644 --- a/gcc/config/cris/predicates.md +++ b/gcc/config/cris/predicates.md @@ -76,6 +76,10 @@ (match_test "cris_simple_address_operand (XEXP (op, 0), Pmode)")))) +(define_predicate "cris_nonsp_register_operand" + (and (match_operand 0 "register_operand") + (match_test "op != stack_pointer_rtx"))) + ;; The caller needs to use :SI. (define_predicate "cris_bdap_sign_extend_operand" ; Disabled until diff --git a/gcc/config/darwin-c.c b/gcc/config/darwin-c.c index ed547b27468d7..88ba752656ec1 100644 --- a/gcc/config/darwin-c.c +++ b/gcc/config/darwin-c.c @@ -571,21 +571,34 @@ find_subframework_header (cpp_reader *pfile, const char *header, cpp_dir **dirp) } /* Return the value of darwin_macosx_version_min suitable for the - __ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__ macro, - so '10.4.2' becomes 1040. The lowest digit is always zero. + __ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__ macro, so '10.4.2' + becomes 1040 and '10.10.0' becomes 101000. The lowest digit is + always zero, as is the second lowest for '10.10.x' and above. Print a warning if the version number can't be understood. */ static const char * version_as_macro (void) { - static char result[] = "1000"; + static char result[7] = "1000"; + int minorDigitIdx; if (strncmp (darwin_macosx_version_min, "10.", 3) != 0) goto fail; if (! ISDIGIT (darwin_macosx_version_min[3])) goto fail; - result[2] = darwin_macosx_version_min[3]; - if (darwin_macosx_version_min[4] != '\0' - && darwin_macosx_version_min[4] != '.') + + minorDigitIdx = 3; + result[2] = darwin_macosx_version_min[minorDigitIdx++]; + if (ISDIGIT (darwin_macosx_version_min[minorDigitIdx])) + { + /* Starting with OS X 10.10, the macro ends '00' rather than '0', + i.e. 10.10.x becomes 101000 rather than 10100. */ + result[3] = darwin_macosx_version_min[minorDigitIdx++]; + result[4] = '0'; + result[5] = '0'; + result[6] = '\0'; + } + if (darwin_macosx_version_min[minorDigitIdx] != '\0' + && darwin_macosx_version_min[minorDigitIdx] != '.') goto fail; return result; diff --git a/gcc/config/darwin-driver.c b/gcc/config/darwin-driver.c index 41076002308fa..33fccb6746f67 100644 --- a/gcc/config/darwin-driver.c +++ b/gcc/config/darwin-driver.c @@ -29,8 +29,8 @@ along with GCC; see the file COPYING3. If not see #include #include "xregex.h" -static bool -darwin_find_version_from_kernel (char *new_flag) +static char * +darwin_find_version_from_kernel (void) { char osversion[32]; size_t osversion_len = sizeof (osversion) - 1; @@ -39,6 +39,7 @@ darwin_find_version_from_kernel (char *new_flag) char minor_vers[6]; char * version_p; char * version_pend; + char * new_flag; /* Determine the version of the running OS. If we can't, warn user, and do nothing. */ @@ -46,7 +47,7 @@ darwin_find_version_from_kernel (char *new_flag) &osversion_len, NULL, 0) == -1) { warning (0, "sysctl for kern.osversion failed: %m"); - return false; + return NULL; } /* Try to parse the first two parts of the OS version number. Warn @@ -57,8 +58,6 @@ darwin_find_version_from_kernel (char *new_flag) version_p = osversion + 1; if (ISDIGIT (*version_p)) major_vers = major_vers * 10 + (*version_p++ - '0'); - if (major_vers > 4 + 9) - goto parse_failed; if (*version_p++ != '.') goto parse_failed; version_pend = strchr(version_p, '.'); @@ -74,17 +73,16 @@ darwin_find_version_from_kernel (char *new_flag) if (major_vers - 4 <= 4) /* On 10.4 and earlier, the old linker is used which does not support three-component system versions. */ - sprintf (new_flag, "10.%d", major_vers - 4); + asprintf (&new_flag, "10.%d", major_vers - 4); else - sprintf (new_flag, "10.%d.%s", major_vers - 4, - minor_vers); + asprintf (&new_flag, "10.%d.%s", major_vers - 4, minor_vers); - return true; + return new_flag; parse_failed: warning (0, "couldn%'t understand kern.osversion %q.*s", (int) osversion_len, osversion); - return false; + return NULL; } #endif @@ -105,7 +103,7 @@ darwin_default_min_version (unsigned int *decoded_options_count, const unsigned int argc = *decoded_options_count; struct cl_decoded_option *const argv = *decoded_options; unsigned int i; - static char new_flag[sizeof ("10.0.0") + 6]; + const char *new_flag; /* If the command-line is empty, just return. */ if (argc <= 1) @@ -142,16 +140,16 @@ darwin_default_min_version (unsigned int *decoded_options_count, #ifndef CROSS_DIRECTORY_STRUCTURE - /* Try to find the version from the kernel, if we fail - we print a message - and give up. */ - if (!darwin_find_version_from_kernel (new_flag)) - return; + /* Try to find the version from the kernel, if we fail - we print a message + and give up. */ + new_flag = darwin_find_version_from_kernel (); + if (!new_flag) + return; #else - /* For cross-compilers, default to the target OS version. */ - - strncpy (new_flag, DEF_MIN_OSX_VERSION, sizeof (new_flag)); + /* For cross-compilers, default to the target OS version. */ + new_flag = DEF_MIN_OSX_VERSION; #endif /* CROSS_DIRECTORY_STRUCTURE */ @@ -165,7 +163,6 @@ darwin_default_min_version (unsigned int *decoded_options_count, memcpy (*decoded_options + 2, argv + 1, (argc - 1) * sizeof (struct cl_decoded_option)); return; - } /* Translate -filelist and -framework options in *DECODED_OPTIONS diff --git a/gcc/config/darwin-protos.h b/gcc/config/darwin-protos.h index 0755e94692ad3..70b7fb00959b3 100644 --- a/gcc/config/darwin-protos.h +++ b/gcc/config/darwin-protos.h @@ -25,6 +25,7 @@ extern void machopic_validate_stub_or_non_lazy_ptr (const char *); extern void machopic_output_function_base_name (FILE *); extern const char *machopic_indirection_name (rtx, bool); extern const char *machopic_mcount_stub_name (void); +extern bool machopic_should_output_picbase_label (void); #ifdef RTX_CODE diff --git a/gcc/config/darwin.c b/gcc/config/darwin.c index a049a5d079623..d4700034699e6 100644 --- a/gcc/config/darwin.c +++ b/gcc/config/darwin.c @@ -369,14 +369,13 @@ machopic_gen_offset (rtx orig) static GTY(()) const char * function_base_func_name; static GTY(()) int current_pic_label_num; +static GTY(()) int emitted_pic_label_num; -void -machopic_output_function_base_name (FILE *file) +static void +update_pic_label_number_if_needed (void) { const char *current_name; - /* If dynamic-no-pic is on, we should not get here. */ - gcc_assert (!MACHO_DYNAMIC_NO_PIC_P); /* When we are generating _get_pc thunks within stubs, there is no current function. */ if (current_function_decl) @@ -394,7 +393,28 @@ machopic_output_function_base_name (FILE *file) ++current_pic_label_num; function_base_func_name = "L_machopic_stub_dummy"; } - fprintf (file, "L%011d$pb", current_pic_label_num); +} + +void +machopic_output_function_base_name (FILE *file) +{ + /* If dynamic-no-pic is on, we should not get here. */ + gcc_assert (!MACHO_DYNAMIC_NO_PIC_P); + + update_pic_label_number_if_needed (); + fprintf (file, "L%d$pb", current_pic_label_num); +} + +bool +machopic_should_output_picbase_label (void) +{ + update_pic_label_number_if_needed (); + + if (current_pic_label_num == emitted_pic_label_num) + return false; + + emitted_pic_label_num = current_pic_label_num; + return true; } /* The suffix attached to non-lazy pointer symbols. */ @@ -1309,6 +1329,9 @@ is_objc_metadata (tree decl) return NULL_TREE; } +static int classes_seen; +static int objc_metadata_seen; + /* Return the section required for Objective C ABI 2 metadata. */ static section * darwin_objc2_section (tree decl ATTRIBUTE_UNUSED, tree meta, section * base) @@ -1318,12 +1341,9 @@ darwin_objc2_section (tree decl ATTRIBUTE_UNUSED, tree meta, section * base) gcc_assert (TREE_CODE (ident) == IDENTIFIER_NODE); p = IDENTIFIER_POINTER (ident); - /* If we are in LTO, then we don't know the state of flag_next_runtime - or flag_objc_abi when the code was generated. We set these from the - meta-data - which is needed to deal with const string constructors. */ + gcc_checking_assert (flag_next_runtime == 1 && flag_objc_abi == 2); - flag_next_runtime = 1; - flag_objc_abi = 2; + objc_metadata_seen = 1; if (base == data_section) base = darwin_sections[objc2_metadata_section]; @@ -1346,7 +1366,10 @@ darwin_objc2_section (tree decl ATTRIBUTE_UNUSED, tree meta, section * base) else if (!strncmp (p, "V2_NLCL", 7)) return darwin_sections[objc2_nonlazy_class_section]; else if (!strncmp (p, "V2_CLAB", 7)) - return darwin_sections[objc2_classlist_section]; + { + classes_seen = 1; + return darwin_sections[objc2_classlist_section]; + } else if (!strncmp (p, "V2_SRFS", 7)) return darwin_sections[objc2_selector_refs_section]; else if (!strncmp (p, "V2_NLCA", 7)) @@ -1381,12 +1404,9 @@ darwin_objc1_section (tree decl ATTRIBUTE_UNUSED, tree meta, section * base) gcc_assert (TREE_CODE (ident) == IDENTIFIER_NODE); p = IDENTIFIER_POINTER (ident); - /* If we are in LTO, then we don't know the state of flag_next_runtime - or flag_objc_abi when the code was generated. We set these from the - meta-data - which is needed to deal with const string constructors. */ - flag_next_runtime = 1; - if (!global_options_set.x_flag_objc_abi) - flag_objc_abi = 1; + gcc_checking_assert (flag_next_runtime == 1 && flag_objc_abi < 2); + + objc_metadata_seen = 1; /* String sections first, cos there are lots of strings. */ if (!strncmp (p, "V1_STRG", 7)) @@ -1399,7 +1419,10 @@ darwin_objc1_section (tree decl ATTRIBUTE_UNUSED, tree meta, section * base) return darwin_sections[objc_meth_var_types_section]; else if (!strncmp (p, "V1_CLAS", 7)) - return darwin_sections[objc_class_section]; + { + classes_seen = 1; + return darwin_sections[objc_class_section]; + } else if (!strncmp (p, "V1_META", 7)) return darwin_sections[objc_meta_class_section]; else if (!strncmp (p, "V1_CATG", 7)) @@ -1583,8 +1606,6 @@ machopic_select_section (tree decl, if (TREE_CODE (name) == TYPE_DECL) name = DECL_NAME (name); - /* FIXME: This is unsatisfactory for LTO, since it relies on other - metadata determining the source FE. */ if (!strcmp (IDENTIFIER_POINTER (name), "__builtin_ObjCString")) { if (flag_next_runtime) @@ -2825,6 +2846,33 @@ darwin_file_end (void) finalize_ctors (); if (!vec_safe_is_empty (dtors)) finalize_dtors (); + + /* If we are expecting to output NeXT ObjC meta-data, (and we actually see + some) then we output the fix-and-continue marker (Image Info). + This applies to Objective C, Objective C++ and LTO with either language + as part of the input. */ + if (flag_next_runtime && objc_metadata_seen) + { + unsigned int flags = 0; + if (flag_objc_abi >= 2) + { + flags = 16; + output_section_asm_op + (darwin_sections[objc2_image_info_section]->unnamed.data); + } + else + output_section_asm_op + (darwin_sections[objc_image_info_section]->unnamed.data); + + ASM_OUTPUT_ALIGN (asm_out_file, 2); + fputs ("L_OBJC_ImageInfo:\n", asm_out_file); + + flags |= (flag_replace_objc_classes && classes_seen) ? 1 : 0; + flags |= flag_objc_gc ? 2 : 0; + + fprintf (asm_out_file, "\t.long\t0\n\t.long\t%u\n", flags); + } + machopic_finish (asm_out_file); if (strcmp (lang_hooks.name, "GNU C++") == 0) { diff --git a/gcc/config/elfos.h b/gcc/config/elfos.h index 438302345cf11..43aab7362f3d5 100644 --- a/gcc/config/elfos.h +++ b/gcc/config/elfos.h @@ -287,7 +287,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see /* Write the extra assembler code needed to declare an object properly. */ #ifdef HAVE_GAS_GNU_UNIQUE_OBJECT -#define USE_GNU_UNIQUE_OBJECT 1 +#define USE_GNU_UNIQUE_OBJECT flag_gnu_unique #else #define USE_GNU_UNIQUE_OBJECT 0 #endif diff --git a/gcc/config/epiphany/epiphany.c b/gcc/config/epiphany/epiphany.c index 782dc7b3e753e..fb565e833f278 100644 --- a/gcc/config/epiphany/epiphany.c +++ b/gcc/config/epiphany/epiphany.c @@ -181,6 +181,8 @@ epiphany_init (void) = { &pass_split_all_insns.pass, "mode_sw", 1, PASS_POS_INSERT_AFTER }; + static const int num_modes[] = NUM_MODES_FOR_MODE_SWITCHING; +#define N_ENTITIES ARRAY_SIZE (num_modes) epiphany_init_reg_tables (); @@ -196,6 +198,8 @@ epiphany_init (void) register_pass (&mode_sw3_info); register_pass (&insert_use_info); register_pass (&mode_sw2_info); + /* Verify that NUM_MODES_FOR_MODE_SWITCHING has one value per entity. */ + gcc_assert (N_ENTITIES == EPIPHANY_MSW_ENTITY_NUM); #if 1 /* As long as peep2_rescan is not implemented, (see http://gcc.gnu.org/ml/gcc-patches/2011-10/msg02819.html,) @@ -1712,18 +1716,28 @@ epiphany_expand_prologue (void) register save. */ if (current_frame_info.last_slot >= 0) { + rtx ip, mem2, insn, note; + gcc_assert (current_frame_info.last_slot != GPR_FP || (!current_frame_info.need_fp && current_frame_info.first_slot < 0)); off = GEN_INT (-current_frame_info.last_slot_offset); mem = gen_frame_mem (BLKmode, gen_rtx_PLUS (Pmode, stack_pointer_rtx, off)); - reg = gen_rtx_REG (Pmode, GPR_IP); - frame_move_insn (reg, off); - frame_insn (gen_stack_adjust_str - (gen_frame_mem (word_mode, stack_pointer_rtx), - gen_rtx_REG (word_mode, current_frame_info.last_slot), - reg, mem)); + ip = gen_rtx_REG (Pmode, GPR_IP); + frame_move_insn (ip, off); + reg = gen_rtx_REG (word_mode, current_frame_info.last_slot), + mem2 = gen_frame_mem (word_mode, stack_pointer_rtx), + insn = frame_insn (gen_stack_adjust_str (mem2, reg, ip, mem)); + /* Instruction scheduling can separate the instruction setting IP from + INSN so that dwarf2out_frame_debug_expr becomes confused what the + temporary register is. Example: _gcov.o */ + note = gen_rtx_SET (VOIDmode, stack_pointer_rtx, + gen_rtx_PLUS (Pmode, stack_pointer_rtx, off)); + note = gen_rtx_PARALLEL (VOIDmode, + gen_rtvec (2, gen_rtx_SET (VOIDmode, mem2, reg), + note)); + add_reg_note (insn, REG_FRAME_RELATED_EXPR, note); } /* If there is only one or no register to save, yet we have a large frame, use an add. */ @@ -1741,44 +1755,6 @@ epiphany_expand_prologue (void) } frame_insn (gen_stack_adjust_add (off, mem)); } - - /* Mode switching uses get_hard_reg_initial_val after - emit_initial_value_sets, so we have to fix this up now. */ - save_config = has_hard_reg_initial_val (SImode, CONFIG_REGNUM); - if (save_config) - { - if (REG_P (save_config)) - { - if (REGNO (save_config) >= FIRST_PSEUDO_REGISTER) - gcc_assert (!df_regs_ever_live_p (REGNO (save_config))); - else - frame_move_insn (save_config, - get_hard_reg_initial_reg (save_config)); - } - else - { - rtx save_dst = save_config; - - reg = gen_rtx_REG (SImode, GPR_IP); - gcc_assert (MEM_P (save_dst)); - if (!memory_operand (save_dst, SImode)) - { - rtx addr = XEXP (save_dst, 0); - rtx reg2 = gen_rtx_REG (SImode, GPR_16); - - gcc_assert (GET_CODE (addr) == PLUS); - gcc_assert (XEXP (addr, 0) == hard_frame_pointer_rtx - || XEXP (addr, 0) == stack_pointer_rtx); - emit_move_insn (reg2, XEXP (addr, 1)); - save_dst - = replace_equiv_address (save_dst, - gen_rtx_PLUS (Pmode, XEXP (addr, 0), - reg2)); - } - emit_move_insn (reg, get_hard_reg_initial_reg (save_config)); - emit_move_insn (save_dst, reg); - } - } } void @@ -2239,6 +2215,7 @@ epiphany_optimize_mode_switching (int entity) { case EPIPHANY_MSW_ENTITY_AND: case EPIPHANY_MSW_ENTITY_OR: + case EPIPHANY_MSW_ENTITY_CONFIG: return true; case EPIPHANY_MSW_ENTITY_NEAREST: case EPIPHANY_MSW_ENTITY_TRUNC: @@ -2257,7 +2234,8 @@ epiphany_optimize_mode_switching (int entity) int epiphany_mode_priority_to_mode (int entity, unsigned priority) { - if (entity == EPIPHANY_MSW_ENTITY_AND || entity == EPIPHANY_MSW_ENTITY_OR) + if (entity == EPIPHANY_MSW_ENTITY_AND || entity == EPIPHANY_MSW_ENTITY_OR + || entity== EPIPHANY_MSW_ENTITY_CONFIG) return priority; if (priority > 3) switch (priority) @@ -2309,7 +2287,8 @@ epiphany_mode_needed (int entity, rtx insn) if (recog_memoized (insn) < 0) { if (entity == EPIPHANY_MSW_ENTITY_AND - || entity == EPIPHANY_MSW_ENTITY_OR) + || entity == EPIPHANY_MSW_ENTITY_OR + || entity == EPIPHANY_MSW_ENTITY_CONFIG) return 2; return FP_MODE_NONE; } @@ -2318,9 +2297,24 @@ epiphany_mode_needed (int entity, rtx insn) switch (entity) { case EPIPHANY_MSW_ENTITY_AND: - return mode != FP_MODE_INT ? 1 : 2; + return mode != FP_MODE_NONE && mode != FP_MODE_INT ? 1 : 2; case EPIPHANY_MSW_ENTITY_OR: return mode == FP_MODE_INT ? 1 : 2; + case EPIPHANY_MSW_ENTITY_CONFIG: + /* We must know/save config before we set it to something else. + Where we need the original value, we are fine with having it + just unchanged from the function start. + Because of the nature of the mode switching optimization, + a restore will be dominated by a clobber. */ + if (mode != FP_MODE_NONE && mode != FP_MODE_CALLER) + return 1; + /* A cpecial case are abnormal edges, which are deemed to clobber + the mode as well. We need to pin this effect on a actually + dominating insn, and one where the frame can be accessed, too, in + case the pseudo used to save CONFIG doesn't get a hard register. */ + if (CALL_P (insn) && find_reg_note (insn, REG_EH_REGION, NULL_RTX)) + return 1; + return 2; case EPIPHANY_MSW_ENTITY_ROUND_KNOWN: if (recog_memoized (insn) == CODE_FOR_set_fp_mode) mode = (enum attr_fp_mode) epiphany_mode_after (entity, mode, insn); @@ -2364,6 +2358,10 @@ epiphany_mode_entry_exit (int entity, bool exit) if (exit) return normal_mode == FP_MODE_INT ? 1 : 2; return 0; + case EPIPHANY_MSW_ENTITY_CONFIG: + if (exit) + return 2; + return normal_mode == FP_MODE_CALLER ? 0 : 1; case EPIPHANY_MSW_ENTITY_ROUND_UNKNOWN: if (normal_mode == FP_MODE_ROUND_NEAREST || normal_mode == FP_MODE_ROUND_TRUNC) @@ -2390,6 +2388,18 @@ epiphany_mode_after (int entity, int last_mode, rtx insn) return 0; return last_mode; } + /* If there is an abnormal edge, we don't want the config register to + be 'saved' again at the destination. + The frame pointer adjustment is inside a PARALLEL because of the + flags clobber. */ + if (entity == EPIPHANY_MSW_ENTITY_CONFIG && NONJUMP_INSN_P (insn) + && GET_CODE (PATTERN (insn)) == PARALLEL + && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET + && SET_DEST (XVECEXP (PATTERN (insn), 0, 0)) == frame_pointer_rtx) + { + gcc_assert (cfun->has_nonlocal_label); + return 1; + } if (recog_memoized (insn) < 0) return last_mode; if (get_attr_fp_mode (insn) == FP_MODE_ROUND_UNKNOWN @@ -2443,12 +2453,25 @@ emit_set_fp_mode (int entity, int mode, HARD_REG_SET regs_live ATTRIBUTE_UNUSED) emit_move_insn (MACHINE_FUNCTION (cfun)->or_mask, GEN_INT(0x00080000)); return; } + else if (entity == EPIPHANY_MSW_ENTITY_CONFIG) + { + /* Mode switching optimization is done after emit_initial_value_sets, + so we have to take care of CONFIG_REGNUM here. */ + gcc_assert (mode >= 0 && mode <= 2); + rtx save = get_hard_reg_initial_val (SImode, CONFIG_REGNUM); + if (mode == 1) + emit_insn (gen_save_config (save)); + return; + } fp_mode = (enum attr_fp_mode) mode; src = NULL_RTX; switch (fp_mode) { case FP_MODE_CALLER: + /* The EPIPHANY_MSW_ENTITY_CONFIG processing must come later + so that the config save gets inserted before the first use. */ + gcc_assert (entity > EPIPHANY_MSW_ENTITY_CONFIG); src = get_hard_reg_initial_val (SImode, CONFIG_REGNUM); mask = MACHINE_FUNCTION (cfun)->and_mask; break; diff --git a/gcc/config/epiphany/epiphany.h b/gcc/config/epiphany/epiphany.h index 42b16300284c8..5d91bd4d48146 100644 --- a/gcc/config/epiphany/epiphany.h +++ b/gcc/config/epiphany/epiphany.h @@ -895,7 +895,8 @@ enum epiphany_function_type finally an entity that runs in a second mode switching pass to resolve FP_MODE_ROUND_UNKNOWN. */ #define NUM_MODES_FOR_MODE_SWITCHING \ - { 2, 2, FP_MODE_NONE, FP_MODE_NONE, FP_MODE_NONE, FP_MODE_NONE, FP_MODE_NONE } + { 2, 2, 2, \ + FP_MODE_NONE, FP_MODE_NONE, FP_MODE_NONE, FP_MODE_NONE, FP_MODE_NONE } #define MODE_NEEDED(ENTITY, INSN) epiphany_mode_needed((ENTITY), (INSN)) @@ -917,11 +918,13 @@ enum { EPIPHANY_MSW_ENTITY_AND, EPIPHANY_MSW_ENTITY_OR, + EPIPHANY_MSW_ENTITY_CONFIG, /* 1 means config is known or saved. */ EPIPHANY_MSW_ENTITY_NEAREST, EPIPHANY_MSW_ENTITY_TRUNC, EPIPHANY_MSW_ENTITY_ROUND_UNKNOWN, EPIPHANY_MSW_ENTITY_ROUND_KNOWN, - EPIPHANY_MSW_ENTITY_FPU_OMNIBUS + EPIPHANY_MSW_ENTITY_FPU_OMNIBUS, + EPIPHANY_MSW_ENTITY_NUM }; extern int epiphany_normal_fp_rounding; diff --git a/gcc/config/epiphany/epiphany.md b/gcc/config/epiphany/epiphany.md index 6375d3f8c97c9..1b758b51130d8 100644 --- a/gcc/config/epiphany/epiphany.md +++ b/gcc/config/epiphany/epiphany.md @@ -1432,6 +1432,16 @@ [(set_attr "type" "flow") (set_attr "length" "20,4")]) +(define_insn_and_split "save_config" + [(set (match_operand:SI 0 "gpr_operand" "=r") (reg:SI CONFIG_REGNUM)) + (use (reg:SI FP_NEAREST_REGNUM)) + (use (reg:SI FP_TRUNCATE_REGNUM)) + (use (reg:SI FP_ANYFP_REGNUM))] + "" + "#" + "reload_completed" + [(set (match_dup 0) (reg:SI CONFIG_REGNUM))]) + (define_insn_and_split "set_fp_mode" [(set (reg:SI FP_NEAREST_REGNUM) (match_operand:SI 0 "set_fp_mode_operand" "rCfm")) diff --git a/gcc/config/i386/avx2intrin.h b/gcc/config/i386/avx2intrin.h index 801867ecd4f7b..006c6240785f2 100644 --- a/gcc/config/i386/avx2intrin.h +++ b/gcc/config/i386/avx2intrin.h @@ -637,6 +637,13 @@ _mm256_sign_epi32 (__m256i __X, __m256i __Y) } #ifdef __OPTIMIZE__ +extern __inline __m256i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_bslli_epi128 (__m256i __A, const int __N) +{ + return (__m256i)__builtin_ia32_pslldqi256 (__A, __N * 8); +} + extern __inline __m256i __attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) _mm256_slli_si256 (__m256i __A, const int __N) @@ -644,6 +651,8 @@ _mm256_slli_si256 (__m256i __A, const int __N) return (__m256i)__builtin_ia32_pslldqi256 (__A, __N * 8); } #else +#define _mm256_bslli_epi128(A, N) \ + ((__m256i)__builtin_ia32_pslldqi256 ((__m256i)(A), (int)(N) * 8)) #define _mm256_slli_si256(A, N) \ ((__m256i)__builtin_ia32_pslldqi256 ((__m256i)(A), (int)(N) * 8)) #endif @@ -719,6 +728,13 @@ _mm256_sra_epi32 (__m256i __A, __m128i __B) } #ifdef __OPTIMIZE__ +extern __inline __m256i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_bsrli_epi128 (__m256i __A, const int __N) +{ + return (__m256i)__builtin_ia32_psrldqi256 (__A, __N * 8); +} + extern __inline __m256i __attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) _mm256_srli_si256 (__m256i __A, const int __N) @@ -726,6 +742,8 @@ _mm256_srli_si256 (__m256i __A, const int __N) return (__m256i)__builtin_ia32_psrldqi256 (__A, __N * 8); } #else +#define _mm256_bsrli_epi128(A, N) \ + ((__m256i)__builtin_ia32_psrldqi256 ((__m256i)(A), (int)(N) * 8)) #define _mm256_srli_si256(A, N) \ ((__m256i)__builtin_ia32_psrldqi256 ((__m256i)(A), (int)(N) * 8)) #endif @@ -921,7 +939,7 @@ _mm256_broadcastsd_pd (__m128d __X) extern __inline __m256i __attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) -_mm_broadcastsi128_si256 (__m128i __X) +_mm256_broadcastsi128_si256 (__m128i __X) { return (__m256i) __builtin_ia32_vbroadcastsi256 ((__v2di)__X); } diff --git a/gcc/config/i386/bmiintrin.h b/gcc/config/i386/bmiintrin.h index 0087f5c06e004..fc7f2ec221213 100644 --- a/gcc/config/i386/bmiintrin.h +++ b/gcc/config/i386/bmiintrin.h @@ -38,7 +38,6 @@ __tzcnt_u16 (unsigned short __X) return __builtin_ctzs (__X); } - extern __inline unsigned int __attribute__((__gnu_inline__, __always_inline__, __artificial__)) __andn_u32 (unsigned int __X, unsigned int __Y) { @@ -51,24 +50,47 @@ __bextr_u32 (unsigned int __X, unsigned int __Y) return __builtin_ia32_bextr_u32 (__X, __Y); } +extern __inline unsigned int __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_bextr_u32 (unsigned int __X, unsigned int __Y, unsigned __Z) +{ + return __builtin_ia32_bextr_u32 (__X, ((__Y & 0xff) | ((__Z & 0xff) << 8))); +} + extern __inline unsigned int __attribute__((__gnu_inline__, __always_inline__, __artificial__)) __blsi_u32 (unsigned int __X) { return __X & -__X; } +extern __inline unsigned int __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_blsi_u32 (unsigned int __X) +{ + return __blsi_u32 (__X); +} + extern __inline unsigned int __attribute__((__gnu_inline__, __always_inline__, __artificial__)) __blsmsk_u32 (unsigned int __X) { return __X ^ (__X - 1); } +extern __inline unsigned int __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_blsmsk_u32 (unsigned int __X) +{ + return __blsmsk_u32 (__X); +} + extern __inline unsigned int __attribute__((__gnu_inline__, __always_inline__, __artificial__)) __blsr_u32 (unsigned int __X) { return __X & (__X - 1); } +extern __inline unsigned int __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_blsr_u32 (unsigned int __X) +{ + return __blsr_u32 (__X); +} extern __inline unsigned int __attribute__((__gnu_inline__, __always_inline__, __artificial__)) __tzcnt_u32 (unsigned int __X) @@ -76,6 +98,12 @@ __tzcnt_u32 (unsigned int __X) return __builtin_ctz (__X); } +extern __inline unsigned int __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_tzcnt_u32 (unsigned int __X) +{ + return __builtin_ctz (__X); +} + #ifdef __x86_64__ extern __inline unsigned long long __attribute__((__gnu_inline__, __always_inline__, __artificial__)) @@ -90,30 +118,60 @@ __bextr_u64 (unsigned long long __X, unsigned long long __Y) return __builtin_ia32_bextr_u64 (__X, __Y); } +extern __inline unsigned long long __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_bextr_u64 (unsigned long long __X, unsigned int __Y, unsigned int __Z) +{ + return __builtin_ia32_bextr_u64 (__X, ((__Y & 0xff) | ((__Z & 0xff) << 8))); +} + extern __inline unsigned long long __attribute__((__gnu_inline__, __always_inline__, __artificial__)) __blsi_u64 (unsigned long long __X) { return __X & -__X; } +extern __inline unsigned long long __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_blsi_u64 (unsigned long long __X) +{ + return __blsi_u64 (__X); +} + extern __inline unsigned long long __attribute__((__gnu_inline__, __always_inline__, __artificial__)) __blsmsk_u64 (unsigned long long __X) { return __X ^ (__X - 1); } +extern __inline unsigned long long __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_blsmsk_u64 (unsigned long long __X) +{ + return __blsmsk_u64 (__X); +} + extern __inline unsigned long long __attribute__((__gnu_inline__, __always_inline__, __artificial__)) __blsr_u64 (unsigned long long __X) { return __X & (__X - 1); } +extern __inline unsigned long long __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_blsr_u64 (unsigned long long __X) +{ + return __blsr_u64 (__X); +} + extern __inline unsigned long long __attribute__((__gnu_inline__, __always_inline__, __artificial__)) __tzcnt_u64 (unsigned long long __X) { return __builtin_ctzll (__X); } +extern __inline unsigned long long __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_tzcnt_u64 (unsigned long long __X) +{ + return __builtin_ctzll (__X); +} + #endif /* __x86_64__ */ #endif /* _BMIINTRIN_H_INCLUDED */ diff --git a/gcc/config/i386/driver-i386.c b/gcc/config/i386/driver-i386.c index 256cb6a7df262..87b6a1b4ab6b5 100644 --- a/gcc/config/i386/driver-i386.c +++ b/gcc/config/i386/driver-i386.c @@ -126,6 +126,18 @@ decode_caches_intel (unsigned reg, bool xeon_mp, case 0x0c: level1->sizekb = 16; level1->assoc = 4; level1->line = 32; break; + case 0x0d: + level1->sizekb = 16; level1->assoc = 4; level1->line = 64; + break; + case 0x0e: + level1->sizekb = 24; level1->assoc = 6; level1->line = 64; + break; + case 0x21: + level2->sizekb = 256; level2->assoc = 8; level2->line = 64; + break; + case 0x24: + level2->sizekb = 1024; level2->assoc = 16; level2->line = 64; + break; case 0x2c: level1->sizekb = 32; level1->assoc = 8; level1->line = 64; break; @@ -162,6 +174,9 @@ decode_caches_intel (unsigned reg, bool xeon_mp, case 0x45: level2->sizekb = 2048; level2->assoc = 4; level2->line = 32; break; + case 0x48: + level2->sizekb = 3072; level2->assoc = 12; level2->line = 64; + break; case 0x49: if (xeon_mp) break; @@ -203,6 +218,9 @@ decode_caches_intel (unsigned reg, bool xeon_mp, case 0x7f: level2->sizekb = 512; level2->assoc = 2; level2->line = 64; break; + case 0x80: + level2->sizekb = 512; level2->assoc = 8; level2->line = 64; + break; case 0x82: level2->sizekb = 256; level2->assoc = 8; level2->line = 32; break; @@ -470,6 +488,28 @@ const char *host_detect_local_cpu (int argc, const char **argv) has_xsaveopt = eax & bit_XSAVEOPT; } + /* Check cpuid level of extended features. */ + __cpuid (0x80000000, ext_level, ebx, ecx, edx); + + if (ext_level > 0x80000000) + { + __cpuid (0x80000001, eax, ebx, ecx, edx); + + has_lahf_lm = ecx & bit_LAHF_LM; + has_sse4a = ecx & bit_SSE4a; + has_abm = ecx & bit_ABM; + has_lwp = ecx & bit_LWP; + has_fma4 = ecx & bit_FMA4; + has_xop = ecx & bit_XOP; + has_tbm = ecx & bit_TBM; + has_lzcnt = ecx & bit_LZCNT; + has_prfchw = ecx & bit_PRFCHW; + + has_longmode = edx & bit_LM; + has_3dnowp = edx & bit_3DNOWP; + has_3dnow = edx & bit_3DNOW; + } + /* Get XCR_XFEATURE_ENABLED_MASK register with xgetbv. */ #define XCR_XFEATURE_ENABLED_MASK 0x0 #define XSTATE_FP 0x1 @@ -488,36 +528,18 @@ const char *host_detect_local_cpu (int argc, const char **argv) has_avx2 = 0; has_fma = 0; has_fma4 = 0; + has_f16c = 0; has_xop = 0; has_xsave = 0; has_xsaveopt = 0; } - /* Check cpuid level of extended features. */ - __cpuid (0x80000000, ext_level, ebx, ecx, edx); - - if (ext_level > 0x80000000) - { - __cpuid (0x80000001, eax, ebx, ecx, edx); - - has_lahf_lm = ecx & bit_LAHF_LM; - has_sse4a = ecx & bit_SSE4a; - has_abm = ecx & bit_ABM; - has_lwp = ecx & bit_LWP; - has_fma4 = ecx & bit_FMA4; - has_xop = ecx & bit_XOP; - has_tbm = ecx & bit_TBM; - has_lzcnt = ecx & bit_LZCNT; - has_prfchw = ecx & bit_PRFCHW; - - has_longmode = edx & bit_LM; - has_3dnowp = edx & bit_3DNOWP; - has_3dnow = edx & bit_3DNOW; - } - if (!arch) { - if (vendor == signature_AMD_ebx) + if (vendor == signature_AMD_ebx + || vendor == signature_CENTAUR_ebx + || vendor == signature_CYRIX_ebx + || vendor == signature_NSC_ebx) cache = detect_caches_amd (ext_level); else if (vendor == signature_INTEL_ebx) { @@ -560,6 +582,37 @@ const char *host_detect_local_cpu (int argc, const char **argv) else processor = PROCESSOR_PENTIUM; } + else if (vendor == signature_CENTAUR_ebx) + { + if (arch) + { + switch (family) + { + case 6: + if (model > 9) + /* Use the default detection procedure. */ + processor = PROCESSOR_GENERIC32; + else if (model == 9) + cpu = "c3-2"; + else if (model >= 6) + cpu = "c3"; + else + processor = PROCESSOR_GENERIC32; + break; + case 5: + if (has_3dnow) + cpu = "winchip2"; + else if (has_mmx) + cpu = "winchip2-c6"; + else + processor = PROCESSOR_GENERIC32; + break; + default: + /* We have no idea. */ + processor = PROCESSOR_GENERIC32; + } + } + } else { switch (family) @@ -604,13 +657,18 @@ const char *host_detect_local_cpu (int argc, const char **argv) /* Atom. */ cpu = "atom"; break; + case 0x0f: + /* Merom. */ + case 0x17: + case 0x1d: + /* Penryn. */ + cpu = "core2"; + break; case 0x1a: case 0x1e: case 0x1f: case 0x2e: /* Nehalem. */ - cpu = "corei7"; - break; case 0x25: case 0x2c: case 0x2f: @@ -622,20 +680,25 @@ const char *host_detect_local_cpu (int argc, const char **argv) /* Sandy Bridge. */ cpu = "corei7-avx"; break; - case 0x17: - case 0x1d: - /* Penryn. */ - cpu = "core2"; + case 0x3a: + case 0x3e: + /* Ivy Bridge. */ + cpu = "core-avx-i"; break; - case 0x0f: - /* Merom. */ - cpu = "core2"; + case 0x3c: + case 0x45: + case 0x46: + /* Haswell. */ + cpu = "core-avx2"; break; default: if (arch) { /* This is unknown family 0x6 CPU. */ - if (has_avx) + if (has_avx2) + /* Assume Haswell. */ + cpu = "core-avx2"; + else if (has_avx) /* Assume Sandy Bridge. */ cpu = "corei7-avx"; else if (has_sse4_2) @@ -650,6 +713,11 @@ const char *host_detect_local_cpu (int argc, const char **argv) /* Assume Core 2. */ cpu = "core2"; } + else if (has_longmode) + /* Perhaps some emulator? Assume x86-64, otherwise gcc + -march=native would be unusable for 64-bit compilations, + as all the CPUs below are 32-bit only. */ + cpu = "x86-64"; else if (has_sse3) /* It is Core Duo. */ cpu = "pentium-m"; diff --git a/gcc/config/i386/emmintrin.h b/gcc/config/i386/emmintrin.h index cf404a1353673..3aa88a7c9a5b0 100644 --- a/gcc/config/i386/emmintrin.h +++ b/gcc/config/i386/emmintrin.h @@ -1142,6 +1142,18 @@ _mm_srai_epi32 (__m128i __A, int __B) } #ifdef __OPTIMIZE__ +extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm_bsrli_si128 (__m128i __A, const int __N) +{ + return (__m128i)__builtin_ia32_psrldqi128 (__A, __N * 8); +} + +extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm_bslli_si128 (__m128i __A, const int __N) +{ + return (__m128i)__builtin_ia32_pslldqi128 (__A, __N * 8); +} + extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__)) _mm_srli_si128 (__m128i __A, const int __N) { @@ -1154,6 +1166,10 @@ _mm_slli_si128 (__m128i __A, const int __N) return (__m128i)__builtin_ia32_pslldqi128 (__A, __N * 8); } #else +#define _mm_bsrli_si128(A, N) \ + ((__m128i)__builtin_ia32_psrldqi128 ((__m128i)(A), (int)(N) * 8)) +#define _mm_bslli_si128(A, N) \ + ((__m128i)__builtin_ia32_pslldqi128 ((__m128i)(A), (int)(N) * 8)) #define _mm_srli_si128(A, N) \ ((__m128i)__builtin_ia32_psrldqi128 ((__m128i)(A), (int)(N) * 8)) #define _mm_slli_si128(A, N) \ diff --git a/gcc/config/i386/f16cintrin.h b/gcc/config/i386/f16cintrin.h index 88903c16231f9..4a29fccffe708 100644 --- a/gcc/config/i386/f16cintrin.h +++ b/gcc/config/i386/f16cintrin.h @@ -35,7 +35,7 @@ extern __inline float __attribute__((__gnu_inline__, __always_inline__, __artificial__)) _cvtsh_ss (unsigned short __S) { - __v8hi __H = __extension__ (__v8hi){ __S, 0, 0, 0, 0, 0, 0, 0 }; + __v8hi __H = __extension__ (__v8hi){ (short) __S, 0, 0, 0, 0, 0, 0, 0 }; __v4sf __A = __builtin_ia32_vcvtph2ps (__H); return __builtin_ia32_vec_ext_v4sf (__A, 0); } diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index b835c5da2abbf..40dec967ce80e 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -1378,7 +1378,7 @@ struct processor_costs nocona_cost = { 8, /* MMX or SSE register to integer */ 8, /* size of l1 cache. */ 1024, /* size of l2 cache. */ - 128, /* size of prefetch block */ + 64, /* size of prefetch block */ 8, /* number of parallel prefetches */ 1, /* Branch cost */ COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */ @@ -1894,10 +1894,10 @@ static unsigned int initial_ix86_tune_features[X86_TUNE_LAST] = { m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_ATOM | m_AMDFAM10 | m_BDVER | m_GENERIC, /* X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL */ - m_COREI7 | m_AMDFAM10 | m_BDVER | m_BTVER, + m_COREI7 | m_HASWELL | m_AMDFAM10 | m_BDVER | m_BTVER, /* X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL */ - m_COREI7 | m_BDVER, + m_COREI7 | m_HASWELL| m_BDVER, /* X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL */ m_BDVER , @@ -2409,6 +2409,7 @@ static tree ix86_veclibabi_acml (enum built_in_function, tree, tree); /* Processor target table, indexed by processor number */ struct ptt { + const char *const name; /* processor name */ const struct processor_costs *cost; /* Processor costs */ const int align_loop; /* Default alignments. */ const int align_loop_max_skip; @@ -2417,66 +2418,31 @@ struct ptt const int align_func; }; +/* This table must be in sync with enum processor_type in i386.h. */ static const struct ptt processor_target_table[PROCESSOR_max] = { - {&i386_cost, 4, 3, 4, 3, 4}, - {&i486_cost, 16, 15, 16, 15, 16}, - {&pentium_cost, 16, 7, 16, 7, 16}, - {&pentiumpro_cost, 16, 15, 16, 10, 16}, - {&geode_cost, 0, 0, 0, 0, 0}, - {&k6_cost, 32, 7, 32, 7, 32}, - {&athlon_cost, 16, 7, 16, 7, 16}, - {&pentium4_cost, 0, 0, 0, 0, 0}, - {&k8_cost, 16, 7, 16, 7, 16}, - {&nocona_cost, 0, 0, 0, 0, 0}, - /* Core 2 */ - {&core_cost, 16, 10, 16, 10, 16}, - /* Core i7 */ - {&core_cost, 16, 10, 16, 10, 16}, - /* Core avx2 */ - {&core_cost, 16, 10, 16, 10, 16}, - {&generic32_cost, 16, 7, 16, 7, 16}, - {&generic64_cost, 16, 10, 16, 10, 16}, - {&amdfam10_cost, 32, 24, 32, 7, 32}, - {&bdver1_cost, 32, 24, 32, 7, 32}, - {&bdver2_cost, 32, 24, 32, 7, 32}, - {&bdver3_cost, 32, 24, 32, 7, 32}, - {&btver1_cost, 32, 24, 32, 7, 32}, - {&btver2_cost, 32, 24, 32, 7, 32}, - {&atom_cost, 16, 15, 16, 7, 16} -}; - -static const char *const cpu_names[TARGET_CPU_DEFAULT_max] = -{ - "generic", - "i386", - "i486", - "pentium", - "pentium-mmx", - "pentiumpro", - "pentium2", - "pentium3", - "pentium4", - "pentium-m", - "prescott", - "nocona", - "core2", - "corei7", - "core-avx2", - "atom", - "geode", - "k6", - "k6-2", - "k6-3", - "athlon", - "athlon-4", - "k8", - "amdfam10", - "bdver1", - "bdver2", - "bdver3", - "btver1", - "btver2" + {"generic", &generic32_cost, 16, 7, 16, 7, 16}, + {"generic", &generic64_cost, 16, 10, 16, 10, 16}, + {"i386", &i386_cost, 4, 3, 4, 3, 4}, + {"i486", &i486_cost, 16, 15, 16, 15, 16}, + {"pentium", &pentium_cost, 16, 7, 16, 7, 16}, + {"pentiumpro", &pentiumpro_cost, 16, 15, 16, 10, 16}, + {"pentium4", &pentium4_cost, 0, 0, 0, 0, 0}, + {"nocona", &nocona_cost, 0, 0, 0, 0, 0}, + {"core2", &core_cost, 16, 10, 16, 10, 16}, + {"corei7", &core_cost, 16, 10, 16, 10, 16}, + {"core-avx2", &core_cost, 16, 10, 16, 10, 16}, + {"atom", &atom_cost, 16, 15, 16, 7, 16}, + {"geode", &geode_cost, 0, 0, 0, 0, 0}, + {"k6", &k6_cost, 32, 7, 32, 7, 32}, + {"athlon", &athlon_cost, 16, 7, 16, 7, 16}, + {"k8", &k8_cost, 16, 7, 16, 7, 16}, + {"amdfam10", &amdfam10_cost, 32, 24, 32, 7, 32}, + {"bdver1", &bdver1_cost, 16, 10, 16, 7, 11}, + {"bdver2", &bdver2_cost, 16, 10, 16, 7, 11}, + {"bdver3", &bdver3_cost, 16, 10, 16, 7, 11}, + {"btver1", &btver1_cost, 16, 10, 16, 7, 11}, + {"btver2", &btver2_cost, 16, 10, 16, 7, 11} }; static bool @@ -2877,9 +2843,10 @@ ix86_option_override_internal (bool main_args_p) {"pentium", PROCESSOR_PENTIUM, CPU_PENTIUM, 0}, {"pentium-mmx", PROCESSOR_PENTIUM, CPU_PENTIUM, PTA_MMX}, {"winchip-c6", PROCESSOR_I486, CPU_NONE, PTA_MMX}, - {"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW}, - {"c3", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW}, - {"c3-2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX | PTA_SSE}, + {"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW | PTA_PRFCHW}, + {"c3", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW | PTA_PRFCHW}, + {"c3-2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, + PTA_MMX | PTA_SSE | PTA_FXSR}, {"i686", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0}, {"pentiumpro", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0}, {"pentium2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX | PTA_FXSR}, @@ -2902,8 +2869,8 @@ ix86_option_override_internal (bool main_args_p) PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 | PTA_CX16 | PTA_FXSR}, {"corei7", PROCESSOR_COREI7, CPU_COREI7, - PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 - | PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_CX16 | PTA_FXSR}, + PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 + | PTA_SSE4_1 | PTA_SSE4_2 | PTA_CX16 | PTA_POPCNT | PTA_FXSR}, {"corei7-avx", PROCESSOR_COREI7, CPU_COREI7, PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AVX @@ -2919,55 +2886,55 @@ ix86_option_override_internal (bool main_args_p) | PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AVX | PTA_AVX2 | PTA_CX16 | PTA_POPCNT | PTA_AES | PTA_PCLMUL | PTA_FSGSBASE | PTA_RDRND | PTA_F16C | PTA_BMI | PTA_BMI2 | PTA_LZCNT - | PTA_FMA | PTA_MOVBE | PTA_RTM | PTA_HLE | PTA_FXSR | PTA_XSAVE + | PTA_FMA | PTA_MOVBE | PTA_HLE | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT}, {"atom", PROCESSOR_ATOM, CPU_ATOM, PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 | PTA_CX16 | PTA_MOVBE | PTA_FXSR}, {"geode", PROCESSOR_GEODE, CPU_GEODE, - PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE}, + PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE | PTA_PRFCHW}, {"k6", PROCESSOR_K6, CPU_K6, PTA_MMX}, - {"k6-2", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW}, - {"k6-3", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW}, + {"k6-2", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW | PTA_PRFCHW}, + {"k6-3", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW | PTA_PRFCHW}, {"athlon", PROCESSOR_ATHLON, CPU_ATHLON, - PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE}, + PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE | PTA_PRFCHW}, {"athlon-tbird", PROCESSOR_ATHLON, CPU_ATHLON, - PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE}, + PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE | PTA_PRFCHW}, {"athlon-4", PROCESSOR_ATHLON, CPU_ATHLON, - PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE}, + PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_PRFCHW | PTA_FXSR}, {"athlon-xp", PROCESSOR_ATHLON, CPU_ATHLON, - PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE}, + PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_PRFCHW | PTA_FXSR}, {"athlon-mp", PROCESSOR_ATHLON, CPU_ATHLON, - PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE}, + PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_PRFCHW | PTA_FXSR}, {"x86-64", PROCESSOR_K8, CPU_K8, - PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_NO_SAHF}, + PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR}, {"k8", PROCESSOR_K8, CPU_K8, PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE - | PTA_SSE2 | PTA_NO_SAHF}, + | PTA_SSE2 | PTA_NO_SAHF | PTA_PRFCHW | PTA_FXSR}, {"k8-sse3", PROCESSOR_K8, CPU_K8, PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE - | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF}, + | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_PRFCHW | PTA_FXSR}, {"opteron", PROCESSOR_K8, CPU_K8, PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE - | PTA_SSE2 | PTA_NO_SAHF}, + | PTA_SSE2 | PTA_NO_SAHF | PTA_PRFCHW | PTA_FXSR}, {"opteron-sse3", PROCESSOR_K8, CPU_K8, PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE - | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF}, + | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_PRFCHW | PTA_FXSR}, {"athlon64", PROCESSOR_K8, CPU_K8, PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE - | PTA_SSE2 | PTA_NO_SAHF}, + | PTA_SSE2 | PTA_NO_SAHF | PTA_PRFCHW | PTA_FXSR}, {"athlon64-sse3", PROCESSOR_K8, CPU_K8, PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE - | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF}, + | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_PRFCHW | PTA_FXSR}, {"athlon-fx", PROCESSOR_K8, CPU_K8, PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE - | PTA_SSE2 | PTA_NO_SAHF}, + | PTA_SSE2 | PTA_NO_SAHF | PTA_PRFCHW | PTA_FXSR}, {"amdfam10", PROCESSOR_AMDFAM10, CPU_AMDFAM10, - PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE - | PTA_SSE2 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM}, + PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2 + | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR}, {"barcelona", PROCESSOR_AMDFAM10, CPU_AMDFAM10, - PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE - | PTA_SSE2 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM}, + PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2 + | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR}, {"bdver1", PROCESSOR_BDVER1, CPU_BDVER1, PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1 @@ -2982,7 +2949,7 @@ ix86_option_override_internal (bool main_args_p) {"bdver3", PROCESSOR_BDVER3, CPU_BDVER3, PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1 - | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX + | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4 | PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C | PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT}, @@ -3124,7 +3091,8 @@ ix86_option_override_internal (bool main_args_p) ix86_tune_string = ix86_arch_string; if (!ix86_tune_string) { - ix86_tune_string = cpu_names[TARGET_CPU_DEFAULT]; + ix86_tune_string + = processor_target_table[TARGET_CPU_DEFAULT].name; ix86_tune_defaulted = 1; } @@ -3579,14 +3547,18 @@ ix86_option_override_internal (bool main_args_p) ix86_isa_flags |= OPTION_MASK_ISA_MMX & ~ix86_isa_flags_explicit; /* Enable SSE prefetch. */ - if (TARGET_SSE || TARGET_PRFCHW) + if (TARGET_SSE || (TARGET_PRFCHW && !TARGET_3DNOW)) x86_prefetch_sse = true; - /* Turn on popcnt instruction for -msse4.2 or -mabm. */ + /* Enable prefetch{,w} instructions for -m3dnow. */ + if (TARGET_3DNOW) + ix86_isa_flags |= OPTION_MASK_ISA_PRFCHW & ~ix86_isa_flags_explicit; + + /* Enable popcnt instruction for -msse4.2 or -mabm. */ if (TARGET_SSE4_2 || TARGET_ABM) ix86_isa_flags |= OPTION_MASK_ISA_POPCNT & ~ix86_isa_flags_explicit; - /* Turn on lzcnt instruction for -mabm. */ + /* Enable lzcnt instruction for -mabm. */ if (TARGET_ABM) ix86_isa_flags |= OPTION_MASK_ISA_LZCNT & ~ix86_isa_flags_explicit; @@ -3763,24 +3735,19 @@ ix86_option_override_internal (bool main_args_p) ix86_gen_leave = gen_leave_rex64; if (Pmode == DImode) { - ix86_gen_monitor = gen_sse3_monitor64_di; ix86_gen_tls_global_dynamic_64 = gen_tls_global_dynamic_64_di; ix86_gen_tls_local_dynamic_base_64 = gen_tls_local_dynamic_base_64_di; } else { - ix86_gen_monitor = gen_sse3_monitor64_si; ix86_gen_tls_global_dynamic_64 = gen_tls_global_dynamic_64_si; ix86_gen_tls_local_dynamic_base_64 = gen_tls_local_dynamic_base_64_si; } } else - { - ix86_gen_leave = gen_leave; - ix86_gen_monitor = gen_sse3_monitor; - } + ix86_gen_leave = gen_leave; if (Pmode == DImode) { @@ -3792,6 +3759,7 @@ ix86_option_override_internal (bool main_args_p) ix86_gen_allocate_stack_worker = gen_allocate_stack_worker_probe_di; ix86_gen_adjust_stack_and_probe = gen_adjust_stack_and_probedi; ix86_gen_probe_stack_range = gen_probe_stack_rangedi; + ix86_gen_monitor = gen_sse3_monitor_di; } else { @@ -3803,6 +3771,7 @@ ix86_option_override_internal (bool main_args_p) ix86_gen_allocate_stack_worker = gen_allocate_stack_worker_probe_si; ix86_gen_adjust_stack_and_probe = gen_adjust_stack_and_probesi; ix86_gen_probe_stack_range = gen_probe_stack_rangesi; + ix86_gen_monitor = gen_sse3_monitor_si; } #ifdef USE_IX86_CLD @@ -4076,19 +4045,15 @@ ix86_function_specific_print (FILE *file, int indent, = ix86_target_string (ptr->x_ix86_isa_flags, ptr->x_target_flags, NULL, NULL, ptr->x_ix86_fpmath, false); + gcc_assert (ptr->arch < PROCESSOR_max); fprintf (file, "%*sarch = %d (%s)\n", indent, "", - ptr->arch, - ((ptr->arch < TARGET_CPU_DEFAULT_max) - ? cpu_names[ptr->arch] - : "")); + ptr->arch, processor_target_table[ptr->arch].name); + gcc_assert (ptr->tune < PROCESSOR_max); fprintf (file, "%*stune = %d (%s)\n", indent, "", - ptr->tune, - ((ptr->tune < TARGET_CPU_DEFAULT_max) - ? cpu_names[ptr->tune] - : "")); + ptr->tune, processor_target_table[ptr->tune].name); fprintf (file, "%*sbranch_cost = %d\n", indent, "", ptr->branch_cost); @@ -4686,6 +4651,28 @@ x86_64_elf_select_section (tree decl, int reloc, return default_elf_select_section (decl, reloc, align); } +/* Select a set of attributes for section NAME based on the properties + of DECL and whether or not RELOC indicates that DECL's initializer + might contain runtime relocations. */ + +static unsigned int ATTRIBUTE_UNUSED +x86_64_elf_section_type_flags (tree decl, const char *name, int reloc) +{ + unsigned int flags = default_section_type_flags (decl, name, reloc); + + if (decl == NULL_TREE + && (strcmp (name, ".ldata.rel.ro") == 0 + || strcmp (name, ".ldata.rel.ro.local") == 0)) + flags |= SECTION_RELRO; + + if (strcmp (name, ".lbss") == 0 + || strncmp (name, ".lbss.", 5) == 0 + || strncmp (name, ".gnu.linkonce.lb.", 16) == 0) + flags |= SECTION_BSS; + + return flags; +} + /* Build up a unique section name, expressed as a STRING_CST node, and assign it to DECL_SECTION_NAME (decl). RELOC indicates whether the initial value of EXP requires @@ -5189,7 +5176,12 @@ ix86_function_regparm (const_tree type, const_tree decl) /* Use register calling convention for local functions when possible. */ if (decl && TREE_CODE (decl) == FUNCTION_DECL - && optimize + /* Caller and callee must agree on the calling convention, so + checking here just optimize means that with + __attribute__((optimize (...))) caller could use regparm convention + and callee not, or vice versa. Instead look at whether the callee + is optimized or not. */ + && opt_for_fn (decl, optimize) && !(profile_flag && !flag_fentry)) { /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */ @@ -5385,6 +5377,17 @@ ix86_legitimate_combined_insn (rtx insn) bool win; int j; + /* For pre-AVX disallow unaligned loads/stores where the + instructions don't support it. */ + if (!TARGET_AVX + && VECTOR_MODE_P (GET_MODE (op)) + && misaligned_operand (op, GET_MODE (op))) + { + int min_align = get_attr_ssememalign (insn); + if (min_align == 0) + return false; + } + /* A unary operator may be accepted by the predicate, but it is irrelevant for matching constraints. */ if (UNARY_P (op)) @@ -5448,6 +5451,7 @@ bool ix86_function_arg_regno_p (int regno) { int i; + enum calling_abi call_abi; const int *parm_regs; if (!TARGET_64BIT) @@ -5478,16 +5482,18 @@ ix86_function_arg_regno_p (int regno) /* TODO: The function should depend on current function ABI but builtins.c would need updating then. Therefore we use the default ABI. */ + call_abi = ix86_cfun_abi (); /* RAX is used as hidden argument to va_arg functions. */ - if (ix86_abi == SYSV_ABI && regno == AX_REG) + if (call_abi == SYSV_ABI && regno == AX_REG) return true; - if (ix86_abi == MS_ABI) + if (call_abi == MS_ABI) parm_regs = x86_64_ms_abi_int_parameter_registers; else parm_regs = x86_64_int_parameter_registers; - for (i = 0; i < (ix86_abi == MS_ABI + + for (i = 0; i < (call_abi == MS_ABI ? X86_64_MS_REGPARM_MAX : X86_64_REGPARM_MAX); i++) if (regno == parm_regs[i]) return true; @@ -5536,7 +5542,18 @@ ix86_function_type_abi (const_tree fntype) if (abi == SYSV_ABI) { if (lookup_attribute ("ms_abi", TYPE_ATTRIBUTES (fntype))) - abi = MS_ABI; + { + if (TARGET_X32) + { + static bool warned = false; + if (!warned) + { + error ("X32 does not support ms_abi attribute"); + warned = true; + } + } + abi = MS_ABI; + } } else if (lookup_attribute ("sysv_abi", TYPE_ATTRIBUTES (fntype))) abi = SYSV_ABI; @@ -5723,9 +5740,9 @@ init_cumulative_args (CUMULATIVE_ARGS *cum, /* Argument info to initialize */ cum->nregs = 0; cum->sse_nregs = 0; cum->mmx_nregs = 0; - cum->warn_avx = 0; - cum->warn_sse = 0; - cum->warn_mmx = 0; + cum->warn_avx = false; + cum->warn_sse = false; + cum->warn_mmx = false; return; } @@ -5766,10 +5783,14 @@ init_cumulative_args (CUMULATIVE_ARGS *cum, /* Argument info to initialize */ The midde-end can't deal with the vector types > 16 bytes. In this case, we return the original mode and warn ABI change if CUM isn't - NULL. */ + NULL. + + If INT_RETURN is true, warn ABI change if the vector mode isn't + available for function return value. */ static enum machine_mode -type_natural_mode (const_tree type, const CUMULATIVE_ARGS *cum) +type_natural_mode (const_tree type, const CUMULATIVE_ARGS *cum, + bool in_return) { enum machine_mode mode = TYPE_MODE (type); @@ -5795,33 +5816,61 @@ type_natural_mode (const_tree type, const CUMULATIVE_ARGS *cum) if (size == 32 && !TARGET_AVX) { static bool warnedavx; + static bool warnedavx_ret; - if (cum - && !warnedavx - && cum->warn_avx) + if (cum && cum->warn_avx && !warnedavx) { - warnedavx = true; - warning (0, "AVX vector argument without AVX " - "enabled changes the ABI"); + if (warning (OPT_Wpsabi, "AVX vector argument " + "without AVX enabled changes the ABI")) + warnedavx = true; } + else if (in_return && !warnedavx_ret) + { + if (warning (OPT_Wpsabi, "AVX vector return " + "without AVX enabled changes the ABI")) + warnedavx_ret = true; + } + return TYPE_MODE (type); } - else if ((size == 8 || size == 16) && !TARGET_SSE) + else if (((size == 8 && TARGET_64BIT) || size == 16) + && !TARGET_SSE) { static bool warnedsse; + static bool warnedsse_ret; - if (cum - && !warnedsse - && cum->warn_sse) + if (cum && cum->warn_sse && !warnedsse) + { + if (warning (OPT_Wpsabi, "SSE vector argument " + "without SSE enabled changes the ABI")) + warnedsse = true; + } + else if (!TARGET_64BIT && in_return && !warnedsse_ret) { - warnedsse = true; - warning (0, "SSE vector argument without SSE " - "enabled changes the ABI"); + if (warning (OPT_Wpsabi, "SSE vector return " + "without SSE enabled changes the ABI")) + warnedsse_ret = true; } - return mode; } - else - return mode; + else if ((size == 8 && !TARGET_64BIT) && !TARGET_MMX) + { + static bool warnedmmx; + static bool warnedmmx_ret; + + if (cum && cum->warn_mmx && !warnedmmx) + { + if (warning (OPT_Wpsabi, "MMX vector argument " + "without MMX enabled changes the ABI")) + warnedmmx = true; + } + else if (in_return && !warnedmmx_ret) + { + if (warning (OPT_Wpsabi, "MMX vector return " + "without MMX enabled changes the ABI")) + warnedmmx_ret = true; + } + } + return mode; } gcc_unreachable (); @@ -6166,25 +6215,28 @@ classify_argument (enum machine_mode mode, const_tree type, case CHImode: case CQImode: { - int size = (bit_offset % 64)+ (int) GET_MODE_BITSIZE (mode); + int size = bit_offset + (int) GET_MODE_BITSIZE (mode); - if (size <= 32) + /* Analyze last 128 bits only. */ + size = (size - 1) & 0x7f; + + if (size < 32) { classes[0] = X86_64_INTEGERSI_CLASS; return 1; } - else if (size <= 64) + else if (size < 64) { classes[0] = X86_64_INTEGER_CLASS; return 1; } - else if (size <= 64+32) + else if (size < 64+32) { classes[0] = X86_64_INTEGER_CLASS; classes[1] = X86_64_INTEGERSI_CLASS; return 2; } - else if (size <= 64+64) + else if (size < 64+64) { classes[0] = classes[1] = X86_64_INTEGER_CLASS; return 2; @@ -6391,7 +6443,7 @@ construct_container (enum machine_mode mode, enum machine_mode orig_mode, /* Likewise, error if the ABI requires us to return values in the x87 registers and the user specified -mno-80387. */ - if (!TARGET_80387 && in_return) + if (in_return && !TARGET_FLOAT_RETURNS_IN_80387) for (i = 0; i < n; i++) if (regclass[i] == X86_64_X87_CLASS || regclass[i] == X86_64_X87UP_CLASS @@ -6451,7 +6503,7 @@ construct_container (enum machine_mode mode, enum machine_mode orig_mode, if (n == 2 && regclass[0] == X86_64_INTEGER_CLASS && regclass[1] == X86_64_INTEGER_CLASS - && (mode == CDImode || mode == TImode || mode == TFmode) + && (mode == CDImode || mode == TImode) && intreg[0] + 1 == intreg[1]) return gen_rtx_REG (mode, intreg[0]); @@ -6701,7 +6753,7 @@ ix86_function_arg_advance (cumulative_args_t cum_v, enum machine_mode mode, words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD; if (type) - mode = type_natural_mode (type, NULL); + mode = type_natural_mode (type, NULL, false); if (TARGET_64BIT && (cum ? cum->call_abi : ix86_abi) == MS_ABI) function_arg_advance_ms_64 (cum, bytes, words); @@ -6729,8 +6781,6 @@ function_arg_32 (const CUMULATIVE_ARGS *cum, enum machine_mode mode, enum machine_mode orig_mode, const_tree type, HOST_WIDE_INT bytes, HOST_WIDE_INT words) { - static bool warnedsse, warnedmmx; - /* Avoid the AL settings for the Unix64 ABI. */ if (mode == VOIDmode) return constm1_rtx; @@ -6787,12 +6837,6 @@ function_arg_32 (const CUMULATIVE_ARGS *cum, enum machine_mode mode, case V2DFmode: if (!type || !AGGREGATE_TYPE_P (type)) { - if (!TARGET_SSE && !warnedsse && cum->warn_sse) - { - warnedsse = true; - warning (0, "SSE vector argument without SSE enabled " - "changes the ABI"); - } if (cum->sse_nregs) return gen_reg_or_parallel (mode, orig_mode, cum->sse_regno + FIRST_SSE_REG); @@ -6825,12 +6869,6 @@ function_arg_32 (const CUMULATIVE_ARGS *cum, enum machine_mode mode, case V1DImode: if (!type || !AGGREGATE_TYPE_P (type)) { - if (!TARGET_MMX && !warnedmmx && cum->warn_mmx) - { - warnedmmx = true; - warning (0, "MMX vector argument without MMX enabled " - "changes the ABI"); - } if (cum->mmx_nregs) return gen_reg_or_parallel (mode, orig_mode, cum->mmx_regno + FIRST_MMX_REG); @@ -6953,7 +6991,7 @@ ix86_function_arg (cumulative_args_t cum_v, enum machine_mode omode, /* To simplify the code below, represent vector types with a vector mode even if MMX/SSE are not active. */ if (type && TREE_CODE (type) == VECTOR_TYPE) - mode = type_natural_mode (type, cum); + mode = type_natural_mode (type, cum, false); if (TARGET_64BIT && (cum ? cum->call_abi : ix86_abi) == MS_ABI) arg = function_arg_ms_64 (cum, mode, omode, named, bytes); @@ -7211,20 +7249,28 @@ ix86_function_value_regno_p (const unsigned int regno) switch (regno) { case AX_REG: + case DX_REG: return true; + case DI_REG: + case SI_REG: + return TARGET_64BIT && ix86_cfun_abi () != MS_ABI; - case FIRST_FLOAT_REG: + /* Complex values are returned in %st(0)/%st(1) pair. */ + case ST0_REG: + case ST1_REG: /* TODO: The function should depend on current function ABI but builtins.c would need updating then. Therefore we use the default ABI. */ - if (TARGET_64BIT && ix86_abi == MS_ABI) + if (TARGET_64BIT && ix86_cfun_abi () == MS_ABI) return false; return TARGET_FLOAT_RETURNS_IN_80387; - case FIRST_SSE_REG: + /* Complex values are returned in %xmm0/%xmm1 pair. */ + case XMM0_REG: + case XMM1_REG: return TARGET_SSE; - case FIRST_MMX_REG: + case MM0_REG: if (TARGET_MACHO || TARGET_64BIT) return false; return TARGET_MMX; @@ -7396,7 +7442,7 @@ ix86_function_value (const_tree valtype, const_tree fntype_or_decl, enum machine_mode mode, orig_mode; orig_mode = TYPE_MODE (valtype); - mode = type_natural_mode (valtype, NULL); + mode = type_natural_mode (valtype, NULL, true); return ix86_function_value_1 (valtype, fntype_or_decl, orig_mode, mode); } @@ -7511,7 +7557,7 @@ ix86_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED) #ifdef SUBTARGET_RETURN_IN_MEMORY return SUBTARGET_RETURN_IN_MEMORY (type, fntype); #else - const enum machine_mode mode = type_natural_mode (type, NULL); + const enum machine_mode mode = type_natural_mode (type, NULL, true); if (TARGET_64BIT) { @@ -7525,52 +7571,6 @@ ix86_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED) #endif } -/* When returning SSE vector types, we have a choice of either - (1) being abi incompatible with a -march switch, or - (2) generating an error. - Given no good solution, I think the safest thing is one warning. - The user won't be able to use -Werror, but.... - - Choose the STRUCT_VALUE_RTX hook because that's (at present) only - called in response to actually generating a caller or callee that - uses such a type. As opposed to TARGET_RETURN_IN_MEMORY, which is called - via aggregate_value_p for general type probing from tree-ssa. */ - -static rtx -ix86_struct_value_rtx (tree type, int incoming ATTRIBUTE_UNUSED) -{ - static bool warnedsse, warnedmmx; - - if (!TARGET_64BIT && type) - { - /* Look at the return type of the function, not the function type. */ - enum machine_mode mode = TYPE_MODE (TREE_TYPE (type)); - - if (!TARGET_SSE && !warnedsse) - { - if (mode == TImode - || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16)) - { - warnedsse = true; - warning (0, "SSE vector return without SSE enabled " - "changes the ABI"); - } - } - - if (!TARGET_MMX && !warnedmmx) - { - if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8) - { - warnedmmx = true; - warning (0, "MMX vector return without MMX enabled " - "changes the ABI"); - } - } - } - - return NULL; -} - /* Create the va_list data type. */ @@ -7995,7 +7995,7 @@ ix86_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p, size = int_size_in_bytes (type); rsize = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD; - nat_mode = type_natural_mode (type, NULL); + nat_mode = type_natural_mode (type, NULL, false); switch (nat_mode) { case V8SFmode: @@ -8716,17 +8716,12 @@ output_set_got (rtx dest, rtx label ATTRIBUTE_UNUSED) if (!flag_pic) { - xops[2] = gen_rtx_LABEL_REF (Pmode, label ? label : gen_label_rtx ()); + if (TARGET_MACHO) + /* We don't need a pic base, we're not producing pic. */ + gcc_unreachable (); + xops[2] = gen_rtx_LABEL_REF (Pmode, label ? label : gen_label_rtx ()); output_asm_insn ("mov%z0\t{%2, %0|%0, %2}", xops); - -#if TARGET_MACHO - /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This - is what will be referenced by the Mach-O PIC subsystem. */ - if (!label) - ASM_OUTPUT_LABEL (asm_out_file, MACHOPIC_FUNCTION_BASE_NAME); -#endif - targetm.asm_out.internal_label (asm_out_file, "L", CODE_LABEL_NUMBER (XEXP (xops[2], 0))); } @@ -8739,12 +8734,18 @@ output_set_got (rtx dest, rtx label ATTRIBUTE_UNUSED) xops[2] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name)); xops[2] = gen_rtx_MEM (QImode, xops[2]); output_asm_insn ("call\t%X2", xops); - /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This - is what will be referenced by the Mach-O PIC subsystem. */ + #if TARGET_MACHO - if (!label) + /* Output the Mach-O "canonical" pic base label name ("Lxx$pb") here. + This is what will be referenced by the Mach-O PIC subsystem. */ + if (machopic_should_output_picbase_label () || !label) ASM_OUTPUT_LABEL (asm_out_file, MACHOPIC_FUNCTION_BASE_NAME); - else + + /* When we are restoring the pic base at the site of a nonlocal label, + and we decided to emit the pic base above, we will still output a + local label used for calculating the correction offset (even though + the offset will be 0 in that case). */ + if (label) targetm.asm_out.internal_label (asm_out_file, "L", CODE_LABEL_NUMBER (label)); #endif @@ -8826,7 +8827,8 @@ ix86_save_reg (unsigned int regno, bool maybe_eh_return) && (df_regs_ever_live_p (REAL_PIC_OFFSET_TABLE_REGNUM) || crtl->profile || crtl->calls_eh_return - || crtl->uses_const_pool)) + || crtl->uses_const_pool + || cfun->has_nonlocal_label)) return ix86_select_alt_pic_regnum () == INVALID_REGNUM; if (crtl->calls_eh_return && maybe_eh_return) @@ -10495,6 +10497,10 @@ ix86_expand_prologue (void) if (sp_is_cfa_reg) m->fs.cfa_offset += UNITS_PER_WORD; RTX_FRAME_RELATED_P (insn) = 1; + add_reg_note (insn, REG_FRAME_RELATED_EXPR, + gen_rtx_SET (VOIDmode, stack_pointer_rtx, + plus_constant (Pmode, stack_pointer_rtx, + -UNITS_PER_WORD))); } } @@ -10508,6 +10514,10 @@ ix86_expand_prologue (void) if (sp_is_cfa_reg) m->fs.cfa_offset += UNITS_PER_WORD; RTX_FRAME_RELATED_P (insn) = 1; + add_reg_note (insn, REG_FRAME_RELATED_EXPR, + gen_rtx_SET (VOIDmode, stack_pointer_rtx, + plus_constant (Pmode, stack_pointer_rtx, + -UNITS_PER_WORD))); } } @@ -10534,18 +10544,20 @@ ix86_expand_prologue (void) } m->fs.sp_offset += allocate; + /* Use stack_pointer_rtx for relative addressing so that code + works for realigned stack, too. */ if (r10_live && eax_live) { - t = choose_baseaddr (m->fs.sp_offset - allocate); + t = gen_rtx_PLUS (Pmode, stack_pointer_rtx, eax); emit_move_insn (gen_rtx_REG (word_mode, R10_REG), gen_frame_mem (word_mode, t)); - t = choose_baseaddr (m->fs.sp_offset - allocate - UNITS_PER_WORD); + t = plus_constant (Pmode, t, UNITS_PER_WORD); emit_move_insn (gen_rtx_REG (word_mode, AX_REG), gen_frame_mem (word_mode, t)); } else if (eax_live || r10_live) { - t = choose_baseaddr (m->fs.sp_offset - allocate); + t = gen_rtx_PLUS (Pmode, stack_pointer_rtx, eax); emit_move_insn (gen_rtx_REG (word_mode, (eax_live ? AX_REG : R10_REG)), gen_frame_mem (word_mode, t)); @@ -11138,8 +11150,9 @@ ix86_expand_epilogue (int style) m->fs.cfa_offset -= UNITS_PER_WORD; m->fs.sp_offset -= UNITS_PER_WORD; - add_reg_note (insn, REG_CFA_ADJUST_CFA, - copy_rtx (XVECEXP (PATTERN (insn), 0, 1))); + rtx x = plus_constant (Pmode, stack_pointer_rtx, UNITS_PER_WORD); + x = gen_rtx_SET (VOIDmode, stack_pointer_rtx, x); + add_reg_note (insn, REG_CFA_ADJUST_CFA, x); add_reg_note (insn, REG_CFA_REGISTER, gen_rtx_SET (VOIDmode, ecx, pc_rtx)); RTX_FRAME_RELATED_P (insn) = 1; @@ -11535,30 +11548,6 @@ ix86_live_on_entry (bitmap regs) } } -/* Determine if op is suitable SUBREG RTX for address. */ - -static bool -ix86_address_subreg_operand (rtx op) -{ - enum machine_mode mode; - - if (!REG_P (op)) - return false; - - mode = GET_MODE (op); - - if (GET_MODE_CLASS (mode) != MODE_INT) - return false; - - /* Don't allow SUBREGs that span more than a word. It can lead to spill - failures when the register is one word out of a two word structure. */ - if (GET_MODE_SIZE (mode) > UNITS_PER_WORD) - return false; - - /* Allow only SUBREGs of non-eliminable hard registers. */ - return register_no_elim_operand (op, mode); -} - /* Extract the parts of an RTL expression that is a valid memory address for an instruction. Return 0 if the structure of the address is grossly off. Return -1 if the address contains ASHIFT, so it is not @@ -11615,7 +11604,7 @@ ix86_decompose_address (rtx addr, struct ix86_address *out) base = addr; else if (GET_CODE (addr) == SUBREG) { - if (ix86_address_subreg_operand (SUBREG_REG (addr))) + if (REG_P (SUBREG_REG (addr))) base = addr; else return 0; @@ -11679,7 +11668,7 @@ ix86_decompose_address (rtx addr, struct ix86_address *out) break; case SUBREG: - if (!ix86_address_subreg_operand (SUBREG_REG (op))) + if (!REG_P (SUBREG_REG (op))) return 0; /* FALLTHRU */ @@ -11724,19 +11713,6 @@ ix86_decompose_address (rtx addr, struct ix86_address *out) scale = 1 << scale; retval = -1; } - else if (CONST_INT_P (addr)) - { - if (!x86_64_immediate_operand (addr, VOIDmode)) - return 0; - - /* Constant addresses are sign extended to 64bit, we have to - prevent addresses from 0x80000000 to 0xffffffff in x32 mode. */ - if (TARGET_X32 - && val_signbit_known_set_p (SImode, INTVAL (addr))) - return 0; - - disp = addr; - } else disp = addr; /* displacement */ @@ -11745,18 +11721,12 @@ ix86_decompose_address (rtx addr, struct ix86_address *out) if (REG_P (index)) ; else if (GET_CODE (index) == SUBREG - && ix86_address_subreg_operand (SUBREG_REG (index))) + && REG_P (SUBREG_REG (index))) ; else return 0; } -/* Address override works only on the (%reg) part of %fs:(%reg). */ - if (seg != SEG_DEFAULT - && ((base && GET_MODE (base) != word_mode) - || (index && GET_MODE (index) != word_mode))) - return 0; - /* Extract the integral value of scale. */ if (scale_rtx) { @@ -12232,6 +12202,45 @@ ix86_legitimize_reload_address (rtx x, return false; } +/* Determine if op is suitable RTX for an address register. + Return naked register if a register or a register subreg is + found, otherwise return NULL_RTX. */ + +static rtx +ix86_validate_address_register (rtx op) +{ + enum machine_mode mode = GET_MODE (op); + + /* Only SImode or DImode registers can form the address. */ + if (mode != SImode && mode != DImode) + return NULL_RTX; + + if (REG_P (op)) + return op; + else if (GET_CODE (op) == SUBREG) + { + rtx reg = SUBREG_REG (op); + + if (!REG_P (reg)) + return NULL_RTX; + + mode = GET_MODE (reg); + + /* Don't allow SUBREGs that span more than a word. It can + lead to spill failures when the register is one word out + of a two word structure. */ + if (GET_MODE_SIZE (mode) > UNITS_PER_WORD) + return NULL_RTX; + + /* Allow only SUBREGs of non-eliminable hard registers. */ + if (register_no_elim_operand (reg, mode)) + return reg; + } + + /* Op is not a register. */ + return NULL_RTX; +} + /* Recognizes RTL expressions that are valid memory addresses for an instruction. The MODE argument is the machine mode for the MEM expression that wants to use this address. @@ -12247,6 +12256,7 @@ ix86_legitimate_address_p (enum machine_mode mode ATTRIBUTE_UNUSED, struct ix86_address parts; rtx base, index, disp; HOST_WIDE_INT scale; + enum ix86_address_seg seg; if (ix86_decompose_address (addr, &parts) <= 0) /* Decomposition failed. */ @@ -12256,21 +12266,14 @@ ix86_legitimate_address_p (enum machine_mode mode ATTRIBUTE_UNUSED, index = parts.index; disp = parts.disp; scale = parts.scale; + seg = parts.seg; /* Validate base register. */ if (base) { - rtx reg; - - if (REG_P (base)) - reg = base; - else if (GET_CODE (base) == SUBREG && REG_P (SUBREG_REG (base))) - reg = SUBREG_REG (base); - else - /* Base is not a register. */ - return false; + rtx reg = ix86_validate_address_register (base); - if (GET_MODE (base) != SImode && GET_MODE (base) != DImode) + if (reg == NULL_RTX) return false; if ((strict && ! REG_OK_FOR_BASE_STRICT_P (reg)) @@ -12282,17 +12285,9 @@ ix86_legitimate_address_p (enum machine_mode mode ATTRIBUTE_UNUSED, /* Validate index register. */ if (index) { - rtx reg; - - if (REG_P (index)) - reg = index; - else if (GET_CODE (index) == SUBREG && REG_P (SUBREG_REG (index))) - reg = SUBREG_REG (index); - else - /* Index is not a register. */ - return false; + rtx reg = ix86_validate_address_register (index); - if (GET_MODE (index) != SImode && GET_MODE (index) != DImode) + if (reg == NULL_RTX) return false; if ((strict && ! REG_OK_FOR_INDEX_STRICT_P (reg)) @@ -12306,6 +12301,12 @@ ix86_legitimate_address_p (enum machine_mode mode ATTRIBUTE_UNUSED, && GET_MODE (base) != GET_MODE (index)) return false; + /* Address override works only on the (%reg) part of %fs:(%reg). */ + if (seg != SEG_DEFAULT + && ((base && GET_MODE (base) != word_mode) + || (index && GET_MODE (index) != word_mode))) + return false; + /* Validate scale factor. */ if (scale != 1) { @@ -12427,6 +12428,12 @@ ix86_legitimate_address_p (enum machine_mode mode ATTRIBUTE_UNUSED, && !x86_64_immediate_operand (disp, VOIDmode)) /* Displacement is out of range. */ return false; + /* In x32 mode, constant addresses are sign extended to 64bit, so + we have to prevent addresses from 0x80000000 to 0xffffffff. */ + else if (TARGET_X32 && !(index || base) + && CONST_INT_P (disp) + && val_signbit_known_set_p (SImode, INTVAL (disp))) + return false; } /* Everything looks valid. */ @@ -13591,21 +13598,29 @@ ix86_delegitimize_address (rtx x) x = replace_equiv_address_nv (orig_x, x); return x; } - if (GET_CODE (x) != CONST - || GET_CODE (XEXP (x, 0)) != UNSPEC - || (XINT (XEXP (x, 0), 1) != UNSPEC_GOTPCREL - && XINT (XEXP (x, 0), 1) != UNSPEC_PCREL) - || (!MEM_P (orig_x) && XINT (XEXP (x, 0), 1) != UNSPEC_PCREL)) - return ix86_delegitimize_tls_address (orig_x); - x = XVECEXP (XEXP (x, 0), 0, 0); - if (GET_MODE (orig_x) != GET_MODE (x) && MEM_P (orig_x)) + + if (GET_CODE (x) == CONST + && GET_CODE (XEXP (x, 0)) == UNSPEC + && (XINT (XEXP (x, 0), 1) == UNSPEC_GOTPCREL + || XINT (XEXP (x, 0), 1) == UNSPEC_PCREL) + && (MEM_P (orig_x) || XINT (XEXP (x, 0), 1) == UNSPEC_PCREL)) { - x = simplify_gen_subreg (GET_MODE (orig_x), x, - GET_MODE (x), 0); - if (x == NULL_RTX) - return orig_x; + x = XVECEXP (XEXP (x, 0), 0, 0); + if (GET_MODE (orig_x) != GET_MODE (x) && MEM_P (orig_x)) + { + x = simplify_gen_subreg (GET_MODE (orig_x), x, + GET_MODE (x), 0); + if (x == NULL_RTX) + return orig_x; + } + return x; } - return x; + + if (ix86_cmodel != CM_MEDIUM_PIC && ix86_cmodel != CM_LARGE_PIC) + return ix86_delegitimize_tls_address (orig_x); + + /* Fall thru into the code shared with -m32 for -mcmodel=large -fpic + and -mcmodel=medium -fpic. */ } if (GET_CODE (x) != PLUS @@ -13642,10 +13657,12 @@ ix86_delegitimize_address (rtx x) if (GET_CODE (x) == UNSPEC && ((XINT (x, 1) == UNSPEC_GOT && MEM_P (orig_x) && !addend) - || (XINT (x, 1) == UNSPEC_GOTOFF && !MEM_P (orig_x)))) + || (XINT (x, 1) == UNSPEC_GOTOFF && !MEM_P (orig_x)) + || (XINT (x, 1) == UNSPEC_PLTOFF && ix86_cmodel == CM_LARGE_PIC + && !MEM_P (orig_x) && !addend))) result = XVECEXP (x, 0, 0); - if (TARGET_MACHO && darwin_local_data_pic (x) + if (!TARGET_64BIT && TARGET_MACHO && darwin_local_data_pic (x) && !MEM_P (orig_x)) result = XVECEXP (x, 0, 0); @@ -13781,8 +13798,6 @@ put_condition_code (enum rtx_code code, enum machine_mode mode, bool reverse, Those same assemblers have the same but opposite lossage on cmov. */ if (mode == CCmode) suffix = fp ? "nbe" : "a"; - else if (mode == CCCmode) - suffix = "b"; else gcc_unreachable (); break; @@ -13804,8 +13819,12 @@ put_condition_code (enum rtx_code code, enum machine_mode mode, bool reverse, } break; case LTU: - gcc_assert (mode == CCmode || mode == CCCmode); - suffix = "b"; + if (mode == CCmode) + suffix = "b"; + else if (mode == CCCmode) + suffix = fp ? "b" : "c"; + else + gcc_unreachable (); break; case GE: switch (mode) @@ -13825,20 +13844,20 @@ put_condition_code (enum rtx_code code, enum machine_mode mode, bool reverse, } break; case GEU: - /* ??? As above. */ - gcc_assert (mode == CCmode || mode == CCCmode); - suffix = fp ? "nb" : "ae"; + if (mode == CCmode) + suffix = "nb"; + else if (mode == CCCmode) + suffix = fp ? "nb" : "nc"; + else + gcc_unreachable (); break; case LE: gcc_assert (mode == CCmode || mode == CCGCmode || mode == CCNOmode); suffix = "le"; break; case LEU: - /* ??? As above. */ if (mode == CCmode) suffix = "be"; - else if (mode == CCCmode) - suffix = fp ? "nb" : "ae"; else gcc_unreachable (); break; @@ -15304,7 +15323,7 @@ ix86_avx_u128_mode_needed (rtx insn) rtx arg = XEXP (XEXP (link, 0), 0); if (ix86_check_avx256_register (&arg, NULL)) - return AVX_U128_ANY; + return AVX_U128_DIRTY; } } @@ -15424,8 +15443,8 @@ ix86_avx_u128_mode_after (int mode, rtx insn) { bool avx_reg256_found = false; note_stores (pat, ix86_check_avx256_stores, &avx_reg256_found); - if (!avx_reg256_found) - return AVX_U128_CLEAN; + + return avx_reg256_found ? AVX_U128_DIRTY : AVX_U128_CLEAN; } /* Otherwise, return current mode. Remember that if insn @@ -17314,8 +17333,18 @@ ix86_avoid_lea_for_addr (rtx insn, rtx operands[]) if (!TARGET_OPT_AGU || optimize_function_for_size_p (cfun)) return false; - /* Check it is correct to split here. */ - if (!ix86_ok_to_clobber_flags(insn)) + /* The "at least two components" test below might not catch simple + move or zero extension insns if parts.base is non-NULL and parts.disp + is const0_rtx as the only components in the address, e.g. if the + register is %rbp or %r13. As this test is much cheaper and moves or + zero extensions are the common case, do this check first. */ + if (REG_P (operands[1]) + || (SImode_address_operand (operands[1], VOIDmode) + && REG_P (XEXP (operands[1], 0)))) + return false; + + /* Check if it is OK to split here. */ + if (!ix86_ok_to_clobber_flags (insn)) return false; ok = ix86_decompose_address (operands[1], &parts); @@ -18450,12 +18479,7 @@ ix86_cc_mode (enum rtx_code code, rtx op0, rtx op1) return CCmode; case GTU: /* CF=0 & ZF=0 */ case LEU: /* CF=1 | ZF=1 */ - /* Detect overflow checks. They need just the carry flag. */ - if (GET_CODE (op0) == MINUS - && rtx_equal_p (op1, XEXP (op0, 0))) - return CCCmode; - else - return CCmode; + return CCmode; /* Codes possibly doable only with sign flag when comparing against zero. */ case GE: /* SF=OF or SF=0 */ @@ -20434,7 +20458,7 @@ ix86_expand_vec_perm (rtx operands[]) vec[i * 2 + 1] = const1_rtx; } vt = gen_rtx_CONST_VECTOR (maskmode, gen_rtvec_v (w, vec)); - vt = force_const_mem (maskmode, vt); + vt = validize_mem (force_const_mem (maskmode, vt)); t1 = expand_simple_binop (maskmode, PLUS, t1, vt, t1, 1, OPTAB_DIRECT); @@ -20464,7 +20488,7 @@ ix86_expand_vec_perm (rtx operands[]) return; case V8SFmode: - mask = gen_lowpart (V8SFmode, mask); + mask = gen_lowpart (V8SImode, mask); if (one_operand_shuffle) emit_insn (gen_avx2_permvarv8sf (target, op0, mask)); else @@ -20503,7 +20527,7 @@ ix86_expand_vec_perm (rtx operands[]) t1 = gen_reg_rtx (V32QImode); t2 = gen_reg_rtx (V32QImode); t3 = gen_reg_rtx (V32QImode); - vt2 = GEN_INT (128); + vt2 = GEN_INT (-128); for (i = 0; i < 32; i++) vec[i] = vt2; vt = gen_rtx_CONST_VECTOR (V32QImode, gen_rtvec_v (32, vec)); @@ -20631,7 +20655,7 @@ ix86_expand_vec_perm (rtx operands[]) for (i = 0; i < 16; ++i) vec[i] = GEN_INT (i/e * e); vt = gen_rtx_CONST_VECTOR (V16QImode, gen_rtvec_v (16, vec)); - vt = force_const_mem (V16QImode, vt); + vt = validize_mem (force_const_mem (V16QImode, vt)); if (TARGET_XOP) emit_insn (gen_xop_pperm (mask, mask, mask, vt)); else @@ -20642,7 +20666,7 @@ ix86_expand_vec_perm (rtx operands[]) for (i = 0; i < 16; ++i) vec[i] = GEN_INT (i % e); vt = gen_rtx_CONST_VECTOR (V16QImode, gen_rtvec_v (16, vec)); - vt = force_const_mem (V16QImode, vt); + vt = validize_mem (force_const_mem (V16QImode, vt)); emit_insn (gen_addv16qi3 (mask, mask, vt)); } @@ -21190,7 +21214,7 @@ ix86_split_long_move (rtx operands[]) Do an lea to the last part and use only one colliding move. */ else if (collisions > 1) { - rtx base; + rtx base, addr, tls_base = NULL_RTX; collisions = 1; @@ -21201,10 +21225,50 @@ ix86_split_long_move (rtx operands[]) if (GET_MODE (base) != Pmode) base = gen_rtx_REG (Pmode, REGNO (base)); - emit_insn (gen_rtx_SET (VOIDmode, base, XEXP (part[1][0], 0))); + addr = XEXP (part[1][0], 0); + if (TARGET_TLS_DIRECT_SEG_REFS) + { + struct ix86_address parts; + int ok = ix86_decompose_address (addr, &parts); + gcc_assert (ok); + if (parts.seg != SEG_DEFAULT) + { + /* It is not valid to use %gs: or %fs: in + lea though, so we need to remove it from the + address used for lea and add it to each individual + memory loads instead. */ + addr = copy_rtx (addr); + rtx *x = &addr; + while (GET_CODE (*x) == PLUS) + { + for (i = 0; i < 2; i++) + { + rtx u = XEXP (*x, i); + if (GET_CODE (u) == ZERO_EXTEND) + u = XEXP (u, 0); + if (GET_CODE (u) == UNSPEC + && XINT (u, 1) == UNSPEC_TP) + { + tls_base = XEXP (*x, i); + *x = XEXP (*x, 1 - i); + break; + } + } + if (tls_base) + break; + x = &XEXP (*x, 0); + } + gcc_assert (tls_base); + } + } + emit_insn (gen_rtx_SET (VOIDmode, base, addr)); + if (tls_base) + base = gen_rtx_PLUS (GET_MODE (base), base, tls_base); part[1][0] = replace_equiv_address (part[1][0], base); for (i = 1; i < nparts; i++) { + if (tls_base) + base = copy_rtx (base); tmp = plus_constant (Pmode, base, UNITS_PER_WORD * i); part[1][i] = replace_equiv_address (part[1][i], tmp); } @@ -21704,6 +21768,21 @@ counter_mode (rtx count_exp) return SImode; } +/* Copy the address to a Pmode register. This is used for x32 to + truncate DImode TLS address to a SImode register. */ + +static rtx +ix86_copy_addr_to_reg (rtx addr) +{ + if (GET_MODE (addr) == Pmode || GET_MODE (addr) == VOIDmode) + return copy_addr_to_reg (addr); + else + { + gcc_assert (GET_MODE (addr) == DImode && Pmode == SImode); + return gen_rtx_SUBREG (SImode, copy_to_mode_reg (DImode, addr), 0); + } +} + /* When SRCPTR is non-NULL, output simple loop to move memory pointer to SRCPTR to DESTPTR via chunks of MODE unrolled UNROLL times, overall size is COUNT specified in bytes. When SRCPTR is NULL, output the @@ -22692,8 +22771,8 @@ ix86_expand_movmem (rtx dst, rtx src, rtx count_exp, rtx align_exp, gcc_assert (alg != no_stringop); if (!count) count_exp = copy_to_mode_reg (GET_MODE (count_exp), count_exp); - destreg = copy_addr_to_reg (XEXP (dst, 0)); - srcreg = copy_addr_to_reg (XEXP (src, 0)); + destreg = ix86_copy_addr_to_reg (XEXP (dst, 0)); + srcreg = ix86_copy_addr_to_reg (XEXP (src, 0)); switch (alg) { case libcall: @@ -23083,7 +23162,7 @@ ix86_expand_setmem (rtx dst, rtx count_exp, rtx val_exp, rtx align_exp, gcc_assert (alg != no_stringop); if (!count) count_exp = copy_to_mode_reg (counter_mode (count_exp), count_exp); - destreg = copy_addr_to_reg (XEXP (dst, 0)); + destreg = ix86_copy_addr_to_reg (XEXP (dst, 0)); switch (alg) { case libcall: @@ -24538,7 +24617,7 @@ add_parameter_dependencies (rtx call, rtx head) /* Add output depdendence between two function arguments if chain of output arguments contains likely spilled HW registers. */ if (is_spilled) - add_dependence (last, insn, REG_DEP_OUTPUT); + add_dependence (first_arg, insn, REG_DEP_OUTPUT); first_arg = last = insn; } else @@ -24623,13 +24702,17 @@ ix86_dependencies_evaluation_hook (rtx head, rtx tail) { edge e; edge_iterator ei; - /* Assume that region is SCC, i.e. all immediate predecessors - of non-head block are in the same region. */ + + /* Regions are SCCs with the exception of selective + scheduling with pipelining of outer blocks enabled. + So also check that immediate predecessors of a non-head + block are in the same region. */ FOR_EACH_EDGE (e, ei, bb->preds) { /* Avoid creating of loop-carried dependencies through - using topological odering in region. */ - if (BLOCK_TO_BB (bb->index) > BLOCK_TO_BB (e->src->index)) + using topological ordering in the region. */ + if (rgn == CONTAINING_RGN (e->src->index) + && BLOCK_TO_BB (bb->index) > BLOCK_TO_BB (e->src->index)) add_dependee_for_func_arg (first_arg, e->src); } } @@ -24952,7 +25035,8 @@ ix86_constant_alignment (tree exp, int align) int ix86_data_alignment (tree type, int align) { - int max_align = optimize_size ? BITS_PER_WORD : MIN (256, MAX_OFILE_ALIGNMENT); + int max_align + = optimize_size ? BITS_PER_WORD : MIN (256, MAX_OFILE_ALIGNMENT); if (AGGREGATE_TYPE_P (type) && TYPE_SIZE (type) @@ -27948,8 +28032,8 @@ static const struct builtin_description bdesc_multi_arg[] = { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv8hi3, "__builtin_ia32_vpshlw", IX86_BUILTIN_VPSHLW, UNKNOWN, (int)MULTI_ARG_2_HI }, { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv16qi3, "__builtin_ia32_vpshlb", IX86_BUILTIN_VPSHLB, UNKNOWN, (int)MULTI_ARG_2_QI }, - { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv4sf2, "__builtin_ia32_vfrczss", IX86_BUILTIN_VFRCZSS, UNKNOWN, (int)MULTI_ARG_2_SF }, - { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv2df2, "__builtin_ia32_vfrczsd", IX86_BUILTIN_VFRCZSD, UNKNOWN, (int)MULTI_ARG_2_DF }, + { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv4sf2, "__builtin_ia32_vfrczss", IX86_BUILTIN_VFRCZSS, UNKNOWN, (int)MULTI_ARG_1_SF }, + { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv2df2, "__builtin_ia32_vfrczsd", IX86_BUILTIN_VFRCZSD, UNKNOWN, (int)MULTI_ARG_1_DF }, { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4sf2, "__builtin_ia32_vfrczps", IX86_BUILTIN_VFRCZPS, UNKNOWN, (int)MULTI_ARG_1_SF }, { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv2df2, "__builtin_ia32_vfrczpd", IX86_BUILTIN_VFRCZPD, UNKNOWN, (int)MULTI_ARG_1_DF }, { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv8sf2, "__builtin_ia32_vfrczps256", IX86_BUILTIN_VFRCZPS256, UNKNOWN, (int)MULTI_ARG_1_SF2 }, @@ -28930,10 +29014,11 @@ dispatch_function_versions (tree dispatch_decl, if (predicate_chain == NULL_TREE) continue; + function_version_info [actual_versions].version_decl = version_decl; + function_version_info [actual_versions].predicate_chain + = predicate_chain; + function_version_info [actual_versions].dispatch_priority = priority; actual_versions++; - function_version_info [ix - 1].version_decl = version_decl; - function_version_info [ix - 1].predicate_chain = predicate_chain; - function_version_info [ix - 1].dispatch_priority = priority; } /* Sort the versions according to descending order of dispatch priority. The @@ -31208,11 +31293,12 @@ ix86_expand_args_builtin (const struct builtin_description *d, static rtx ix86_expand_special_args_builtin (const struct builtin_description *d, - tree exp, rtx target) + tree exp, rtx target) { tree arg; rtx pat, op; unsigned int i, nargs, arg_adjust, memory; + bool aligned_mem = false; struct { rtx op; @@ -31258,6 +31344,15 @@ ix86_expand_special_args_builtin (const struct builtin_description *d, nargs = 1; klass = load; memory = 0; + switch (icode) + { + case CODE_FOR_sse4_1_movntdqa: + case CODE_FOR_avx2_movntdqa: + aligned_mem = true; + break; + default: + break; + } break; case VOID_FTYPE_PV2SF_V4SF: case VOID_FTYPE_PV4DI_V4DI: @@ -31275,6 +31370,26 @@ ix86_expand_special_args_builtin (const struct builtin_description *d, klass = store; /* Reserve memory operand for target. */ memory = ARRAY_SIZE (args); + switch (icode) + { + /* These builtins and instructions require the memory + to be properly aligned. */ + case CODE_FOR_avx_movntv4di: + case CODE_FOR_sse2_movntv2di: + case CODE_FOR_avx_movntv8sf: + case CODE_FOR_sse_movntv4sf: + case CODE_FOR_sse4a_vmmovntv4sf: + case CODE_FOR_avx_movntv4df: + case CODE_FOR_sse2_movntv2df: + case CODE_FOR_sse4a_vmmovntv2df: + case CODE_FOR_sse2_movntidi: + case CODE_FOR_sse_movntq: + case CODE_FOR_sse2_movntisi: + aligned_mem = true; + break; + default: + break; + } break; case V4SF_FTYPE_V4SF_PCV2SF: case V2DF_FTYPE_V2DF_PCDOUBLE: @@ -31331,6 +31446,17 @@ ix86_expand_special_args_builtin (const struct builtin_description *d, { op = force_reg (Pmode, convert_to_mode (Pmode, op, 1)); target = gen_rtx_MEM (tmode, op); + /* target at this point has just BITS_PER_UNIT MEM_ALIGN + on it. Try to improve it using get_pointer_alignment, + and if the special builtin is one that requires strict + mode alignment, also from it's GET_MODE_ALIGNMENT. + Failure to do so could lead to ix86_legitimate_combined_insn + rejecting all changes to such insns. */ + unsigned int align = get_pointer_alignment (arg); + if (aligned_mem && align < GET_MODE_ALIGNMENT (tmode)) + align = GET_MODE_ALIGNMENT (tmode); + if (MEM_ALIGN (target) < align) + set_mem_align (target, align); } else target = force_reg (tmode, op); @@ -31376,8 +31502,17 @@ ix86_expand_special_args_builtin (const struct builtin_description *d, /* This must be the memory operand. */ op = force_reg (Pmode, convert_to_mode (Pmode, op, 1)); op = gen_rtx_MEM (mode, op); - gcc_assert (GET_MODE (op) == mode - || GET_MODE (op) == VOIDmode); + /* op at this point has just BITS_PER_UNIT MEM_ALIGN + on it. Try to improve it using get_pointer_alignment, + and if the special builtin is one that requires strict + mode alignment, also from it's GET_MODE_ALIGNMENT. + Failure to do so could lead to ix86_legitimate_combined_insn + rejecting all changes to such insns. */ + unsigned int align = get_pointer_alignment (arg); + if (aligned_mem && align < GET_MODE_ALIGNMENT (mode)) + align = GET_MODE_ALIGNMENT (mode); + if (MEM_ALIGN (op) < align) + set_mem_align (op, align); } else { @@ -31775,7 +31910,13 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, } if (target == 0) - target = gen_reg_rtx (mode); + { + /* mode is VOIDmode if __builtin_rd* has been called + without lhs. */ + if (mode == VOIDmode) + return target; + target = gen_reg_rtx (mode); + } if (TARGET_64BIT) { @@ -31984,7 +32125,8 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, else op2 = gen_rtx_SUBREG (SImode, op0, 0); - if (target == 0) + if (target == 0 + || !register_operand (target, SImode)) target = gen_reg_rtx (SImode); pat = gen_rtx_GEU (VOIDmode, gen_rtx_REG (CCCmode, FLAGS_REG), @@ -32026,7 +32168,8 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, const0_rtx); emit_insn (gen_rtx_SET (VOIDmode, op2, pat)); - if (target == 0) + if (target == 0 + || !register_operand (target, SImode)) target = gen_reg_rtx (SImode); emit_insn (gen_zero_extendqisi2 (target, op2)); @@ -32165,7 +32308,9 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, mode4 = insn_data[icode].operand[5].mode; if (target == NULL_RTX - || GET_MODE (target) != insn_data[icode].operand[0].mode) + || GET_MODE (target) != insn_data[icode].operand[0].mode + || !insn_data[icode].operand[0].predicate (target, + GET_MODE (target))) subtarget = gen_reg_rtx (insn_data[icode].operand[0].mode); else subtarget = target; @@ -33836,10 +33981,10 @@ ix86_hard_regno_mode_ok (int regno, enum machine_mode mode) { /* We implement the move patterns for all vector modes into and out of SSE registers, even when no operation instructions - are available. OImode move is available only when AVX is - enabled. */ - return ((TARGET_AVX && mode == OImode) - || VALID_AVX256_REG_MODE (mode) + are available. OImode and AVX modes are available only when + AVX is enabled. */ + return ((TARGET_AVX + && VALID_AVX256_REG_OR_OI_MODE (mode)) || VALID_SSE_REG_MODE (mode) || VALID_SSE2_REG_MODE (mode) || VALID_MMX_REG_MODE (mode) @@ -33862,6 +34007,11 @@ ix86_hard_regno_mode_ok (int regno, enum machine_mode mode) return true; if (!TARGET_PARTIAL_REG_STALL) return true; + /* LRA checks if the hard register is OK for the given mode. + QImode values can live in non-QI regs, so we allow all + registers here. */ + if (lra_in_progress) + return true; return !can_create_pseudo_p (); } /* We handle both integer and floats in the general purpose registers. */ @@ -34170,6 +34320,13 @@ ix86_rtx_costs (rtx x, int code_i, int outer_code_i, int opno, int *total, { if (CONST_INT_P (XEXP (x, 1))) *total = cost->shift_const; + else if (GET_CODE (XEXP (x, 1)) == SUBREG + && GET_CODE (XEXP (XEXP (x, 1), 0)) == AND) + { + /* Return the cost after shift-and truncation. */ + *total = cost->shift_var; + return true; + } else *total = cost->shift_var; } @@ -34965,7 +35122,7 @@ x86_output_mi_thunk (FILE *file, { tmp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, fnaddr), UNSPEC_GOTPCREL); tmp = gen_rtx_CONST (Pmode, tmp); - fnaddr = gen_rtx_MEM (Pmode, tmp); + fnaddr = gen_const_mem (Pmode, tmp); } } else @@ -34985,8 +35142,9 @@ x86_output_mi_thunk (FILE *file, output_set_got (tmp, NULL_RTX); fnaddr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, fnaddr), UNSPEC_GOT); - fnaddr = gen_rtx_PLUS (Pmode, fnaddr, tmp); - fnaddr = gen_rtx_MEM (Pmode, fnaddr); + fnaddr = gen_rtx_CONST (Pmode, fnaddr); + fnaddr = gen_rtx_PLUS (Pmode, tmp, fnaddr); + fnaddr = gen_const_mem (Pmode, fnaddr); } } @@ -35177,7 +35335,10 @@ ix86_avoid_jump_mispredicts (void) The smallest offset in the page INSN can start is the case where START ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN). We add p2align to 16byte window with maxskip 15 - NBYTES + sizeof (INSN). - */ + + Don't consider asm goto as jump, while it can contain a jump, it doesn't + have to, control transfer to label(s) can be performed through other + means, and also we estimate minimum length of all asm stmts as 0. */ for (insn = start; insn; insn = NEXT_INSN (insn)) { int min_size; @@ -35205,6 +35366,7 @@ ix86_avoid_jump_mispredicts (void) { start = NEXT_INSN (start); if ((JUMP_P (start) + && asm_noperands (PATTERN (start)) < 0 && GET_CODE (PATTERN (start)) != ADDR_VEC && GET_CODE (PATTERN (start)) != ADDR_DIFF_VEC) || CALL_P (start)) @@ -35223,6 +35385,7 @@ ix86_avoid_jump_mispredicts (void) fprintf (dump_file, "Insn %i estimated to %i bytes\n", INSN_UID (insn), min_size); if ((JUMP_P (insn) + && asm_noperands (PATTERN (insn)) < 0 && GET_CODE (PATTERN (insn)) != ADDR_VEC && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC) || CALL_P (insn)) @@ -35234,6 +35397,7 @@ ix86_avoid_jump_mispredicts (void) { start = NEXT_INSN (start); if ((JUMP_P (start) + && asm_noperands (PATTERN (start)) < 0 && GET_CODE (PATTERN (start)) != ADDR_VEC && GET_CODE (PATTERN (start)) != ADDR_DIFF_VEC) || CALL_P (start)) @@ -35427,6 +35591,46 @@ ix86_pad_short_function (void) } } +/* Fix up a Windows system unwinder issue. If an EH region falls thru into + the epilogue, the Windows system unwinder will apply epilogue logic and + produce incorrect offsets. This can be avoided by adding a nop between + the last insn that can throw and the first insn of the epilogue. */ + +static void +ix86_seh_fixup_eh_fallthru (void) +{ + edge e; + edge_iterator ei; + + FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR->preds) + { + rtx insn, next; + + /* Find the beginning of the epilogue. */ + for (insn = BB_END (e->src); insn != NULL; insn = PREV_INSN (insn)) + if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_EPILOGUE_BEG) + break; + if (insn == NULL) + continue; + + /* We only care about preceeding insns that can throw. */ + insn = prev_active_insn (insn); + if (insn == NULL || !can_throw_internal (insn)) + continue; + + /* Do not separate calls from their debug information. */ + for (next = NEXT_INSN (insn); next != NULL; next = NEXT_INSN (next)) + if (NOTE_P (next) + && (NOTE_KIND (next) == NOTE_INSN_VAR_LOCATION + || NOTE_KIND (next) == NOTE_INSN_CALL_ARG_LOCATION)) + insn = next; + else + break; + + emit_insn_after (gen_nops (const1_rtx), insn); + } +} + /* Implement machine specific optimizations. We implement padding of returns for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */ static void @@ -35436,6 +35640,9 @@ ix86_reorg (void) with old MDEP_REORGS that are not CFG based. Recompute it now. */ compute_bb_for_insn (); + if (TARGET_SEH && current_function_has_exception_handlers ()) + ix86_seh_fixup_eh_fallthru (); + if (optimize && optimize_function_for_speed_p (cfun)) { if (TARGET_PAD_SHORT_FUNCTION) @@ -38666,8 +38873,8 @@ expand_vec_perm_pshufb (struct expand_vec_perm_d *d) op0 = gen_lowpart (V4DImode, d->op0); op1 = gen_lowpart (V4DImode, d->op1); rperm[0] - = GEN_INT (((d->perm[0] & (nelt / 2)) ? 1 : 0) - || ((d->perm[nelt / 2] & (nelt / 2)) ? 2 : 0)); + = GEN_INT ((d->perm[0] / (nelt / 2)) + | ((d->perm[nelt / 2] / (nelt / 2)) * 16)); emit_insn (gen_avx2_permv2ti (target, op0, op1, rperm[0])); return true; } @@ -39273,7 +39480,9 @@ expand_vec_perm_interleave2 (struct expand_vec_perm_d *d) else dfinal.perm[i] = e; } - dfinal.op0 = gen_reg_rtx (dfinal.vmode); + + if (!d->testing_p) + dfinal.op0 = gen_reg_rtx (dfinal.vmode); dfinal.op1 = dfinal.op0; dfinal.one_operand_p = true; dremap.target = dfinal.op0; @@ -39708,6 +39917,9 @@ expand_vec_perm_pshufb2 (struct expand_vec_perm_d *d) return false; gcc_assert (!d->one_operand_p); + if (d->testing_p) + return true; + nelt = d->nelt; eltsz = GET_MODE_SIZE (GET_MODE_INNER (d->vmode)); @@ -39907,6 +40119,8 @@ expand_vec_perm_even_odd_1 (struct expand_vec_perm_d *d, unsigned odd) switch (d->vmode) { case V4DFmode: + if (d->testing_p) + break; t1 = gen_reg_rtx (V4DFmode); t2 = gen_reg_rtx (V4DFmode); @@ -39926,6 +40140,8 @@ expand_vec_perm_even_odd_1 (struct expand_vec_perm_d *d, unsigned odd) { int mask = odd ? 0xdd : 0x88; + if (d->testing_p) + break; t1 = gen_reg_rtx (V8SFmode); t2 = gen_reg_rtx (V8SFmode); t3 = gen_reg_rtx (V8SFmode); @@ -39967,6 +40183,8 @@ expand_vec_perm_even_odd_1 (struct expand_vec_perm_d *d, unsigned odd) return expand_vec_perm_pshufb2 (d); else { + if (d->testing_p) + break; /* We need 2*log2(N)-1 operations to achieve odd/even with interleave. */ t1 = gen_reg_rtx (V8HImode); @@ -39988,6 +40206,8 @@ expand_vec_perm_even_odd_1 (struct expand_vec_perm_d *d, unsigned odd) return expand_vec_perm_pshufb2 (d); else { + if (d->testing_p) + break; t1 = gen_reg_rtx (V16QImode); t2 = gen_reg_rtx (V16QImode); t3 = gen_reg_rtx (V16QImode); @@ -40020,6 +40240,9 @@ expand_vec_perm_even_odd_1 (struct expand_vec_perm_d *d, unsigned odd) return expand_vec_perm_even_odd_1 (&d_copy, odd); } + if (d->testing_p) + break; + t1 = gen_reg_rtx (V4DImode); t2 = gen_reg_rtx (V4DImode); @@ -40046,6 +40269,9 @@ expand_vec_perm_even_odd_1 (struct expand_vec_perm_d *d, unsigned odd) return expand_vec_perm_even_odd_1 (&d_copy, odd); } + if (d->testing_p) + break; + t1 = gen_reg_rtx (V8SImode); t2 = gen_reg_rtx (V8SImode); @@ -40138,6 +40364,8 @@ expand_vec_perm_broadcast_1 (struct expand_vec_perm_d *d) case V16QImode: /* These can be implemented via interleave. We save one insn by stopping once we have promoted to V4SImode and then use pshufd. */ + if (d->testing_p) + return true; do { rtx dest; @@ -40716,7 +40944,9 @@ ix86_expand_mul_widen_evenodd (rtx dest, rtx op1, rtx op2, the even slots. For some cpus this is faster than a PSHUFD. */ if (odd_p) { - if (TARGET_XOP && mode == V4SImode) + /* For XOP use vpmacsdqh, but only for smult, as it is only + signed. */ + if (TARGET_XOP && mode == V4SImode && !uns_p) { x = force_reg (wmode, CONST0_RTX (wmode)); emit_insn (gen_xop_pmacsdqh (dest, op1, op2, x)); @@ -41198,7 +41428,8 @@ ix86_enum_va_list (int idx, const char **pname, tree *ptree) #undef TARGET_SCHED_ADJUST_PRIORITY #define TARGET_SCHED_ADJUST_PRIORITY ix86_adjust_priority #undef TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK -#define TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK ix86_dependencies_evaluation_hook +#define TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK \ + ix86_dependencies_evaluation_hook /* The size of the dispatch window is the total number of bytes of object code allowed in a window. */ @@ -42185,6 +42416,8 @@ ix86_memmodel_check (unsigned HOST_WIDE_INT val) #undef TARGET_ATTRIBUTE_TABLE #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table +#undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P +#define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true #if TARGET_DLLIMPORT_DECL_ATTRIBUTES # undef TARGET_MERGE_DECL_ATTRIBUTES # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes @@ -42370,8 +42603,6 @@ ix86_memmodel_check (unsigned HOST_WIDE_INT val) #undef TARGET_PROMOTE_PROTOTYPES #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true -#undef TARGET_STRUCT_VALUE_RTX -#define TARGET_STRUCT_VALUE_RTX ix86_struct_value_rtx #undef TARGET_SETUP_INCOMING_VARARGS #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs #undef TARGET_MUST_PASS_IN_STACK diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index a69862c549f4a..335cf611d7984 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -197,10 +197,10 @@ extern const struct processor_costs ix86_size_cost; /* Macros used in the machine description to test the flags. */ -/* configure can arrange to make this 2, to force a 486. */ +/* configure can arrange to change it. */ #ifndef TARGET_CPU_DEFAULT -#define TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT_generic +#define TARGET_CPU_DEFAULT PROCESSOR_GENERIC32 #endif #ifndef TARGET_FPMATH_DEFAULT @@ -591,43 +591,6 @@ extern const char *host_detect_local_cpu (int argc, const char **argv); /* Target Pragmas. */ #define REGISTER_TARGET_PRAGMAS() ix86_register_pragmas () -enum target_cpu_default -{ - TARGET_CPU_DEFAULT_generic = 0, - - TARGET_CPU_DEFAULT_i386, - TARGET_CPU_DEFAULT_i486, - TARGET_CPU_DEFAULT_pentium, - TARGET_CPU_DEFAULT_pentium_mmx, - TARGET_CPU_DEFAULT_pentiumpro, - TARGET_CPU_DEFAULT_pentium2, - TARGET_CPU_DEFAULT_pentium3, - TARGET_CPU_DEFAULT_pentium4, - TARGET_CPU_DEFAULT_pentium_m, - TARGET_CPU_DEFAULT_prescott, - TARGET_CPU_DEFAULT_nocona, - TARGET_CPU_DEFAULT_core2, - TARGET_CPU_DEFAULT_corei7, - TARGET_CPU_DEFAULT_haswell, - TARGET_CPU_DEFAULT_atom, - - TARGET_CPU_DEFAULT_geode, - TARGET_CPU_DEFAULT_k6, - TARGET_CPU_DEFAULT_k6_2, - TARGET_CPU_DEFAULT_k6_3, - TARGET_CPU_DEFAULT_athlon, - TARGET_CPU_DEFAULT_athlon_sse, - TARGET_CPU_DEFAULT_k8, - TARGET_CPU_DEFAULT_amdfam10, - TARGET_CPU_DEFAULT_bdver1, - TARGET_CPU_DEFAULT_bdver2, - TARGET_CPU_DEFAULT_bdver3, - TARGET_CPU_DEFAULT_btver1, - TARGET_CPU_DEFAULT_btver2, - - TARGET_CPU_DEFAULT_max -}; - #ifndef CC1_SPEC #define CC1_SPEC "%(cc1_cpu) " #endif @@ -2089,32 +2052,33 @@ do { \ with x86-64 medium memory model */ #define DEFAULT_LARGE_SECTION_THRESHOLD 65536 -/* Which processor to tune code generation for. */ +/* Which processor to tune code generation for. These must be in sync + with processor_target_table in i386.c. */ enum processor_type { - PROCESSOR_I386 = 0, /* 80386 */ + PROCESSOR_GENERIC32 = 0, + PROCESSOR_GENERIC64, + PROCESSOR_I386, /* 80386 */ PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */ PROCESSOR_PENTIUM, PROCESSOR_PENTIUMPRO, - PROCESSOR_GEODE, - PROCESSOR_K6, - PROCESSOR_ATHLON, PROCESSOR_PENTIUM4, - PROCESSOR_K8, PROCESSOR_NOCONA, PROCESSOR_CORE2, PROCESSOR_COREI7, PROCESSOR_HASWELL, - PROCESSOR_GENERIC32, - PROCESSOR_GENERIC64, + PROCESSOR_ATOM, + PROCESSOR_GEODE, + PROCESSOR_K6, + PROCESSOR_ATHLON, + PROCESSOR_K8, PROCESSOR_AMDFAM10, PROCESSOR_BDVER1, PROCESSOR_BDVER2, PROCESSOR_BDVER3, PROCESSOR_BTVER1, PROCESSOR_BTVER2, - PROCESSOR_ATOM, PROCESSOR_max }; diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 24d1012d5ce02..c08a2245dd126 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -222,6 +222,8 @@ UNSPECV_XEND UNSPECV_XABORT UNSPECV_XTEST + + UNSPECV_NLGR ]) ;; Constants to represent rounding modes in the ROUND instruction @@ -361,6 +363,13 @@ (const_string "unknown")] (const_string "integer"))) +;; The minimum required alignment of vector mode memory operands of the SSE +;; (non-VEX/EVEX) instruction in bits, if it is different from +;; GET_MODE_ALIGNMENT of the operand, otherwise 0. If an instruction has +;; multiple alternatives, this should be conservative maximum of those minimum +;; required alignments. +(define_attr "ssememalign" "" (const_int 0)) + ;; The (bounding maximum) length of an instruction immediate. (define_attr "length_immediate" "" (cond [(eq_attr "type" "incdec,setcc,icmov,str,lea,other,multi,idiv,leave, @@ -1568,7 +1577,7 @@ split_double_mode (DImode, &operands[1], 1, &operands[2], &operands[3]); operands[1] = gen_lowpart (DImode, operands[2]); - operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx, + operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (4))); }) @@ -1585,7 +1594,7 @@ split_double_mode (DImode, &operands[1], 1, &operands[2], &operands[3]); operands[1] = gen_lowpart (DImode, operands[2]); - operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx, + operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (4))); }) @@ -1798,6 +1807,8 @@ (set (attr "mode") (cond [(eq_attr "alternative" "0,1") (const_string "DI") + (not (match_test "TARGET_SSE2")) + (const_string "V4SF") (match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL") (const_string "V4SF") (and (eq_attr "alternative" "4") @@ -1854,15 +1865,16 @@ [(set_attr "type" "sselog1,ssemov,ssemov") (set_attr "prefix" "maybe_vex") (set (attr "mode") - (cond [(match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL") + (cond [(not (match_test "TARGET_SSE2")) + (const_string "V4SF") + (match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL") (const_string "V4SF") (and (eq_attr "alternative" "2") (match_test "TARGET_SSE_TYPELESS_STORES")) (const_string "V4SF") (match_test "TARGET_AVX") (const_string "TI") - (ior (not (match_test "TARGET_SSE2")) - (match_test "optimize_function_for_size_p (cfun)")) + (match_test "optimize_function_for_size_p (cfun)") (const_string "V4SF") ] (const_string "TI")))]) @@ -1933,7 +1945,8 @@ (const_string "ssemov") (eq_attr "alternative" "15,16") (const_string "ssecvt") - (match_operand 1 "pic_32bit_operand") + (and (match_operand 0 "register_operand") + (match_operand 1 "pic_32bit_operand")) (const_string "lea") ] (const_string "imov"))) @@ -2159,7 +2172,8 @@ (const_string "sselog1") (eq_attr "alternative" "7,8,9,10,11") (const_string "ssemov") - (match_operand 1 "pic_32bit_operand") + (and (match_operand 0 "register_operand") + (match_operand 1 "pic_32bit_operand")) (const_string "lea") ] (const_string "imov"))) @@ -2311,7 +2325,7 @@ "TARGET_LP64 && ix86_check_movabs (insn, 0)" "@ movabs{}\t{%1, %P0|[%P0], %1} - mov{}\t{%1, %a0|%a0, %1}" + mov{}\t{%1, %a0| PTR %a0, %1}" [(set_attr "type" "imov") (set_attr "modrm" "0,*") (set_attr "length_address" "8,0") @@ -2325,7 +2339,7 @@ "TARGET_LP64 && ix86_check_movabs (insn, 1)" "@ movabs{}\t{%P1, %0|%0, [%P1]} - mov{}\t{%a1, %0|%0, %a1}" + mov{}\t{%a1, %0|%0, PTR %a1}" [(set_attr "type" "imov") (set_attr "modrm" "0,*") (set_attr "length_address" "8,0") @@ -2710,7 +2724,20 @@ "reload_completed" [(set (reg:P SP_REG) (plus:P (reg:P SP_REG) (match_dup 2))) (set (mem:SF (reg:P SP_REG)) (match_dup 1))] - "operands[2] = GEN_INT (-GET_MODE_SIZE (mode));") +{ + rtx op = XEXP (operands[0], 0); + if (GET_CODE (op) == PRE_DEC) + { + gcc_assert (!TARGET_64BIT); + op = GEN_INT (-4); + } + else + { + op = XEXP (XEXP (op, 1), 1); + gcc_assert (CONST_INT_P (op)); + } + operands[2] = op; +}) (define_split [(set (match_operand:SF 0 "push_operand") @@ -3281,7 +3308,7 @@ (cond [(eq_attr "alternative" "0,1,2") (const_string "fmov") (eq_attr "alternative" "3,4") - (const_string "multi") + (const_string "imov") (eq_attr "alternative" "5") (const_string "sselog1") (eq_attr "alternative" "9,10,11,14,15") @@ -3432,10 +3459,10 @@ (define_insn "*zero_extendsidi2_rex64" [(set (match_operand:DI 0 "nonimmediate_operand" - "=r ,o,?*Ym,?*y,?*Yi,?*x") + "=r ,o,?*Ym,?!*y,?*Yi,?*x") (zero_extend:DI (match_operand:SI 1 "x86_64_zext_general_operand" - "rmWz,0,r ,m ,r ,m")))] + "rmWz,0,r ,m ,r ,m")))] "TARGET_64BIT" { switch (get_attr_type (insn)) @@ -3466,9 +3493,9 @@ (define_insn "*zero_extendsidi2" [(set (match_operand:DI 0 "nonimmediate_operand" - "=ro,?r,?o,?*Ym,?*y,?*Yi,?*x") + "=ro,?r,?o,?*Ym,?!*y,?*Yi,?*x") (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" - "0 ,rm,r ,r ,m ,r ,m")))] + "0 ,rm,r ,r ,m ,r ,m")))] "!TARGET_64BIT" "@ # @@ -3647,22 +3674,8 @@ "!TARGET_64BIT" "#") -;; Extend to memory case when source register does die. -(define_split - [(set (match_operand:DI 0 "memory_operand") - (sign_extend:DI (match_operand:SI 1 "register_operand"))) - (clobber (reg:CC FLAGS_REG)) - (clobber (match_operand:SI 2 "register_operand"))] - "(reload_completed - && dead_or_set_p (insn, operands[1]) - && !reg_mentioned_p (operands[1], operands[0]))" - [(set (match_dup 3) (match_dup 1)) - (parallel [(set (match_dup 1) (ashiftrt:SI (match_dup 1) (const_int 31))) - (clobber (reg:CC FLAGS_REG))]) - (set (match_dup 4) (match_dup 1))] - "split_double_mode (DImode, &operands[0], 1, &operands[3], &operands[4]);") - -;; Extend to memory case when source register does not die. +;; Split the memory case. If the source register doesn't die, it will stay +;; this way, if it does die, following peephole2s take care of it. (define_split [(set (match_operand:DI 0 "memory_operand") (sign_extend:DI (match_operand:SI 1 "register_operand"))) @@ -3691,6 +3704,44 @@ DONE; }) +;; Peepholes for the case where the source register does die, after +;; being split with the above splitter. +(define_peephole2 + [(set (match_operand:SI 0 "memory_operand") + (match_operand:SI 1 "register_operand")) + (set (match_operand:SI 2 "register_operand") (match_dup 1)) + (parallel [(set (match_dup 2) + (ashiftrt:SI (match_dup 2) (const_int 31))) + (clobber (reg:CC FLAGS_REG))]) + (set (match_operand:SI 3 "memory_operand") (match_dup 2))] + "REGNO (operands[1]) != REGNO (operands[2]) + && peep2_reg_dead_p (2, operands[1]) + && peep2_reg_dead_p (4, operands[2]) + && !reg_mentioned_p (operands[2], operands[3])" + [(set (match_dup 0) (match_dup 1)) + (parallel [(set (match_dup 1) (ashiftrt:SI (match_dup 1) (const_int 31))) + (clobber (reg:CC FLAGS_REG))]) + (set (match_dup 3) (match_dup 1))]) + +(define_peephole2 + [(set (match_operand:SI 0 "memory_operand") + (match_operand:SI 1 "register_operand")) + (parallel [(set (match_operand:SI 2 "register_operand") + (ashiftrt:SI (match_dup 1) (const_int 31))) + (clobber (reg:CC FLAGS_REG))]) + (set (match_operand:SI 3 "memory_operand") (match_dup 2))] + "/* cltd is shorter than sarl $31, %eax */ + !optimize_function_for_size_p (cfun) + && true_regnum (operands[1]) == AX_REG + && true_regnum (operands[2]) == DX_REG + && peep2_reg_dead_p (2, operands[1]) + && peep2_reg_dead_p (3, operands[2]) + && !reg_mentioned_p (operands[2], operands[3])" + [(set (match_dup 0) (match_dup 1)) + (parallel [(set (match_dup 1) (ashiftrt:SI (match_dup 1) (const_int 31))) + (clobber (reg:CC FLAGS_REG))]) + (set (match_dup 3) (match_dup 1))]) + ;; Extend to register case. Optimize case where source and destination ;; registers match and cases where we can use cltd. (define_split @@ -5290,66 +5341,37 @@ ;; Avoid store forwarding (partial memory) stall penalty by extending ;; SImode value to DImode through XMM register instead of pushing two -;; SImode values to stack. Note that even !TARGET_INTER_UNIT_MOVES -;; targets benefit from this optimization. Also note that fild -;; loads from memory only. +;; SImode values to stack. Also note that fild loads from memory only. -(define_insn "*floatunssi2_1" - [(set (match_operand:X87MODEF 0 "register_operand" "=f,f") +(define_insn_and_split "*floatunssi2_i387_with_xmm" + [(set (match_operand:X87MODEF 0 "register_operand" "=f") (unsigned_float:X87MODEF - (match_operand:SI 1 "nonimmediate_operand" "x,m"))) - (clobber (match_operand:DI 2 "memory_operand" "=m,m")) - (clobber (match_scratch:SI 3 "=X,x"))] + (match_operand:SI 1 "nonimmediate_operand" "rm"))) + (clobber (match_scratch:DI 3 "=x")) + (clobber (match_operand:DI 2 "memory_operand" "=m"))] "!TARGET_64BIT && TARGET_80387 && X87_ENABLE_FLOAT (mode, DImode) - && TARGET_SSE" + && TARGET_SSE2 && TARGET_INTER_UNIT_MOVES" "#" - [(set_attr "type" "multi") - (set_attr "mode" "")]) - -(define_split - [(set (match_operand:X87MODEF 0 "register_operand") - (unsigned_float:X87MODEF - (match_operand:SI 1 "register_operand"))) - (clobber (match_operand:DI 2 "memory_operand")) - (clobber (match_scratch:SI 3))] - "!TARGET_64BIT - && TARGET_80387 && X87_ENABLE_FLOAT (mode, DImode) - && TARGET_SSE - && reload_completed" - [(set (match_dup 2) (match_dup 1)) - (set (match_dup 0) - (float:X87MODEF (match_dup 2)))] - "operands[1] = simplify_gen_subreg (DImode, operands[1], SImode, 0);") - -(define_split - [(set (match_operand:X87MODEF 0 "register_operand") - (unsigned_float:X87MODEF - (match_operand:SI 1 "memory_operand"))) - (clobber (match_operand:DI 2 "memory_operand")) - (clobber (match_scratch:SI 3))] - "!TARGET_64BIT - && TARGET_80387 && X87_ENABLE_FLOAT (mode, DImode) - && TARGET_SSE - && reload_completed" - [(set (match_dup 2) (match_dup 3)) + "&& reload_completed" + [(set (match_dup 3) (zero_extend:DI (match_dup 1))) + (set (match_dup 2) (match_dup 3)) (set (match_dup 0) (float:X87MODEF (match_dup 2)))] -{ - emit_move_insn (operands[3], operands[1]); - operands[3] = simplify_gen_subreg (DImode, operands[3], SImode, 0); -}) + "" + [(set_attr "type" "multi") + (set_attr "mode" "")]) (define_expand "floatunssi2" [(parallel [(set (match_operand:X87MODEF 0 "register_operand") (unsigned_float:X87MODEF (match_operand:SI 1 "nonimmediate_operand"))) - (clobber (match_dup 2)) - (clobber (match_scratch:SI 3))])] + (clobber (match_scratch:DI 3)) + (clobber (match_dup 2))])] "!TARGET_64BIT && ((TARGET_80387 && X87_ENABLE_FLOAT (mode, DImode) - && TARGET_SSE) + && TARGET_SSE2 && TARGET_INTER_UNIT_MOVES) || (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH))" { if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) @@ -5414,6 +5436,12 @@ mode = SImode; ix86_split_lea_for_addr (curr_insn, operands, mode); + + /* Zero-extend return register to DImode for zero-extended addresses. */ + if (mode != mode) + emit_insn (gen_zero_extendsidi2 + (operands[0], gen_lowpart (mode, operands[0]))); + DONE; } [(set_attr "type" "lea") @@ -6560,7 +6588,7 @@ (set_attr "use_carry" "1") (set_attr "mode" "")]) -;; Overflow setting add and subtract instructions +;; Overflow setting add instructions (define_insn "*add3_cconly_overflow" [(set (reg:CCC FLAGS_REG) @@ -6575,43 +6603,31 @@ [(set_attr "type" "alu") (set_attr "mode" "")]) -(define_insn "*sub3_cconly_overflow" - [(set (reg:CCC FLAGS_REG) - (compare:CCC - (minus:SWI - (match_operand:SWI 0 "nonimmediate_operand" "m,") - (match_operand:SWI 1 "" ",m")) - (match_dup 0)))] - "" - "cmp{}\t{%1, %0|%0, %1}" - [(set_attr "type" "icmp") - (set_attr "mode" "")]) - -(define_insn "*3_cc_overflow" +(define_insn "*add3_cc_overflow" [(set (reg:CCC FLAGS_REG) (compare:CCC - (plusminus:SWI - (match_operand:SWI 1 "nonimmediate_operand" "0,0") + (plus:SWI + (match_operand:SWI 1 "nonimmediate_operand" "%0,0") (match_operand:SWI 2 "" ",m")) (match_dup 1))) (set (match_operand:SWI 0 "nonimmediate_operand" "=m,") - (plusminus:SWI (match_dup 1) (match_dup 2)))] - "ix86_binary_operator_ok (, mode, operands)" - "{}\t{%2, %0|%0, %2}" + (plus:SWI (match_dup 1) (match_dup 2)))] + "ix86_binary_operator_ok (PLUS, mode, operands)" + "add{}\t{%2, %0|%0, %2}" [(set_attr "type" "alu") (set_attr "mode" "")]) -(define_insn "*si3_zext_cc_overflow" +(define_insn "*addsi3_zext_cc_overflow" [(set (reg:CCC FLAGS_REG) (compare:CCC - (plusminus:SI - (match_operand:SI 1 "nonimmediate_operand" "0") + (plus:SI + (match_operand:SI 1 "nonimmediate_operand" "%0") (match_operand:SI 2 "x86_64_general_operand" "rme")) (match_dup 1))) (set (match_operand:DI 0 "register_operand" "=r") - (zero_extend:DI (plusminus:SI (match_dup 1) (match_dup 2))))] - "TARGET_64BIT && ix86_binary_operator_ok (, SImode, operands)" - "{l}\t{%2, %k0|%k0, %2}" + (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))] + "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)" + "add{l}\t{%2, %k0|%k0, %2}" [(set_attr "type" "alu") (set_attr "mode" "SI")]) @@ -7983,7 +7999,18 @@ (const_int 0))) (set (match_operand:DI 0 "nonimmediate_operand" "=r,r,rm") (and:DI (match_dup 1) (match_dup 2)))] - "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode) + "TARGET_64BIT + && ix86_match_ccmode + (insn, + /* If we are going to emit andl instead of andq, and the operands[2] + constant might have the SImode sign bit set, make sure the sign + flag isn't tested, because the instruction will set the sign flag + based on bit 31 rather than bit 63. If it isn't CONST_INT, + conservatively assume it might have bit 31 set. */ + (satisfies_constraint_Z (operands[2]) + && (!CONST_INT_P (operands[2]) + || val_signbit_known_set_p (SImode, INTVAL (operands[2])))) + ? CCZmode : CCNOmode) && ix86_binary_operator_ok (AND, DImode, operands)" "@ and{l}\t{%k2, %k0|%k0, %k2} @@ -9136,28 +9163,20 @@ }) ;; Avoid useless masking of count operand. -(define_insn_and_split "*ashl3_mask" +(define_insn "*ashl3_mask" [(set (match_operand:SWI48 0 "nonimmediate_operand" "=rm") (ashift:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "0") (subreg:QI (and:SI - (match_operand:SI 2 "nonimmediate_operand" "c") + (match_operand:SI 2 "register_operand" "c") (match_operand:SI 3 "const_int_operand" "n")) 0))) (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (ASHIFT, mode, operands) && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (mode)-1)) == GET_MODE_BITSIZE (mode)-1" - "#" - "&& 1" - [(parallel [(set (match_dup 0) - (ashift:SWI48 (match_dup 1) (match_dup 2))) - (clobber (reg:CC FLAGS_REG))])] { - if (can_create_pseudo_p ()) - operands [2] = force_reg (SImode, operands[2]); - - operands[2] = simplify_gen_subreg (QImode, operands[2], SImode, 0); + return "sal{}\t{%b2, %0|%0, %b2}"; } [(set_attr "type" "ishift") (set_attr "mode" "")]) @@ -9646,28 +9665,20 @@ "ix86_expand_binary_operator (, mode, operands); DONE;") ;; Avoid useless masking of count operand. -(define_insn_and_split "*3_mask" +(define_insn "*3_mask" [(set (match_operand:SWI48 0 "nonimmediate_operand" "=rm") (any_shiftrt:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "0") (subreg:QI (and:SI - (match_operand:SI 2 "nonimmediate_operand" "c") + (match_operand:SI 2 "register_operand" "c") (match_operand:SI 3 "const_int_operand" "n")) 0))) (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (, mode, operands) && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (mode)-1)) == GET_MODE_BITSIZE (mode)-1" - "#" - "&& 1" - [(parallel [(set (match_dup 0) - (any_shiftrt:SWI48 (match_dup 1) (match_dup 2))) - (clobber (reg:CC FLAGS_REG))])] { - if (can_create_pseudo_p ()) - operands [2] = force_reg (SImode, operands[2]); - - operands[2] = simplify_gen_subreg (QImode, operands[2], SImode, 0); + return "{}\t{%b2, %0|%0, %b2}"; } [(set_attr "type" "ishift") (set_attr "mode" "")]) @@ -10109,28 +10120,20 @@ "ix86_expand_binary_operator (, mode, operands); DONE;") ;; Avoid useless masking of count operand. -(define_insn_and_split "*3_mask" +(define_insn "*3_mask" [(set (match_operand:SWI48 0 "nonimmediate_operand" "=rm") (any_rotate:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "0") (subreg:QI (and:SI - (match_operand:SI 2 "nonimmediate_operand" "c") + (match_operand:SI 2 "register_operand" "c") (match_operand:SI 3 "const_int_operand" "n")) 0))) (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (, mode, operands) && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (mode)-1)) == GET_MODE_BITSIZE (mode)-1" - "#" - "&& 1" - [(parallel [(set (match_dup 0) - (any_rotate:SWI48 (match_dup 1) (match_dup 2))) - (clobber (reg:CC FLAGS_REG))])] { - if (can_create_pseudo_p ()) - operands [2] = force_reg (SImode, operands[2]); - - operands[2] = simplify_gen_subreg (QImode, operands[2], SImode, 0); + return "{}\t{%b2, %0|%0, %b2}"; } [(set_attr "type" "rotate") (set_attr "mode" "")]) @@ -12117,8 +12120,8 @@ (define_insn "bmi_bextr_" [(set (match_operand:SWI48 0 "register_operand" "=r,r") - (unspec:SWI48 [(match_operand:SWI48 1 "register_operand" "r,r") - (match_operand:SWI48 2 "nonimmediate_operand" "r,m")] + (unspec:SWI48 [(match_operand:SWI48 1 "nonimmediate_operand" "r,m") + (match_operand:SWI48 2 "register_operand" "r,r")] UNSPEC_BEXTR)) (clobber (reg:CC FLAGS_REG))] "TARGET_BMI" @@ -12169,18 +12172,52 @@ (set_attr "mode" "")]) ;; BMI2 instructions. -(define_insn "bmi2_bzhi_3" +(define_expand "bmi2_bzhi_3" + [(parallel + [(set (match_operand:SWI48 0 "register_operand") + (zero_extract:SWI48 + (match_operand:SWI48 1 "nonimmediate_operand") + (umin:SWI48 + (and:SWI48 (match_operand:SWI48 2 "register_operand") + (const_int 255)) + (match_dup 3)) + (const_int 0))) + (clobber (reg:CC FLAGS_REG))])] + "TARGET_BMI2" + "operands[3] = GEN_INT (GET_MODE_BITSIZE (mode));") + +(define_insn "*bmi2_bzhi_3" [(set (match_operand:SWI48 0 "register_operand" "=r") - (and:SWI48 (match_operand:SWI48 1 "register_operand" "r") - (lshiftrt:SWI48 (const_int -1) - (match_operand:SWI48 2 "nonimmediate_operand" "rm")))) + (zero_extract:SWI48 + (match_operand:SWI48 1 "nonimmediate_operand" "rm") + (umin:SWI48 + (and:SWI48 (match_operand:SWI48 2 "register_operand" "r") + (const_int 255)) + (match_operand:SWI48 3 "const_int_operand" "n")) + (const_int 0))) (clobber (reg:CC FLAGS_REG))] - "TARGET_BMI2" + "TARGET_BMI2 && INTVAL (operands[3]) == GET_MODE_BITSIZE (mode)" "bzhi\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "bitmanip") (set_attr "prefix" "vex") (set_attr "mode" "")]) +(define_mode_attr k [(SI "k") (DI "q")]) +(define_insn "*bmi2_bzhi_3_1" + [(set (match_operand:SWI48 0 "register_operand" "=r") + (zero_extract:SWI48 + (match_operand:SWI48 1 "nonimmediate_operand" "rm") + (umin:SWI48 + (zero_extend:SWI48 (match_operand:QI 2 "register_operand" "r")) + (match_operand:SWI48 3 "const_int_operand" "n")) + (const_int 0))) + (clobber (reg:CC FLAGS_REG))] + "TARGET_BMI2 && INTVAL (operands[3]) == GET_MODE_BITSIZE (mode)" + "bzhi\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "type" "bitmanip") + (set_attr "prefix" "vex") + (set_attr "mode" "")]) + (define_insn "bmi2_pdep_3" [(set (match_operand:SWI48 0 "register_operand" "=r") (unspec:SWI48 [(match_operand:SWI48 1 "register_operand" "r") @@ -13515,7 +13552,8 @@ (set (reg:CCFP FPSR_REG) (unspec:CCFP [(match_dup 2) (match_dup 3)] UNSPEC_C2_FLAG))] - "TARGET_USE_FANCY_MATH_387" + "TARGET_USE_FANCY_MATH_387 + && flag_finite_math_only" "fprem" [(set_attr "type" "fpspc") (set_attr "mode" "XF")]) @@ -13524,7 +13562,8 @@ [(use (match_operand:XF 0 "register_operand")) (use (match_operand:XF 1 "general_operand")) (use (match_operand:XF 2 "general_operand"))] - "TARGET_USE_FANCY_MATH_387" + "TARGET_USE_FANCY_MATH_387 + && flag_finite_math_only" { rtx label = gen_label_rtx (); @@ -13547,7 +13586,8 @@ [(use (match_operand:MODEF 0 "register_operand")) (use (match_operand:MODEF 1 "general_operand")) (use (match_operand:MODEF 2 "general_operand"))] - "TARGET_USE_FANCY_MATH_387" + "TARGET_USE_FANCY_MATH_387 + && flag_finite_math_only" { rtx (*gen_truncxf) (rtx, rtx); @@ -13586,7 +13626,8 @@ (set (reg:CCFP FPSR_REG) (unspec:CCFP [(match_dup 2) (match_dup 3)] UNSPEC_C2_FLAG))] - "TARGET_USE_FANCY_MATH_387" + "TARGET_USE_FANCY_MATH_387 + && flag_finite_math_only" "fprem1" [(set_attr "type" "fpspc") (set_attr "mode" "XF")]) @@ -13595,7 +13636,8 @@ [(use (match_operand:XF 0 "register_operand")) (use (match_operand:XF 1 "general_operand")) (use (match_operand:XF 2 "general_operand"))] - "TARGET_USE_FANCY_MATH_387" + "TARGET_USE_FANCY_MATH_387 + && flag_finite_math_only" { rtx label = gen_label_rtx (); @@ -13618,7 +13660,8 @@ [(use (match_operand:MODEF 0 "register_operand")) (use (match_operand:MODEF 1 "general_operand")) (use (match_operand:MODEF 2 "general_operand"))] - "TARGET_USE_FANCY_MATH_387" + "TARGET_USE_FANCY_MATH_387 + && flag_finite_math_only" { rtx (*gen_truncxf) (rtx, rtx); @@ -16643,7 +16686,37 @@ emit_insn (gen_set_got (pic_offset_table_rtx)); DONE; }) - + +(define_insn_and_split "nonlocal_goto_receiver" + [(unspec_volatile [(const_int 0)] UNSPECV_NLGR)] + "TARGET_MACHO && !TARGET_64BIT && flag_pic" + "#" + "&& reload_completed" + [(const_int 0)] +{ + if (crtl->uses_pic_offset_table) + { + rtx xops[3]; + rtx label_rtx = gen_label_rtx (); + rtx tmp; + + /* Get a new pic base. */ + emit_insn (gen_set_got_labelled (pic_offset_table_rtx, label_rtx)); + /* Correct this with the offset from the new to the old. */ + xops[0] = xops[1] = pic_offset_table_rtx; + label_rtx = gen_rtx_LABEL_REF (SImode, label_rtx); + tmp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, label_rtx), + UNSPEC_MACHOPIC_OFFSET); + xops[2] = gen_rtx_CONST (Pmode, tmp); + ix86_expand_binary_operator (MINUS, SImode, xops); + } + else + /* No pic reg restore needed. */ + emit_note (NOTE_INSN_DELETED); + + DONE; +}) + ;; Avoid redundant prefixes by splitting HImode arithmetic to SImode. (define_split @@ -17040,6 +17113,7 @@ "(TARGET_READ_MODIFY_WRITE || optimize_insn_for_size_p ()) && peep2_reg_dead_p (4, operands[0]) && !reg_overlap_mentioned_p (operands[0], operands[1]) + && !reg_overlap_mentioned_p (operands[0], operands[2]) && (mode != QImode || immediate_operand (operands[2], QImode) || q_regs_operand (operands[2], QImode)) @@ -17104,6 +17178,7 @@ || immediate_operand (operands[2], SImode) || q_regs_operand (operands[2], SImode)) && !reg_overlap_mentioned_p (operands[0], operands[1]) + && !reg_overlap_mentioned_p (operands[0], operands[2]) && ix86_match_ccmode (peep2_next_insn (3), (GET_CODE (operands[3]) == PLUS || GET_CODE (operands[3]) == MINUS) @@ -17532,28 +17607,31 @@ (define_insn "trap" [(trap_if (const_int 1) (const_int 6))] "" - { return ASM_SHORT "0x0b0f"; } +{ +#ifdef HAVE_AS_IX86_UD2 + return "ud2"; +#else + return ASM_SHORT "0x0b0f"; +#endif +} [(set_attr "length" "2")]) (define_expand "prefetch" [(prefetch (match_operand 0 "address_operand") (match_operand:SI 1 "const_int_operand") (match_operand:SI 2 "const_int_operand"))] - "TARGET_PREFETCH_SSE || TARGET_3DNOW" + "TARGET_PREFETCH_SSE || TARGET_PRFCHW" { - int rw = INTVAL (operands[1]); + bool write = INTVAL (operands[1]) != 0; int locality = INTVAL (operands[2]); - gcc_assert (rw == 0 || rw == 1); gcc_assert (IN_RANGE (locality, 0, 3)); - if (TARGET_PRFCHW && rw) - operands[2] = GEN_INT (3); /* Use 3dNOW prefetch in case we are asking for write prefetch not supported by SSE counterpart or the SSE prefetch is not available (K6 machines). Otherwise use SSE prefetch as it allows specifying of locality. */ - else if (TARGET_3DNOW && (!TARGET_PREFETCH_SSE || rw)) + if (TARGET_PRFCHW && (write || !TARGET_PREFETCH_SSE)) operands[2] = GEN_INT (3); else operands[1] = const0_rtx; @@ -17584,7 +17662,7 @@ [(prefetch (match_operand 0 "address_operand" "p") (match_operand:SI 1 "const_int_operand" "n") (const_int 3))] - "TARGET_3DNOW || TARGET_PRFCHW" + "TARGET_PRFCHW" { if (INTVAL (operands[1]) == 0) return "prefetch\t%a0"; diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md index f5657b964a098..61614e112467c 100644 --- a/gcc/config/i386/predicates.md +++ b/gcc/config/i386/predicates.md @@ -806,11 +806,16 @@ ;; a segment override. Defined as a special predicate to allow ;; mode-less const_int operands pass to address_operand. (define_special_predicate "lea_address_operand" - (match_operand 0 "address_operand") + (match_test "address_operand (op, VOIDmode)") { struct ix86_address parts; int ok; + if (!CONST_INT_P (op) + && mode != VOIDmode + && GET_MODE (op) != mode) + return false; + ok = ix86_decompose_address (op, &parts); gcc_assert (ok); return parts.seg == SEG_DEFAULT; @@ -823,7 +828,7 @@ ;; Return true if op if a valid base register, displacement or ;; sum of base register and displacement for VSIB addressing. (define_predicate "vsib_address_operand" - (match_operand 0 "address_operand") + (match_test "address_operand (op, VOIDmode)") { struct ix86_address parts; int ok; @@ -835,19 +840,28 @@ return false; /* VSIB addressing doesn't support (%rip). */ - if (parts.disp && GET_CODE (parts.disp) == CONST) + if (parts.disp) { - disp = XEXP (parts.disp, 0); - if (GET_CODE (disp) == PLUS) - disp = XEXP (disp, 0); - if (GET_CODE (disp) == UNSPEC) - switch (XINT (disp, 1)) - { - case UNSPEC_GOTPCREL: - case UNSPEC_PCREL: - case UNSPEC_GOTNTPOFF: - return false; - } + disp = parts.disp; + if (GET_CODE (disp) == CONST) + { + disp = XEXP (disp, 0); + if (GET_CODE (disp) == PLUS) + disp = XEXP (disp, 0); + if (GET_CODE (disp) == UNSPEC) + switch (XINT (disp, 1)) + { + case UNSPEC_GOTPCREL: + case UNSPEC_PCREL: + case UNSPEC_GOTNTPOFF: + return false; + } + } + if (TARGET_64BIT + && flag_pic + && (GET_CODE (disp) == SYMBOL_REF + || GET_CODE (disp) == LABEL_REF)) + return false; } return true; diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index e2bb68ba18f9c..4877b73d0ca14 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -605,6 +605,7 @@ } [(set_attr "type" "ssemov") (set_attr "movu" "1") + (set_attr "ssememalign" "8") (set_attr "prefix" "maybe_vex") (set (attr "mode") (cond [(match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL") @@ -634,6 +635,7 @@ } [(set_attr "type" "ssemov") (set_attr "movu" "1") + (set_attr "ssememalign" "8") (set_attr "prefix" "maybe_vex") (set (attr "mode") (cond [(ior (match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL") @@ -663,6 +665,7 @@ } [(set_attr "type" "ssemov") (set_attr "movu" "1") + (set_attr "ssememalign" "8") (set (attr "prefix_data16") (if_then_else (match_test "TARGET_AVX") @@ -696,6 +699,7 @@ } [(set_attr "type" "ssemov") (set_attr "movu" "1") + (set_attr "ssememalign" "8") (set (attr "prefix_data16") (if_then_else (match_test "TARGET_AVX") @@ -721,6 +725,7 @@ "%vlddqu\t{%1, %0|%0, %1}" [(set_attr "type" "ssemov") (set_attr "movu" "1") + (set_attr "ssememalign" "8") (set (attr "prefix_data16") (if_then_else (match_test "TARGET_AVX") @@ -1001,6 +1006,7 @@ vrcpss\t{%1, %2, %0|%0, %2, %1}" [(set_attr "isa" "noavx,avx") (set_attr "type" "sse") + (set_attr "ssememalign" "32") (set_attr "atom_sse_attr" "rcp") (set_attr "btver2_sse_attr" "rcp") (set_attr "prefix" "orig,vex") @@ -1089,6 +1095,7 @@ vrsqrtss\t{%1, %2, %0|%0, %2, %1}" [(set_attr "isa" "noavx,avx") (set_attr "type" "sse") + (set_attr "ssememalign" "32") (set_attr "prefix" "orig,vex") (set_attr "mode" "SF")]) @@ -2844,6 +2851,7 @@ "%vcvtdq2pd\t{%1, %0|%0, %q1}" [(set_attr "type" "ssecvt") (set_attr "prefix" "maybe_vex") + (set_attr "ssememalign" "64") (set_attr "mode" "V2DF")]) (define_insn "avx_cvtpd2dq256" @@ -3109,7 +3117,7 @@ (define_expand "vec_unpacks_hi_v8sf" [(set (match_dup 2) (vec_select:V4SF - (match_operand:V8SF 1 "nonimmediate_operand") + (match_operand:V8SF 1 "register_operand") (parallel [(const_int 4) (const_int 5) (const_int 6) (const_int 7)]))) (set (match_operand:V4DF 0 "register_operand") @@ -3572,6 +3580,7 @@ %vmovhps\t{%2, %0|%0, %2}" [(set_attr "isa" "noavx,avx,noavx,avx,*") (set_attr "type" "ssemov") + (set_attr "ssememalign" "64") (set_attr "prefix" "orig,vex,orig,vex,maybe_vex") (set_attr "mode" "V4SF,V4SF,V2SF,V2SF,V2SF")]) @@ -3603,7 +3612,7 @@ (vec_select:V4SF (vec_concat:V8SF (match_operand:V4SF 1 "nonimmediate_operand" " 0,x,0,x,0") - (match_operand:V4SF 2 "nonimmediate_operand" " x,x,m,x,x")) + (match_operand:V4SF 2 "nonimmediate_operand" " x,x,m,m,x")) (parallel [(const_int 0) (const_int 1) (const_int 4) @@ -3617,6 +3626,7 @@ %vmovlps\t{%2, %H0|%H0, %2}" [(set_attr "isa" "noavx,avx,noavx,avx,*") (set_attr "type" "ssemov") + (set_attr "ssememalign" "64") (set_attr "prefix" "orig,vex,orig,vex,maybe_vex") (set_attr "mode" "V4SF,V4SF,V2SF,V2SF,V2SF")]) @@ -3941,6 +3951,7 @@ %vmovhlps\t{%1, %d0|%d0, %1} %vmovlps\t{%H1, %d0|%d0, %H1}" [(set_attr "type" "ssemov") + (set_attr "ssememalign" "64") (set_attr "prefix" "maybe_vex") (set_attr "mode" "V2SF,V4SF,V2SF")]) @@ -3980,6 +3991,7 @@ %vmovlps\t{%2, %H0|%H0, %2}" [(set_attr "isa" "noavx,avx,noavx,avx,*") (set_attr "type" "ssemov") + (set_attr "ssememalign" "64") (set_attr "prefix" "orig,vex,orig,vex,maybe_vex") (set_attr "mode" "V2SF,V2SF,V4SF,V4SF,V2SF")]) @@ -4033,6 +4045,7 @@ %vmovlps\t{%2, %0|%0, %2}" [(set_attr "isa" "noavx,avx,noavx,avx,*") (set_attr "type" "sseshuf,sseshuf,ssemov,ssemov,ssemov") + (set_attr "ssememalign" "64") (set_attr "length_immediate" "1,1,*,*,*") (set_attr "prefix" "orig,vex,orig,vex,maybe_vex") (set_attr "mode" "V4SF,V4SF,V2SF,V2SF,V2SF")]) @@ -4642,7 +4655,8 @@ vmovlpd\t{%H1, %2, %0|%0, %2, %H1} %vmovhpd\t{%1, %0|%0, %1}" [(set_attr "isa" "noavx,avx,sse3,noavx,avx,*") - (set_attr "type" "sselog,sselog,sselog,ssemov,ssemov,ssemov") + (set_attr "type" "sselog,sselog,sselog,ssemov,ssemov,ssemov") + (set_attr "ssememalign" "64") (set_attr "prefix_data16" "*,*,*,1,*,1") (set_attr "prefix" "orig,vex,maybe_vex,orig,vex,maybe_vex") (set_attr "mode" "V2DF,V2DF,DF,V1DF,V1DF,V1DF")]) @@ -4744,6 +4758,7 @@ %vmovlpd\t{%2, %H0|%H0, %2}" [(set_attr "isa" "noavx,avx,sse3,noavx,avx,*") (set_attr "type" "sselog,sselog,sselog,ssemov,ssemov,ssemov") + (set_attr "ssememalign" "64") (set_attr "prefix_data16" "*,*,*,1,*,1") (set_attr "prefix" "orig,vex,maybe_vex,orig,vex,maybe_vex") (set_attr "mode" "V2DF,V2DF,DF,V1DF,V1DF,V1DF")]) @@ -4982,6 +4997,7 @@ movhlps\t{%1, %0|%0, %1} movlps\t{%H1, %0|%0, %H1}" [(set_attr "type" "ssemov") + (set_attr "ssememalign" "64") (set_attr "mode" "V2SF,V4SF,V2SF")]) ;; Avoid combining registers from different units in a single alternative, @@ -5077,6 +5093,7 @@ #" [(set_attr "isa" "noavx,avx,noavx,avx,*,*,*") (set_attr "type" "ssemov,ssemov,sselog,sselog,ssemov,fmov,imov") + (set_attr "ssememalign" "64") (set_attr "prefix_data16" "1,*,*,*,*,*,*") (set_attr "prefix" "orig,vex,orig,vex,*,*,*") (set_attr "mode" "V1DF,V1DF,V2DF,V2DF,DF,DF,DF")]) @@ -5145,6 +5162,7 @@ (const_string "imov") ] (const_string "ssemov"))) + (set_attr "ssememalign" "64") (set_attr "prefix_data16" "*,1,*,*,*,*,1,*,*,*,*") (set_attr "length_immediate" "*,*,*,*,*,1,*,*,*,*,*") (set_attr "prefix" "maybe_vex,orig,vex,orig,vex,orig,orig,vex,*,*,*") @@ -5189,6 +5207,7 @@ (const_string "1") (const_string "*"))) (set_attr "length_immediate" "*,*,*,*,*,1,*,*,*") + (set_attr "ssememalign" "64") (set_attr "prefix" "orig,vex,orig,vex,maybe_vex,orig,orig,vex,maybe_vex") (set_attr "mode" "DF,DF,V1DF,V1DF,V1DF,V2DF,V1DF,V1DF,V1DF")]) @@ -5638,7 +5657,7 @@ if (TARGET_SSE4_1) { if (CONSTANT_P (operands[2])) - operands[2] = force_const_mem (mode, operands[2]); + operands[2] = validize_mem (force_const_mem (mode, operands[2])); ix86_fixup_binary_operands_no_copy (MULT, mode, operands); } else @@ -7350,7 +7369,7 @@ movss\t{%2, %0|%0, %2} movss\t{%2, %0|%0, %2} vmovss\t{%2, %1, %0|%0, %1, %2}" - [(set_attr "isa" "sse2,*,noavx,noavx,avx") + [(set_attr "isa" "sse2,sse2,noavx,noavx,avx") (set_attr "type" "ssemov") (set_attr "prefix" "maybe_vex,maybe_vex,orig,orig,vex") (set_attr "mode" "TI,TI,V4SF,SF,SF")]) @@ -7758,9 +7777,17 @@ (mem:V16QI (match_dup 0))] UNSPEC_MASKMOV))] "TARGET_SSE2" - "%vmaskmovdqu\t{%2, %1|%1, %2}" +{ + /* We can't use %^ here due to ASM_OUTPUT_OPCODE processing + that requires %v to be at the beginning of the opcode name. */ + if (Pmode != word_mode) + fputs ("\taddr32", asm_out_file); + return "%vmaskmovdqu\t{%2, %1|%1, %2}"; +} [(set_attr "type" "ssemov") (set_attr "prefix_data16" "1") + (set (attr "length_address") + (symbol_ref ("Pmode != word_mode"))) ;; The implicit %rdi operand confuses default length_vex computation. (set (attr "length_vex") (symbol_ref ("3 + REX_SSE_REGNO_P (REGNO (operands[2]))"))) @@ -7796,10 +7823,12 @@ (set_attr "atom_sse_attr" "fence") (set_attr "memory" "unknown")]) - +;; As per AMD and Intel ISA manuals, the first operand is extensions +;; and it goes to %ecx. The second operand received is hints and it goes +;; to %eax. (define_insn "sse3_mwait" - [(unspec_volatile [(match_operand:SI 0 "register_operand" "a") - (match_operand:SI 1 "register_operand" "c")] + [(unspec_volatile [(match_operand:SI 0 "register_operand" "c") + (match_operand:SI 1 "register_operand" "a")] UNSPECV_MWAIT)] "TARGET_SSE3" ;; 64bit version is "mwait %rax,%rcx". But only lower 32bits are used. @@ -7808,26 +7837,18 @@ "mwait" [(set_attr "length" "3")]) -(define_insn "sse3_monitor" - [(unspec_volatile [(match_operand:SI 0 "register_operand" "a") - (match_operand:SI 1 "register_operand" "c") - (match_operand:SI 2 "register_operand" "d")] - UNSPECV_MONITOR)] - "TARGET_SSE3 && !TARGET_64BIT" - "monitor\t%0, %1, %2" - [(set_attr "length" "3")]) - -(define_insn "sse3_monitor64_" +(define_insn "sse3_monitor_" [(unspec_volatile [(match_operand:P 0 "register_operand" "a") (match_operand:SI 1 "register_operand" "c") (match_operand:SI 2 "register_operand" "d")] UNSPECV_MONITOR)] - "TARGET_SSE3 && TARGET_64BIT" + "TARGET_SSE3" ;; 64bit version is "monitor %rax,%rcx,%rdx". But only lower 32bits in ;; RCX and RDX are used. Since 32bit register operands are implicitly ;; zero extended to 64bit, we only need to set up 32bit registers. - "monitor" - [(set_attr "length" "3")]) + "%^monitor" + [(set (attr "length") + (symbol_ref ("(Pmode != word_mode) + 3")))]) ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; @@ -8736,6 +8757,7 @@ "TARGET_SSE4_1" "%vpmovbw\t{%1, %0|%0, %q1}" [(set_attr "type" "ssemov") + (set_attr "ssememalign" "64") (set_attr "prefix_extra" "1") (set_attr "prefix" "maybe_vex") (set_attr "mode" "TI")]) @@ -8766,6 +8788,7 @@ "TARGET_SSE4_1" "%vpmovbd\t{%1, %0|%0, %k1}" [(set_attr "type" "ssemov") + (set_attr "ssememalign" "32") (set_attr "prefix_extra" "1") (set_attr "prefix" "maybe_vex") (set_attr "mode" "TI")]) @@ -8791,6 +8814,7 @@ "TARGET_SSE4_1" "%vpmovwd\t{%1, %0|%0, %q1}" [(set_attr "type" "ssemov") + (set_attr "ssememalign" "64") (set_attr "prefix_extra" "1") (set_attr "prefix" "maybe_vex") (set_attr "mode" "TI")]) @@ -8818,6 +8842,7 @@ "TARGET_SSE4_1" "%vpmovbq\t{%1, %0|%0, %w1}" [(set_attr "type" "ssemov") + (set_attr "ssememalign" "16") (set_attr "prefix_extra" "1") (set_attr "prefix" "maybe_vex") (set_attr "mode" "TI")]) @@ -8845,6 +8870,7 @@ "TARGET_SSE4_1" "%vpmovwq\t{%1, %0|%0, %k1}" [(set_attr "type" "ssemov") + (set_attr "ssememalign" "32") (set_attr "prefix_extra" "1") (set_attr "prefix" "maybe_vex") (set_attr "mode" "TI")]) @@ -8868,6 +8894,7 @@ "TARGET_SSE4_1" "%vpmovdq\t{%1, %0|%0, %q1}" [(set_attr "type" "ssemov") + (set_attr "ssememalign" "64") (set_attr "prefix_extra" "1") (set_attr "prefix" "maybe_vex") (set_attr "mode" "TI")]) @@ -9151,6 +9178,7 @@ [(set_attr "type" "sselog") (set_attr "prefix_data16" "1") (set_attr "prefix_extra" "1") + (set_attr "ssememalign" "8") (set_attr "length_immediate" "1") (set_attr "memory" "none,load") (set_attr "mode" "TI")]) @@ -9213,6 +9241,7 @@ [(set_attr "type" "sselog") (set_attr "prefix_data16" "1") (set_attr "prefix_extra" "1") + (set_attr "ssememalign" "8") (set_attr "length_immediate" "1") (set_attr "memory" "load") (set_attr "mode" "TI")]) @@ -9240,6 +9269,7 @@ (set_attr "prefix_data16" "1") (set_attr "prefix_extra" "1") (set_attr "prefix" "maybe_vex") + (set_attr "ssememalign" "8") (set_attr "length_immediate" "1") (set_attr "btver2_decode" "vector") (set_attr "memory" "none,load") @@ -9267,6 +9297,7 @@ [(set_attr "type" "sselog") (set_attr "prefix_data16" "1") (set_attr "prefix_extra" "1") + (set_attr "ssememalign" "8") (set_attr "length_immediate" "1") (set_attr "prefix" "maybe_vex") (set_attr "btver2_decode" "vector") @@ -9293,6 +9324,7 @@ [(set_attr "type" "sselog") (set_attr "prefix_data16" "1") (set_attr "prefix_extra" "1") + (set_attr "ssememalign" "8") (set_attr "length_immediate" "1") (set_attr "memory" "none,load,none,load") (set_attr "btver2_decode" "vector,vector,vector,vector") @@ -9346,6 +9378,7 @@ [(set_attr "type" "sselog") (set_attr "prefix_data16" "1") (set_attr "prefix_extra" "1") + (set_attr "ssememalign" "8") (set_attr "length_immediate" "1") (set_attr "memory" "none,load") (set_attr "mode" "TI")]) @@ -9399,6 +9432,7 @@ [(set_attr "type" "sselog") (set_attr "prefix_data16" "1") (set_attr "prefix_extra" "1") + (set_attr "ssememalign" "8") (set_attr "length_immediate" "1") (set_attr "memory" "load") (set_attr "mode" "TI")]) @@ -9421,6 +9455,7 @@ [(set_attr "type" "sselog") (set_attr "prefix_data16" "1") (set_attr "prefix_extra" "1") + (set_attr "ssememalign" "8") (set_attr "length_immediate" "1") (set_attr "prefix" "maybe_vex") (set_attr "memory" "none,load") @@ -9445,6 +9480,7 @@ [(set_attr "type" "sselog") (set_attr "prefix_data16" "1") (set_attr "prefix_extra" "1") + (set_attr "ssememalign" "8") (set_attr "length_immediate" "1") (set_attr "prefix" "maybe_vex") (set_attr "memory" "none,load") @@ -9469,6 +9505,7 @@ [(set_attr "type" "sselog") (set_attr "prefix_data16" "1") (set_attr "prefix_extra" "1") + (set_attr "ssememalign" "8") (set_attr "length_immediate" "1") (set_attr "memory" "none,load,none,load") (set_attr "prefix" "maybe_vex") @@ -9942,7 +9979,8 @@ (match_operand:SI 2 "const_0_to__operand" "n")))] "TARGET_XOP" { - operands[3] = GEN_INT (( * 8) - INTVAL (operands[2])); + operands[3] + = GEN_INT (GET_MODE_BITSIZE (mode) - INTVAL (operands[2])); return \"vprot\t{%3, %1, %0|%0, %1, %3}\"; } [(set_attr "type" "sseishft") @@ -10212,21 +10250,18 @@ [(set_attr "type" "ssecvt1") (set_attr "mode" "")]) -;; scalar insns (define_expand "xop_vmfrcz2" [(set (match_operand:VF_128 0 "register_operand") (vec_merge:VF_128 (unspec:VF_128 [(match_operand:VF_128 1 "nonimmediate_operand")] UNSPEC_FRCZ) - (match_dup 3) + (match_dup 2) (const_int 1)))] "TARGET_XOP" -{ - operands[3] = CONST0_RTX (mode); -}) + "operands[2] = CONST0_RTX (mode);") -(define_insn "*xop_vmfrcz_" +(define_insn "*xop_vmfrcz2" [(set (match_operand:VF_128 0 "register_operand" "=x") (vec_merge:VF_128 (unspec:VF_128 diff --git a/gcc/config/i386/t-rtems b/gcc/config/i386/t-rtems index 6161ec100909f..fef4c22e9c164 100644 --- a/gcc/config/i386/t-rtems +++ b/gcc/config/i386/t-rtems @@ -17,11 +17,10 @@ # . # -MULTILIB_OPTIONS = mtune=i486/mtune=pentium/mtune=pentiumpro \ -msoft-float +MULTILIB_OPTIONS = mtune=i486/mtune=pentium/mtune=pentiumpro msoft-float MULTILIB_DIRNAMES= m486 mpentium mpentiumpro soft-float -MULTILIB_MATCHES = msoft-float=mno-m80387 -MULTILIB_MATCHES += mtune?pentium=mtune?k6 mtune?pentiumpro=mtune?mathlon +MULTILIB_MATCHES = msoft-float=mno-80387 +MULTILIB_MATCHES += mtune?pentium=mtune?k6 mtune?pentiumpro=mtune?athlon MULTILIB_EXCEPTIONS = \ mtune=pentium/*msoft-float* \ mtune=pentiumpro/*msoft-float* diff --git a/gcc/config/i386/winnt.c b/gcc/config/i386/winnt.c index 118b1ecb0074b..1e49a461a107a 100644 --- a/gcc/config/i386/winnt.c +++ b/gcc/config/i386/winnt.c @@ -476,7 +476,7 @@ i386_pe_section_type_flags (tree decl, const char *name, int reloc) flags |= SECTION_PE_SHARED; } - if (decl && DECL_ONE_ONLY (decl)) + if (decl && DECL_P (decl) && DECL_ONE_ONLY (decl)) flags |= SECTION_LINKONCE; /* See if we already have an entry for this section. */ @@ -547,8 +547,9 @@ i386_pe_asm_named_section (const char *name, unsigned int flags, sets 'discard' characteristic, rather than telling linker to warn of size or content mismatch, so do the same. */ bool discard = (flags & SECTION_CODE) - || lookup_attribute ("selectany", - DECL_ATTRIBUTES (decl)); + || (TREE_CODE (decl) != IDENTIFIER_NODE + && lookup_attribute ("selectany", + DECL_ATTRIBUTES (decl))); fprintf (asm_out_file, "\t.linkonce %s\n", (discard ? "discard" : "same_size")); } diff --git a/gcc/config/i386/x86-64.h b/gcc/config/i386/x86-64.h index c103c5865a31d..66f96d98e2e8f 100644 --- a/gcc/config/i386/x86-64.h +++ b/gcc/config/i386/x86-64.h @@ -103,3 +103,6 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see #undef TARGET_ASM_UNIQUE_SECTION #define TARGET_ASM_UNIQUE_SECTION x86_64_elf_unique_section + +#undef TARGET_SECTION_TYPE_FLAGS +#define TARGET_SECTION_TYPE_FLAGS x86_64_elf_section_type_flags diff --git a/gcc/config/i386/xopintrin.h b/gcc/config/i386/xopintrin.h index 66b0f0de5c987..d2a99a1674a80 100644 --- a/gcc/config/i386/xopintrin.h +++ b/gcc/config/i386/xopintrin.h @@ -745,13 +745,17 @@ _mm_frcz_pd (__m128d __A) extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__)) _mm_frcz_ss (__m128 __A, __m128 __B) { - return (__m128) __builtin_ia32_vfrczss ((__v4sf)__A, (__v4sf)__B); + return (__m128) __builtin_ia32_movss ((__v4sf)__A, + (__v4sf) + __builtin_ia32_vfrczss ((__v4sf)__B)); } extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__)) _mm_frcz_sd (__m128d __A, __m128d __B) { - return (__m128d) __builtin_ia32_vfrczsd ((__v2df)__A, (__v2df)__B); + return (__m128d) __builtin_ia32_movsd ((__v2df)__A, + (__v2df) + __builtin_ia32_vfrczsd ((__v2df)__B)); } extern __inline __m256 __attribute__((__gnu_inline__, __always_inline__, __artificial__)) diff --git a/gcc/config/m68k/m68k.c b/gcc/config/m68k/m68k.c index 5e3236fa8deb6..a662bed81b5aa 100644 --- a/gcc/config/m68k/m68k.c +++ b/gcc/config/m68k/m68k.c @@ -3325,12 +3325,12 @@ handle_move_double (rtx operands[2], latehalf[1] = adjust_address (operands[1], SImode, 0); } - /* If insn is effectively movd N(sp),-(sp) then we will do the - high word first. We should use the adjusted operand 1 (which is N+4(sp)) - for the low word as well, to compensate for the first decrement of sp. */ + /* If insn is effectively movd N(REG),-(REG) then we will do the high + word first. We should use the adjusted operand 1 (which is N+4(REG)) + for the low word as well, to compensate for the first decrement of + REG. */ if (optype0 == PUSHOP - && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM - && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1])) + && reg_overlap_mentioned_p (XEXP (XEXP (operands[0], 0), 0), operands[1])) operands[1] = middlehalf[1] = latehalf[1]; /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)), diff --git a/gcc/config/microblaze/linux.h b/gcc/config/microblaze/linux.h index a7b7a1adcfa56..ac78e9afad369 100644 --- a/gcc/config/microblaze/linux.h +++ b/gcc/config/microblaze/linux.h @@ -22,6 +22,9 @@ #undef TARGET_SUPPORTS_PIC #define TARGET_SUPPORTS_PIC 1 +#undef CPP_SPEC +#define CPP_SPEC "%{posix:-D_POSIX_SOURCE} %{pthread:-D_REENTRANT}" + #undef TLS_NEEDS_GOT #define TLS_NEEDS_GOT 1 diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c index c121c2baec32e..89793b05fe593 100644 --- a/gcc/config/microblaze/microblaze.c +++ b/gcc/config/microblaze/microblaze.c @@ -1609,21 +1609,28 @@ static int microblaze_version_to_int (const char *version) { const char *p, *v; - const char *tmpl = "vX.YY.Z"; + const char *tmpl = "vXX.YY.Z"; int iver = 0; p = version; v = tmpl; - while (*v) + while (*p) { if (*v == 'X') { /* Looking for major */ - if (!(*p >= '0' && *p <= '9')) - return -1; - iver += (int) (*p - '0'); - iver *= 10; - } + if (*p == '.') + { + *v++; + } + else + { + if (!(*p >= '0' && *p <= '9')) + return -1; + iver += (int) (*p - '0'); + iver *= 10; + } + } else if (*v == 'Y') { /* Looking for minor */ if (!(*p >= '0' && *p <= '9')) @@ -3064,6 +3071,73 @@ expand_pic_symbol_ref (enum machine_mode mode ATTRIBUTE_UNUSED, rtx op) return result; } +static void +microblaze_asm_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, + HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset, + tree function) +{ + rtx this_rtx, insn, funexp; + + reload_completed = 1; + epilogue_completed = 1; + + /* Mark the end of the (empty) prologue. */ + emit_note (NOTE_INSN_PROLOGUE_END); + + /* Find the "this" pointer. If the function returns a structure, + the structure return pointer is in MB_ABI_FIRST_ARG_REGNUM. */ + if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)) + this_rtx = gen_rtx_REG (Pmode, (MB_ABI_FIRST_ARG_REGNUM + 1)); + else + this_rtx = gen_rtx_REG (Pmode, MB_ABI_FIRST_ARG_REGNUM); + + /* Apply the constant offset, if required. */ + if (delta) + emit_insn (gen_addsi3 (this_rtx, this_rtx, GEN_INT (delta))); + + /* Apply the offset from the vtable, if required. */ + if (vcall_offset) + { + rtx vcall_offset_rtx = GEN_INT (vcall_offset); + rtx temp1 = gen_rtx_REG (Pmode, MB_ABI_TEMP1_REGNUM); + + emit_move_insn (temp1, gen_rtx_MEM (Pmode, this_rtx)); + + rtx loc = gen_rtx_PLUS (Pmode, temp1, vcall_offset_rtx); + emit_move_insn (temp1, gen_rtx_MEM (Pmode, loc)); + + emit_insn (gen_addsi3 (this_rtx, this_rtx, temp1)); + } + + /* Generate a tail call to the target function. */ + if (!TREE_USED (function)) + { + assemble_external (function); + TREE_USED (function) = 1; + } + + funexp = XEXP (DECL_RTL (function), 0); + rtx temp2 = gen_rtx_REG (Pmode, MB_ABI_TEMP2_REGNUM); + + if (flag_pic) + emit_move_insn (temp2, expand_pic_symbol_ref (Pmode, funexp)); + else + emit_move_insn (temp2, funexp); + + emit_insn (gen_indirect_jump (temp2)); + + /* Run just enough of rest_of_compilation. This sequence was + "borrowed" from rs6000.c. */ + insn = get_insns (); + shorten_branches (insn); + final_start_function (insn, file, 1); + final (insn, file, 1); + final_end_function (); + + reload_completed = 0; + epilogue_completed = 0; +} + bool microblaze_expand_move (enum machine_mode mode, rtx operands[]) { @@ -3234,65 +3308,45 @@ microblaze_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) emit_move_insn (mem, fnaddr); } -/* Emit instruction to perform compare. - cmp is (compare_op op0 op1). */ -static rtx -microblaze_emit_compare (enum machine_mode mode, rtx cmp, enum rtx_code *cmp_code) +/* Generate conditional branch -- first, generate test condition, + second, generate correct branch instruction. */ + +void +microblaze_expand_conditional_branch (enum machine_mode mode, rtx operands[]) { - rtx cmp_op0 = XEXP (cmp, 0); - rtx cmp_op1 = XEXP (cmp, 1); + enum rtx_code code = GET_CODE (operands[0]); + rtx cmp_op0 = operands[1]; + rtx cmp_op1 = operands[2]; + rtx label1 = operands[3]; rtx comp_reg = gen_reg_rtx (SImode); - enum rtx_code code = *cmp_code; - + rtx condition; + gcc_assert ((GET_CODE (cmp_op0) == REG) || (GET_CODE (cmp_op0) == SUBREG)); /* If comparing against zero, just test source reg. */ - if (cmp_op1 == const0_rtx) - return cmp_op0; + if (cmp_op1 == const0_rtx) + { + comp_reg = cmp_op0; + condition = gen_rtx_fmt_ee (signed_condition (code), SImode, comp_reg, const0_rtx); + emit_jump_insn (gen_condjump (condition, label1)); + } - if (code == EQ || code == NE) + else if (code == EQ || code == NE) { /* Use xor for equal/not-equal comparison. */ emit_insn (gen_xorsi3 (comp_reg, cmp_op0, cmp_op1)); + condition = gen_rtx_fmt_ee (signed_condition (code), SImode, comp_reg, const0_rtx); + emit_jump_insn (gen_condjump (condition, label1)); } - else if (code == GT || code == GTU || code == LE || code == LEU) - { - /* MicroBlaze compare is not symmetrical. */ - /* Swap argument order. */ - cmp_op1 = force_reg (mode, cmp_op1); - if (code == GT || code == LE) - emit_insn (gen_signed_compare (comp_reg, cmp_op0, cmp_op1)); - else - emit_insn (gen_unsigned_compare (comp_reg, cmp_op0, cmp_op1)); - /* Translate test condition. */ - *cmp_code = swap_condition (code); - } - else /* if (code == GE || code == GEU || code == LT || code == LTU) */ + else { + /* Generate compare and branch in single instruction. */ cmp_op1 = force_reg (mode, cmp_op1); - if (code == GE || code == LT) - emit_insn (gen_signed_compare (comp_reg, cmp_op1, cmp_op0)); - else - emit_insn (gen_unsigned_compare (comp_reg, cmp_op1, cmp_op0)); + condition = gen_rtx_fmt_ee (code, mode, cmp_op0, cmp_op1); + emit_jump_insn (gen_branch_compare(condition, cmp_op0, cmp_op1, label1)); } - - return comp_reg; } -/* Generate conditional branch -- first, generate test condition, - second, generate correct branch instruction. */ - -void -microblaze_expand_conditional_branch (enum machine_mode mode, rtx operands[]) -{ - enum rtx_code code = GET_CODE (operands[0]); - rtx comp; - rtx condition; - - comp = microblaze_emit_compare (mode, operands[0], &code); - condition = gen_rtx_fmt_ee (signed_condition (code), SImode, comp, const0_rtx); - emit_jump_insn (gen_condjump (condition, operands[3])); -} void microblaze_expand_conditional_branch_sf (rtx operands[]) @@ -3501,6 +3555,12 @@ microblaze_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x #undef TARGET_SECONDARY_RELOAD #define TARGET_SECONDARY_RELOAD microblaze_secondary_reload +#undef TARGET_ASM_OUTPUT_MI_THUNK +#define TARGET_ASM_OUTPUT_MI_THUNK microblaze_asm_output_mi_thunk + +#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK +#define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true + #undef TARGET_SCHED_ADJUST_COST #define TARGET_SCHED_ADJUST_COST microblaze_adjust_cost diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h index bc4d9a128d1de..34c87c980ac0b 100644 --- a/gcc/config/microblaze/microblaze.h +++ b/gcc/config/microblaze/microblaze.h @@ -213,6 +213,12 @@ extern enum pipeline_type microblaze_pipe; #define STRICT_ALIGNMENT 1 #define PCC_BITFIELD_TYPE_MATTERS 1 +#undef SIZE_TYPE +#define SIZE_TYPE "unsigned int" + +#undef PTRDIFF_TYPE +#define PTRDIFF_TYPE "int" + #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \ && (ALIGN) < BITS_PER_WORD \ @@ -407,9 +413,6 @@ extern enum reg_class microblaze_regno_to_class[]; || GET_MODE (X) == VOIDmode) \ ? (GR_REGS) : (CLASS)))) -#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ - (GET_MODE_CLASS (MODE) == MODE_INT) - /* Stack layout; function entry, exit and calling. */ #define STACK_GROWS_DOWNWARD diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md index 3618cad524b6b..7d613f443512b 100644 --- a/gcc/config/microblaze/microblaze.md +++ b/gcc/config/microblaze/microblaze.md @@ -74,7 +74,7 @@ ;; bshift Shift operations (define_attr "type" - "unknown,branch,jump,call,load,store,move,arith,darith,imul,idiv,icmp,multi,nop,no_delay_arith,no_delay_load,no_delay_store,no_delay_imul,no_delay_move,bshift,fadd,frsub,fmul,fdiv,fcmp,fsl,fsqrt,fcvt" + "unknown,branch,jump,call,load,store,move,arith,darith,imul,idiv,icmp,multi,nop,no_delay_arith,no_delay_load,no_delay_store,no_delay_imul,no_delay_move,bshift,fadd,frsub,fmul,fdiv,fcmp,fsl,fsqrt,fcvt,trap" (const_string "unknown")) ;; Main data type used by the insn @@ -365,7 +365,8 @@ [(set (match_operand:HI 0 "register_operand" "=r") (bswap:HI (match_operand:HI 1 "register_operand" "r")))] "TARGET_REORDER" - "swaph %0, %1" + "swapb %0, %1 + swaph %0, %0" ) ;;---------------------------------------------------------------- @@ -1472,7 +1473,7 @@ (set_attr "length" "124")] ) -(define_insn "*ashlri_reg" +(define_insn "*ashrsi_reg" [(set (match_operand:SI 0 "register_operand" "=&d") (ashiftrt:SI (match_operand:SI 1 "register_operand" "d") (match_operand:SI 2 "register_operand" "d")))] @@ -1561,7 +1562,7 @@ (set_attr "length" "124")] ) -(define_insn "*lshlri_reg" +(define_insn "*lshrsi_reg" [(set (match_operand:SI 0 "register_operand" "=&d") (lshiftrt:SI (match_operand:SI 1 "register_operand" "d") (match_operand:SI 2 "register_operand" "d")))] @@ -1622,34 +1623,12 @@ (set_attr "length" "4")] ) -(define_insn "signed_compare" - [(set (match_operand:SI 0 "register_operand" "=d") - (unspec - [(match_operand:SI 1 "register_operand" "d") - (match_operand:SI 2 "register_operand" "d")] UNSPEC_CMP))] - "" - "cmp\t%0,%1,%2" - [(set_attr "type" "arith") - (set_attr "mode" "SI") - (set_attr "length" "4")]) - -(define_insn "unsigned_compare" - [(set (match_operand:SI 0 "register_operand" "=d") - (unspec - [(match_operand:SI 1 "register_operand" "d") - (match_operand:SI 2 "register_operand" "d")] UNSPEC_CMPU))] - "" - "cmpu\t%0,%1,%2" - [(set_attr "type" "arith") - (set_attr "mode" "SI") - (set_attr "length" "4")]) - ;;---------------------------------------------------------------- ;; Setting a register from an floating point comparison. ;;---------------------------------------------------------------- (define_insn "cstoresf4" [(set (match_operand:SI 0 "register_operand" "=r") - (match_operator 1 "comparison_operator" + (match_operator:SI 1 "ordered_comparison_operator" [(match_operand:SF 2 "register_operand" "r") (match_operand:SF 3 "register_operand" "r")]))] "TARGET_HARD_FLOAT" @@ -1678,7 +1657,7 @@ (define_expand "cbranchsf4" [(set (pc) - (if_then_else (match_operator 0 "comparison_operator" + (if_then_else (match_operator 0 "ordered_comparison_operator" [(match_operand:SF 1 "register_operand") (match_operand:SF 2 "register_operand")]) (label_ref (match_operand 3 "")) @@ -1717,6 +1696,47 @@ (set_attr "length" "4")] ) +(define_insn "branch_compare" + [(set (pc) + (if_then_else (match_operator:SI 0 "cmp_op" + [(match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "register_operand" "d") + ]) + (label_ref (match_operand 3)) + (pc))) + (clobber(reg:SI R_TMP))] + "" + { + operands[4] = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM); + enum rtx_code code = GET_CODE (operands[0]); + + if (code == GT || code == LE) + { + output_asm_insn ("cmp\tr18,%z1,%z2", operands); + code = swap_condition (code); + } + else if (code == GTU || code == LEU) + { + output_asm_insn ("cmpu\tr18,%z1,%z2", operands); + code = swap_condition (code); + } + else if (code == GE || code == LT) + { + output_asm_insn ("cmp\tr18,%z2,%z1", operands); + } + else if (code == GEU || code == LTU) + { + output_asm_insn ("cmpu\tr18,%z2,%z1", operands); + } + + operands[0] = gen_rtx_fmt_ee (signed_condition (code), SImode, operands[4], const0_rtx); + return "b%C0i%?\tr18,%3"; + } + [(set_attr "type" "branch") + (set_attr "mode" "none") + (set_attr "length" "12")] +) + ;;---------------------------------------------------------------- ;; Unconditional branches ;;---------------------------------------------------------------- @@ -2201,6 +2221,14 @@ (set_attr "mode" "none") (set_attr "length" "4")]) +;; Trap instruction pattern for __builtin_trap. Same as the glibc ABORT_INSTRUCTION +(define_insn "trap" + [(trap_if (const_int 1) (const_int 0))] + "" + "brki\tr0,-1" + [(set_attr "type" "trap")] +) + ;; The insn to set GOT. The hardcoded number "8" accounts for $pc difference ;; between "mfs" and "addik" instructions. (define_insn "set_got" diff --git a/gcc/config/microblaze/predicates.md b/gcc/config/microblaze/predicates.md index 5fd1bd403720c..2c23291a9f7ca 100644 --- a/gcc/config/microblaze/predicates.md +++ b/gcc/config/microblaze/predicates.md @@ -119,3 +119,7 @@ ;; Test for valid PIC call operand (define_predicate "call_insn_plt_operand" (match_test "PLT_ADDR_P (op)")) + +;; Return if the code of this rtx pattern is a comparison. +(define_predicate "cmp_op" + (match_code "gt,ge,gtu,geu,lt,le,ltu,leu")) diff --git a/gcc/config/mips/driver-native.c b/gcc/config/mips/driver-native.c index 8b7ed5b553005..758efa9a4a690 100644 --- a/gcc/config/mips/driver-native.c +++ b/gcc/config/mips/driver-native.c @@ -58,11 +58,17 @@ host_detect_local_cpu (int argc, const char **argv) if (strncmp (buf, "cpu model", sizeof ("cpu model") - 1) == 0) { if (strstr (buf, "Godson2 V0.2") != NULL - || strstr (buf, "Loongson-2 V0.2") != NULL) + || strstr (buf, "Loongson-2 V0.2") != NULL + || strstr (buf, "Loongson-2E") != NULL) cpu = "loongson2e"; else if (strstr (buf, "Godson2 V0.3") != NULL - || strstr (buf, "Loongson-2 V0.3") != NULL) + || strstr (buf, "Loongson-2 V0.3") != NULL + || strstr (buf, "Loongson-2F") != NULL) cpu = "loongson2f"; + else if (strstr (buf, "Godson3 V0.5") != NULL + || strstr (buf, "Loongson-3 V0.5") != NULL + || strstr (buf, "Loongson-3A") != NULL) + cpu = "loongson3a"; else if (strstr (buf, "SiByte SB1") != NULL) cpu = "sb1"; else if (strstr (buf, "R5000") != NULL) diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index 252e828480e44..41c5d6b6b1f3f 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -3560,17 +3560,6 @@ mips_set_reg_reg_cost (enum machine_mode mode) } } -/* Return the cost of an operand X that can be trucated for free. - SPEED says whether we're optimizing for size or speed. */ - -static int -mips_truncated_op_cost (rtx x, bool speed) -{ - if (GET_CODE (x) == TRUNCATE) - x = XEXP (x, 0); - return set_src_cost (x, speed); -} - /* Implement TARGET_RTX_COSTS. */ static bool @@ -3951,13 +3940,12 @@ mips_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED, case ZERO_EXTEND: if (outer_code == SET && ISA_HAS_BADDU + && (GET_CODE (XEXP (x, 0)) == TRUNCATE + || GET_CODE (XEXP (x, 0)) == SUBREG) && GET_MODE (XEXP (x, 0)) == QImode - && GET_CODE (XEXP (x, 0)) == PLUS) + && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS) { - rtx plus = XEXP (x, 0); - *total = (COSTS_N_INSNS (1) - + mips_truncated_op_cost (XEXP (plus, 0), speed) - + mips_truncated_op_cost (XEXP (plus, 1), speed)); + *total = set_src_cost (XEXP (XEXP (x, 0), 0), speed); return true; } *total = mips_zero_extend_cost (mode, XEXP (x, 0)); @@ -8057,7 +8045,7 @@ mips_print_operand (FILE *file, rtx op, int letter) case 't': { int truth = (code == NE) == (letter == 'T'); - fputc ("zfnt"[truth * 2 + (GET_MODE (op) == CCmode)], file); + fputc ("zfnt"[truth * 2 + ST_REG_P (REGNO (XEXP (op, 0)))], file); } break; diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index 0acce14bd8c92..d6e721d30f5d9 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -949,6 +949,11 @@ struct mips_cpu_info { || TARGET_SMARTMIPS) \ && !TARGET_MIPS16) +/* ISA has the WSBH (word swap bytes within halfwords) instruction. + 64-bit targets also provide DSBH and DSHD. */ +#define ISA_HAS_WSBH ((ISA_MIPS32R2 || ISA_MIPS64R2) \ + && !TARGET_MIPS16) + /* ISA has data prefetch instructions. This controls use of 'pref'. */ #define ISA_HAS_PREFETCH ((ISA_MIPS4 \ || TARGET_LOONGSON_2EF \ diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 7aa461dbd6954..2a0c695c807ca 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -73,6 +73,11 @@ UNSPEC_STORE_LEFT UNSPEC_STORE_RIGHT + ;; Integer operations that are too cumbersome to describe directly. + UNSPEC_WSBH + UNSPEC_DSBH + UNSPEC_DSHD + ;; Floating-point moves. UNSPEC_LOAD_LOW UNSPEC_LOAD_HIGH @@ -1294,20 +1299,32 @@ ;; Combiner patterns for unsigned byte-add. -(define_insn "*baddu_si" +(define_insn "*baddu_si_eb" + [(set (match_operand:SI 0 "register_operand" "=d") + (zero_extend:SI + (subreg:QI + (plus:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "register_operand" "d")) 3)))] + "ISA_HAS_BADDU && BYTES_BIG_ENDIAN" + "baddu\\t%0,%1,%2" + [(set_attr "alu_type" "add")]) + +(define_insn "*baddu_si_el" [(set (match_operand:SI 0 "register_operand" "=d") (zero_extend:SI - (plus:QI (match_operand:QI 1 "register_operand" "d") - (match_operand:QI 2 "register_operand" "d"))))] - "ISA_HAS_BADDU" + (subreg:QI + (plus:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "register_operand" "d")) 0)))] + "ISA_HAS_BADDU && !BYTES_BIG_ENDIAN" "baddu\\t%0,%1,%2" [(set_attr "alu_type" "add")]) (define_insn "*baddu_di" [(set (match_operand:GPR 0 "register_operand" "=d") (zero_extend:GPR - (plus:QI (truncate:QI (match_operand:DI 1 "register_operand" "d")) - (truncate:QI (match_operand:DI 2 "register_operand" "d")))))] + (truncate:QI + (plus:DI (match_operand:DI 1 "register_operand" "d") + (match_operand:DI 2 "register_operand" "d")))))] "ISA_HAS_BADDU && TARGET_64BIT" "baddu\\t%0,%1,%2" [(set_attr "alu_type" "add")]) @@ -5367,6 +5384,56 @@ } [(set_attr "type" "shift") (set_attr "mode" "")]) + +(define_insn "bswaphi2" + [(set (match_operand:HI 0 "register_operand" "=d") + (bswap:HI (match_operand:HI 1 "register_operand" "d")))] + "ISA_HAS_WSBH" + "wsbh\t%0,%1" + [(set_attr "type" "shift")]) + +(define_insn_and_split "bswapsi2" + [(set (match_operand:SI 0 "register_operand" "=d") + (bswap:SI (match_operand:SI 1 "register_operand" "d")))] + "ISA_HAS_WSBH && ISA_HAS_ROR" + "#" + "" + [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_WSBH)) + (set (match_dup 0) (rotatert:SI (match_dup 0) (const_int 16)))] + "" + [(set_attr "length" "8")]) + +(define_insn_and_split "bswapdi2" + [(set (match_operand:DI 0 "register_operand" "=d") + (bswap:DI (match_operand:DI 1 "register_operand" "d")))] + "TARGET_64BIT && ISA_HAS_WSBH" + "#" + "" + [(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_DSBH)) + (set (match_dup 0) (unspec:DI [(match_dup 0)] UNSPEC_DSHD))] + "" + [(set_attr "length" "8")]) + +(define_insn "wsbh" + [(set (match_operand:SI 0 "register_operand" "=d") + (unspec:SI [(match_operand:SI 1 "register_operand" "d")] UNSPEC_WSBH))] + "ISA_HAS_WSBH" + "wsbh\t%0,%1" + [(set_attr "type" "shift")]) + +(define_insn "dsbh" + [(set (match_operand:DI 0 "register_operand" "=d") + (unspec:DI [(match_operand:DI 1 "register_operand" "d")] UNSPEC_DSBH))] + "TARGET_64BIT && ISA_HAS_WSBH" + "dsbh\t%0,%1" + [(set_attr "type" "shift")]) + +(define_insn "dshd" + [(set (match_operand:DI 0 "register_operand" "=d") + (unspec:DI [(match_operand:DI 1 "register_operand" "d")] UNSPEC_DSHD))] + "TARGET_64BIT && ISA_HAS_WSBH" + "dshd\t%0,%1" + [(set_attr "type" "shift")]) ;; ;; .................... diff --git a/gcc/config/pa/pa-linux.h b/gcc/config/pa/pa-linux.h index 939f5c22bc75e..f9da314e983de 100644 --- a/gcc/config/pa/pa-linux.h +++ b/gcc/config/pa/pa-linux.h @@ -28,7 +28,7 @@ along with GCC; see the file COPYING3. If not see while (0) #undef CPP_SPEC -#define CPP_SPEC "%{posix:-D_POSIX_SOURCE}" +#define CPP_SPEC "%{posix:-D_POSIX_SOURCE} %{pthread:-D_REENTRANT}" #undef ASM_SPEC #define ASM_SPEC \ diff --git a/gcc/config/pa/pa.c b/gcc/config/pa/pa.c index 0d39483d908ec..7fdc9b679e5fc 100644 --- a/gcc/config/pa/pa.c +++ b/gcc/config/pa/pa.c @@ -513,6 +513,12 @@ pa_option_override (void) write_symbols = NO_DEBUG; } +#ifdef AUTO_INC_DEC + /* FIXME: Disable auto increment and decrement processing until reload + is completed. See PR middle-end 56791. */ + flag_auto_inc_dec = reload_completed; +#endif + /* We only support the "big PIC" model now. And we always generate PIC code when in 64bit mode. */ if (flag_pic == 1 || TARGET_64BIT) @@ -792,7 +798,9 @@ legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg) /* Extract CODE_LABEL. */ orig = XEXP (orig, 0); add_reg_note (insn, REG_LABEL_OPERAND, orig); - LABEL_NUSES (orig)++; + /* Make sure we have label and not a note. */ + if (LABEL_P (orig)) + LABEL_NUSES (orig)++; } crtl->uses_pic_offset_table = 1; return reg; @@ -904,9 +912,12 @@ static rtx legitimize_tls_address (rtx addr) { rtx ret, insn, tmp, t1, t2, tp; - enum tls_model model = SYMBOL_REF_TLS_MODEL (addr); - switch (model) + /* Currently, we can't handle anything but a SYMBOL_REF. */ + if (GET_CODE (addr) != SYMBOL_REF) + return addr; + + switch (SYMBOL_REF_TLS_MODEL (addr)) { case TLS_MODEL_GLOBAL_DYNAMIC: tmp = gen_reg_rtx (Pmode); @@ -1027,7 +1038,7 @@ hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, && !REG_POINTER (XEXP (x, 1))) return gen_rtx_PLUS (Pmode, XEXP (x, 1), XEXP (x, 0)); - if (PA_SYMBOL_REF_TLS_P (x)) + if (pa_tls_referenced_p (x)) return legitimize_tls_address (x); else if (flag_pic) return legitimize_pic_address (x, mode, gen_reg_rtx (Pmode)); @@ -1908,9 +1919,10 @@ pa_emit_move_sequence (rtx *operands, enum machine_mode mode, rtx scratch_reg) not consider them legitimate constants. Loop optimizations can call the emit_move_xxx with one as a source. */ if ((GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode)) - || function_label_operand (operand1, VOIDmode) || (GET_CODE (operand1) == HIGH - && symbolic_operand (XEXP (operand1, 0), mode))) + && symbolic_operand (XEXP (operand1, 0), mode)) + || function_label_operand (operand1, VOIDmode) + || pa_tls_referenced_p (operand1)) { int ishighonly = 0; @@ -2191,11 +2203,11 @@ pa_emit_move_sequence (rtx *operands, enum machine_mode mode, rtx scratch_reg) gen_rtx_HIGH (mode, operand1))); emit_move_insn (temp, gen_rtx_LO_SUM (mode, temp, operand1)); if (mode == DImode) - emit_insn (gen_insvdi (operand0, GEN_INT (32), - const0_rtx, temp)); + insn = emit_insn (gen_insvdi (operand0, GEN_INT (32), + const0_rtx, temp)); else - emit_insn (gen_insvsi (operand0, GEN_INT (32), - const0_rtx, temp)); + insn = emit_insn (gen_insvsi (operand0, GEN_INT (32), + const0_rtx, temp)); } else { @@ -2217,11 +2229,15 @@ pa_emit_move_sequence (rtx *operands, enum machine_mode mode, rtx scratch_reg) } if (mode == DImode) - emit_insn (gen_insvdi (operand0, GEN_INT (len), - GEN_INT (pos), GEN_INT (v5))); + insn = emit_insn (gen_insvdi (operand0, + GEN_INT (len), + GEN_INT (pos), + GEN_INT (v5))); else - emit_insn (gen_insvsi (operand0, GEN_INT (len), - GEN_INT (pos), GEN_INT (v5))); + insn = emit_insn (gen_insvsi (operand0, + GEN_INT (len), + GEN_INT (pos), + GEN_INT (v5))); len = pos > 0 && pos < 5 ? pos : 5; pos -= len; @@ -2573,28 +2589,29 @@ pa_output_move_double (rtx *operands) && GET_CODE (XEXP (addr, 0)) == MULT) { rtx xoperands[4]; - rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0); - if (!reg_overlap_mentioned_p (high_reg, addr)) - { - xoperands[0] = high_reg; - xoperands[1] = XEXP (addr, 1); - xoperands[2] = XEXP (XEXP (addr, 0), 0); - xoperands[3] = XEXP (XEXP (addr, 0), 1); - output_asm_insn ("{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0}", - xoperands); - return "ldw 4(%0),%R0\n\tldw 0(%0),%0"; - } - else - { - xoperands[0] = high_reg; - xoperands[1] = XEXP (addr, 1); - xoperands[2] = XEXP (XEXP (addr, 0), 0); - xoperands[3] = XEXP (XEXP (addr, 0), 1); - output_asm_insn ("{sh%O3addl %2,%1,%R0|shladd,l %2,%O3,%1,%R0}", - xoperands); - return "ldw 0(%R0),%0\n\tldw 4(%R0),%R0"; - } + /* Load address into left half of destination register. */ + xoperands[0] = gen_rtx_SUBREG (SImode, operands[0], 0); + xoperands[1] = XEXP (addr, 1); + xoperands[2] = XEXP (XEXP (addr, 0), 0); + xoperands[3] = XEXP (XEXP (addr, 0), 1); + output_asm_insn ("{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0}", + xoperands); + return "ldw 4(%0),%R0\n\tldw 0(%0),%0"; + } + else if (GET_CODE (addr) == PLUS + && REG_P (XEXP (addr, 0)) + && REG_P (XEXP (addr, 1))) + { + rtx xoperands[3]; + + /* Load address into left half of destination register. */ + xoperands[0] = gen_rtx_SUBREG (SImode, operands[0], 0); + xoperands[1] = XEXP (addr, 0); + xoperands[2] = XEXP (addr, 1); + output_asm_insn ("{addl|add,l} %1,%2,%0", + xoperands); + return "ldw 4(%0),%R0\n\tldw 0(%0),%0"; } } @@ -2617,14 +2634,14 @@ pa_output_move_double (rtx *operands) if (optype0 == REGOP) latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); else if (optype0 == OFFSOP) - latehalf[0] = adjust_address (operands[0], SImode, 4); + latehalf[0] = adjust_address_nv (operands[0], SImode, 4); else latehalf[0] = operands[0]; if (optype1 == REGOP) latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); else if (optype1 == OFFSOP) - latehalf[1] = adjust_address (operands[1], SImode, 4); + latehalf[1] = adjust_address_nv (operands[1], SImode, 4); else if (optype1 == CNSTOP) split_double (operands[1], &operands[1], &latehalf[1]); else @@ -3225,7 +3242,12 @@ pa_assemble_integer (rtx x, unsigned int size, int aligned_p) && aligned_p && function_label_operand (x, VOIDmode)) { - fputs (size == 8? "\t.dword\tP%" : "\t.word\tP%", asm_out_file); + fputs (size == 8? "\t.dword\t" : "\t.word\t", asm_out_file); + + /* We don't want an OPD when generating fast indirect calls. */ + if (!TARGET_FAST_INDIRECT_CALLS) + fputs ("P%", asm_out_file); + output_addr_const (asm_out_file, x); fputc ('\n', asm_out_file); return true; @@ -4036,7 +4058,8 @@ pa_expand_prologue (void) || (! TARGET_64BIT && df_regs_ever_live_p (i + 1))) { rtx addr, insn, reg; - addr = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg)); + addr = gen_rtx_MEM (DFmode, + gen_rtx_POST_INC (word_mode, tmpreg)); reg = gen_rtx_REG (DFmode, i); insn = emit_move_insn (addr, reg); if (DO_FRAME_NOTES) @@ -4147,8 +4170,7 @@ static void pa_output_function_epilogue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED) { rtx insn = get_last_insn (); - - last_address = 0; + bool extra_nop; /* pa_expand_epilogue does the dirty work now. We just need to output the assembler directives which denote the end @@ -4172,26 +4194,36 @@ pa_output_function_epilogue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED) if (insn && GET_CODE (insn) == CALL_INSN) { fputs ("\tnop\n", file); - last_address += 4; + extra_nop = true; } + else + extra_nop = false; fputs ("\t.EXIT\n\t.PROCEND\n", file); if (TARGET_SOM && TARGET_GAS) { - /* We done with this subspace except possibly for some additional + /* We are done with this subspace except possibly for some additional debug information. Forget that we are in this subspace to ensure that the next function is output in its own subspace. */ in_section = NULL; cfun->machine->in_nsubspa = 2; } + /* Thunks do their own insn accounting. */ + if (cfun->is_thunk) + return; + if (INSN_ADDRESSES_SET_P ()) { + last_address = extra_nop ? 4 : 0; insn = get_last_nonnote_insn (); - last_address += INSN_ADDRESSES (INSN_UID (insn)); - if (INSN_P (insn)) - last_address += insn_default_length (insn); + if (insn) + { + last_address += INSN_ADDRESSES (INSN_UID (insn)); + if (INSN_P (insn)) + last_address += insn_default_length (insn); + } last_address = ((last_address + FUNCTION_BOUNDARY / BITS_PER_UNIT - 1) & ~(FUNCTION_BOUNDARY / BITS_PER_UNIT - 1)); } @@ -4329,7 +4361,8 @@ pa_expand_epilogue (void) if (df_regs_ever_live_p (i) || (! TARGET_64BIT && df_regs_ever_live_p (i + 1))) { - rtx src = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg)); + rtx src = gen_rtx_MEM (DFmode, + gen_rtx_POST_INC (word_mode, tmpreg)); rtx dest = gen_rtx_REG (DFmode, i); emit_move_insn (dest, src); } @@ -5388,6 +5421,7 @@ pa_output_global_address (FILE *file, rtx x, int round_constant) switch (GET_CODE (XEXP (XEXP (x, 0), 0))) { + case LABEL_REF: case SYMBOL_REF: base = XEXP (XEXP (x, 0), 0); output_addr_const (file, base); @@ -5401,6 +5435,7 @@ pa_output_global_address (FILE *file, rtx x, int round_constant) switch (GET_CODE (XEXP (XEXP (x, 0), 1))) { + case LABEL_REF: case SYMBOL_REF: base = XEXP (XEXP (x, 0), 1); output_addr_const (file, base); @@ -7529,7 +7564,7 @@ pa_attr_length_millicode_call (rtx insn) if (!TARGET_LONG_CALLS && distance < MAX_PCREL17F_OFFSET) return 8; - if (TARGET_LONG_ABS_CALL && !flag_pic) + if (!flag_pic) return 12; return 24; @@ -8094,7 +8129,8 @@ pa_attr_length_indirect_call (rtx insn) return 12; if (TARGET_FAST_INDIRECT_CALLS - || (!TARGET_PORTABLE_RUNTIME + || (!TARGET_LONG_CALLS + && !TARGET_PORTABLE_RUNTIME && ((TARGET_PA_20 && !TARGET_SOM && distance < 7600000) || distance < MAX_PCREL17F_OFFSET))) return 8; @@ -8255,8 +8291,7 @@ pa_asm_output_mi_thunk (FILE *file, tree thunk_fndecl, HOST_WIDE_INT delta, xoperands[1] = XEXP (DECL_RTL (thunk_fndecl), 0); xoperands[2] = GEN_INT (delta); - ASM_OUTPUT_LABEL (file, XSTR (xoperands[1], 0)); - fprintf (file, "\t.PROC\n\t.CALLINFO FRAME=0,NO_CALLS\n\t.ENTRY\n"); + final_start_function (emit_barrier (), file, 1); /* Output the thunk. We know that the function is in the same translation unit (i.e., the same space) as the thunk, and that @@ -8286,12 +8321,16 @@ pa_asm_output_mi_thunk (FILE *file, tree thunk_fndecl, HOST_WIDE_INT delta, || ((DECL_SECTION_NAME (thunk_fndecl) == DECL_SECTION_NAME (function)) && last_address < 262132))) + /* In this case, we need to be able to reach the start of + the stub table even though the function is likely closer + and can be jumped to directly. */ || (targetm_common.have_named_sections && DECL_SECTION_NAME (thunk_fndecl) == NULL && DECL_SECTION_NAME (function) == NULL - && last_address < 262132) + && total_code_bytes < MAX_PCREL17F_OFFSET) + /* Likewise. */ || (!targetm_common.have_named_sections - && last_address < 262132)))) + && total_code_bytes < MAX_PCREL17F_OFFSET)))) { if (!val_14) output_asm_insn ("addil L'%2,%%r26", xoperands); @@ -8462,16 +8501,7 @@ pa_asm_output_mi_thunk (FILE *file, tree thunk_fndecl, HOST_WIDE_INT delta, } } - fprintf (file, "\t.EXIT\n\t.PROCEND\n"); - - if (TARGET_SOM && TARGET_GAS) - { - /* We done with this subspace except possibly for some additional - debug information. Forget that we are in this subspace to ensure - that the next function is output in its own subspace. */ - in_section = NULL; - cfun->machine->in_nsubspa = 2; - } + final_end_function (); if (TARGET_SOM && flag_pic && TREE_PUBLIC (function)) { @@ -10387,7 +10417,7 @@ pa_legitimate_constant_p (enum machine_mode mode, rtx x) /* TLS_MODEL_GLOBAL_DYNAMIC and TLS_MODEL_LOCAL_DYNAMIC are not legitimate constants. The other variants can't be handled by the move patterns after reload starts. */ - if (PA_SYMBOL_REF_TLS_P (x)) + if (pa_tls_referenced_p (x)) return false; if (TARGET_64BIT && GET_CODE (x) == CONST_DOUBLE) @@ -10512,13 +10542,13 @@ pa_legitimate_address_p (enum machine_mode mode, rtx x, bool strict) /* When INT14_OK_STRICT is false, a secondary reload is needed to adjust the displacement of SImode and DImode floating point - instructions. So, we return false when STRICT is true. We + instructions but this may fail when the register also needs + reloading. So, we return false when STRICT is true. We also reject long displacements for float mode addresses since the majority of accesses will use floating point instructions that don't support 14-bit offsets. */ if (!INT14_OK_STRICT - && reload_in_progress - && strict + && (strict || !(reload_in_progress || reload_completed)) && mode != QImode && mode != HImode) return false; @@ -10578,8 +10608,7 @@ pa_legitimate_address_p (enum machine_mode mode, rtx x, bool strict) return true; if (!INT14_OK_STRICT - && reload_in_progress - && strict + && (strict || !(reload_in_progress || reload_completed)) && mode != QImode && mode != HImode) return false; diff --git a/gcc/config/pa/pa.h b/gcc/config/pa/pa.h index 620768fb04d5b..16fa8c54bcb83 100644 --- a/gcc/config/pa/pa.h +++ b/gcc/config/pa/pa.h @@ -784,9 +784,9 @@ extern int may_call_alloca; #define MAX_REGS_PER_ADDRESS 2 -/* Non-TLS symbolic references. */ -#define PA_SYMBOL_REF_TLS_P(RTX) \ - (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0) +/* TLS symbolic reference. */ +#define PA_SYMBOL_REF_TLS_P(X) \ + (GET_CODE (X) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (X) != 0) /* Recognize any constant value that is a valid address except for symbolic addresses. We get better CSE by rejecting them @@ -796,7 +796,8 @@ extern int may_call_alloca; #define CONSTANT_ADDRESS_P(X) \ ((GET_CODE (X) == LABEL_REF \ || (GET_CODE (X) == SYMBOL_REF && !SYMBOL_REF_TLS_MODEL (X)) \ - || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \ + || GET_CODE (X) == CONST_INT \ + || (GET_CODE (X) == CONST && !pa_tls_referenced_p (X)) \ || GET_CODE (X) == HIGH) \ && (reload_in_progress || reload_completed \ || ! pa_symbolic_expression_p (X))) diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md index 5e6d5652e71c4..ce98d8aedfdf8 100644 --- a/gcc/config/pa/pa.md +++ b/gcc/config/pa/pa.md @@ -123,7 +123,7 @@ ;; type "binary" insns have two input operands (1,2) and one output (0) (define_attr "type" - "move,unary,binary,shift,nullshift,compare,load,store,uncond_branch,btable_branch,branch,cbranch,fbranch,call,sibcall,dyncall,fpload,fpstore,fpalu,fpcc,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,multi,milli,sh_func_adrs,parallel_branch,fpstore_load,store_fpload" + "move,unary,binary,shift,nullshift,compare,load,store,uncond_branch,btable_branch,branch,cbranch,fbranch,call,sibcall,dyncall,fpload,fpstore,fpalu,fpcc,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,multi,milli,sh_func_adrs,parallel_branch,fpstore_load,store_fpload,trap" (const_string "binary")) (define_attr "pa_combine_type" @@ -166,7 +166,7 @@ ;; For conditional branches. Frame related instructions are not allowed ;; because they confuse the unwind support. (define_attr "in_branch_delay" "false,true" - (if_then_else (and (eq_attr "type" "!uncond_branch,btable_branch,branch,cbranch,fbranch,call,sibcall,dyncall,multi,milli,sh_func_adrs,parallel_branch") + (if_then_else (and (eq_attr "type" "!uncond_branch,btable_branch,branch,cbranch,fbranch,call,sibcall,dyncall,multi,milli,sh_func_adrs,parallel_branch,trap") (eq_attr "length" "4") (not (match_test "RTX_FRAME_RELATED_P (insn)"))) (const_string "true") @@ -175,7 +175,7 @@ ;; Disallow instructions which use the FPU since they will tie up the FPU ;; even if the instruction is nullified. (define_attr "in_nullified_branch_delay" "false,true" - (if_then_else (and (eq_attr "type" "!uncond_branch,btable_branch,branch,cbranch,fbranch,call,sibcall,dyncall,multi,milli,sh_func_adrs,fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,parallel_branch") + (if_then_else (and (eq_attr "type" "!uncond_branch,btable_branch,branch,cbranch,fbranch,call,sibcall,dyncall,multi,milli,sh_func_adrs,fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,parallel_branch,trap") (eq_attr "length" "4") (not (match_test "RTX_FRAME_RELATED_P (insn)"))) (const_string "true") @@ -184,7 +184,7 @@ ;; For calls and millicode calls. Allow unconditional branches in the ;; delay slot. (define_attr "in_call_delay" "false,true" - (cond [(and (eq_attr "type" "!uncond_branch,btable_branch,branch,cbranch,fbranch,call,sibcall,dyncall,multi,milli,sh_func_adrs,parallel_branch") + (cond [(and (eq_attr "type" "!uncond_branch,btable_branch,branch,cbranch,fbranch,call,sibcall,dyncall,multi,milli,sh_func_adrs,parallel_branch,trap") (eq_attr "length" "4") (not (match_test "RTX_FRAME_RELATED_P (insn)"))) (const_string "true") @@ -833,46 +833,46 @@ (define_insn "scc" [(set (match_operand:SI 0 "register_operand" "=r") (match_operator:SI 3 "comparison_operator" - [(match_operand:SI 1 "register_operand" "r") + [(match_operand:SI 1 "reg_or_0_operand" "rM") (match_operand:SI 2 "arith11_operand" "rI")]))] "" - "{com%I2clr|cmp%I2clr},%B3 %2,%1,%0\;ldi 1,%0" + "{com%I2clr|cmp%I2clr},%B3 %2,%r1,%0\;ldi 1,%0" [(set_attr "type" "binary") (set_attr "length" "8")]) (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r") (match_operator:DI 3 "comparison_operator" - [(match_operand:DI 1 "register_operand" "r") + [(match_operand:DI 1 "reg_or_0_operand" "rM") (match_operand:DI 2 "arith11_operand" "rI")]))] "TARGET_64BIT" - "cmp%I2clr,*%B3 %2,%1,%0\;ldi 1,%0" + "cmp%I2clr,*%B3 %2,%r1,%0\;ldi 1,%0" [(set_attr "type" "binary") (set_attr "length" "8")]) (define_insn "iorscc" [(set (match_operand:SI 0 "register_operand" "=r") (ior:SI (match_operator:SI 3 "comparison_operator" - [(match_operand:SI 1 "register_operand" "r") + [(match_operand:SI 1 "reg_or_0_operand" "rM") (match_operand:SI 2 "arith11_operand" "rI")]) (match_operator:SI 6 "comparison_operator" - [(match_operand:SI 4 "register_operand" "r") + [(match_operand:SI 4 "reg_or_0_operand" "rM") (match_operand:SI 5 "arith11_operand" "rI")])))] "" - "{com%I2clr|cmp%I2clr},%S3 %2,%1,%%r0\;{com%I5clr|cmp%I5clr},%B6 %5,%4,%0\;ldi 1,%0" + "{com%I2clr|cmp%I2clr},%S3 %2,%r1,%%r0\;{com%I5clr|cmp%I5clr},%B6 %5,%r4,%0\;ldi 1,%0" [(set_attr "type" "binary") (set_attr "length" "12")]) (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r") (ior:DI (match_operator:DI 3 "comparison_operator" - [(match_operand:DI 1 "register_operand" "r") + [(match_operand:DI 1 "reg_or_0_operand" "rM") (match_operand:DI 2 "arith11_operand" "rI")]) (match_operator:DI 6 "comparison_operator" - [(match_operand:DI 4 "register_operand" "r") + [(match_operand:DI 4 "reg_or_0_operand" "rM") (match_operand:DI 5 "arith11_operand" "rI")])))] "TARGET_64BIT" - "cmp%I2clr,*%S3 %2,%1,%%r0\;cmp%I5clr,*%B6 %5,%4,%0\;ldi 1,%0" + "cmp%I2clr,*%S3 %2,%r1,%%r0\;cmp%I5clr,*%B6 %5,%r4,%0\;ldi 1,%0" [(set_attr "type" "binary") (set_attr "length" "12")]) @@ -881,20 +881,20 @@ (define_insn "negscc" [(set (match_operand:SI 0 "register_operand" "=r") (neg:SI (match_operator:SI 3 "comparison_operator" - [(match_operand:SI 1 "register_operand" "r") + [(match_operand:SI 1 "reg_or_0_operand" "rM") (match_operand:SI 2 "arith11_operand" "rI")])))] "" - "{com%I2clr|cmp%I2clr},%B3 %2,%1,%0\;ldi -1,%0" + "{com%I2clr|cmp%I2clr},%B3 %2,%r1,%0\;ldi -1,%0" [(set_attr "type" "binary") (set_attr "length" "8")]) (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r") (neg:DI (match_operator:DI 3 "comparison_operator" - [(match_operand:DI 1 "register_operand" "r") + [(match_operand:DI 1 "reg_or_0_operand" "rM") (match_operand:DI 2 "arith11_operand" "rI")])))] "TARGET_64BIT" - "cmp%I2clr,*%B3 %2,%1,%0\;ldi -1,%0" + "cmp%I2clr,*%B3 %2,%r1,%0\;ldi -1,%0" [(set_attr "type" "binary") (set_attr "length" "8")]) @@ -5331,6 +5331,15 @@ [(set_attr "type" "binary,binary") (set_attr "length" "4,4")]) +;; Trap instructions. + +(define_insn "trap" + [(trap_if (const_int 1) (const_int 0))] + "" + "{addit|addi,tc},<> 1,%%r0,%%r0" + [(set_attr "type" "trap") + (set_attr "length" "4")]) + ;; Clobbering a "register_operand" instead of a match_scratch ;; in operand3 of millicode calls avoids spilling %r1 and ;; produces better code. diff --git a/gcc/config/rs6000/altivec.h b/gcc/config/rs6000/altivec.h index fd6d07f50ff75..ad485d6eb78da 100644 --- a/gcc/config/rs6000/altivec.h +++ b/gcc/config/rs6000/altivec.h @@ -124,6 +124,7 @@ #define vec_vcfux __builtin_vec_vcfux #define vec_cts __builtin_vec_cts #define vec_ctu __builtin_vec_ctu +#define vec_cpsgn __builtin_vec_copysign #define vec_expte __builtin_vec_expte #define vec_floor __builtin_vec_floor #define vec_loge __builtin_vec_loge @@ -214,8 +215,10 @@ #define vec_lvsl __builtin_vec_lvsl #define vec_lvsr __builtin_vec_lvsr #define vec_max __builtin_vec_max +#define vec_mergee __builtin_vec_vmrgew #define vec_mergeh __builtin_vec_mergeh #define vec_mergel __builtin_vec_mergel +#define vec_mergeo __builtin_vec_vmrgow #define vec_min __builtin_vec_min #define vec_mladd __builtin_vec_mladd #define vec_msum __builtin_vec_msum @@ -319,6 +322,59 @@ #define vec_sqrt __builtin_vec_sqrt #define vec_vsx_ld __builtin_vec_vsx_ld #define vec_vsx_st __builtin_vec_vsx_st +#define vec_xl __builtin_vec_vsx_ld +#define vec_xst __builtin_vec_vsx_st + +/* Note, xxsldi and xxpermdi were added as __builtin_vsx_ functions + instead of __builtin_vec_ */ +#define vec_xxsldwi __builtin_vsx_xxsldwi +#define vec_xxpermdi __builtin_vsx_xxpermdi +#endif + +#ifdef _ARCH_PWR8 +/* Vector additions added in ISA 2.07. */ +#define vec_eqv __builtin_vec_eqv +#define vec_nand __builtin_vec_nand +#define vec_orc __builtin_vec_orc +#define vec_vaddcuq __builtin_vec_vaddcuq +#define vec_vaddudm __builtin_vec_vaddudm +#define vec_vadduqm __builtin_vec_vadduqm +#define vec_vbpermq __builtin_vec_vbpermq +#define vec_vclz __builtin_vec_vclz +#define vec_cntlz __builtin_vec_vclz +#define vec_vclzb __builtin_vec_vclzb +#define vec_vclzd __builtin_vec_vclzd +#define vec_vclzh __builtin_vec_vclzh +#define vec_vclzw __builtin_vec_vclzw +#define vec_vaddecuq __builtin_vec_vaddecuq +#define vec_vaddeuqm __builtin_vec_vaddeuqm +#define vec_vsubecuq __builtin_vec_vsubecuq +#define vec_vsubeuqm __builtin_vec_vsubeuqm +#define vec_vgbbd __builtin_vec_vgbbd +#define vec_vmaxsd __builtin_vec_vmaxsd +#define vec_vmaxud __builtin_vec_vmaxud +#define vec_vminsd __builtin_vec_vminsd +#define vec_vminud __builtin_vec_vminud +#define vec_vmrgew __builtin_vec_vmrgew +#define vec_vmrgow __builtin_vec_vmrgow +#define vec_vpksdss __builtin_vec_vpksdss +#define vec_vpksdus __builtin_vec_vpksdus +#define vec_vpkudum __builtin_vec_vpkudum +#define vec_vpkudus __builtin_vec_vpkudus +#define vec_vpopcnt __builtin_vec_vpopcnt +#define vec_vpopcntb __builtin_vec_vpopcntb +#define vec_vpopcntd __builtin_vec_vpopcntd +#define vec_vpopcnth __builtin_vec_vpopcnth +#define vec_vpopcntw __builtin_vec_vpopcntw +#define vec_vrld __builtin_vec_vrld +#define vec_vsld __builtin_vec_vsld +#define vec_vsrad __builtin_vec_vsrad +#define vec_vsrd __builtin_vec_vsrd +#define vec_vsubcuq __builtin_vec_vsubcuq +#define vec_vsubudm __builtin_vec_vsubudm +#define vec_vsubuqm __builtin_vec_vsubuqm +#define vec_vupkhsw __builtin_vec_vupkhsw +#define vec_vupklsw __builtin_vec_vupklsw #endif /* Predicates. diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index 1b0b5c3fb1323..532c452665a65 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -41,15 +41,12 @@ UNSPEC_VMULOSB UNSPEC_VMULOUH UNSPEC_VMULOSH - UNSPEC_VPKUHUM - UNSPEC_VPKUWUM UNSPEC_VPKPX - UNSPEC_VPKSHSS - UNSPEC_VPKSWSS - UNSPEC_VPKUHUS - UNSPEC_VPKSHUS - UNSPEC_VPKUWUS - UNSPEC_VPKSWUS + UNSPEC_VPACK_SIGN_SIGN_SAT + UNSPEC_VPACK_SIGN_UNS_SAT + UNSPEC_VPACK_UNS_UNS_SAT + UNSPEC_VPACK_UNS_UNS_MOD + UNSPEC_VPACK_UNS_UNS_MOD_DIRECT UNSPEC_VSLV4SI UNSPEC_VSLO UNSPEC_VSR @@ -70,13 +67,13 @@ UNSPEC_VCTSXS UNSPEC_VLOGEFP UNSPEC_VEXPTEFP - UNSPEC_VLSDOI - UNSPEC_VUPKHSB + UNSPEC_VSLDOI + UNSPEC_VUNPACK_HI_SIGN + UNSPEC_VUNPACK_LO_SIGN + UNSPEC_VUNPACK_HI_SIGN_DIRECT + UNSPEC_VUNPACK_LO_SIGN_DIRECT UNSPEC_VUPKHPX - UNSPEC_VUPKHSH - UNSPEC_VUPKLSB UNSPEC_VUPKLPX - UNSPEC_VUPKLSH UNSPEC_DST UNSPEC_DSTT UNSPEC_DSTST @@ -134,6 +131,21 @@ UNSPEC_VUPKLS_V4SF UNSPEC_VUPKHU_V4SF UNSPEC_VUPKLU_V4SF + UNSPEC_VGBBD + UNSPEC_VMRGH_DIRECT + UNSPEC_VMRGL_DIRECT + UNSPEC_VSPLT_DIRECT + UNSPEC_VSUMSWS_DIRECT + UNSPEC_VADDCUQ + UNSPEC_VADDEUQM + UNSPEC_VADDECUQ + UNSPEC_VSUBCUQ + UNSPEC_VSUBEUQM + UNSPEC_VSUBECUQ + UNSPEC_VBPERMQ + UNSPEC_BCDADD + UNSPEC_BCDSUB + UNSPEC_BCD_OVERFLOW ]) (define_c_enum "unspecv" @@ -146,6 +158,8 @@ ;; Vec int modes (define_mode_iterator VI [V4SI V8HI V16QI]) +;; Like VI, but add ISA 2.07 integer vector ops +(define_mode_iterator VI2 [V4SI V8HI V16QI V2DI]) ;; Short vec in modes (define_mode_iterator VIshort [V8HI V16QI]) ;; Vec float modes @@ -154,13 +168,24 @@ (define_mode_iterator V [V4SI V8HI V16QI V4SF]) ;; Vec modes for move/logical/permute ops, include vector types for move not ;; otherwise handled by altivec (v2df, v2di, ti) -(define_mode_iterator VM [V4SI V8HI V16QI V4SF V2DF V2DI TI]) +(define_mode_iterator VM [V4SI V8HI V16QI V4SF V2DF V2DI V1TI TI]) ;; Like VM, except don't do TImode -(define_mode_iterator VM2 [V4SI V8HI V16QI V4SF V2DF V2DI]) - -(define_mode_attr VI_char [(V4SI "w") (V8HI "h") (V16QI "b")]) -(define_mode_attr VI_scalar [(V4SI "SI") (V8HI "HI") (V16QI "QI")]) +(define_mode_iterator VM2 [V4SI V8HI V16QI V4SF V2DF V2DI V1TI]) + +(define_mode_attr VI_char [(V2DI "d") (V4SI "w") (V8HI "h") (V16QI "b")]) +(define_mode_attr VI_scalar [(V2DI "DI") (V4SI "SI") (V8HI "HI") (V16QI "QI")]) +(define_mode_attr VI_unit [(V16QI "VECTOR_UNIT_ALTIVEC_P (V16QImode)") + (V8HI "VECTOR_UNIT_ALTIVEC_P (V8HImode)") + (V4SI "VECTOR_UNIT_ALTIVEC_P (V4SImode)") + (V2DI "VECTOR_UNIT_P8_VECTOR_P (V2DImode)") + (V1TI "VECTOR_UNIT_ALTIVEC_P (V1TImode)")]) + +;; Vector pack/unpack +(define_mode_iterator VP [V2DI V4SI V8HI]) +(define_mode_attr VP_small [(V2DI "V4SI") (V4SI "V8HI") (V8HI "V16QI")]) +(define_mode_attr VP_small_lc [(V2DI "v4si") (V4SI "v8hi") (V8HI "v16qi")]) +(define_mode_attr VU_char [(V2DI "w") (V4SI "h") (V8HI "b")]) ;; Vector move instructions. (define_insn "*altivec_mov" @@ -378,10 +403,10 @@ ;; add (define_insn "add3" - [(set (match_operand:VI 0 "register_operand" "=v") - (plus:VI (match_operand:VI 1 "register_operand" "v") - (match_operand:VI 2 "register_operand" "v")))] - "TARGET_ALTIVEC" + [(set (match_operand:VI2 0 "register_operand" "=v") + (plus:VI2 (match_operand:VI2 1 "register_operand" "v") + (match_operand:VI2 2 "register_operand" "v")))] + "" "vaddum %0,%1,%2" [(set_attr "type" "vecsimple")]) @@ -398,17 +423,17 @@ (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") (match_operand:V4SI 2 "register_operand" "v")] UNSPEC_VADDCUW))] - "TARGET_ALTIVEC" + "VECTOR_UNIT_ALTIVEC_P (V4SImode)" "vaddcuw %0,%1,%2" [(set_attr "type" "vecsimple")]) (define_insn "altivec_vaddus" [(set (match_operand:VI 0 "register_operand" "=v") (unspec:VI [(match_operand:VI 1 "register_operand" "v") - (match_operand:VI 2 "register_operand" "v")] + (match_operand:VI 2 "register_operand" "v")] UNSPEC_VADDU)) (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] - "TARGET_ALTIVEC" + "" "vaddus %0,%1,%2" [(set_attr "type" "vecsimple")]) @@ -418,16 +443,16 @@ (match_operand:VI 2 "register_operand" "v")] UNSPEC_VADDS)) (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] - "TARGET_ALTIVEC" + "VECTOR_UNIT_ALTIVEC_P (mode)" "vaddss %0,%1,%2" [(set_attr "type" "vecsimple")]) ;; sub (define_insn "sub3" - [(set (match_operand:VI 0 "register_operand" "=v") - (minus:VI (match_operand:VI 1 "register_operand" "v") - (match_operand:VI 2 "register_operand" "v")))] - "TARGET_ALTIVEC" + [(set (match_operand:VI2 0 "register_operand" "=v") + (minus:VI2 (match_operand:VI2 1 "register_operand" "v") + (match_operand:VI2 2 "register_operand" "v")))] + "" "vsubum %0,%1,%2" [(set_attr "type" "vecsimple")]) @@ -444,7 +469,7 @@ (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") (match_operand:V4SI 2 "register_operand" "v")] UNSPEC_VSUBCUW))] - "TARGET_ALTIVEC" + "VECTOR_UNIT_ALTIVEC_P (V4SImode)" "vsubcuw %0,%1,%2" [(set_attr "type" "vecsimple")]) @@ -454,7 +479,7 @@ (match_operand:VI 2 "register_operand" "v")] UNSPEC_VSUBU)) (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] - "TARGET_ALTIVEC" + "VECTOR_UNIT_ALTIVEC_P (mode)" "vsubus %0,%1,%2" [(set_attr "type" "vecsimple")]) @@ -464,7 +489,7 @@ (match_operand:VI 2 "register_operand" "v")] UNSPEC_VSUBS)) (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] - "TARGET_ALTIVEC" + "VECTOR_UNIT_ALTIVEC_P (mode)" "vsubss %0,%1,%2" [(set_attr "type" "vecsimple")]) @@ -483,7 +508,7 @@ (unspec:VI [(match_operand:VI 1 "register_operand" "v") (match_operand:VI 2 "register_operand" "v")] UNSPEC_VAVGS))] - "TARGET_ALTIVEC" + "VECTOR_UNIT_ALTIVEC_P (mode)" "vavgs %0,%1,%2" [(set_attr "type" "vecsimple")]) @@ -492,31 +517,31 @@ (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v") (match_operand:V4SF 2 "register_operand" "v")] UNSPEC_VCMPBFP))] - "TARGET_ALTIVEC" + "VECTOR_UNIT_ALTIVEC_P (V4SImode)" "vcmpbfp %0,%1,%2" [(set_attr "type" "veccmp")]) (define_insn "*altivec_eq" - [(set (match_operand:VI 0 "altivec_register_operand" "=v") - (eq:VI (match_operand:VI 1 "altivec_register_operand" "v") - (match_operand:VI 2 "altivec_register_operand" "v")))] - "TARGET_ALTIVEC" + [(set (match_operand:VI2 0 "altivec_register_operand" "=v") + (eq:VI2 (match_operand:VI2 1 "altivec_register_operand" "v") + (match_operand:VI2 2 "altivec_register_operand" "v")))] + "" "vcmpequ %0,%1,%2" [(set_attr "type" "veccmp")]) (define_insn "*altivec_gt" - [(set (match_operand:VI 0 "altivec_register_operand" "=v") - (gt:VI (match_operand:VI 1 "altivec_register_operand" "v") - (match_operand:VI 2 "altivec_register_operand" "v")))] - "TARGET_ALTIVEC" + [(set (match_operand:VI2 0 "altivec_register_operand" "=v") + (gt:VI2 (match_operand:VI2 1 "altivec_register_operand" "v") + (match_operand:VI2 2 "altivec_register_operand" "v")))] + "" "vcmpgts %0,%1,%2" [(set_attr "type" "veccmp")]) (define_insn "*altivec_gtu" - [(set (match_operand:VI 0 "altivec_register_operand" "=v") - (gtu:VI (match_operand:VI 1 "altivec_register_operand" "v") - (match_operand:VI 2 "altivec_register_operand" "v")))] - "TARGET_ALTIVEC" + [(set (match_operand:VI2 0 "altivec_register_operand" "=v") + (gtu:VI2 (match_operand:VI2 1 "altivec_register_operand" "v") + (match_operand:VI2 2 "altivec_register_operand" "v")))] + "" "vcmpgtu %0,%1,%2" [(set_attr "type" "veccmp")]) @@ -642,7 +667,7 @@ convert_move (small_swap, swap, 0); low_product = gen_reg_rtx (V4SImode); - emit_insn (gen_vec_widen_umult_odd_v8hi (low_product, one, two)); + emit_insn (gen_altivec_vmulouh (low_product, one, two)); high_product = gen_reg_rtx (V4SImode); emit_insn (gen_altivec_vmsumuhm (high_product, one, small_swap, zero)); @@ -666,13 +691,22 @@ rtx high = gen_reg_rtx (V4SImode); rtx low = gen_reg_rtx (V4SImode); - emit_insn (gen_vec_widen_smult_even_v8hi (even, operands[1], operands[2])); - emit_insn (gen_vec_widen_smult_odd_v8hi (odd, operands[1], operands[2])); - - emit_insn (gen_altivec_vmrghw (high, even, odd)); - emit_insn (gen_altivec_vmrglw (low, even, odd)); - - emit_insn (gen_altivec_vpkuwum (operands[0], high, low)); + if (BYTES_BIG_ENDIAN) + { + emit_insn (gen_altivec_vmulesh (even, operands[1], operands[2])); + emit_insn (gen_altivec_vmulosh (odd, operands[1], operands[2])); + emit_insn (gen_altivec_vmrghw_direct (high, even, odd)); + emit_insn (gen_altivec_vmrglw_direct (low, even, odd)); + emit_insn (gen_altivec_vpkuwum_direct (operands[0], high, low)); + } + else + { + emit_insn (gen_altivec_vmulosh (even, operands[1], operands[2])); + emit_insn (gen_altivec_vmulesh (odd, operands[1], operands[2])); + emit_insn (gen_altivec_vmrghw_direct (high, odd, even)); + emit_insn (gen_altivec_vmrglw_direct (low, odd, even)); + emit_insn (gen_altivec_vpkuwum_direct (operands[0], low, high)); + } DONE; }") @@ -744,18 +778,18 @@ ;; max (define_insn "umax3" - [(set (match_operand:VI 0 "register_operand" "=v") - (umax:VI (match_operand:VI 1 "register_operand" "v") - (match_operand:VI 2 "register_operand" "v")))] - "TARGET_ALTIVEC" + [(set (match_operand:VI2 0 "register_operand" "=v") + (umax:VI2 (match_operand:VI2 1 "register_operand" "v") + (match_operand:VI2 2 "register_operand" "v")))] + "" "vmaxu %0,%1,%2" [(set_attr "type" "vecsimple")]) (define_insn "smax3" - [(set (match_operand:VI 0 "register_operand" "=v") - (smax:VI (match_operand:VI 1 "register_operand" "v") - (match_operand:VI 2 "register_operand" "v")))] - "TARGET_ALTIVEC" + [(set (match_operand:VI2 0 "register_operand" "=v") + (smax:VI2 (match_operand:VI2 1 "register_operand" "v") + (match_operand:VI2 2 "register_operand" "v")))] + "" "vmaxs %0,%1,%2" [(set_attr "type" "vecsimple")]) @@ -768,18 +802,18 @@ [(set_attr "type" "veccmp")]) (define_insn "umin3" - [(set (match_operand:VI 0 "register_operand" "=v") - (umin:VI (match_operand:VI 1 "register_operand" "v") - (match_operand:VI 2 "register_operand" "v")))] - "TARGET_ALTIVEC" + [(set (match_operand:VI2 0 "register_operand" "=v") + (umin:VI2 (match_operand:VI2 1 "register_operand" "v") + (match_operand:VI2 2 "register_operand" "v")))] + "" "vminu %0,%1,%2" [(set_attr "type" "vecsimple")]) (define_insn "smin3" - [(set (match_operand:VI 0 "register_operand" "=v") - (smin:VI (match_operand:VI 1 "register_operand" "v") - (match_operand:VI 2 "register_operand" "v")))] - "TARGET_ALTIVEC" + [(set (match_operand:VI2 0 "register_operand" "=v") + (smin:VI2 (match_operand:VI2 1 "register_operand" "v") + (match_operand:VI2 2 "register_operand" "v")))] + "" "vmins %0,%1,%2" [(set_attr "type" "vecsimple")]) @@ -823,9 +857,41 @@ "vmladduhm %0,%1,%2,%3" [(set_attr "type" "veccomplex")]) -(define_insn "altivec_vmrghb" +(define_expand "altivec_vmrghb" + [(use (match_operand:V16QI 0 "register_operand" "")) + (use (match_operand:V16QI 1 "register_operand" "")) + (use (match_operand:V16QI 2 "register_operand" ""))] + "TARGET_ALTIVEC" +{ + rtvec v; + rtx x; + + /* Special handling for LE with -maltivec=be. */ + if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG) + { + v = gen_rtvec (16, GEN_INT (8), GEN_INT (24), GEN_INT (9), GEN_INT (25), + GEN_INT (10), GEN_INT (26), GEN_INT (11), GEN_INT (27), + GEN_INT (12), GEN_INT (28), GEN_INT (13), GEN_INT (29), + GEN_INT (14), GEN_INT (30), GEN_INT (15), GEN_INT (31)); + x = gen_rtx_VEC_CONCAT (V32QImode, operands[2], operands[1]); + } + else + { + v = gen_rtvec (16, GEN_INT (0), GEN_INT (16), GEN_INT (1), GEN_INT (17), + GEN_INT (2), GEN_INT (18), GEN_INT (3), GEN_INT (19), + GEN_INT (4), GEN_INT (20), GEN_INT (5), GEN_INT (21), + GEN_INT (6), GEN_INT (22), GEN_INT (7), GEN_INT (23)); + x = gen_rtx_VEC_CONCAT (V32QImode, operands[1], operands[2]); + } + + x = gen_rtx_VEC_SELECT (V16QImode, x, gen_rtx_PARALLEL (VOIDmode, v)); + emit_insn (gen_rtx_SET (VOIDmode, operands[0], x)); + DONE; +}) + +(define_insn "*altivec_vmrghb_internal" [(set (match_operand:V16QI 0 "register_operand" "=v") - (vec_select:V16QI + (vec_select:V16QI (vec_concat:V32QI (match_operand:V16QI 1 "register_operand" "v") (match_operand:V16QI 2 "register_operand" "v")) @@ -838,12 +904,54 @@ (const_int 6) (const_int 22) (const_int 7) (const_int 23)])))] "TARGET_ALTIVEC" +{ + if (BYTES_BIG_ENDIAN) + return "vmrghb %0,%1,%2"; + else + return "vmrglb %0,%2,%1"; +} + [(set_attr "type" "vecperm")]) + +(define_insn "altivec_vmrghb_direct" + [(set (match_operand:V16QI 0 "register_operand" "=v") + (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") + (match_operand:V16QI 2 "register_operand" "v")] + UNSPEC_VMRGH_DIRECT))] + "TARGET_ALTIVEC" "vmrghb %0,%1,%2" [(set_attr "type" "vecperm")]) -(define_insn "altivec_vmrghh" +(define_expand "altivec_vmrghh" + [(use (match_operand:V8HI 0 "register_operand" "")) + (use (match_operand:V8HI 1 "register_operand" "")) + (use (match_operand:V8HI 2 "register_operand" ""))] + "TARGET_ALTIVEC" +{ + rtvec v; + rtx x; + + /* Special handling for LE with -maltivec=be. */ + if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG) + { + v = gen_rtvec (8, GEN_INT (4), GEN_INT (12), GEN_INT (5), GEN_INT (13), + GEN_INT (6), GEN_INT (14), GEN_INT (7), GEN_INT (15)); + x = gen_rtx_VEC_CONCAT (V16HImode, operands[2], operands[1]); + } + else + { + v = gen_rtvec (8, GEN_INT (0), GEN_INT (8), GEN_INT (1), GEN_INT (9), + GEN_INT (2), GEN_INT (10), GEN_INT (3), GEN_INT (11)); + x = gen_rtx_VEC_CONCAT (V16HImode, operands[1], operands[2]); + } + + x = gen_rtx_VEC_SELECT (V8HImode, x, gen_rtx_PARALLEL (VOIDmode, v)); + emit_insn (gen_rtx_SET (VOIDmode, operands[0], x)); + DONE; +}) + +(define_insn "*altivec_vmrghh_internal" [(set (match_operand:V8HI 0 "register_operand" "=v") - (vec_select:V8HI + (vec_select:V8HI (vec_concat:V16HI (match_operand:V8HI 1 "register_operand" "v") (match_operand:V8HI 2 "register_operand" "v")) @@ -852,10 +960,50 @@ (const_int 2) (const_int 10) (const_int 3) (const_int 11)])))] "TARGET_ALTIVEC" +{ + if (BYTES_BIG_ENDIAN) + return "vmrghh %0,%1,%2"; + else + return "vmrglh %0,%2,%1"; +} + [(set_attr "type" "vecperm")]) + +(define_insn "altivec_vmrghh_direct" + [(set (match_operand:V8HI 0 "register_operand" "=v") + (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") + (match_operand:V8HI 2 "register_operand" "v")] + UNSPEC_VMRGH_DIRECT))] + "TARGET_ALTIVEC" "vmrghh %0,%1,%2" [(set_attr "type" "vecperm")]) -(define_insn "altivec_vmrghw" +(define_expand "altivec_vmrghw" + [(use (match_operand:V4SI 0 "register_operand" "")) + (use (match_operand:V4SI 1 "register_operand" "")) + (use (match_operand:V4SI 2 "register_operand" ""))] + "VECTOR_MEM_ALTIVEC_P (V4SImode)" +{ + rtvec v; + rtx x; + + /* Special handling for LE with -maltivec=be. */ + if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG) + { + v = gen_rtvec (4, GEN_INT (2), GEN_INT (6), GEN_INT (3), GEN_INT (7)); + x = gen_rtx_VEC_CONCAT (V8SImode, operands[2], operands[1]); + } + else + { + v = gen_rtvec (4, GEN_INT (0), GEN_INT (4), GEN_INT (1), GEN_INT (5)); + x = gen_rtx_VEC_CONCAT (V8SImode, operands[1], operands[2]); + } + + x = gen_rtx_VEC_SELECT (V4SImode, x, gen_rtx_PARALLEL (VOIDmode, v)); + emit_insn (gen_rtx_SET (VOIDmode, operands[0], x)); + DONE; +}) + +(define_insn "*altivec_vmrghw_internal" [(set (match_operand:V4SI 0 "register_operand" "=v") (vec_select:V4SI (vec_concat:V8SI @@ -864,6 +1012,20 @@ (parallel [(const_int 0) (const_int 4) (const_int 1) (const_int 5)])))] "VECTOR_MEM_ALTIVEC_P (V4SImode)" +{ + if (BYTES_BIG_ENDIAN) + return "vmrghw %0,%1,%2"; + else + return "vmrglw %0,%2,%1"; +} + [(set_attr "type" "vecperm")]) + +(define_insn "altivec_vmrghw_direct" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") + (match_operand:V4SI 2 "register_operand" "v")] + UNSPEC_VMRGH_DIRECT))] + "TARGET_ALTIVEC" "vmrghw %0,%1,%2" [(set_attr "type" "vecperm")]) @@ -876,10 +1038,47 @@ (parallel [(const_int 0) (const_int 4) (const_int 1) (const_int 5)])))] "VECTOR_MEM_ALTIVEC_P (V4SFmode)" - "vmrghw %0,%1,%2" +{ + if (BYTES_BIG_ENDIAN) + return "vmrghw %0,%1,%2"; + else + return "vmrglw %0,%2,%1"; +} [(set_attr "type" "vecperm")]) -(define_insn "altivec_vmrglb" +(define_expand "altivec_vmrglb" + [(use (match_operand:V16QI 0 "register_operand" "")) + (use (match_operand:V16QI 1 "register_operand" "")) + (use (match_operand:V16QI 2 "register_operand" ""))] + "TARGET_ALTIVEC" +{ + rtvec v; + rtx x; + + /* Special handling for LE with -maltivec=be. */ + if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG) + { + v = gen_rtvec (16, GEN_INT (0), GEN_INT (16), GEN_INT (1), GEN_INT (17), + GEN_INT (2), GEN_INT (18), GEN_INT (3), GEN_INT (19), + GEN_INT (4), GEN_INT (20), GEN_INT (5), GEN_INT (21), + GEN_INT (6), GEN_INT (22), GEN_INT (7), GEN_INT (23)); + x = gen_rtx_VEC_CONCAT (V32QImode, operands[2], operands[1]); + } + else + { + v = gen_rtvec (16, GEN_INT (8), GEN_INT (24), GEN_INT (9), GEN_INT (25), + GEN_INT (10), GEN_INT (26), GEN_INT (11), GEN_INT (27), + GEN_INT (12), GEN_INT (28), GEN_INT (13), GEN_INT (29), + GEN_INT (14), GEN_INT (30), GEN_INT (15), GEN_INT (31)); + x = gen_rtx_VEC_CONCAT (V32QImode, operands[1], operands[2]); + } + + x = gen_rtx_VEC_SELECT (V16QImode, x, gen_rtx_PARALLEL (VOIDmode, v)); + emit_insn (gen_rtx_SET (VOIDmode, operands[0], x)); + DONE; +}) + +(define_insn "*altivec_vmrglb_internal" [(set (match_operand:V16QI 0 "register_operand" "=v") (vec_select:V16QI (vec_concat:V32QI @@ -894,10 +1093,52 @@ (const_int 14) (const_int 30) (const_int 15) (const_int 31)])))] "TARGET_ALTIVEC" +{ + if (BYTES_BIG_ENDIAN) + return "vmrglb %0,%1,%2"; + else + return "vmrghb %0,%2,%1"; +} + [(set_attr "type" "vecperm")]) + +(define_insn "altivec_vmrglb_direct" + [(set (match_operand:V16QI 0 "register_operand" "=v") + (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") + (match_operand:V16QI 2 "register_operand" "v")] + UNSPEC_VMRGL_DIRECT))] + "TARGET_ALTIVEC" "vmrglb %0,%1,%2" [(set_attr "type" "vecperm")]) -(define_insn "altivec_vmrglh" +(define_expand "altivec_vmrglh" + [(use (match_operand:V8HI 0 "register_operand" "")) + (use (match_operand:V8HI 1 "register_operand" "")) + (use (match_operand:V8HI 2 "register_operand" ""))] + "TARGET_ALTIVEC" +{ + rtvec v; + rtx x; + + /* Special handling for LE with -maltivec=be. */ + if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG) + { + v = gen_rtvec (8, GEN_INT (0), GEN_INT (8), GEN_INT (1), GEN_INT (9), + GEN_INT (2), GEN_INT (10), GEN_INT (3), GEN_INT (11)); + x = gen_rtx_VEC_CONCAT (V16HImode, operands[2], operands[1]); + } + else + { + v = gen_rtvec (8, GEN_INT (4), GEN_INT (12), GEN_INT (5), GEN_INT (13), + GEN_INT (6), GEN_INT (14), GEN_INT (7), GEN_INT (15)); + x = gen_rtx_VEC_CONCAT (V16HImode, operands[1], operands[2]); + } + + x = gen_rtx_VEC_SELECT (V8HImode, x, gen_rtx_PARALLEL (VOIDmode, v)); + emit_insn (gen_rtx_SET (VOIDmode, operands[0], x)); + DONE; +}) + +(define_insn "*altivec_vmrglh_internal" [(set (match_operand:V8HI 0 "register_operand" "=v") (vec_select:V8HI (vec_concat:V16HI @@ -908,10 +1149,50 @@ (const_int 6) (const_int 14) (const_int 7) (const_int 15)])))] "TARGET_ALTIVEC" +{ + if (BYTES_BIG_ENDIAN) + return "vmrglh %0,%1,%2"; + else + return "vmrghh %0,%2,%1"; +} + [(set_attr "type" "vecperm")]) + +(define_insn "altivec_vmrglh_direct" + [(set (match_operand:V8HI 0 "register_operand" "=v") + (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") + (match_operand:V8HI 2 "register_operand" "v")] + UNSPEC_VMRGL_DIRECT))] + "TARGET_ALTIVEC" "vmrglh %0,%1,%2" [(set_attr "type" "vecperm")]) -(define_insn "altivec_vmrglw" +(define_expand "altivec_vmrglw" + [(use (match_operand:V4SI 0 "register_operand" "")) + (use (match_operand:V4SI 1 "register_operand" "")) + (use (match_operand:V4SI 2 "register_operand" ""))] + "VECTOR_MEM_ALTIVEC_P (V4SImode)" +{ + rtvec v; + rtx x; + + /* Special handling for LE with -maltivec=be. */ + if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG) + { + v = gen_rtvec (4, GEN_INT (0), GEN_INT (4), GEN_INT (1), GEN_INT (5)); + x = gen_rtx_VEC_CONCAT (V8SImode, operands[2], operands[1]); + } + else + { + v = gen_rtvec (4, GEN_INT (2), GEN_INT (6), GEN_INT (3), GEN_INT (7)); + x = gen_rtx_VEC_CONCAT (V8SImode, operands[1], operands[2]); + } + + x = gen_rtx_VEC_SELECT (V4SImode, x, gen_rtx_PARALLEL (VOIDmode, v)); + emit_insn (gen_rtx_SET (VOIDmode, operands[0], x)); + DONE; +}) + +(define_insn "*altivec_vmrglw_internal" [(set (match_operand:V4SI 0 "register_operand" "=v") (vec_select:V4SI (vec_concat:V8SI @@ -920,6 +1201,20 @@ (parallel [(const_int 2) (const_int 6) (const_int 3) (const_int 7)])))] "VECTOR_MEM_ALTIVEC_P (V4SImode)" +{ + if (BYTES_BIG_ENDIAN) + return "vmrglw %0,%1,%2"; + else + return "vmrghw %0,%2,%1"; +} + [(set_attr "type" "vecperm")]) + +(define_insn "altivec_vmrglw_direct" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") + (match_operand:V4SI 2 "register_operand" "v")] + UNSPEC_VMRGL_DIRECT))] + "TARGET_ALTIVEC" "vmrglw %0,%1,%2" [(set_attr "type" "vecperm")]) @@ -932,10 +1227,154 @@ (parallel [(const_int 2) (const_int 6) (const_int 3) (const_int 7)])))] "VECTOR_MEM_ALTIVEC_P (V4SFmode)" - "vmrglw %0,%1,%2" +{ + if (BYTES_BIG_ENDIAN) + return "vmrglw %0,%1,%2"; + else + return "vmrghw %0,%2,%1"; +} [(set_attr "type" "vecperm")]) -(define_insn "vec_widen_umult_even_v16qi" +;; Power8 vector merge even/odd +(define_insn "p8_vmrgew" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (vec_select:V4SI + (vec_concat:V8SI + (match_operand:V4SI 1 "register_operand" "v") + (match_operand:V4SI 2 "register_operand" "v")) + (parallel [(const_int 0) (const_int 4) + (const_int 2) (const_int 6)])))] + "TARGET_P8_VECTOR" +{ + if (BYTES_BIG_ENDIAN) + return "vmrgew %0,%1,%2"; + else + return "vmrgow %0,%2,%1"; +} + [(set_attr "type" "vecperm")]) + +(define_insn "p8_vmrgow" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (vec_select:V4SI + (vec_concat:V8SI + (match_operand:V4SI 1 "register_operand" "v") + (match_operand:V4SI 2 "register_operand" "v")) + (parallel [(const_int 1) (const_int 5) + (const_int 3) (const_int 7)])))] + "TARGET_P8_VECTOR" +{ + if (BYTES_BIG_ENDIAN) + return "vmrgow %0,%1,%2"; + else + return "vmrgew %0,%2,%1"; +} + [(set_attr "type" "vecperm")]) + +(define_expand "vec_widen_umult_even_v16qi" + [(use (match_operand:V8HI 0 "register_operand" "")) + (use (match_operand:V16QI 1 "register_operand" "")) + (use (match_operand:V16QI 2 "register_operand" ""))] + "TARGET_ALTIVEC" +{ + if (VECTOR_ELT_ORDER_BIG) + emit_insn (gen_altivec_vmuleub (operands[0], operands[1], operands[2])); + else + emit_insn (gen_altivec_vmuloub (operands[0], operands[1], operands[2])); + DONE; +}) + +(define_expand "vec_widen_smult_even_v16qi" + [(use (match_operand:V8HI 0 "register_operand" "")) + (use (match_operand:V16QI 1 "register_operand" "")) + (use (match_operand:V16QI 2 "register_operand" ""))] + "TARGET_ALTIVEC" +{ + if (VECTOR_ELT_ORDER_BIG) + emit_insn (gen_altivec_vmulesb (operands[0], operands[1], operands[2])); + else + emit_insn (gen_altivec_vmulosb (operands[0], operands[1], operands[2])); + DONE; +}) + +(define_expand "vec_widen_umult_even_v8hi" + [(use (match_operand:V4SI 0 "register_operand" "")) + (use (match_operand:V8HI 1 "register_operand" "")) + (use (match_operand:V8HI 2 "register_operand" ""))] + "TARGET_ALTIVEC" +{ + if (VECTOR_ELT_ORDER_BIG) + emit_insn (gen_altivec_vmuleuh (operands[0], operands[1], operands[2])); + else + emit_insn (gen_altivec_vmulouh (operands[0], operands[1], operands[2])); + DONE; +}) + +(define_expand "vec_widen_smult_even_v8hi" + [(use (match_operand:V4SI 0 "register_operand" "")) + (use (match_operand:V8HI 1 "register_operand" "")) + (use (match_operand:V8HI 2 "register_operand" ""))] + "TARGET_ALTIVEC" +{ + if (VECTOR_ELT_ORDER_BIG) + emit_insn (gen_altivec_vmulesh (operands[0], operands[1], operands[2])); + else + emit_insn (gen_altivec_vmulosh (operands[0], operands[1], operands[2])); + DONE; +}) + +(define_expand "vec_widen_umult_odd_v16qi" + [(use (match_operand:V8HI 0 "register_operand" "")) + (use (match_operand:V16QI 1 "register_operand" "")) + (use (match_operand:V16QI 2 "register_operand" ""))] + "TARGET_ALTIVEC" +{ + if (VECTOR_ELT_ORDER_BIG) + emit_insn (gen_altivec_vmuloub (operands[0], operands[1], operands[2])); + else + emit_insn (gen_altivec_vmuleub (operands[0], operands[1], operands[2])); + DONE; +}) + +(define_expand "vec_widen_smult_odd_v16qi" + [(use (match_operand:V8HI 0 "register_operand" "")) + (use (match_operand:V16QI 1 "register_operand" "")) + (use (match_operand:V16QI 2 "register_operand" ""))] + "TARGET_ALTIVEC" +{ + if (VECTOR_ELT_ORDER_BIG) + emit_insn (gen_altivec_vmulosb (operands[0], operands[1], operands[2])); + else + emit_insn (gen_altivec_vmulesb (operands[0], operands[1], operands[2])); + DONE; +}) + +(define_expand "vec_widen_umult_odd_v8hi" + [(use (match_operand:V4SI 0 "register_operand" "")) + (use (match_operand:V8HI 1 "register_operand" "")) + (use (match_operand:V8HI 2 "register_operand" ""))] + "TARGET_ALTIVEC" +{ + if (VECTOR_ELT_ORDER_BIG) + emit_insn (gen_altivec_vmulouh (operands[0], operands[1], operands[2])); + else + emit_insn (gen_altivec_vmuleuh (operands[0], operands[1], operands[2])); + DONE; +}) + +(define_expand "vec_widen_smult_odd_v8hi" + [(use (match_operand:V4SI 0 "register_operand" "")) + (use (match_operand:V8HI 1 "register_operand" "")) + (use (match_operand:V8HI 2 "register_operand" ""))] + "TARGET_ALTIVEC" +{ + if (VECTOR_ELT_ORDER_BIG) + emit_insn (gen_altivec_vmulosh (operands[0], operands[1], operands[2])); + else + emit_insn (gen_altivec_vmulesh (operands[0], operands[1], operands[2])); + DONE; +}) + +(define_insn "altivec_vmuleub" [(set (match_operand:V8HI 0 "register_operand" "=v") (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v") (match_operand:V16QI 2 "register_operand" "v")] @@ -944,43 +1383,25 @@ "vmuleub %0,%1,%2" [(set_attr "type" "veccomplex")]) -(define_insn "vec_widen_smult_even_v16qi" +(define_insn "altivec_vmuloub" [(set (match_operand:V8HI 0 "register_operand" "=v") (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v") (match_operand:V16QI 2 "register_operand" "v")] - UNSPEC_VMULESB))] - "TARGET_ALTIVEC" - "vmulesb %0,%1,%2" - [(set_attr "type" "veccomplex")]) - -(define_insn "vec_widen_umult_even_v8hi" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") - (match_operand:V8HI 2 "register_operand" "v")] - UNSPEC_VMULEUH))] - "TARGET_ALTIVEC" - "vmuleuh %0,%1,%2" - [(set_attr "type" "veccomplex")]) - -(define_insn "vec_widen_smult_even_v8hi" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") - (match_operand:V8HI 2 "register_operand" "v")] - UNSPEC_VMULESH))] + UNSPEC_VMULOUB))] "TARGET_ALTIVEC" - "vmulesh %0,%1,%2" + "vmuloub %0,%1,%2" [(set_attr "type" "veccomplex")]) -(define_insn "vec_widen_umult_odd_v16qi" +(define_insn "altivec_vmulesb" [(set (match_operand:V8HI 0 "register_operand" "=v") (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v") (match_operand:V16QI 2 "register_operand" "v")] - UNSPEC_VMULOUB))] + UNSPEC_VMULESB))] "TARGET_ALTIVEC" - "vmuloub %0,%1,%2" + "vmulesb %0,%1,%2" [(set_attr "type" "veccomplex")]) -(define_insn "vec_widen_smult_odd_v16qi" +(define_insn "altivec_vmulosb" [(set (match_operand:V8HI 0 "register_operand" "=v") (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v") (match_operand:V16QI 2 "register_operand" "v")] @@ -989,7 +1410,16 @@ "vmulosb %0,%1,%2" [(set_attr "type" "veccomplex")]) -(define_insn "vec_widen_umult_odd_v8hi" +(define_insn "altivec_vmuleuh" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") + (match_operand:V8HI 2 "register_operand" "v")] + UNSPEC_VMULEUH))] + "TARGET_ALTIVEC" + "vmuleuh %0,%1,%2" + [(set_attr "type" "veccomplex")]) + +(define_insn "altivec_vmulouh" [(set (match_operand:V4SI 0 "register_operand" "=v") (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") (match_operand:V8HI 2 "register_operand" "v")] @@ -998,158 +1428,121 @@ "vmulouh %0,%1,%2" [(set_attr "type" "veccomplex")]) -(define_insn "vec_widen_smult_odd_v8hi" +(define_insn "altivec_vmulesh" [(set (match_operand:V4SI 0 "register_operand" "=v") (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") (match_operand:V8HI 2 "register_operand" "v")] - UNSPEC_VMULOSH))] + UNSPEC_VMULESH))] "TARGET_ALTIVEC" - "vmulosh %0,%1,%2" + "vmulesh %0,%1,%2" [(set_attr "type" "veccomplex")]) - -;; logical ops. Have the logical ops follow the memory ops in -;; terms of whether to prefer VSX or Altivec - -(define_insn "*altivec_and3" - [(set (match_operand:VM 0 "register_operand" "=v") - (and:VM (match_operand:VM 1 "register_operand" "v") - (match_operand:VM 2 "register_operand" "v")))] - "VECTOR_MEM_ALTIVEC_P (mode)" - "vand %0,%1,%2" - [(set_attr "type" "vecsimple")]) - -(define_insn "*altivec_ior3" - [(set (match_operand:VM 0 "register_operand" "=v") - (ior:VM (match_operand:VM 1 "register_operand" "v") - (match_operand:VM 2 "register_operand" "v")))] - "VECTOR_MEM_ALTIVEC_P (mode)" - "vor %0,%1,%2" - [(set_attr "type" "vecsimple")]) - -(define_insn "*altivec_xor3" - [(set (match_operand:VM 0 "register_operand" "=v") - (xor:VM (match_operand:VM 1 "register_operand" "v") - (match_operand:VM 2 "register_operand" "v")))] - "VECTOR_MEM_ALTIVEC_P (mode)" - "vxor %0,%1,%2" - [(set_attr "type" "vecsimple")]) - -(define_insn "*altivec_one_cmpl2" - [(set (match_operand:VM 0 "register_operand" "=v") - (not:VM (match_operand:VM 1 "register_operand" "v")))] - "VECTOR_MEM_ALTIVEC_P (mode)" - "vnor %0,%1,%1" - [(set_attr "type" "vecsimple")]) - -(define_insn "*altivec_nor3" - [(set (match_operand:VM 0 "register_operand" "=v") - (not:VM (ior:VM (match_operand:VM 1 "register_operand" "v") - (match_operand:VM 2 "register_operand" "v"))))] - "VECTOR_MEM_ALTIVEC_P (mode)" - "vnor %0,%1,%2" - [(set_attr "type" "vecsimple")]) - -(define_insn "*altivec_andc3" - [(set (match_operand:VM 0 "register_operand" "=v") - (and:VM (not:VM (match_operand:VM 2 "register_operand" "v")) - (match_operand:VM 1 "register_operand" "v")))] - "VECTOR_MEM_ALTIVEC_P (mode)" - "vandc %0,%1,%2" - [(set_attr "type" "vecsimple")]) - -(define_insn "altivec_vpkuhum" - [(set (match_operand:V16QI 0 "register_operand" "=v") - (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v") - (match_operand:V8HI 2 "register_operand" "v")] - UNSPEC_VPKUHUM))] +(define_insn "altivec_vmulosh" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") + (match_operand:V8HI 2 "register_operand" "v")] + UNSPEC_VMULOSH))] "TARGET_ALTIVEC" - "vpkuhum %0,%1,%2" - [(set_attr "type" "vecperm")]) + "vmulosh %0,%1,%2" + [(set_attr "type" "veccomplex")]) -(define_insn "altivec_vpkuwum" - [(set (match_operand:V8HI 0 "register_operand" "=v") - (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") - (match_operand:V4SI 2 "register_operand" "v")] - UNSPEC_VPKUWUM))] - "TARGET_ALTIVEC" - "vpkuwum %0,%1,%2" - [(set_attr "type" "vecperm")]) +;; Vector pack/unpack (define_insn "altivec_vpkpx" [(set (match_operand:V8HI 0 "register_operand" "=v") (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") (match_operand:V4SI 2 "register_operand" "v")] UNSPEC_VPKPX))] "TARGET_ALTIVEC" - "vpkpx %0,%1,%2" + "* + { + if (VECTOR_ELT_ORDER_BIG) + return \"vpkpx %0,%1,%2\"; + else + return \"vpkpx %0,%2,%1\"; + }" [(set_attr "type" "vecperm")]) -(define_insn "altivec_vpkshss" - [(set (match_operand:V16QI 0 "register_operand" "=v") - (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v") - (match_operand:V8HI 2 "register_operand" "v")] - UNSPEC_VPKSHSS)) - (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] - "TARGET_ALTIVEC" - "vpkshss %0,%1,%2" +(define_insn "altivec_vpksss" + [(set (match_operand: 0 "register_operand" "=v") + (unspec: [(match_operand:VP 1 "register_operand" "v") + (match_operand:VP 2 "register_operand" "v")] + UNSPEC_VPACK_SIGN_SIGN_SAT))] + "" + "* + { + if (VECTOR_ELT_ORDER_BIG) + return \"vpksss %0,%1,%2\"; + else + return \"vpksss %0,%2,%1\"; + }" [(set_attr "type" "vecperm")]) -(define_insn "altivec_vpkswss" - [(set (match_operand:V8HI 0 "register_operand" "=v") - (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") - (match_operand:V4SI 2 "register_operand" "v")] - UNSPEC_VPKSWSS)) - (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] - "TARGET_ALTIVEC" - "vpkswss %0,%1,%2" +(define_insn "altivec_vpksus" + [(set (match_operand: 0 "register_operand" "=v") + (unspec: [(match_operand:VP 1 "register_operand" "v") + (match_operand:VP 2 "register_operand" "v")] + UNSPEC_VPACK_SIGN_UNS_SAT))] + "" + "* + { + if (VECTOR_ELT_ORDER_BIG) + return \"vpksus %0,%1,%2\"; + else + return \"vpksus %0,%2,%1\"; + }" [(set_attr "type" "vecperm")]) -(define_insn "altivec_vpkuhus" - [(set (match_operand:V16QI 0 "register_operand" "=v") - (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v") - (match_operand:V8HI 2 "register_operand" "v")] - UNSPEC_VPKUHUS)) - (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] - "TARGET_ALTIVEC" - "vpkuhus %0,%1,%2" +(define_insn "altivec_vpkuus" + [(set (match_operand: 0 "register_operand" "=v") + (unspec: [(match_operand:VP 1 "register_operand" "v") + (match_operand:VP 2 "register_operand" "v")] + UNSPEC_VPACK_UNS_UNS_SAT))] + "" + "* + { + if (VECTOR_ELT_ORDER_BIG) + return \"vpkuus %0,%1,%2\"; + else + return \"vpkuus %0,%2,%1\"; + }" [(set_attr "type" "vecperm")]) -(define_insn "altivec_vpkshus" - [(set (match_operand:V16QI 0 "register_operand" "=v") - (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v") - (match_operand:V8HI 2 "register_operand" "v")] - UNSPEC_VPKSHUS)) - (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] - "TARGET_ALTIVEC" - "vpkshus %0,%1,%2" +(define_insn "altivec_vpkuum" + [(set (match_operand: 0 "register_operand" "=v") + (unspec: [(match_operand:VP 1 "register_operand" "v") + (match_operand:VP 2 "register_operand" "v")] + UNSPEC_VPACK_UNS_UNS_MOD))] + "" + "* + { + if (VECTOR_ELT_ORDER_BIG) + return \"vpkuum %0,%1,%2\"; + else + return \"vpkuum %0,%2,%1\"; + }" [(set_attr "type" "vecperm")]) -(define_insn "altivec_vpkuwus" - [(set (match_operand:V8HI 0 "register_operand" "=v") - (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") - (match_operand:V4SI 2 "register_operand" "v")] - UNSPEC_VPKUWUS)) - (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] - "TARGET_ALTIVEC" - "vpkuwus %0,%1,%2" - [(set_attr "type" "vecperm")]) - -(define_insn "altivec_vpkswus" - [(set (match_operand:V8HI 0 "register_operand" "=v") - (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") - (match_operand:V4SI 2 "register_operand" "v")] - UNSPEC_VPKSWUS)) - (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] - "TARGET_ALTIVEC" - "vpkswus %0,%1,%2" +(define_insn "altivec_vpkuum_direct" + [(set (match_operand: 0 "register_operand" "=v") + (unspec: [(match_operand:VP 1 "register_operand" "v") + (match_operand:VP 2 "register_operand" "v")] + UNSPEC_VPACK_UNS_UNS_MOD_DIRECT))] + "" + "* + { + if (BYTES_BIG_ENDIAN) + return \"vpkuum %0,%1,%2\"; + else + return \"vpkuum %0,%2,%1\"; + }" [(set_attr "type" "vecperm")]) (define_insn "*altivec_vrl" - [(set (match_operand:VI 0 "register_operand" "=v") - (rotate:VI (match_operand:VI 1 "register_operand" "v") - (match_operand:VI 2 "register_operand" "v")))] - "TARGET_ALTIVEC" + [(set (match_operand:VI2 0 "register_operand" "=v") + (rotate:VI2 (match_operand:VI2 1 "register_operand" "v") + (match_operand:VI2 2 "register_operand" "v")))] + "" "vrl %0,%1,%2" [(set_attr "type" "vecsimple")]) @@ -1172,26 +1565,26 @@ [(set_attr "type" "vecperm")]) (define_insn "*altivec_vsl" - [(set (match_operand:VI 0 "register_operand" "=v") - (ashift:VI (match_operand:VI 1 "register_operand" "v") - (match_operand:VI 2 "register_operand" "v")))] - "TARGET_ALTIVEC" + [(set (match_operand:VI2 0 "register_operand" "=v") + (ashift:VI2 (match_operand:VI2 1 "register_operand" "v") + (match_operand:VI2 2 "register_operand" "v")))] + "" "vsl %0,%1,%2" [(set_attr "type" "vecsimple")]) (define_insn "*altivec_vsr" - [(set (match_operand:VI 0 "register_operand" "=v") - (lshiftrt:VI (match_operand:VI 1 "register_operand" "v") - (match_operand:VI 2 "register_operand" "v")))] - "TARGET_ALTIVEC" + [(set (match_operand:VI2 0 "register_operand" "=v") + (lshiftrt:VI2 (match_operand:VI2 1 "register_operand" "v") + (match_operand:VI2 2 "register_operand" "v")))] + "" "vsr %0,%1,%2" [(set_attr "type" "vecsimple")]) (define_insn "*altivec_vsra" - [(set (match_operand:VI 0 "register_operand" "=v") - (ashiftrt:VI (match_operand:VI 1 "register_operand" "v") - (match_operand:VI 2 "register_operand" "v")))] - "TARGET_ALTIVEC" + [(set (match_operand:VI2 0 "register_operand" "=v") + (ashiftrt:VI2 (match_operand:VI2 1 "register_operand" "v") + (match_operand:VI2 2 "register_operand" "v")))] + "" "vsra %0,%1,%2" [(set_attr "type" "vecsimple")]) @@ -1233,64 +1626,242 @@ "vsum4ss %0,%1,%2" [(set_attr "type" "veccomplex")]) +;; FIXME: For the following two patterns, the scratch should only be +;; allocated for !VECTOR_ELT_ORDER_BIG, and the instructions should +;; be emitted separately. (define_insn "altivec_vsum2sws" [(set (match_operand:V4SI 0 "register_operand" "=v") (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") (match_operand:V4SI 2 "register_operand" "v")] UNSPEC_VSUM2SWS)) - (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] + (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR)) + (clobber (match_scratch:V4SI 3 "=v"))] "TARGET_ALTIVEC" - "vsum2sws %0,%1,%2" - [(set_attr "type" "veccomplex")]) +{ + if (VECTOR_ELT_ORDER_BIG) + return "vsum2sws %0,%1,%2"; + else + return "vsldoi %3,%2,%2,12\n\tvsum2sws %3,%1,%3\n\tvsldoi %0,%3,%3,4"; +} + [(set_attr "type" "veccomplex") + (set (attr "length") + (if_then_else + (match_test "VECTOR_ELT_ORDER_BIG") + (const_string "4") + (const_string "12")))]) (define_insn "altivec_vsumsws" [(set (match_operand:V4SI 0 "register_operand" "=v") (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") (match_operand:V4SI 2 "register_operand" "v")] UNSPEC_VSUMSWS)) + (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR)) + (clobber (match_scratch:V4SI 3 "=v"))] + "TARGET_ALTIVEC" +{ + if (VECTOR_ELT_ORDER_BIG) + return "vsumsws %0,%1,%2"; + else + return "vspltw %3,%2,0\n\tvsumsws %3,%1,%3\n\tvsldoi %0,%3,%3,12"; +} + [(set_attr "type" "veccomplex") + (set (attr "length") + (if_then_else + (match_test "(VECTOR_ELT_ORDER_BIG)") + (const_string "4") + (const_string "12")))]) + +(define_insn "altivec_vsumsws_direct" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") + (match_operand:V4SI 2 "register_operand" "v")] + UNSPEC_VSUMSWS_DIRECT)) (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] "TARGET_ALTIVEC" "vsumsws %0,%1,%2" [(set_attr "type" "veccomplex")]) -(define_insn "altivec_vspltb" +(define_expand "altivec_vspltb" + [(use (match_operand:V16QI 0 "register_operand" "")) + (use (match_operand:V16QI 1 "register_operand" "")) + (use (match_operand:QI 2 "u5bit_cint_operand" ""))] + "TARGET_ALTIVEC" +{ + rtvec v; + rtx x; + + /* Special handling for LE with -maltivec=be. We have to reflect + the actual selected index for the splat in the RTL. */ + if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG) + operands[2] = GEN_INT (15 - INTVAL (operands[2])); + + v = gen_rtvec (1, operands[2]); + x = gen_rtx_VEC_SELECT (QImode, operands[1], gen_rtx_PARALLEL (VOIDmode, v)); + x = gen_rtx_VEC_DUPLICATE (V16QImode, x); + emit_insn (gen_rtx_SET (VOIDmode, operands[0], x)); + DONE; +}) + +(define_insn "*altivec_vspltb_internal" [(set (match_operand:V16QI 0 "register_operand" "=v") (vec_duplicate:V16QI (vec_select:QI (match_operand:V16QI 1 "register_operand" "v") (parallel [(match_operand:QI 2 "u5bit_cint_operand" "")]))))] "TARGET_ALTIVEC" +{ + /* For true LE, this adjusts the selected index. For LE with + -maltivec=be, this reverses what was done in the define_expand + because the instruction already has big-endian bias. */ + if (!BYTES_BIG_ENDIAN) + operands[2] = GEN_INT (15 - INTVAL (operands[2])); + + return "vspltb %0,%1,%2"; +} + [(set_attr "type" "vecperm")]) + +(define_insn "altivec_vspltb_direct" + [(set (match_operand:V16QI 0 "register_operand" "=v") + (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") + (match_operand:QI 2 "u5bit_cint_operand" "i")] + UNSPEC_VSPLT_DIRECT))] + "TARGET_ALTIVEC" "vspltb %0,%1,%2" [(set_attr "type" "vecperm")]) -(define_insn "altivec_vsplth" +(define_expand "altivec_vsplth" + [(use (match_operand:V8HI 0 "register_operand" "")) + (use (match_operand:V8HI 1 "register_operand" "")) + (use (match_operand:QI 2 "u5bit_cint_operand" ""))] + "TARGET_ALTIVEC" +{ + rtvec v; + rtx x; + + /* Special handling for LE with -maltivec=be. We have to reflect + the actual selected index for the splat in the RTL. */ + if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG) + operands[2] = GEN_INT (7 - INTVAL (operands[2])); + + v = gen_rtvec (1, operands[2]); + x = gen_rtx_VEC_SELECT (HImode, operands[1], gen_rtx_PARALLEL (VOIDmode, v)); + x = gen_rtx_VEC_DUPLICATE (V8HImode, x); + emit_insn (gen_rtx_SET (VOIDmode, operands[0], x)); + DONE; +}) + +(define_insn "*altivec_vsplth_internal" [(set (match_operand:V8HI 0 "register_operand" "=v") (vec_duplicate:V8HI (vec_select:HI (match_operand:V8HI 1 "register_operand" "v") (parallel [(match_operand:QI 2 "u5bit_cint_operand" "")]))))] "TARGET_ALTIVEC" +{ + /* For true LE, this adjusts the selected index. For LE with + -maltivec=be, this reverses what was done in the define_expand + because the instruction already has big-endian bias. */ + if (!BYTES_BIG_ENDIAN) + operands[2] = GEN_INT (7 - INTVAL (operands[2])); + + return "vsplth %0,%1,%2"; +} + [(set_attr "type" "vecperm")]) + +(define_insn "altivec_vsplth_direct" + [(set (match_operand:V8HI 0 "register_operand" "=v") + (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") + (match_operand:QI 2 "u5bit_cint_operand" "i")] + UNSPEC_VSPLT_DIRECT))] + "TARGET_ALTIVEC" "vsplth %0,%1,%2" [(set_attr "type" "vecperm")]) -(define_insn "altivec_vspltw" +(define_expand "altivec_vspltw" + [(use (match_operand:V4SI 0 "register_operand" "")) + (use (match_operand:V4SI 1 "register_operand" "")) + (use (match_operand:QI 2 "u5bit_cint_operand" ""))] + "TARGET_ALTIVEC" +{ + rtvec v; + rtx x; + + /* Special handling for LE with -maltivec=be. We have to reflect + the actual selected index for the splat in the RTL. */ + if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG) + operands[2] = GEN_INT (3 - INTVAL (operands[2])); + + v = gen_rtvec (1, operands[2]); + x = gen_rtx_VEC_SELECT (SImode, operands[1], gen_rtx_PARALLEL (VOIDmode, v)); + x = gen_rtx_VEC_DUPLICATE (V4SImode, x); + emit_insn (gen_rtx_SET (VOIDmode, operands[0], x)); + DONE; +}) + +(define_insn "*altivec_vspltw_internal" [(set (match_operand:V4SI 0 "register_operand" "=v") (vec_duplicate:V4SI (vec_select:SI (match_operand:V4SI 1 "register_operand" "v") (parallel [(match_operand:QI 2 "u5bit_cint_operand" "i")]))))] "TARGET_ALTIVEC" +{ + /* For true LE, this adjusts the selected index. For LE with + -maltivec=be, this reverses what was done in the define_expand + because the instruction already has big-endian bias. */ + if (!BYTES_BIG_ENDIAN) + operands[2] = GEN_INT (3 - INTVAL (operands[2])); + + return "vspltw %0,%1,%2"; +} + [(set_attr "type" "vecperm")]) + +(define_insn "altivec_vspltw_direct" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") + (match_operand:QI 2 "u5bit_cint_operand" "i")] + UNSPEC_VSPLT_DIRECT))] + "TARGET_ALTIVEC" "vspltw %0,%1,%2" [(set_attr "type" "vecperm")]) -(define_insn "altivec_vspltsf" +(define_expand "altivec_vspltsf" + [(use (match_operand:V4SF 0 "register_operand" "")) + (use (match_operand:V4SF 1 "register_operand" "")) + (use (match_operand:QI 2 "u5bit_cint_operand" ""))] + "TARGET_ALTIVEC" +{ + rtvec v; + rtx x; + + /* Special handling for LE with -maltivec=be. We have to reflect + the actual selected index for the splat in the RTL. */ + if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG) + operands[2] = GEN_INT (3 - INTVAL (operands[2])); + + v = gen_rtvec (1, operands[2]); + x = gen_rtx_VEC_SELECT (SFmode, operands[1], gen_rtx_PARALLEL (VOIDmode, v)); + x = gen_rtx_VEC_DUPLICATE (V4SFmode, x); + emit_insn (gen_rtx_SET (VOIDmode, operands[0], x)); + DONE; +}) + +(define_insn "*altivec_vspltsf_internal" [(set (match_operand:V4SF 0 "register_operand" "=v") (vec_duplicate:V4SF (vec_select:SF (match_operand:V4SF 1 "register_operand" "v") (parallel [(match_operand:QI 2 "u5bit_cint_operand" "i")]))))] "VECTOR_UNIT_ALTIVEC_P (V4SFmode)" - "vspltw %0,%1,%2" +{ + /* For true LE, this adjusts the selected index. For LE with + -maltivec=be, this reverses what was done in the define_expand + because the instruction already has big-endian bias. */ + if (!BYTES_BIG_ENDIAN) + operands[2] = GEN_INT (3 - INTVAL (operands[2])); + + return "vspltw %0,%1,%2"; +} [(set_attr "type" "vecperm")]) (define_insn "altivec_vspltis" @@ -1308,7 +1879,22 @@ "vrfiz %0,%1" [(set_attr "type" "vecfloat")]) -(define_insn "altivec_vperm_" +(define_expand "altivec_vperm_" + [(set (match_operand:VM 0 "register_operand" "=v") + (unspec:VM [(match_operand:VM 1 "register_operand" "v") + (match_operand:VM 2 "register_operand" "v") + (match_operand:V16QI 3 "register_operand" "v")] + UNSPEC_VPERM))] + "TARGET_ALTIVEC" +{ + if (!VECTOR_ELT_ORDER_BIG) + { + altivec_expand_vec_perm_le (operands); + DONE; + } +}) + +(define_insn "*altivec_vperm__internal" [(set (match_operand:VM 0 "register_operand" "=v") (unspec:VM [(match_operand:VM 1 "register_operand" "v") (match_operand:VM 2 "register_operand" "v") @@ -1318,7 +1904,22 @@ "vperm %0,%1,%2,%3" [(set_attr "type" "vecperm")]) -(define_insn "altivec_vperm__uns" +(define_expand "altivec_vperm__uns" + [(set (match_operand:VM 0 "register_operand" "=v") + (unspec:VM [(match_operand:VM 1 "register_operand" "v") + (match_operand:VM 2 "register_operand" "v") + (match_operand:V16QI 3 "register_operand" "v")] + UNSPEC_VPERM_UNS))] + "TARGET_ALTIVEC" +{ + if (!VECTOR_ELT_ORDER_BIG) + { + altivec_expand_vec_perm_le (operands); + DONE; + } +}) + +(define_insn "*altivec_vperm__uns_internal" [(set (match_operand:VM 0 "register_operand" "=v") (unspec:VM [(match_operand:VM 1 "register_operand" "v") (match_operand:VM 2 "register_operand" "v") @@ -1335,7 +1936,12 @@ (match_operand:V16QI 3 "register_operand" "")] UNSPEC_VPERM))] "TARGET_ALTIVEC" - "") +{ + if (!BYTES_BIG_ENDIAN) { + altivec_expand_vec_perm_le (operands); + DONE; + } +}) (define_expand "vec_perm_constv16qi" [(match_operand:V16QI 0 "register_operand" "") @@ -1471,94 +2077,114 @@ (unspec:VM [(match_operand:VM 1 "register_operand" "v") (match_operand:VM 2 "register_operand" "v") (match_operand:QI 3 "immediate_operand" "i")] - UNSPEC_VLSDOI))] + UNSPEC_VSLDOI))] "TARGET_ALTIVEC" "vsldoi %0,%1,%2,%3" [(set_attr "type" "vecperm")]) -(define_insn "altivec_vupkhsb" - [(set (match_operand:V8HI 0 "register_operand" "=v") - (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")] - UNSPEC_VUPKHSB))] - "TARGET_ALTIVEC" - "vupkhsb %0,%1" +(define_insn "altivec_vupkhs" + [(set (match_operand:VP 0 "register_operand" "=v") + (unspec:VP [(match_operand: 1 "register_operand" "v")] + UNSPEC_VUNPACK_HI_SIGN))] + "" +{ + if (VECTOR_ELT_ORDER_BIG) + return "vupkhs %0,%1"; + else + return "vupkls %0,%1"; +} [(set_attr "type" "vecperm")]) -(define_insn "altivec_vupkhpx" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] - UNSPEC_VUPKHPX))] - "TARGET_ALTIVEC" - "vupkhpx %0,%1" +(define_insn "*altivec_vupkhs_direct" + [(set (match_operand:VP 0 "register_operand" "=v") + (unspec:VP [(match_operand: 1 "register_operand" "v")] + UNSPEC_VUNPACK_HI_SIGN_DIRECT))] + "" + "vupkhs %0,%1" [(set_attr "type" "vecperm")]) -(define_insn "altivec_vupkhsh" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] - UNSPEC_VUPKHSH))] - "TARGET_ALTIVEC" - "vupkhsh %0,%1" +(define_insn "altivec_vupkls" + [(set (match_operand:VP 0 "register_operand" "=v") + (unspec:VP [(match_operand: 1 "register_operand" "v")] + UNSPEC_VUNPACK_LO_SIGN))] + "" +{ + if (VECTOR_ELT_ORDER_BIG) + return "vupkls %0,%1"; + else + return "vupkhs %0,%1"; +} [(set_attr "type" "vecperm")]) -(define_insn "altivec_vupklsb" - [(set (match_operand:V8HI 0 "register_operand" "=v") - (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")] - UNSPEC_VUPKLSB))] - "TARGET_ALTIVEC" - "vupklsb %0,%1" +(define_insn "*altivec_vupkls_direct" + [(set (match_operand:VP 0 "register_operand" "=v") + (unspec:VP [(match_operand: 1 "register_operand" "v")] + UNSPEC_VUNPACK_LO_SIGN_DIRECT))] + "" + "vupkls %0,%1" [(set_attr "type" "vecperm")]) -(define_insn "altivec_vupklpx" +(define_insn "altivec_vupkhpx" [(set (match_operand:V4SI 0 "register_operand" "=v") (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] - UNSPEC_VUPKLPX))] + UNSPEC_VUPKHPX))] "TARGET_ALTIVEC" - "vupklpx %0,%1" +{ + if (VECTOR_ELT_ORDER_BIG) + return "vupkhpx %0,%1"; + else + return "vupklpx %0,%1"; +} [(set_attr "type" "vecperm")]) -(define_insn "altivec_vupklsh" +(define_insn "altivec_vupklpx" [(set (match_operand:V4SI 0 "register_operand" "=v") (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] - UNSPEC_VUPKLSH))] + UNSPEC_VUPKLPX))] "TARGET_ALTIVEC" - "vupklsh %0,%1" +{ + if (VECTOR_ELT_ORDER_BIG) + return "vupklpx %0,%1"; + else + return "vupkhpx %0,%1"; +} [(set_attr "type" "vecperm")]) ;; Compare vectors producing a vector result and a predicate, setting CR6 to ;; indicate a combined status (define_insn "*altivec_vcmpequ_p" [(set (reg:CC 74) - (unspec:CC [(eq:CC (match_operand:VI 1 "register_operand" "v") - (match_operand:VI 2 "register_operand" "v"))] + (unspec:CC [(eq:CC (match_operand:VI2 1 "register_operand" "v") + (match_operand:VI2 2 "register_operand" "v"))] UNSPEC_PREDICATE)) - (set (match_operand:VI 0 "register_operand" "=v") - (eq:VI (match_dup 1) - (match_dup 2)))] - "VECTOR_UNIT_ALTIVEC_P (mode)" + (set (match_operand:VI2 0 "register_operand" "=v") + (eq:VI2 (match_dup 1) + (match_dup 2)))] + "" "vcmpequ. %0,%1,%2" [(set_attr "type" "veccmp")]) (define_insn "*altivec_vcmpgts_p" [(set (reg:CC 74) - (unspec:CC [(gt:CC (match_operand:VI 1 "register_operand" "v") - (match_operand:VI 2 "register_operand" "v"))] + (unspec:CC [(gt:CC (match_operand:VI2 1 "register_operand" "v") + (match_operand:VI2 2 "register_operand" "v"))] UNSPEC_PREDICATE)) - (set (match_operand:VI 0 "register_operand" "=v") - (gt:VI (match_dup 1) - (match_dup 2)))] - "VECTOR_UNIT_ALTIVEC_P (mode)" + (set (match_operand:VI2 0 "register_operand" "=v") + (gt:VI2 (match_dup 1) + (match_dup 2)))] + "" "vcmpgts. %0,%1,%2" [(set_attr "type" "veccmp")]) (define_insn "*altivec_vcmpgtu_p" [(set (reg:CC 74) - (unspec:CC [(gtu:CC (match_operand:VI 1 "register_operand" "v") - (match_operand:VI 2 "register_operand" "v"))] + (unspec:CC [(gtu:CC (match_operand:VI2 1 "register_operand" "v") + (match_operand:VI2 2 "register_operand" "v"))] UNSPEC_PREDICATE)) - (set (match_operand:VI 0 "register_operand" "=v") - (gtu:VI (match_dup 1) - (match_dup 2)))] - "VECTOR_UNIT_ALTIVEC_P (mode)" + (set (match_operand:VI2 0 "register_operand" "=v") + (gtu:VI2 (match_dup 1) + (match_dup 2)))] + "" "vcmpgtu. %0,%1,%2" [(set_attr "type" "veccmp")]) @@ -1671,7 +2297,31 @@ "dststt %0,%1,%2" [(set_attr "type" "vecsimple")]) -(define_insn "altivec_lvsl" +(define_expand "altivec_lvsl" + [(use (match_operand:V16QI 0 "register_operand" "")) + (use (match_operand:V16QI 1 "memory_operand" ""))] + "TARGET_ALTIVEC" +{ + if (VECTOR_ELT_ORDER_BIG) + emit_insn (gen_altivec_lvsl_direct (operands[0], operands[1])); + else + { + int i; + rtx mask, perm[16], constv, vperm; + mask = gen_reg_rtx (V16QImode); + emit_insn (gen_altivec_lvsl_direct (mask, operands[1])); + for (i = 0; i < 16; ++i) + perm[i] = GEN_INT (i); + constv = gen_rtx_CONST_VECTOR (V16QImode, gen_rtvec_v (16, perm)); + constv = force_reg (V16QImode, constv); + vperm = gen_rtx_UNSPEC (V16QImode, gen_rtvec (3, mask, mask, constv), + UNSPEC_VPERM); + emit_insn (gen_rtx_SET (VOIDmode, operands[0], vperm)); + } + DONE; +}) + +(define_insn "altivec_lvsl_direct" [(set (match_operand:V16QI 0 "register_operand" "=v") (unspec:V16QI [(match_operand:V16QI 1 "memory_operand" "Z")] UNSPEC_LVSL))] @@ -1679,7 +2329,31 @@ "lvsl %0,%y1" [(set_attr "type" "vecload")]) -(define_insn "altivec_lvsr" +(define_expand "altivec_lvsr" + [(use (match_operand:V16QI 0 "register_operand" "")) + (use (match_operand:V16QI 1 "memory_operand" ""))] + "TARGET_ALTIVEC" +{ + if (VECTOR_ELT_ORDER_BIG) + emit_insn (gen_altivec_lvsr_direct (operands[0], operands[1])); + else + { + int i; + rtx mask, perm[16], constv, vperm; + mask = gen_reg_rtx (V16QImode); + emit_insn (gen_altivec_lvsr_direct (mask, operands[1])); + for (i = 0; i < 16; ++i) + perm[i] = GEN_INT (i); + constv = gen_rtx_CONST_VECTOR (V16QImode, gen_rtvec_v (16, perm)); + constv = force_reg (V16QImode, constv); + vperm = gen_rtx_UNSPEC (V16QImode, gen_rtvec (3, mask, mask, constv), + UNSPEC_VPERM); + emit_insn (gen_rtx_SET (VOIDmode, operands[0], vperm)); + } + DONE; +}) + +(define_insn "altivec_lvsr_direct" [(set (match_operand:V16QI 0 "register_operand" "=v") (unspec:V16QI [(match_operand:V16QI 1 "memory_operand" "Z")] UNSPEC_LVSR))] @@ -1710,7 +2384,21 @@ ;; Parallel some of the LVE* and STV*'s with unspecs because some have ;; identical rtl but different instructions-- and gcc gets confused. -(define_insn "altivec_lvex" +(define_expand "altivec_lvex" + [(parallel + [(set (match_operand:VI 0 "register_operand" "=v") + (match_operand:VI 1 "memory_operand" "Z")) + (unspec [(const_int 0)] UNSPEC_LVE)])] + "TARGET_ALTIVEC" +{ + if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG) + { + altivec_expand_lvx_be (operands[0], operands[1], mode, UNSPEC_LVE); + DONE; + } +}) + +(define_insn "*altivec_lvex_internal" [(parallel [(set (match_operand:VI 0 "register_operand" "=v") (match_operand:VI 1 "memory_operand" "Z")) @@ -1728,16 +2416,44 @@ "lvewx %0,%y1" [(set_attr "type" "vecload")]) -(define_insn "altivec_lvxl" +(define_expand "altivec_lvxl_" + [(parallel + [(set (match_operand:VM2 0 "register_operand" "=v") + (match_operand:VM2 1 "memory_operand" "Z")) + (unspec [(const_int 0)] UNSPEC_SET_VSCR)])] + "TARGET_ALTIVEC" +{ + if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG) + { + altivec_expand_lvx_be (operands[0], operands[1], mode, UNSPEC_SET_VSCR); + DONE; + } +}) + +(define_insn "*altivec_lvxl__internal" [(parallel - [(set (match_operand:V4SI 0 "register_operand" "=v") - (match_operand:V4SI 1 "memory_operand" "Z")) + [(set (match_operand:VM2 0 "register_operand" "=v") + (match_operand:VM2 1 "memory_operand" "Z")) (unspec [(const_int 0)] UNSPEC_SET_VSCR)])] "TARGET_ALTIVEC" - "lvxl %0,%y1" + "lvx %0,%y1" [(set_attr "type" "vecload")]) -(define_insn "altivec_lvx_" +(define_expand "altivec_lvx_" + [(parallel + [(set (match_operand:VM2 0 "register_operand" "=v") + (match_operand:VM2 1 "memory_operand" "Z")) + (unspec [(const_int 0)] UNSPEC_LVX)])] + "TARGET_ALTIVEC" +{ + if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG) + { + altivec_expand_lvx_be (operands[0], operands[1], mode, UNSPEC_LVX); + DONE; + } +}) + +(define_insn "altivec_lvx__internal" [(parallel [(set (match_operand:VM2 0 "register_operand" "=v") (match_operand:VM2 1 "memory_operand" "Z")) @@ -1746,7 +2462,21 @@ "lvx %0,%y1" [(set_attr "type" "vecload")]) -(define_insn "altivec_stvx_" +(define_expand "altivec_stvx_" + [(parallel + [(set (match_operand:VM2 0 "memory_operand" "=Z") + (match_operand:VM2 1 "register_operand" "v")) + (unspec [(const_int 0)] UNSPEC_STVX)])] + "TARGET_ALTIVEC" +{ + if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG) + { + altivec_expand_stvx_be (operands[0], operands[1], mode, UNSPEC_STVX); + DONE; + } +}) + +(define_insn "altivec_stvx__internal" [(parallel [(set (match_operand:VM2 0 "memory_operand" "=Z") (match_operand:VM2 1 "register_operand" "v")) @@ -1755,16 +2485,42 @@ "stvx %1,%y0" [(set_attr "type" "vecstore")]) -(define_insn "altivec_stvxl" +(define_expand "altivec_stvxl_" + [(parallel + [(set (match_operand:VM2 0 "memory_operand" "=Z") + (match_operand:VM2 1 "register_operand" "v")) + (unspec [(const_int 0)] UNSPEC_STVXL)])] + "TARGET_ALTIVEC" +{ + if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG) + { + altivec_expand_stvx_be (operands[0], operands[1], mode, UNSPEC_STVXL); + DONE; + } +}) + +(define_insn "*altivec_stvxl__internal" [(parallel - [(set (match_operand:V4SI 0 "memory_operand" "=Z") - (match_operand:V4SI 1 "register_operand" "v")) + [(set (match_operand:VM2 0 "memory_operand" "=Z") + (match_operand:VM2 1 "register_operand" "v")) (unspec [(const_int 0)] UNSPEC_STVXL)])] "TARGET_ALTIVEC" "stvxl %1,%y0" [(set_attr "type" "vecstore")]) -(define_insn "altivec_stvex" +(define_expand "altivec_stvex" + [(set (match_operand: 0 "memory_operand" "=Z") + (unspec: [(match_operand:VI 1 "register_operand" "v")] UNSPEC_STVE))] + "TARGET_ALTIVEC" +{ + if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG) + { + altivec_expand_stvex_be (operands[0], operands[1], mode, UNSPEC_STVE); + DONE; + } +}) + +(define_insn "*altivec_stvex_internal" [(set (match_operand: 0 "memory_operand" "=Z") (unspec: [(match_operand:VI 1 "register_operand" "v")] UNSPEC_STVE))] "TARGET_ALTIVEC" @@ -1779,20 +2535,28 @@ [(set_attr "type" "vecstore")]) ;; Generate -;; vspltis? SCRATCH0,0 +;; xxlxor/vxor SCRATCH0,SCRATCH0,SCRATCH0 ;; vsubu?m SCRATCH2,SCRATCH1,%1 ;; vmaxs? %0,%1,SCRATCH2" (define_expand "abs2" - [(set (match_dup 2) (vec_duplicate:VI (const_int 0))) - (set (match_dup 3) - (minus:VI (match_dup 2) - (match_operand:VI 1 "register_operand" "v"))) - (set (match_operand:VI 0 "register_operand" "=v") - (smax:VI (match_dup 1) (match_dup 3)))] - "TARGET_ALTIVEC" + [(set (match_dup 2) (match_dup 3)) + (set (match_dup 4) + (minus:VI2 (match_dup 2) + (match_operand:VI2 1 "register_operand" "v"))) + (set (match_operand:VI2 0 "register_operand" "=v") + (smax:VI2 (match_dup 1) (match_dup 4)))] + "" { - operands[2] = gen_reg_rtx (GET_MODE (operands[0])); - operands[3] = gen_reg_rtx (GET_MODE (operands[0])); + int i, n_elt = GET_MODE_NUNITS (mode); + rtvec v = rtvec_alloc (n_elt); + + /* Create an all 0 constant. */ + for (i = 0; i < n_elt; ++i) + RTVEC_ELT (v, i) = const0_rtx; + + operands[2] = gen_reg_rtx (mode); + operands[3] = gen_rtx_CONST_VECTOR (mode, v); + operands[4] = gen_reg_rtx (mode); }) ;; Generate @@ -1844,7 +2608,7 @@ emit_insn (gen_altivec_vspltisw (vzero, const0_rtx)); emit_insn (gen_altivec_vsum4ss (vtmp1, operands[1], vzero)); - emit_insn (gen_altivec_vsumsws (dest, vtmp1, vzero)); + emit_insn (gen_altivec_vsumsws_direct (dest, vtmp1, vzero)); DONE; }) @@ -1860,7 +2624,7 @@ emit_insn (gen_altivec_vspltisw (vzero, const0_rtx)); emit_insn (gen_altivec_vsum4ubs (vtmp1, operands[1], vzero)); - emit_insn (gen_altivec_vsumsws (dest, vtmp1, vzero)); + emit_insn (gen_altivec_vsumsws_direct (dest, vtmp1, vzero)); DONE; }) @@ -1950,49 +2714,19 @@ DONE; }") -(define_expand "vec_unpacks_hi_v16qi" - [(set (match_operand:V8HI 0 "register_operand" "=v") - (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")] - UNSPEC_VUPKHSB))] - "TARGET_ALTIVEC" - " -{ - emit_insn (gen_altivec_vupkhsb (operands[0], operands[1])); - DONE; -}") - -(define_expand "vec_unpacks_hi_v8hi" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] - UNSPEC_VUPKHSH))] - "TARGET_ALTIVEC" - " -{ - emit_insn (gen_altivec_vupkhsh (operands[0], operands[1])); - DONE; -}") - -(define_expand "vec_unpacks_lo_v16qi" - [(set (match_operand:V8HI 0 "register_operand" "=v") - (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")] - UNSPEC_VUPKLSB))] - "TARGET_ALTIVEC" - " -{ - emit_insn (gen_altivec_vupklsb (operands[0], operands[1])); - DONE; -}") +(define_expand "vec_unpacks_hi_" + [(set (match_operand:VP 0 "register_operand" "=v") + (unspec:VP [(match_operand: 1 "register_operand" "v")] + UNSPEC_VUNPACK_HI_SIGN_DIRECT))] + "" + "") -(define_expand "vec_unpacks_lo_v8hi" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] - UNSPEC_VUPKLSH))] - "TARGET_ALTIVEC" - " -{ - emit_insn (gen_altivec_vupklsh (operands[0], operands[1])); - DONE; -}") +(define_expand "vec_unpacks_lo_" + [(set (match_operand:VP 0 "register_operand" "=v") + (unspec:VP [(match_operand: 1 "register_operand" "v")] + UNSPEC_VUNPACK_LO_SIGN_DIRECT))] + "" + "") (define_insn "vperm_v8hiv4si" [(set (match_operand:V4SI 0 "register_operand" "=v") @@ -2025,25 +2759,26 @@ rtx vzero = gen_reg_rtx (V8HImode); rtx mask = gen_reg_rtx (V16QImode); rtvec v = rtvec_alloc (16); + bool be = BYTES_BIG_ENDIAN; emit_insn (gen_altivec_vspltish (vzero, const0_rtx)); - RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 16); - RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 0); - RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 16); - RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 1); - RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 16); - RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 2); - RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 16); - RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 3); - RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16); - RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 4); - RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 16); - RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 5); - RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 16); - RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 6); - RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 16); - RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 7); + RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, be ? 16 : 7); + RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, be ? 0 : 16); + RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, be ? 16 : 6); + RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, be ? 1 : 16); + RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, be ? 16 : 5); + RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, be ? 2 : 16); + RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, be ? 16 : 4); + RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, be ? 3 : 16); + RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, be ? 16 : 3); + RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, be ? 4 : 16); + RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, be ? 16 : 2); + RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, be ? 5 : 16); + RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, be ? 16 : 1); + RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, be ? 6 : 16); + RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, be ? 16 : 0); + RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, be ? 7 : 16); emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v))); emit_insn (gen_vperm_v16qiv8hi (operands[0], operands[1], vzero, mask)); @@ -2060,25 +2795,26 @@ rtx vzero = gen_reg_rtx (V4SImode); rtx mask = gen_reg_rtx (V16QImode); rtvec v = rtvec_alloc (16); + bool be = BYTES_BIG_ENDIAN; emit_insn (gen_altivec_vspltisw (vzero, const0_rtx)); - RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 16); - RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 17); - RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 0); - RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 1); - RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 16); - RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 17); - RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 2); - RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 3); - RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16); - RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 17); - RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 4); - RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 5); - RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 16); - RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 17); - RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 6); - RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 7); + RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, be ? 16 : 7); + RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, be ? 17 : 6); + RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, be ? 0 : 17); + RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, be ? 1 : 16); + RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, be ? 16 : 5); + RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, be ? 17 : 4); + RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, be ? 2 : 17); + RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, be ? 3 : 16); + RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, be ? 16 : 3); + RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, be ? 17 : 2); + RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, be ? 4 : 17); + RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, be ? 5 : 16); + RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, be ? 16 : 1); + RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, be ? 17 : 0); + RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, be ? 6 : 17); + RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, be ? 7 : 16); emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v))); emit_insn (gen_vperm_v8hiv4si (operands[0], operands[1], vzero, mask)); @@ -2095,25 +2831,26 @@ rtx vzero = gen_reg_rtx (V8HImode); rtx mask = gen_reg_rtx (V16QImode); rtvec v = rtvec_alloc (16); + bool be = BYTES_BIG_ENDIAN; emit_insn (gen_altivec_vspltish (vzero, const0_rtx)); - RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 16); - RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 8); - RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 16); - RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 9); - RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 16); - RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 10); - RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 16); - RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 11); - RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16); - RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 12); - RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 16); - RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 13); - RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 16); - RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 14); - RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 16); - RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 15); + RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, be ? 16 : 15); + RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, be ? 8 : 16); + RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, be ? 16 : 14); + RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, be ? 9 : 16); + RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, be ? 16 : 13); + RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, be ? 10 : 16); + RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, be ? 16 : 12); + RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, be ? 11 : 16); + RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, be ? 16 : 11); + RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, be ? 12 : 16); + RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, be ? 16 : 10); + RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, be ? 13 : 16); + RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, be ? 16 : 9); + RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, be ? 14 : 16); + RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, be ? 16 : 8); + RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, be ? 15 : 16); emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v))); emit_insn (gen_vperm_v16qiv8hi (operands[0], operands[1], vzero, mask)); @@ -2130,25 +2867,26 @@ rtx vzero = gen_reg_rtx (V4SImode); rtx mask = gen_reg_rtx (V16QImode); rtvec v = rtvec_alloc (16); + bool be = BYTES_BIG_ENDIAN; emit_insn (gen_altivec_vspltisw (vzero, const0_rtx)); - RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 16); - RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 17); - RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 8); - RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 9); - RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 16); - RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 17); - RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 10); - RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 11); - RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16); - RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 17); - RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 12); - RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 13); - RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 16); - RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 17); - RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 14); - RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 15); + RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, be ? 16 : 15); + RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, be ? 17 : 14); + RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, be ? 8 : 17); + RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, be ? 9 : 16); + RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, be ? 16 : 13); + RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, be ? 17 : 12); + RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, be ? 10 : 17); + RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, be ? 11 : 16); + RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, be ? 16 : 11); + RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, be ? 17 : 10); + RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, be ? 12 : 17); + RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, be ? 13 : 16); + RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, be ? 16 : 9); + RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, be ? 17 : 8); + RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, be ? 14 : 17); + RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, be ? 15 : 16); emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v))); emit_insn (gen_vperm_v8hiv4si (operands[0], operands[1], vzero, mask)); @@ -2166,9 +2904,18 @@ rtx ve = gen_reg_rtx (V8HImode); rtx vo = gen_reg_rtx (V8HImode); - emit_insn (gen_vec_widen_umult_even_v16qi (ve, operands[1], operands[2])); - emit_insn (gen_vec_widen_umult_odd_v16qi (vo, operands[1], operands[2])); - emit_insn (gen_altivec_vmrghh (operands[0], ve, vo)); + if (BYTES_BIG_ENDIAN) + { + emit_insn (gen_altivec_vmuleub (ve, operands[1], operands[2])); + emit_insn (gen_altivec_vmuloub (vo, operands[1], operands[2])); + emit_insn (gen_altivec_vmrghh_direct (operands[0], ve, vo)); + } + else + { + emit_insn (gen_altivec_vmuloub (ve, operands[1], operands[2])); + emit_insn (gen_altivec_vmuleub (vo, operands[1], operands[2])); + emit_insn (gen_altivec_vmrghh_direct (operands[0], vo, ve)); + } DONE; }") @@ -2183,9 +2930,18 @@ rtx ve = gen_reg_rtx (V8HImode); rtx vo = gen_reg_rtx (V8HImode); - emit_insn (gen_vec_widen_umult_even_v16qi (ve, operands[1], operands[2])); - emit_insn (gen_vec_widen_umult_odd_v16qi (vo, operands[1], operands[2])); - emit_insn (gen_altivec_vmrglh (operands[0], ve, vo)); + if (BYTES_BIG_ENDIAN) + { + emit_insn (gen_altivec_vmuleub (ve, operands[1], operands[2])); + emit_insn (gen_altivec_vmuloub (vo, operands[1], operands[2])); + emit_insn (gen_altivec_vmrglh_direct (operands[0], ve, vo)); + } + else + { + emit_insn (gen_altivec_vmuloub (ve, operands[1], operands[2])); + emit_insn (gen_altivec_vmuleub (vo, operands[1], operands[2])); + emit_insn (gen_altivec_vmrglh_direct (operands[0], vo, ve)); + } DONE; }") @@ -2200,9 +2956,18 @@ rtx ve = gen_reg_rtx (V8HImode); rtx vo = gen_reg_rtx (V8HImode); - emit_insn (gen_vec_widen_smult_even_v16qi (ve, operands[1], operands[2])); - emit_insn (gen_vec_widen_smult_odd_v16qi (vo, operands[1], operands[2])); - emit_insn (gen_altivec_vmrghh (operands[0], ve, vo)); + if (BYTES_BIG_ENDIAN) + { + emit_insn (gen_altivec_vmulesb (ve, operands[1], operands[2])); + emit_insn (gen_altivec_vmulosb (vo, operands[1], operands[2])); + emit_insn (gen_altivec_vmrghh_direct (operands[0], ve, vo)); + } + else + { + emit_insn (gen_altivec_vmulosb (ve, operands[1], operands[2])); + emit_insn (gen_altivec_vmulesb (vo, operands[1], operands[2])); + emit_insn (gen_altivec_vmrghh_direct (operands[0], vo, ve)); + } DONE; }") @@ -2217,9 +2982,18 @@ rtx ve = gen_reg_rtx (V8HImode); rtx vo = gen_reg_rtx (V8HImode); - emit_insn (gen_vec_widen_smult_even_v16qi (ve, operands[1], operands[2])); - emit_insn (gen_vec_widen_smult_odd_v16qi (vo, operands[1], operands[2])); - emit_insn (gen_altivec_vmrglh (operands[0], ve, vo)); + if (BYTES_BIG_ENDIAN) + { + emit_insn (gen_altivec_vmulesb (ve, operands[1], operands[2])); + emit_insn (gen_altivec_vmulosb (vo, operands[1], operands[2])); + emit_insn (gen_altivec_vmrglh_direct (operands[0], ve, vo)); + } + else + { + emit_insn (gen_altivec_vmulosb (ve, operands[1], operands[2])); + emit_insn (gen_altivec_vmulesb (vo, operands[1], operands[2])); + emit_insn (gen_altivec_vmrglh_direct (operands[0], vo, ve)); + } DONE; }") @@ -2234,9 +3008,18 @@ rtx ve = gen_reg_rtx (V4SImode); rtx vo = gen_reg_rtx (V4SImode); - emit_insn (gen_vec_widen_umult_even_v8hi (ve, operands[1], operands[2])); - emit_insn (gen_vec_widen_umult_odd_v8hi (vo, operands[1], operands[2])); - emit_insn (gen_altivec_vmrghw (operands[0], ve, vo)); + if (BYTES_BIG_ENDIAN) + { + emit_insn (gen_altivec_vmuleuh (ve, operands[1], operands[2])); + emit_insn (gen_altivec_vmulouh (vo, operands[1], operands[2])); + emit_insn (gen_altivec_vmrghw_direct (operands[0], ve, vo)); + } + else + { + emit_insn (gen_altivec_vmulouh (ve, operands[1], operands[2])); + emit_insn (gen_altivec_vmuleuh (vo, operands[1], operands[2])); + emit_insn (gen_altivec_vmrghw_direct (operands[0], vo, ve)); + } DONE; }") @@ -2251,9 +3034,18 @@ rtx ve = gen_reg_rtx (V4SImode); rtx vo = gen_reg_rtx (V4SImode); - emit_insn (gen_vec_widen_umult_even_v8hi (ve, operands[1], operands[2])); - emit_insn (gen_vec_widen_umult_odd_v8hi (vo, operands[1], operands[2])); - emit_insn (gen_altivec_vmrglw (operands[0], ve, vo)); + if (BYTES_BIG_ENDIAN) + { + emit_insn (gen_altivec_vmuleuh (ve, operands[1], operands[2])); + emit_insn (gen_altivec_vmulouh (vo, operands[1], operands[2])); + emit_insn (gen_altivec_vmrglw_direct (operands[0], ve, vo)); + } + else + { + emit_insn (gen_altivec_vmulouh (ve, operands[1], operands[2])); + emit_insn (gen_altivec_vmuleuh (vo, operands[1], operands[2])); + emit_insn (gen_altivec_vmrglw_direct (operands[0], vo, ve)); + } DONE; }") @@ -2268,9 +3060,18 @@ rtx ve = gen_reg_rtx (V4SImode); rtx vo = gen_reg_rtx (V4SImode); - emit_insn (gen_vec_widen_smult_even_v8hi (ve, operands[1], operands[2])); - emit_insn (gen_vec_widen_smult_odd_v8hi (vo, operands[1], operands[2])); - emit_insn (gen_altivec_vmrghw (operands[0], ve, vo)); + if (BYTES_BIG_ENDIAN) + { + emit_insn (gen_altivec_vmulesh (ve, operands[1], operands[2])); + emit_insn (gen_altivec_vmulosh (vo, operands[1], operands[2])); + emit_insn (gen_altivec_vmrghw_direct (operands[0], ve, vo)); + } + else + { + emit_insn (gen_altivec_vmulosh (ve, operands[1], operands[2])); + emit_insn (gen_altivec_vmulesh (vo, operands[1], operands[2])); + emit_insn (gen_altivec_vmrghw_direct (operands[0], vo, ve)); + } DONE; }") @@ -2285,35 +3086,28 @@ rtx ve = gen_reg_rtx (V4SImode); rtx vo = gen_reg_rtx (V4SImode); - emit_insn (gen_vec_widen_smult_even_v8hi (ve, operands[1], operands[2])); - emit_insn (gen_vec_widen_smult_odd_v8hi (vo, operands[1], operands[2])); - emit_insn (gen_altivec_vmrglw (operands[0], ve, vo)); + if (BYTES_BIG_ENDIAN) + { + emit_insn (gen_altivec_vmulesh (ve, operands[1], operands[2])); + emit_insn (gen_altivec_vmulosh (vo, operands[1], operands[2])); + emit_insn (gen_altivec_vmrglw_direct (operands[0], ve, vo)); + } + else + { + emit_insn (gen_altivec_vmulosh (ve, operands[1], operands[2])); + emit_insn (gen_altivec_vmulesh (vo, operands[1], operands[2])); + emit_insn (gen_altivec_vmrglw_direct (operands[0], vo, ve)); + } DONE; }") -(define_expand "vec_pack_trunc_v8hi" - [(set (match_operand:V16QI 0 "register_operand" "=v") - (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v") - (match_operand:V8HI 2 "register_operand" "v")] - UNSPEC_VPKUHUM))] - "TARGET_ALTIVEC" - " -{ - emit_insn (gen_altivec_vpkuhum (operands[0], operands[1], operands[2])); - DONE; -}") - -(define_expand "vec_pack_trunc_v4si" - [(set (match_operand:V8HI 0 "register_operand" "=v") - (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") - (match_operand:V4SI 2 "register_operand" "v")] - UNSPEC_VPKUWUM))] - "TARGET_ALTIVEC" - " -{ - emit_insn (gen_altivec_vpkuwum (operands[0], operands[1], operands[2])); - DONE; -}") +(define_expand "vec_pack_trunc_" + [(set (match_operand: 0 "register_operand" "=v") + (unspec: [(match_operand:VP 1 "register_operand" "v") + (match_operand:VP 2 "register_operand" "v")] + UNSPEC_VPACK_UNS_UNS_MOD))] + "" + "") (define_expand "altivec_negv4sf2" [(use (match_operand:V4SF 0 "register_operand" "")) @@ -2460,3 +3254,243 @@ emit_insn (gen_altivec_vcfux (operands[0], tmp, const0_rtx)); DONE; }") + + +;; Power8 vector instructions encoded as Altivec instructions + +;; Vector count leading zeros +(define_insn "*p8v_clz2" + [(set (match_operand:VI2 0 "register_operand" "=v") + (clz:VI2 (match_operand:VI2 1 "register_operand" "v")))] + "TARGET_P8_VECTOR" + "vclz %0,%1" + [(set_attr "length" "4") + (set_attr "type" "vecsimple")]) + +;; Vector population count +(define_insn "*p8v_popcount2" + [(set (match_operand:VI2 0 "register_operand" "=v") + (popcount:VI2 (match_operand:VI2 1 "register_operand" "v")))] + "TARGET_P8_VECTOR" + "vpopcnt %0,%1" + [(set_attr "length" "4") + (set_attr "type" "vecsimple")]) + +;; Vector Gather Bits by Bytes by Doubleword +(define_insn "p8v_vgbbd" + [(set (match_operand:V16QI 0 "register_operand" "=v") + (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")] + UNSPEC_VGBBD))] + "TARGET_P8_VECTOR" + "vgbbd %0,%1" + [(set_attr "length" "4") + (set_attr "type" "vecsimple")]) + + +;; 128-bit binary integer arithmetic +;; We have a special container type (V1TImode) to allow operations using the +;; ISA 2.07 128-bit binary support to target the VMX/altivec registers without +;; having to worry about the register allocator deciding GPRs are better. + +(define_insn "altivec_vadduqm" + [(set (match_operand:V1TI 0 "register_operand" "=v") + (plus:V1TI (match_operand:V1TI 1 "register_operand" "v") + (match_operand:V1TI 2 "register_operand" "v")))] + "TARGET_VADDUQM" + "vadduqm %0,%1,%2" + [(set_attr "length" "4") + (set_attr "type" "vecsimple")]) + +(define_insn "altivec_vaddcuq" + [(set (match_operand:V1TI 0 "register_operand" "=v") + (unspec:V1TI [(match_operand:V1TI 1 "register_operand" "v") + (match_operand:V1TI 2 "register_operand" "v")] + UNSPEC_VADDCUQ))] + "TARGET_VADDUQM" + "vaddcuq %0,%1,%2" + [(set_attr "length" "4") + (set_attr "type" "vecsimple")]) + +(define_insn "altivec_vsubuqm" + [(set (match_operand:V1TI 0 "register_operand" "=v") + (minus:V1TI (match_operand:V1TI 1 "register_operand" "v") + (match_operand:V1TI 2 "register_operand" "v")))] + "TARGET_VADDUQM" + "vsubuqm %0,%1,%2" + [(set_attr "length" "4") + (set_attr "type" "vecsimple")]) + +(define_insn "altivec_vsubcuq" + [(set (match_operand:V1TI 0 "register_operand" "=v") + (unspec:V1TI [(match_operand:V1TI 1 "register_operand" "v") + (match_operand:V1TI 2 "register_operand" "v")] + UNSPEC_VSUBCUQ))] + "TARGET_VADDUQM" + "vsubcuq %0,%1,%2" + [(set_attr "length" "4") + (set_attr "type" "vecsimple")]) + +(define_insn "altivec_vaddeuqm" + [(set (match_operand:V1TI 0 "register_operand" "=v") + (unspec:V1TI [(match_operand:V1TI 1 "register_operand" "v") + (match_operand:V1TI 2 "register_operand" "v") + (match_operand:V1TI 3 "register_operand" "v")] + UNSPEC_VADDEUQM))] + "TARGET_VADDUQM" + "vaddeuqm %0,%1,%2,%3" + [(set_attr "length" "4") + (set_attr "type" "vecsimple")]) + +(define_insn "altivec_vaddecuq" + [(set (match_operand:V1TI 0 "register_operand" "=v") + (unspec:V1TI [(match_operand:V1TI 1 "register_operand" "v") + (match_operand:V1TI 2 "register_operand" "v") + (match_operand:V1TI 3 "register_operand" "v")] + UNSPEC_VADDECUQ))] + "TARGET_VADDUQM" + "vaddecuq %0,%1,%2,%3" + [(set_attr "length" "4") + (set_attr "type" "vecsimple")]) + +(define_insn "altivec_vsubeuqm" + [(set (match_operand:V1TI 0 "register_operand" "=v") + (unspec:V1TI [(match_operand:V1TI 1 "register_operand" "v") + (match_operand:V1TI 2 "register_operand" "v") + (match_operand:V1TI 3 "register_operand" "v")] + UNSPEC_VSUBEUQM))] + "TARGET_VADDUQM" + "vsubeuqm %0,%1,%2,%3" + [(set_attr "length" "4") + (set_attr "type" "vecsimple")]) + +(define_insn "altivec_vsubecuq" + [(set (match_operand:V1TI 0 "register_operand" "=v") + (unspec:V1TI [(match_operand:V1TI 1 "register_operand" "v") + (match_operand:V1TI 2 "register_operand" "v") + (match_operand:V1TI 3 "register_operand" "v")] + UNSPEC_VSUBECUQ))] + "TARGET_VADDUQM" + "vsubecuq %0,%1,%2,%3" + [(set_attr "length" "4") + (set_attr "type" "vecsimple")]) + +;; We use V2DI as the output type to simplify converting the permute +;; bits into an integer +(define_insn "altivec_vbpermq" + [(set (match_operand:V2DI 0 "register_operand" "=v") + (unspec:V2DI [(match_operand:V16QI 1 "register_operand" "v") + (match_operand:V16QI 2 "register_operand" "v")] + UNSPEC_VBPERMQ))] + "TARGET_P8_VECTOR" + "vbpermq %0,%1,%2" + [(set_attr "length" "4") + (set_attr "type" "vecsimple")]) + +;; Decimal Integer operations +(define_int_iterator UNSPEC_BCD_ADD_SUB [UNSPEC_BCDADD UNSPEC_BCDSUB]) + +(define_int_attr bcd_add_sub [(UNSPEC_BCDADD "add") + (UNSPEC_BCDSUB "sub")]) + +(define_code_iterator BCD_TEST [eq lt gt unordered]) + +(define_insn "bcd" + [(set (match_operand:V1TI 0 "register_operand" "") + (unspec:V1TI [(match_operand:V1TI 1 "register_operand" "") + (match_operand:V1TI 2 "register_operand" "") + (match_operand:QI 3 "const_0_to_1_operand" "")] + UNSPEC_BCD_ADD_SUB)) + (clobber (reg:CCFP 74))] + "TARGET_P8_VECTOR" + "bcd. %0,%1,%2,%3" + [(set_attr "length" "4") + (set_attr "type" "vecsimple")]) + +;; Use a floating point type (V2DFmode) for the compare to set CR6 so that we +;; can use the unordered test for BCD nans and add/subtracts that overflow. An +;; UNORDERED test on an integer type (like V1TImode) is not defined. The type +;; probably should be one that can go in the VMX (Altivec) registers, so we +;; can't use DDmode or DFmode. +(define_insn "*bcd_test" + [(set (reg:CCFP 74) + (compare:CCFP + (unspec:V2DF [(match_operand:V1TI 1 "register_operand" "v") + (match_operand:V1TI 2 "register_operand" "v") + (match_operand:QI 3 "const_0_to_1_operand" "i")] + UNSPEC_BCD_ADD_SUB) + (match_operand:V2DF 4 "zero_constant" "j"))) + (clobber (match_scratch:V1TI 0 "=v"))] + "TARGET_P8_VECTOR" + "bcd. %0,%1,%2,%3" + [(set_attr "length" "4") + (set_attr "type" "vecsimple")]) + +(define_insn "*bcd_test2" + [(set (match_operand:V1TI 0 "register_operand" "=v") + (unspec:V1TI [(match_operand:V1TI 1 "register_operand" "v") + (match_operand:V1TI 2 "register_operand" "v") + (match_operand:QI 3 "const_0_to_1_operand" "i")] + UNSPEC_BCD_ADD_SUB)) + (set (reg:CCFP 74) + (compare:CCFP + (unspec:V2DF [(match_dup 1) + (match_dup 2) + (match_dup 3)] + UNSPEC_BCD_ADD_SUB) + (match_operand:V2DF 4 "zero_constant" "j")))] + "TARGET_P8_VECTOR" + "bcd. %0,%1,%2,%3" + [(set_attr "length" "4") + (set_attr "type" "vecsimple")]) + +(define_expand "bcd_" + [(parallel [(set (reg:CCFP 74) + (compare:CCFP + (unspec:V2DF [(match_operand:V1TI 1 "register_operand" "") + (match_operand:V1TI 2 "register_operand" "") + (match_operand:QI 3 "const_0_to_1_operand" "")] + UNSPEC_BCD_ADD_SUB) + (match_dup 4))) + (clobber (match_scratch:V1TI 5 ""))]) + (set (match_operand:SI 0 "register_operand" "") + (BCD_TEST:SI (reg:CCFP 74) + (const_int 0)))] + "TARGET_P8_VECTOR" +{ + operands[4] = CONST0_RTX (V2DFmode); +}) + +;; Peephole2 pattern to combine a bcdadd/bcdsub that calculates the value and +;; the bcdadd/bcdsub that tests the value. The combiner won't work since +;; CR6 is a hard coded register. Unfortunately, all of the Altivec predicate +;; support is hard coded to use the fixed register CR6 instead of creating +;; a register class for CR6. + +(define_peephole2 + [(parallel [(set (match_operand:V1TI 0 "register_operand" "") + (unspec:V1TI [(match_operand:V1TI 1 "register_operand" "") + (match_operand:V1TI 2 "register_operand" "") + (match_operand:QI 3 "const_0_to_1_operand" "")] + UNSPEC_BCD_ADD_SUB)) + (clobber (reg:CCFP 74))]) + (parallel [(set (reg:CCFP 74) + (compare:CCFP + (unspec:V2DF [(match_dup 1) + (match_dup 2) + (match_dup 3)] + UNSPEC_BCD_ADD_SUB) + (match_operand:V2DF 4 "zero_constant" ""))) + (clobber (match_operand:V1TI 5 "register_operand" ""))])] + "TARGET_P8_VECTOR" + [(parallel [(set (match_dup 0) + (unspec:V1TI [(match_dup 1) + (match_dup 2) + (match_dup 3)] + UNSPEC_BCD_ADD_SUB)) + (set (reg:CCFP 74) + (compare:CCFP + (unspec:V2DF [(match_dup 1) + (match_dup 2) + (match_dup 3)] + UNSPEC_BCD_ADD_SUB) + (match_dup 4)))])]) diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md index ccb61edce45b3..1724d28f7bcc5 100644 --- a/gcc/config/rs6000/constraints.md +++ b/gcc/config/rs6000/constraints.md @@ -52,21 +52,75 @@ "@internal") ;; Use w as a prefix to add VSX modes -;; vector double (V2DF) +;; any VSX register +(define_register_constraint "wa" "rs6000_constraints[RS6000_CONSTRAINT_wa]" + "Any VSX register if the -mvsx option was used or NO_REGS.") + (define_register_constraint "wd" "rs6000_constraints[RS6000_CONSTRAINT_wd]" - "@internal") + "VSX vector register to hold vector double data or NO_REGS.") -;; vector float (V4SF) (define_register_constraint "wf" "rs6000_constraints[RS6000_CONSTRAINT_wf]" - "@internal") + "VSX vector register to hold vector float data or NO_REGS.") + +(define_register_constraint "wg" "rs6000_constraints[RS6000_CONSTRAINT_wg]" + "If -mmfpgpr was used, a floating point register or NO_REGS.") + +(define_register_constraint "wh" "rs6000_constraints[RS6000_CONSTRAINT_wh]" + "Floating point register if direct moves are available, or NO_REGS.") + +;; At present, DImode is not allowed in the Altivec registers. If in the +;; future it is allowed, wi/wj can be set to VSX_REGS instead of FLOAT_REGS. +(define_register_constraint "wi" "rs6000_constraints[RS6000_CONSTRAINT_wi]" + "FP or VSX register to hold 64-bit integers for VSX insns or NO_REGS.") + +(define_register_constraint "wj" "rs6000_constraints[RS6000_CONSTRAINT_wj]" + "FP or VSX register to hold 64-bit integers for direct moves or NO_REGS.") + +(define_register_constraint "wk" "rs6000_constraints[RS6000_CONSTRAINT_wk]" + "FP or VSX register to hold 64-bit doubles for direct moves or NO_REGS.") + +(define_register_constraint "wl" "rs6000_constraints[RS6000_CONSTRAINT_wl]" + "Floating point register if the LFIWAX instruction is enabled or NO_REGS.") + +(define_register_constraint "wm" "rs6000_constraints[RS6000_CONSTRAINT_wm]" + "VSX register if direct move instructions are enabled, or NO_REGS.") + +;; NO_REGs register constraint, used to merge mov{sd,sf}, since movsd can use +;; direct move directly, and movsf can't to move between the register sets. +;; There is a mode_attr that resolves to wm for SDmode and wn for SFmode +(define_register_constraint "wn" "NO_REGS" "No register (NO_REGS).") + +(define_register_constraint "wr" "rs6000_constraints[RS6000_CONSTRAINT_wr]" + "General purpose register if 64-bit instructions are enabled or NO_REGS.") -;; scalar double (DF) (define_register_constraint "ws" "rs6000_constraints[RS6000_CONSTRAINT_ws]" - "@internal") + "VSX vector register to hold scalar double values or NO_REGS.") -;; any VSX register -(define_register_constraint "wa" "rs6000_constraints[RS6000_CONSTRAINT_wa]" - "@internal") +(define_register_constraint "wt" "rs6000_constraints[RS6000_CONSTRAINT_wt]" + "VSX vector register to hold 128 bit integer or NO_REGS.") + +(define_register_constraint "wu" "rs6000_constraints[RS6000_CONSTRAINT_wu]" + "Altivec register to use for float/32-bit int loads/stores or NO_REGS.") + +(define_register_constraint "wv" "rs6000_constraints[RS6000_CONSTRAINT_wv]" + "Altivec register to use for double loads/stores or NO_REGS.") + +(define_register_constraint "ww" "rs6000_constraints[RS6000_CONSTRAINT_ww]" + "FP or VSX register to perform float operations under -mvsx or NO_REGS.") + +(define_register_constraint "wx" "rs6000_constraints[RS6000_CONSTRAINT_wx]" + "Floating point register if the STFIWX instruction is enabled or NO_REGS.") + +(define_register_constraint "wy" "rs6000_constraints[RS6000_CONSTRAINT_wy]" + "FP or VSX register to perform ISA 2.07 float ops or NO_REGS.") + +(define_register_constraint "wz" "rs6000_constraints[RS6000_CONSTRAINT_wz]" + "Floating point register if the LFIWZX instruction is enabled or NO_REGS.") + +;; Lq/stq validates the address for load/store quad +(define_memory_constraint "wQ" + "Memory operand suitable for the load/store quad instructions" + (match_operand 0 "quad_memory_operand")) ;; Altivec style load/store that ignores the bottom bits of the address (define_memory_constraint "wZ" diff --git a/gcc/config/rs6000/crypto.md b/gcc/config/rs6000/crypto.md new file mode 100644 index 0000000000000..683a340e1197c --- /dev/null +++ b/gcc/config/rs6000/crypto.md @@ -0,0 +1,110 @@ +;; Cryptographic instructions added in ISA 2.07 +;; Copyright (C) 2012-2013 Free Software Foundation, Inc. +;; Contributed by Michael Meissner (meissner@linux.vnet.ibm.com) + +;; This file is part of GCC. + +;; GCC is free software; you can redistribute it and/or modify it +;; under the terms of the GNU General Public License as published +;; by the Free Software Foundation; either version 3, or (at your +;; option) any later version. + +;; GCC is distributed in the hope that it will be useful, but WITHOUT +;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +;; License for more details. + +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; . + +;; NOTE: Although this file contains all the instructions from +;; section 5.11 of ISA 2.07, only those in sections 5.11.1 and +;; 5.11.2 are in Category:Vector.Crypto. Those are the only +;; ones controlled by -m[no-]crypto. + +;; FIXME: The builtin names for the instructions in this file +;; are likely to be deprecated in favor of other names to be +;; agreed upon with the XL compilers and LLVM. + +(define_c_enum "unspec" + [UNSPEC_VCIPHER + UNSPEC_VNCIPHER + UNSPEC_VCIPHERLAST + UNSPEC_VNCIPHERLAST + UNSPEC_VSBOX + UNSPEC_VSHASIGMA + UNSPEC_VPERMXOR + UNSPEC_VPMSUM]) + +;; Iterator for VPMSUM/VPERMXOR +(define_mode_iterator CR_mode [V16QI V8HI V4SI V2DI]) + +(define_mode_attr CR_char [(V16QI "b") + (V8HI "h") + (V4SI "w") + (V2DI "d")]) + +;; Iterator for VSHASIGMAD/VSHASIGMAW +(define_mode_iterator CR_hash [V4SI V2DI]) + +;; Iterator for the other crypto functions +(define_int_iterator CR_code [UNSPEC_VCIPHER + UNSPEC_VNCIPHER + UNSPEC_VCIPHERLAST + UNSPEC_VNCIPHERLAST]) + +(define_int_attr CR_insn [(UNSPEC_VCIPHER "vcipher") + (UNSPEC_VNCIPHER "vncipher") + (UNSPEC_VCIPHERLAST "vcipherlast") + (UNSPEC_VNCIPHERLAST "vncipherlast")]) + +;; 2 operand crypto instructions +(define_insn "crypto_" + [(set (match_operand:V2DI 0 "register_operand" "=v") + (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "v") + (match_operand:V2DI 2 "register_operand" "v")] + CR_code))] + "TARGET_CRYPTO" + " %0,%1,%2" + [(set_attr "type" "crypto")]) + +(define_insn "crypto_vpmsum" + [(set (match_operand:CR_mode 0 "register_operand" "=v") + (unspec:CR_mode [(match_operand:CR_mode 1 "register_operand" "v") + (match_operand:CR_mode 2 "register_operand" "v")] + UNSPEC_VPMSUM))] + "TARGET_P8_VECTOR" + "vpmsum %0,%1,%2" + [(set_attr "type" "crypto")]) + +;; 3 operand crypto instructions +(define_insn "crypto_vpermxor_" + [(set (match_operand:CR_mode 0 "register_operand" "=v") + (unspec:CR_mode [(match_operand:CR_mode 1 "register_operand" "v") + (match_operand:CR_mode 2 "register_operand" "v") + (match_operand:CR_mode 3 "register_operand" "v")] + UNSPEC_VPERMXOR))] + "TARGET_P8_VECTOR" + "vpermxor %0,%1,%2,%3" + [(set_attr "type" "crypto")]) + +;; 1 operand crypto instruction +(define_insn "crypto_vsbox" + [(set (match_operand:V2DI 0 "register_operand" "=v") + (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "v")] + UNSPEC_VSBOX))] + "TARGET_CRYPTO" + "vsbox %0,%1" + [(set_attr "type" "crypto")]) + +;; Hash crypto instructions +(define_insn "crypto_vshasigma" + [(set (match_operand:CR_hash 0 "register_operand" "=v") + (unspec:CR_hash [(match_operand:CR_hash 1 "register_operand" "v") + (match_operand:SI 2 "const_0_to_1_operand" "n") + (match_operand:SI 3 "const_0_to_15_operand" "n")] + UNSPEC_VSHASIGMA))] + "TARGET_CRYPTO" + "vshasigma %0,%1,%2,%3" + [(set_attr "type" "crypto")]) diff --git a/gcc/config/rs6000/darwin.h b/gcc/config/rs6000/darwin.h index 9d92d2af4da37..0cf2f4c346d20 100644 --- a/gcc/config/rs6000/darwin.h +++ b/gcc/config/rs6000/darwin.h @@ -205,7 +205,8 @@ extern int darwin_emit_branch_islands; "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", \ "vrsave", "vscr", \ "spe_acc", "spefscr", \ - "sfp" \ + "sfp", \ + "tfhar", "tfiar", "texasr" \ } /* This outputs NAME to FILE. */ diff --git a/gcc/config/rs6000/default64.h b/gcc/config/rs6000/default64.h index 5a6192d186c7c..7a29672a1eac8 100644 --- a/gcc/config/rs6000/default64.h +++ b/gcc/config/rs6000/default64.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler, for 64 bit powerpc linux defaulting to -m64. - Copyright (C) 2003-2013 Free Software Foundation, Inc. + Copyright (C) 2003-2015 Free Software Foundation, Inc. This file is part of GCC. @@ -18,5 +18,14 @@ You should have received a copy of the GNU General Public License along with GCC; see the file COPYING3. If not see . */ +#define RS6000_CPU(NAME, CPU, FLAGS) +#include "rs6000-cpus.def" +#undef RS6000_CPU + +#if (TARGET_DEFAULT & MASK_LITTLE_ENDIAN) +#undef TARGET_DEFAULT +#define TARGET_DEFAULT (ISA_2_7_MASKS_SERVER | MASK_POWERPC64 | MASK_64BIT | MASK_LITTLE_ENDIAN) +#else #undef TARGET_DEFAULT -#define TARGET_DEFAULT (MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_64BIT) +#define TARGET_DEFAULT (MASK_PPC_GFXOPT | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 | MASK_64BIT) +#endif diff --git a/gcc/config/rs6000/dfp.md b/gcc/config/rs6000/dfp.md index f73e115e34235..a3c09390ae100 100644 --- a/gcc/config/rs6000/dfp.md +++ b/gcc/config/rs6000/dfp.md @@ -29,77 +29,6 @@ ]) -(define_expand "movsd" - [(set (match_operand:SD 0 "nonimmediate_operand" "") - (match_operand:SD 1 "any_operand" ""))] - "TARGET_HARD_FLOAT && TARGET_FPRS" - "{ rs6000_emit_move (operands[0], operands[1], SDmode); DONE; }") - -(define_split - [(set (match_operand:SD 0 "gpc_reg_operand" "") - (match_operand:SD 1 "const_double_operand" ""))] - "reload_completed - && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) - || (GET_CODE (operands[0]) == SUBREG - && GET_CODE (SUBREG_REG (operands[0])) == REG - && REGNO (SUBREG_REG (operands[0])) <= 31))" - [(set (match_dup 2) (match_dup 3))] - " -{ - long l; - REAL_VALUE_TYPE rv; - - REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); - REAL_VALUE_TO_TARGET_DECIMAL32 (rv, l); - - if (! TARGET_POWERPC64) - operands[2] = operand_subword (operands[0], 0, 0, SDmode); - else - operands[2] = gen_lowpart (SImode, operands[0]); - - operands[3] = gen_int_mode (l, SImode); -}") - -(define_insn "movsd_hardfloat" - [(set (match_operand:SD 0 "nonimmediate_operand" "=r,r,m,f,*c*l,!r,*h,!r,!r") - (match_operand:SD 1 "input_operand" "r,m,r,f,r,h,0,G,Fn"))] - "(gpc_reg_operand (operands[0], SDmode) - || gpc_reg_operand (operands[1], SDmode)) - && (TARGET_HARD_FLOAT && TARGET_FPRS)" - "@ - mr %0,%1 - lwz%U1%X1 %0,%1 - stw%U0%X0 %1,%0 - fmr %0,%1 - mt%0 %1 - mf%1 %0 - nop - # - #" - [(set_attr "type" "*,load,store,fp,mtjmpr,mfjmpr,*,*,*") - (set_attr "length" "4,4,4,4,4,4,4,4,8")]) - -(define_insn "movsd_softfloat" - [(set (match_operand:SD 0 "nonimmediate_operand" "=r,cl,r,r,m,r,r,r,r,r,*h") - (match_operand:SD 1 "input_operand" "r,r,h,m,r,I,L,R,G,Fn,0"))] - "(gpc_reg_operand (operands[0], SDmode) - || gpc_reg_operand (operands[1], SDmode)) - && (TARGET_SOFT_FLOAT || !TARGET_FPRS)" - "@ - mr %0,%1 - mt%0 %1 - mf%1 %0 - lwz%U1%X1 %0,%1 - stw%U0%X0 %1,%0 - li %0,%1 - lis %0,%v1 - la %0,%a1 - # - # - nop" - [(set_attr "type" "*,mtjmpr,mfjmpr,load,store,*,*,*,*,*,*") - (set_attr "length" "4,4,4,4,4,4,4,4,4,8,4")]) - (define_insn "movsd_store" [(set (match_operand:DD 0 "nonimmediate_operand" "=m") (unspec:DD [(match_operand:SD 1 "input_operand" "d")] @@ -108,7 +37,14 @@ || gpc_reg_operand (operands[1], SDmode)) && TARGET_HARD_FLOAT && TARGET_FPRS" "stfd%U0%X0 %1,%0" - [(set_attr "type" "fpstore") + [(set (attr "type") + (if_then_else + (match_test "update_indexed_address_mem (operands[0], VOIDmode)") + (const_string "fpstore_ux") + (if_then_else + (match_test "update_address_mem (operands[0], VOIDmode)") + (const_string "fpstore_u") + (const_string "fpstore")))) (set_attr "length" "4")]) (define_insn "movsd_load" @@ -119,7 +55,14 @@ || gpc_reg_operand (operands[1], DDmode)) && TARGET_HARD_FLOAT && TARGET_FPRS" "lfd%U1%X1 %0,%1" - [(set_attr "type" "fpload") + [(set (attr "type") + (if_then_else + (match_test "update_indexed_address_mem (operands[1], VOIDmode)") + (const_string "fpload_ux") + (if_then_else + (match_test "update_address_mem (operands[1], VOIDmode)") + (const_string "fpload_u") + (const_string "fpload")))) (set_attr "length" "4")]) ;; Hardware support for decimal floating point operations. @@ -182,211 +125,6 @@ "fnabs %0,%1" [(set_attr "type" "fp")]) -(define_expand "movdd" - [(set (match_operand:DD 0 "nonimmediate_operand" "") - (match_operand:DD 1 "any_operand" ""))] - "" - "{ rs6000_emit_move (operands[0], operands[1], DDmode); DONE; }") - -(define_split - [(set (match_operand:DD 0 "gpc_reg_operand" "") - (match_operand:DD 1 "const_int_operand" ""))] - "! TARGET_POWERPC64 && reload_completed - && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) - || (GET_CODE (operands[0]) == SUBREG - && GET_CODE (SUBREG_REG (operands[0])) == REG - && REGNO (SUBREG_REG (operands[0])) <= 31))" - [(set (match_dup 2) (match_dup 4)) - (set (match_dup 3) (match_dup 1))] - " -{ - int endian = (WORDS_BIG_ENDIAN == 0); - HOST_WIDE_INT value = INTVAL (operands[1]); - - operands[2] = operand_subword (operands[0], endian, 0, DDmode); - operands[3] = operand_subword (operands[0], 1 - endian, 0, DDmode); -#if HOST_BITS_PER_WIDE_INT == 32 - operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx; -#else - operands[4] = GEN_INT (value >> 32); - operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000); -#endif -}") - -(define_split - [(set (match_operand:DD 0 "gpc_reg_operand" "") - (match_operand:DD 1 "const_double_operand" ""))] - "! TARGET_POWERPC64 && reload_completed - && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) - || (GET_CODE (operands[0]) == SUBREG - && GET_CODE (SUBREG_REG (operands[0])) == REG - && REGNO (SUBREG_REG (operands[0])) <= 31))" - [(set (match_dup 2) (match_dup 4)) - (set (match_dup 3) (match_dup 5))] - " -{ - int endian = (WORDS_BIG_ENDIAN == 0); - long l[2]; - REAL_VALUE_TYPE rv; - - REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); - REAL_VALUE_TO_TARGET_DECIMAL64 (rv, l); - - operands[2] = operand_subword (operands[0], endian, 0, DDmode); - operands[3] = operand_subword (operands[0], 1 - endian, 0, DDmode); - operands[4] = gen_int_mode (l[endian], SImode); - operands[5] = gen_int_mode (l[1 - endian], SImode); -}") - -(define_split - [(set (match_operand:DD 0 "gpc_reg_operand" "") - (match_operand:DD 1 "const_double_operand" ""))] - "TARGET_POWERPC64 && reload_completed - && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) - || (GET_CODE (operands[0]) == SUBREG - && GET_CODE (SUBREG_REG (operands[0])) == REG - && REGNO (SUBREG_REG (operands[0])) <= 31))" - [(set (match_dup 2) (match_dup 3))] - " -{ - int endian = (WORDS_BIG_ENDIAN == 0); - long l[2]; - REAL_VALUE_TYPE rv; -#if HOST_BITS_PER_WIDE_INT >= 64 - HOST_WIDE_INT val; -#endif - - REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); - REAL_VALUE_TO_TARGET_DECIMAL64 (rv, l); - - operands[2] = gen_lowpart (DImode, operands[0]); - /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */ -#if HOST_BITS_PER_WIDE_INT >= 64 - val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32 - | ((HOST_WIDE_INT)(unsigned long)l[1 - endian])); - - operands[3] = gen_int_mode (val, DImode); -#else - operands[3] = immed_double_const (l[1 - endian], l[endian], DImode); -#endif -}") - -;; Don't have reload use general registers to load a constant. First, -;; it might not work if the output operand is the equivalent of -;; a non-offsettable memref, but also it is less efficient than loading -;; the constant into an FP register, since it will probably be used there. -;; The "??" is a kludge until we can figure out a more reasonable way -;; of handling these non-offsettable values. -(define_insn "*movdd_hardfloat32" - [(set (match_operand:DD 0 "nonimmediate_operand" "=!r,??r,m,d,d,m,!r,!r,!r") - (match_operand:DD 1 "input_operand" "r,m,r,d,m,d,G,H,F"))] - "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS - && (gpc_reg_operand (operands[0], DDmode) - || gpc_reg_operand (operands[1], DDmode))" - "* -{ - switch (which_alternative) - { - default: - gcc_unreachable (); - case 0: - case 1: - case 2: - return \"#\"; - case 3: - return \"fmr %0,%1\"; - case 4: - return \"lfd%U1%X1 %0,%1\"; - case 5: - return \"stfd%U0%X0 %1,%0\"; - case 6: - case 7: - case 8: - return \"#\"; - } -}" - [(set_attr "type" "two,load,store,fp,fpload,fpstore,*,*,*") - (set_attr "length" "8,16,16,4,4,4,8,12,16")]) - -(define_insn "*movdd_softfloat32" - [(set (match_operand:DD 0 "nonimmediate_operand" "=r,r,m,r,r,r") - (match_operand:DD 1 "input_operand" "r,m,r,G,H,F"))] - "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS) - && (gpc_reg_operand (operands[0], DDmode) - || gpc_reg_operand (operands[1], DDmode))" - "#" - [(set_attr "type" "two,load,store,*,*,*") - (set_attr "length" "8,8,8,8,12,16")]) - -; ld/std require word-aligned displacements -> 'Y' constraint. -; List Y->r and r->Y before r->r for reload. -(define_insn "*movdd_hardfloat64_mfpgpr" - [(set (match_operand:DD 0 "nonimmediate_operand" "=Y,r,!r,d,d,m,*c*l,!r,*h,!r,!r,!r,r,d") - (match_operand:DD 1 "input_operand" "r,Y,r,d,m,d,r,h,0,G,H,F,d,r"))] - "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS - && (gpc_reg_operand (operands[0], DDmode) - || gpc_reg_operand (operands[1], DDmode))" - "@ - std%U0%X0 %1,%0 - ld%U1%X1 %0,%1 - mr %0,%1 - fmr %0,%1 - lfd%U1%X1 %0,%1 - stfd%U0%X0 %1,%0 - mt%0 %1 - mf%1 %0 - nop - # - # - # - mftgpr %0,%1 - mffgpr %0,%1" - [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*,mftgpr,mffgpr") - (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16,4,4")]) - -; ld/std require word-aligned displacements -> 'Y' constraint. -; List Y->r and r->Y before r->r for reload. -(define_insn "*movdd_hardfloat64" - [(set (match_operand:DD 0 "nonimmediate_operand" "=Y,r,!r,d,d,m,*c*l,!r,*h,!r,!r,!r") - (match_operand:DD 1 "input_operand" "r,Y,r,d,m,d,r,h,0,G,H,F"))] - "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS - && (gpc_reg_operand (operands[0], DDmode) - || gpc_reg_operand (operands[1], DDmode))" - "@ - std%U0%X0 %1,%0 - ld%U1%X1 %0,%1 - mr %0,%1 - fmr %0,%1 - lfd%U1%X1 %0,%1 - stfd%U0%X0 %1,%0 - mt%0 %1 - mf%1 %0 - nop - # - # - #" - [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*") - (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")]) - -(define_insn "*movdd_softfloat64" - [(set (match_operand:DD 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h") - (match_operand:DD 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))] - "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS) - && (gpc_reg_operand (operands[0], DDmode) - || gpc_reg_operand (operands[1], DDmode))" - "@ - ld%U1%X1 %0,%1 - std%U0%X0 %1,%0 - mr %0,%1 - mt%0 %1 - mf%1 %0 - # - # - # - nop" - [(set_attr "type" "load,store,*,mtjmpr,mfjmpr,*,*,*,*") - (set_attr "length" "4,4,4,4,4,8,12,16,4")]) - (define_expand "negtd2" [(set (match_operand:TD 0 "gpc_reg_operand" "") (neg:TD (match_operand:TD 1 "gpc_reg_operand" "")))] @@ -394,11 +132,14 @@ "") (define_insn "*negtd2_fpr" - [(set (match_operand:TD 0 "gpc_reg_operand" "=d") - (neg:TD (match_operand:TD 1 "gpc_reg_operand" "d")))] + [(set (match_operand:TD 0 "gpc_reg_operand" "=d,d") + (neg:TD (match_operand:TD 1 "gpc_reg_operand" "0,d")))] "TARGET_HARD_FLOAT && TARGET_FPRS" - "fneg %0,%1" - [(set_attr "type" "fp")]) + "@ + fneg %0,%1 + fneg %0,%1\;fmr %L0,%L1" + [(set_attr "type" "fp") + (set_attr "length" "4,8")]) (define_expand "abstd2" [(set (match_operand:TD 0 "gpc_reg_operand" "") @@ -407,39 +148,24 @@ "") (define_insn "*abstd2_fpr" - [(set (match_operand:TD 0 "gpc_reg_operand" "=d") - (abs:TD (match_operand:TD 1 "gpc_reg_operand" "d")))] + [(set (match_operand:TD 0 "gpc_reg_operand" "=d,d") + (abs:TD (match_operand:TD 1 "gpc_reg_operand" "0,d")))] "TARGET_HARD_FLOAT && TARGET_FPRS" - "fabs %0,%1" - [(set_attr "type" "fp")]) + "@ + fabs %0,%1 + fabs %0,%1\;fmr %L0,%L1" + [(set_attr "type" "fp") + (set_attr "length" "4,8")]) (define_insn "*nabstd2_fpr" - [(set (match_operand:TD 0 "gpc_reg_operand" "=d") - (neg:TD (abs:TD (match_operand:TD 1 "gpc_reg_operand" "d"))))] - "TARGET_HARD_FLOAT && TARGET_FPRS" - "fnabs %0,%1" - [(set_attr "type" "fp")]) - -(define_expand "movtd" - [(set (match_operand:TD 0 "general_operand" "") - (match_operand:TD 1 "any_operand" ""))] + [(set (match_operand:TD 0 "gpc_reg_operand" "=d,d") + (neg:TD (abs:TD (match_operand:TD 1 "gpc_reg_operand" "0,d"))))] "TARGET_HARD_FLOAT && TARGET_FPRS" - "{ rs6000_emit_move (operands[0], operands[1], TDmode); DONE; }") - -; It's important to list the Y->r and r->Y moves before r->r because -; otherwise reload, given m->r, will try to pick r->r and reload it, -; which doesn't make progress. -(define_insn_and_split "*movtd_internal" - [(set (match_operand:TD 0 "nonimmediate_operand" "=m,d,d,Y,r,r") - (match_operand:TD 1 "input_operand" "d,m,d,r,YGHF,r"))] - "TARGET_HARD_FLOAT && TARGET_FPRS - && (gpc_reg_operand (operands[0], TDmode) - || gpc_reg_operand (operands[1], TDmode))" - "#" - "&& reload_completed" - [(pc)] -{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; } - [(set_attr "length" "8,8,8,20,20,16")]) + "@ + fnabs %0,%1 + fnabs %0,%1\;fmr %L0,%L1" + [(set_attr "type" "fp") + (set_attr "length" "4,8")]) ;; Hardware support for decimal floating point operations. @@ -596,3 +322,72 @@ "TARGET_DFP" "dctfixq %0,%1" [(set_attr "type" "fp")]) + + +;; Decimal builtin support + +(define_c_enum "unspec" + [UNSPEC_DDEDPD + UNSPEC_DENBCD + UNSPEC_DXEX + UNSPEC_DIEX + UNSPEC_DSCLI + UNSPEC_DSCRI]) + +(define_mode_iterator D64_D128 [DD TD]) + +(define_mode_attr dfp_suffix [(DD "") + (TD "q")]) + +(define_insn "dfp_ddedpd_" + [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d") + (unspec:D64_D128 [(match_operand:QI 1 "const_0_to_3_operand" "i") + (match_operand:D64_D128 2 "gpc_reg_operand" "d")] + UNSPEC_DDEDPD))] + "TARGET_DFP" + "ddedpd %1,%0,%2" + [(set_attr "type" "fp")]) + +(define_insn "dfp_denbcd_" + [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d") + (unspec:D64_D128 [(match_operand:QI 1 "const_0_to_1_operand" "i") + (match_operand:D64_D128 2 "gpc_reg_operand" "d")] + UNSPEC_DENBCD))] + "TARGET_DFP" + "denbcd %1,%0,%2" + [(set_attr "type" "fp")]) + +(define_insn "dfp_dxex_" + [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d") + (unspec:D64_D128 [(match_operand:D64_D128 1 "gpc_reg_operand" "d")] + UNSPEC_DXEX))] + "TARGET_DFP" + "dxex %0,%1" + [(set_attr "type" "fp")]) + +(define_insn "dfp_diex_" + [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d") + (unspec:D64_D128 [(match_operand:D64_D128 1 "gpc_reg_operand" "d") + (match_operand:D64_D128 2 "gpc_reg_operand" "d")] + UNSPEC_DXEX))] + "TARGET_DFP" + "diex %0,%1,%2" + [(set_attr "type" "fp")]) + +(define_insn "dfp_dscli_" + [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d") + (unspec:D64_D128 [(match_operand:D64_D128 1 "gpc_reg_operand" "d") + (match_operand:QI 2 "immediate_operand" "i")] + UNSPEC_DSCLI))] + "TARGET_DFP" + "dscli %0,%1,%2" + [(set_attr "type" "fp")]) + +(define_insn "dfp_dscri_" + [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d") + (unspec:D64_D128 [(match_operand:D64_D128 1 "gpc_reg_operand" "d") + (match_operand:QI 2 "immediate_operand" "i")] + UNSPEC_DSCRI))] + "TARGET_DFP" + "dscri %0,%1,%2" + [(set_attr "type" "fp")]) diff --git a/gcc/config/rs6000/driver-rs6000.c b/gcc/config/rs6000/driver-rs6000.c index 2f4d1ead8f3c2..82455e7e79a69 100644 --- a/gcc/config/rs6000/driver-rs6000.c +++ b/gcc/config/rs6000/driver-rs6000.c @@ -1,5 +1,5 @@ /* Subroutines for the gcc driver. - Copyright (C) 2007-2013 Free Software Foundation, Inc. + Copyright (C) 2007-2015 Free Software Foundation, Inc. This file is part of GCC. @@ -327,6 +327,12 @@ detect_processor_aix (void) case 0x4000: return "power6"; + case 0x8000: + return "power7"; + + case 0x10000: + return "power8"; + default: return "powerpc"; } diff --git a/gcc/config/rs6000/freebsd64.h b/gcc/config/rs6000/freebsd64.h index b764f763dc2af..cab1f0094d996 100644 --- a/gcc/config/rs6000/freebsd64.h +++ b/gcc/config/rs6000/freebsd64.h @@ -367,7 +367,7 @@ extern int dot_symbols; /* PowerPC64 Linux word-aligns FP doubles when -malign-power is given. */ #undef ADJUST_FIELD_ALIGN #define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \ - ((TARGET_ALTIVEC && TREE_CODE (TREE_TYPE (FIELD)) == VECTOR_TYPE) \ + (rs6000_special_adjust_field_align_p ((FIELD), (COMPUTED)) \ ? 128 \ : (TARGET_64BIT \ && TARGET_ALIGN_NATURAL == 0 \ diff --git a/gcc/config/rs6000/htm.md b/gcc/config/rs6000/htm.md new file mode 100644 index 0000000000000..dbfd0db596212 --- /dev/null +++ b/gcc/config/rs6000/htm.md @@ -0,0 +1,161 @@ +;; Hardware Transactional Memory (HTM) patterns. +;; Copyright (C) 2013-2015 Free Software Foundation, Inc. +;; Contributed by Peter Bergner . + +;; This file is part of GCC. + +;; GCC is free software; you can redistribute it and/or modify it +;; under the terms of the GNU General Public License as published +;; by the Free Software Foundation; either version 3, or (at your +;; option) any later version. + +;; GCC is distributed in the hope that it will be useful, but WITHOUT +;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +;; License for more details. + +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; . + +(define_constants + [(TFHAR_SPR 128) + (TFIAR_SPR 129) + (TEXASR_SPR 130) + (TEXASRU_SPR 131) + (MAX_HTM_OPERANDS 4) + ]) + +;; +;; UNSPEC_VOLATILE usage +;; + +(define_c_enum "unspecv" + [UNSPECV_HTM_TABORT + UNSPECV_HTM_TABORTXC + UNSPECV_HTM_TABORTXCI + UNSPECV_HTM_TBEGIN + UNSPECV_HTM_TCHECK + UNSPECV_HTM_TEND + UNSPECV_HTM_TRECHKPT + UNSPECV_HTM_TRECLAIM + UNSPECV_HTM_TSR + UNSPECV_HTM_TTEST + UNSPECV_HTM_MFSPR + UNSPECV_HTM_MTSPR + ]) + + +(define_insn "tabort" + [(set (match_operand:CC 1 "cc_reg_operand" "=x") + (unspec_volatile:CC [(match_operand:SI 0 "gpc_reg_operand" "r")] + UNSPECV_HTM_TABORT))] + "TARGET_HTM" + "tabort. %0" + [(set_attr "type" "htm") + (set_attr "length" "4")]) + +(define_insn "tabortc" + [(set (match_operand:CC 3 "cc_reg_operand" "=x") + (unspec_volatile:CC [(match_operand 0 "u5bit_cint_operand" "n") + (match_operand:GPR 1 "gpc_reg_operand" "r") + (match_operand:GPR 2 "gpc_reg_operand" "r")] + UNSPECV_HTM_TABORTXC))] + "TARGET_HTM" + "tabortc. %0,%1,%2" + [(set_attr "type" "htm") + (set_attr "length" "4")]) + +(define_insn "tabortci" + [(set (match_operand:CC 3 "cc_reg_operand" "=x") + (unspec_volatile:CC [(match_operand 0 "u5bit_cint_operand" "n") + (match_operand:GPR 1 "gpc_reg_operand" "r") + (match_operand 2 "s5bit_cint_operand" "n")] + UNSPECV_HTM_TABORTXCI))] + "TARGET_HTM" + "tabortci. %0,%1,%2" + [(set_attr "type" "htm") + (set_attr "length" "4")]) + +(define_insn "tbegin" + [(set (match_operand:CC 1 "cc_reg_operand" "=x") + (unspec_volatile:CC [(match_operand 0 "const_0_to_1_operand" "n")] + UNSPECV_HTM_TBEGIN))] + "TARGET_HTM" + "tbegin. %0" + [(set_attr "type" "htm") + (set_attr "length" "4")]) + +(define_insn "tcheck" + [(set (match_operand:CC 0 "cc_reg_operand" "=y") + (unspec_volatile:CC [(const_int 0)] + UNSPECV_HTM_TCHECK))] + "TARGET_HTM" + "tcheck %0" + [(set_attr "type" "htm") + (set_attr "length" "4")]) + +(define_insn "tend" + [(set (match_operand:CC 1 "cc_reg_operand" "=x") + (unspec_volatile:CC [(match_operand 0 "const_0_to_1_operand" "n")] + UNSPECV_HTM_TEND))] + "TARGET_HTM" + "tend. %0" + [(set_attr "type" "htm") + (set_attr "length" "4")]) + +(define_insn "trechkpt" + [(set (match_operand:CC 0 "cc_reg_operand" "=x") + (unspec_volatile:CC [(const_int 0)] + UNSPECV_HTM_TRECHKPT))] + "TARGET_HTM" + "trechkpt." + [(set_attr "type" "htm") + (set_attr "length" "4")]) + +(define_insn "treclaim" + [(set (match_operand:CC 1 "cc_reg_operand" "=x") + (unspec_volatile:CC [(match_operand:SI 0 "gpc_reg_operand" "r")] + UNSPECV_HTM_TRECLAIM))] + "TARGET_HTM" + "treclaim. %0" + [(set_attr "type" "htm") + (set_attr "length" "4")]) + +(define_insn "tsr" + [(set (match_operand:CC 1 "cc_reg_operand" "=x") + (unspec_volatile:CC [(match_operand 0 "const_0_to_1_operand" "n")] + UNSPECV_HTM_TSR))] + "TARGET_HTM" + "tsr. %0" + [(set_attr "type" "htm") + (set_attr "length" "4")]) + +(define_insn "ttest" + [(set (match_operand:CC 0 "cc_reg_operand" "=x") + (unspec_volatile:CC [(const_int 0)] + UNSPECV_HTM_TTEST))] + "TARGET_HTM" + "tabortwci. 0,1,0" + [(set_attr "type" "htm") + (set_attr "length" "4")]) + +(define_insn "htm_mfspr_" + [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") + (unspec_volatile:GPR [(match_operand 1 "u10bit_cint_operand" "n") + (match_operand:GPR 2 "htm_spr_reg_operand" "")] + UNSPECV_HTM_MFSPR))] + "TARGET_HTM" + "mfspr %0,%1"; + [(set_attr "type" "htm") + (set_attr "length" "4")]) + +(define_insn "htm_mtspr_" + [(set (match_operand:GPR 2 "htm_spr_reg_operand" "") + (unspec_volatile:GPR [(match_operand:GPR 0 "gpc_reg_operand" "r") + (match_operand 1 "u10bit_cint_operand" "n")] + UNSPECV_HTM_MTSPR))] + "TARGET_HTM" + "mtspr %1,%0"; + [(set_attr "type" "htm") + (set_attr "length" "4")]) diff --git a/gcc/config/rs6000/htmintrin.h b/gcc/config/rs6000/htmintrin.h new file mode 100644 index 0000000000000..212cc92f85178 --- /dev/null +++ b/gcc/config/rs6000/htmintrin.h @@ -0,0 +1,131 @@ +/* Hardware Transactional Memory (HTM) intrinsics. + Copyright (C) 2013 Free Software Foundation, Inc. + Contributed by Peter Bergner . + + This file is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License as published by the Free + Software Foundation; either version 3 of the License, or (at your option) + any later version. + + This file is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + . */ + +#ifndef __HTM__ +# error "HTM instruction set not enabled" +#endif /* __HTM__ */ + +#ifndef _HTMINTRIN_H +#define _HTMINTRIN_H + +#include + +typedef uint64_t texasr_t; +typedef uint32_t texasru_t; +typedef uint32_t texasrl_t; +typedef uintptr_t tfiar_t; +typedef uintptr_t tfhar_t; + +#define _HTM_STATE(CR0) ((CR0 >> 1) & 0x3) +#define _HTM_NONTRANSACTIONAL 0x0 +#define _HTM_SUSPENDED 0x1 +#define _HTM_TRANSACTIONAL 0x2 + +/* The following macros use the IBM bit numbering for BITNUM + as used in the ISA documentation. */ + +#define _TEXASR_EXTRACT_BITS(TEXASR,BITNUM,SIZE) \ + (((TEXASR) >> (63-(BITNUM))) & ((1<<(SIZE))-1)) +#define _TEXASRU_EXTRACT_BITS(TEXASR,BITNUM,SIZE) \ + (((TEXASR) >> (31-(BITNUM))) & ((1<<(SIZE))-1)) + +#define _TEXASR_FAILURE_CODE(TEXASR) \ + _TEXASR_EXTRACT_BITS(TEXASR, 7, 8) +#define _TEXASRU_FAILURE_CODE(TEXASRU) \ + _TEXASRU_EXTRACT_BITS(TEXASRU, 7, 8) + +#define _TEXASR_FAILURE_PERSISTENT(TEXASR) \ + _TEXASR_EXTRACT_BITS(TEXASR, 7, 1) +#define _TEXASRU_FAILURE_PERSISTENT(TEXASRU) \ + _TEXASRU_EXTRACT_BITS(TEXASRU, 7, 1) + +#define _TEXASR_DISALLOWED(TEXASR) \ + _TEXASR_EXTRACT_BITS(TEXASR, 8, 1) +#define _TEXASRU_DISALLOWED(TEXASRU) \ + _TEXASRU_EXTRACT_BITS(TEXASRU, 8, 1) + +#define _TEXASR_NESTING_OVERFLOW(TEXASR) \ + _TEXASR_EXTRACT_BITS(TEXASR, 9, 1) +#define _TEXASRU_NESTING_OVERFLOW(TEXASRU) \ + _TEXASRU_EXTRACT_BITS(TEXASRU, 9, 1) + +#define _TEXASR_FOOTPRINT_OVERFLOW(TEXASR) \ + _TEXASR_EXTRACT_BITS(TEXASR, 10, 1) +#define _TEXASRU_FOOTPRINT_OVERFLOW(TEXASRU) \ + _TEXASRU_EXTRACT_BITS(TEXASRU, 10, 1) + +#define _TEXASR_SELF_INDUCED_CONFLICT(TEXASR) \ + _TEXASR_EXTRACT_BITS(TEXASR, 11, 1) +#define _TEXASRU_SELF_INDUCED_CONFLICT(TEXASRU) \ + _TEXASRU_EXTRACT_BITS(TEXASRU, 11, 1) + +#define _TEXASR_NON_TRANSACTIONAL_CONFLICT(TEXASR) \ + _TEXASR_EXTRACT_BITS(TEXASR, 12, 1) +#define _TEXASRU_NON_TRANSACTIONAL_CONFLICT(TEXASRU) \ + _TEXASRU_EXTRACT_BITS(TEXASRU, 12, 1) + +#define _TEXASR_TRANSACTION_CONFLICT(TEXASR) \ + _TEXASR_EXTRACT_BITS(TEXASR, 13, 1) +#define _TEXASRU_TRANSACTION_CONFLICT(TEXASRU) \ + _TEXASRU_EXTRACT_BITS(TEXASRU, 13, 1) + +#define _TEXASR_TRANSLATION_INVALIDATION_CONFLICT(TEXASR) \ + _TEXASR_EXTRACT_BITS(TEXASR, 14, 1) +#define _TEXASRU_TRANSLATION_INVALIDATION_CONFLICT(TEXASRU) \ + _TEXASRU_EXTRACT_BITS(TEXASRU, 14, 1) + +#define _TEXASR_IMPLEMENTAION_SPECIFIC(TEXASR) \ + _TEXASR_EXTRACT_BITS(TEXASR, 15, 1) +#define _TEXASRU_IMPLEMENTAION_SPECIFIC(TEXASRU) \ + _TEXASRU_EXTRACT_BITS(TEXASRU, 15, 1) + +#define _TEXASR_INSTRUCTION_FETCH_CONFLICT(TEXASR) \ + _TEXASR_EXTRACT_BITS(TEXASR, 16, 1) +#define _TEXASRU_INSTRUCTION_FETCH_CONFLICT(TEXASRU) \ + _TEXASRU_EXTRACT_BITS(TEXASRU, 16, 1) + +#define _TEXASR_ABORT(TEXASR) \ + _TEXASR_EXTRACT_BITS(TEXASR, 31, 1) +#define _TEXASRU_ABORT(TEXASRU) \ + _TEXASRU_EXTRACT_BITS(TEXASRU, 31, 1) + + +#define _TEXASR_SUSPENDED(TEXASR) \ + _TEXASR_EXTRACT_BITS(TEXASR, 32, 1) + +#define _TEXASR_PRIVILEGE(TEXASR) \ + _TEXASR_EXTRACT_BITS(TEXASR, 35, 2) + +#define _TEXASR_FAILURE_SUMMARY(TEXASR) \ + _TEXASR_EXTRACT_BITS(TEXASR, 36, 1) + +#define _TEXASR_TFIAR_EXACT(TEXASR) \ + _TEXASR_EXTRACT_BITS(TEXASR, 37, 1) + +#define _TEXASR_ROT(TEXASR) \ + _TEXASR_EXTRACT_BITS(TEXASR, 38, 1) + +#define _TEXASR_TRANSACTION_LEVEL(TEXASR) \ + _TEXASR_EXTRACT_BITS(TEXASR, 63, 12) + +#endif /* _HTMINTRIN_H */ diff --git a/gcc/config/rs6000/htmxlintrin.h b/gcc/config/rs6000/htmxlintrin.h new file mode 100644 index 0000000000000..24721b3102d56 --- /dev/null +++ b/gcc/config/rs6000/htmxlintrin.h @@ -0,0 +1,214 @@ +/* XL compiler Hardware Transactional Memory (HTM) execution intrinsics. + Copyright (C) 2013 Free Software Foundation, Inc. + Contributed by Peter Bergner . + + This file is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License as published by the Free + Software Foundation; either version 3 of the License, or (at your option) + any later version. + + This file is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + . */ + +#ifndef __HTM__ +# error "HTM instruction set not enabled" +#endif /* __HTM__ */ + +#ifndef _HTMXLINTRIN_H +#define _HTMXLINTRIN_H + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define _TEXASR_PTR(TM_BUF) \ + ((texasr_t *)((TM_BUF)+0)) +#define _TEXASRU_PTR(TM_BUF) \ + ((texasru_t *)((TM_BUF)+0)) +#define _TEXASRL_PTR(TM_BUF) \ + ((texasrl_t *)((TM_BUF)+4)) +#define _TFIAR_PTR(TM_BUF) \ + ((tfiar_t *)((TM_BUF)+8)) + +typedef char TM_buff_type[16]; + +/* Compatibility macro with s390. This macro can be used to determine + whether a transaction was successfully started from the __TM_begin() + and __TM_simple_begin() intrinsic functions below. */ +#define _HTM_TBEGIN_STARTED 1 + +extern __inline long +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +__TM_simple_begin (void) +{ + if (__builtin_expect (__builtin_tbegin (0), 1)) + return _HTM_TBEGIN_STARTED; + return 0; +} + +extern __inline long +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +__TM_begin (void* const TM_buff) +{ + *_TEXASRL_PTR (TM_buff) = 0; + if (__builtin_expect (__builtin_tbegin (0), 1)) + return _HTM_TBEGIN_STARTED; +#ifdef __powerpc64__ + *_TEXASR_PTR (TM_buff) = __builtin_get_texasr (); +#else + *_TEXASRU_PTR (TM_buff) = __builtin_get_texasru (); + *_TEXASRL_PTR (TM_buff) = __builtin_get_texasr (); +#endif + *_TFIAR_PTR (TM_buff) = __builtin_get_tfiar (); + return 0; +} + +extern __inline long +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +__TM_end (void) +{ + unsigned char status = _HTM_STATE (__builtin_tend (0)); + if (__builtin_expect (status, _HTM_TRANSACTIONAL)) + return 1; + return 0; +} + +extern __inline void +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +__TM_abort (void) +{ + __builtin_tabort (0); +} + +extern __inline void +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +__TM_named_abort (unsigned char const code) +{ + __builtin_tabort (code); +} + +extern __inline void +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +__TM_resume (void) +{ + __builtin_tresume (); +} + +extern __inline void +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +__TM_suspend (void) +{ + __builtin_tsuspend (); +} + +extern __inline long +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +__TM_is_user_abort (void* const TM_buff) +{ + texasru_t texasru = *_TEXASRU_PTR (TM_buff); + return _TEXASRU_ABORT (texasru); +} + +extern __inline long +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +__TM_is_named_user_abort (void* const TM_buff, unsigned char *code) +{ + texasru_t texasru = *_TEXASRU_PTR (TM_buff); + + *code = _TEXASRU_FAILURE_CODE (texasru); + return _TEXASRU_ABORT (texasru); +} + +extern __inline long +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +__TM_is_illegal (void* const TM_buff) +{ + texasru_t texasru = *_TEXASRU_PTR (TM_buff); + return _TEXASRU_DISALLOWED (texasru); +} + +extern __inline long +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +__TM_is_footprint_exceeded (void* const TM_buff) +{ + texasru_t texasru = *_TEXASRU_PTR (TM_buff); + return _TEXASRU_FOOTPRINT_OVERFLOW (texasru); +} + +extern __inline long +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +__TM_nesting_depth (void* const TM_buff) +{ + texasrl_t texasrl; + + if (_HTM_STATE (__builtin_ttest ()) == _HTM_NONTRANSACTIONAL) + { + texasrl = *_TEXASRL_PTR (TM_buff); + if (!_TEXASR_FAILURE_SUMMARY (texasrl)) + texasrl = 0; + } + else + texasrl = (texasrl_t) __builtin_get_texasr (); + + return _TEXASR_TRANSACTION_LEVEL (texasrl); +} + +extern __inline long +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +__TM_is_nested_too_deep(void* const TM_buff) +{ + texasru_t texasru = *_TEXASRU_PTR (TM_buff); + return _TEXASRU_NESTING_OVERFLOW (texasru); +} + +extern __inline long +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +__TM_is_conflict(void* const TM_buff) +{ + texasru_t texasru = *_TEXASRU_PTR (TM_buff); + /* Return TEXASR bits 11 (Self-Induced Conflict) through + 14 (Translation Invalidation Conflict). */ + return (_TEXASRU_EXTRACT_BITS (texasru, 14, 4)) ? 1 : 0; +} + +extern __inline long +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +__TM_is_failure_persistent(void* const TM_buff) +{ + texasru_t texasru = *_TEXASRU_PTR (TM_buff); + return _TEXASRU_FAILURE_PERSISTENT (texasru); +} + +extern __inline long +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +__TM_failure_address(void* const TM_buff) +{ + return *_TFIAR_PTR (TM_buff); +} + +extern __inline long long +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +__TM_failure_code(void* const TM_buff) +{ + return *_TEXASR_PTR (TM_buff); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HTMXLINTRIN_H */ diff --git a/gcc/config/rs6000/linux.h b/gcc/config/rs6000/linux.h index 8ec3548c21abe..f7f2d80c4f2b0 100644 --- a/gcc/config/rs6000/linux.h +++ b/gcc/config/rs6000/linux.h @@ -79,6 +79,24 @@ #undef LINK_OS_DEFAULT_SPEC #define LINK_OS_DEFAULT_SPEC "%(link_os_linux)" +#undef DEFAULT_ASM_ENDIAN +#if (TARGET_DEFAULT & MASK_LITTLE_ENDIAN) +#define DEFAULT_ASM_ENDIAN " -mlittle" +#define LINK_OS_LINUX_EMUL ENDIAN_SELECT(" -m elf32ppclinux", \ + " -m elf32lppclinux", \ + " -m elf32lppclinux") +#else +#define DEFAULT_ASM_ENDIAN " -mbig" +#define LINK_OS_LINUX_EMUL ENDIAN_SELECT(" -m elf32ppclinux", \ + " -m elf32lppclinux", \ + " -m elf32ppclinux") +#endif + +#undef LINK_OS_LINUX_SPEC +#define LINK_OS_LINUX_SPEC LINK_OS_LINUX_EMUL " %{!shared: %{!static: \ + %{rdynamic:-export-dynamic} \ + -dynamic-linker " GNU_USER_DYNAMIC_LINKER "}}" + #define LINK_GCC_C_SEQUENCE_SPEC \ "%{static:--start-group} %G %L %{static:--end-group}%{!static:%G}" diff --git a/gcc/config/rs6000/linux64.h b/gcc/config/rs6000/linux64.h index dc6f67fcc11af..aa74e68393e81 100644 --- a/gcc/config/rs6000/linux64.h +++ b/gcc/config/rs6000/linux64.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler, for 64 bit PowerPC linux. - Copyright (C) 2000-2013 Free Software Foundation, Inc. + Copyright (C) 2000-2015 Free Software Foundation, Inc. This file is part of GCC. @@ -25,9 +25,6 @@ #ifndef RS6000_BI_ARCH -#undef DEFAULT_ABI -#define DEFAULT_ABI ABI_AIX - #undef TARGET_64BIT #define TARGET_64BIT 1 @@ -74,7 +71,7 @@ extern int dot_symbols; #undef PROCESSOR_DEFAULT #define PROCESSOR_DEFAULT PROCESSOR_POWER7 #undef PROCESSOR_DEFAULT64 -#define PROCESSOR_DEFAULT64 PROCESSOR_POWER7 +#define PROCESSOR_DEFAULT64 PROCESSOR_POWER8 /* We don't need to generate entries in .fixup, except when -mrelocatable or -mrelocatable-lib is given. */ @@ -88,13 +85,19 @@ extern int dot_symbols; #define INVALID_64BIT "-m%s not supported in this configuration" #define INVALID_32BIT INVALID_64BIT +#ifdef LINUX64_DEFAULT_ABI_ELFv2 +#define ELFv2_ABI_CHECK (rs6000_elf_abi != 1) +#else +#define ELFv2_ABI_CHECK (rs6000_elf_abi == 2) +#endif + #undef SUBSUBTARGET_OVERRIDE_OPTIONS #define SUBSUBTARGET_OVERRIDE_OPTIONS \ do \ { \ if (!global_options_set.x_rs6000_alignment_flags) \ rs6000_alignment_flags = MASK_ALIGN_NATURAL; \ - if (TARGET_64BIT) \ + if (rs6000_isa_flags & OPTION_MASK_64BIT) \ { \ if (DEFAULT_ABI != ABI_AIX) \ { \ @@ -102,6 +105,12 @@ extern int dot_symbols; error (INVALID_64BIT, "call"); \ } \ dot_symbols = !strcmp (rs6000_abi_name, "aixdesc"); \ + if (ELFv2_ABI_CHECK) \ + { \ + rs6000_current_abi = ABI_ELFv2; \ + if (dot_symbols) \ + error ("-mcall-aixdesc incompatible with -mabi=elfv2"); \ + } \ if (rs6000_isa_flags & OPTION_MASK_RELOCATABLE) \ { \ rs6000_isa_flags &= ~OPTION_MASK_RELOCATABLE; \ @@ -136,8 +145,11 @@ extern int dot_symbols; SET_CMODEL (CMODEL_MEDIUM); \ if (rs6000_current_cmodel != CMODEL_SMALL) \ { \ - TARGET_NO_FP_IN_TOC = 0; \ - TARGET_NO_SUM_IN_TOC = 0; \ + if (!global_options_set.x_TARGET_NO_FP_IN_TOC) \ + TARGET_NO_FP_IN_TOC \ + = rs6000_current_cmodel == CMODEL_MEDIUM; \ + if (!global_options_set.x_TARGET_NO_SUM_IN_TOC) \ + TARGET_NO_SUM_IN_TOC = 0; \ } \ } \ } \ @@ -180,20 +192,14 @@ extern int dot_symbols; #endif #define ASM_SPEC32 "-a32 \ -%{mrelocatable} %{mrelocatable-lib} %{fpic:-K PIC} %{fPIC:-K PIC} \ -%{memb} %{!memb: %{msdata=eabi: -memb}} \ -%{!mlittle: %{!mlittle-endian: %{!mbig: %{!mbig-endian: \ - %{mcall-freebsd: -mbig} \ - %{mcall-i960-old: -mlittle} \ - %{mcall-linux: -mbig} \ - %{mcall-netbsd: -mbig} \ -}}}}" +%{mrelocatable} %{mrelocatable-lib} %{fpic|fpie|fPIC|fPIE:-K PIC} \ +%{memb|msdata=eabi: -memb}" #define ASM_SPEC64 "-a64" #define ASM_SPEC_COMMON "%(asm_cpu) \ -%{,assembler|,assembler-with-cpp: %{mregnames} %{mno-regnames}} \ -%{mlittle} %{mlittle-endian} %{mbig} %{mbig-endian}" +%{,assembler|,assembler-with-cpp: %{mregnames} %{mno-regnames}}" \ + ENDIAN_SELECT(" -mbig", " -mlittle", DEFAULT_ASM_ENDIAN) #undef SUBSUBTARGET_EXTRA_SPECS #define SUBSUBTARGET_EXTRA_SPECS \ @@ -212,10 +218,6 @@ extern int dot_symbols; #ifndef RS6000_BI_ARCH -/* 64-bit PowerPC Linux is always big-endian. */ -#undef OPTION_LITTLE_ENDIAN -#define OPTION_LITTLE_ENDIAN 0 - /* 64-bit PowerPC Linux always has a TOC. */ #undef TARGET_TOC #define TARGET_TOC 1 @@ -240,7 +242,7 @@ extern int dot_symbols; /* PowerPC64 Linux word-aligns FP doubles when -malign-power is given. */ #undef ADJUST_FIELD_ALIGN #define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \ - ((TARGET_ALTIVEC && TREE_CODE (TREE_TYPE (FIELD)) == VECTOR_TYPE) \ + (rs6000_special_adjust_field_align_p ((FIELD), (COMPUTED)) \ ? 128 \ : (TARGET_64BIT \ && TARGET_ALIGN_NATURAL == 0 \ @@ -361,7 +363,11 @@ extern int dot_symbols; #define LINK_OS_DEFAULT_SPEC "%(link_os_linux)" #define GLIBC_DYNAMIC_LINKER32 "/lib/ld.so.1" -#define GLIBC_DYNAMIC_LINKER64 "/lib64/ld64.so.1" +#ifdef LINUX64_DEFAULT_ABI_ELFv2 +#define GLIBC_DYNAMIC_LINKER64 "%{mabi=elfv1:/lib64/ld64.so.1;:/lib64/ld64.so.2}" +#else +#define GLIBC_DYNAMIC_LINKER64 "%{mabi=elfv2:/lib64/ld64.so.2;:/lib64/ld64.so.1}" +#endif #define UCLIBC_DYNAMIC_LINKER32 "/lib/ld-uClibc.so.0" #define UCLIBC_DYNAMIC_LINKER64 "/lib/ld64-uClibc.so.0" #if DEFAULT_LIBC == LIBC_UCLIBC @@ -376,12 +382,30 @@ extern int dot_symbols; #define GNU_USER_DYNAMIC_LINKER64 \ CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER64, UCLIBC_DYNAMIC_LINKER64) +#undef DEFAULT_ASM_ENDIAN +#if (TARGET_DEFAULT & MASK_LITTLE_ENDIAN) +#define DEFAULT_ASM_ENDIAN " -mlittle" +#define LINK_OS_LINUX_EMUL32 ENDIAN_SELECT(" -m elf32ppclinux", \ + " -m elf32lppclinux", \ + " -m elf32lppclinux") +#define LINK_OS_LINUX_EMUL64 ENDIAN_SELECT(" -m elf64ppc", \ + " -m elf64lppc", \ + " -m elf64lppc") +#else +#define DEFAULT_ASM_ENDIAN " -mbig" +#define LINK_OS_LINUX_EMUL32 ENDIAN_SELECT(" -m elf32ppclinux", \ + " -m elf32lppclinux", \ + " -m elf32ppclinux") +#define LINK_OS_LINUX_EMUL64 ENDIAN_SELECT(" -m elf64ppc", \ + " -m elf64lppc", \ + " -m elf64ppc") +#endif -#define LINK_OS_LINUX_SPEC32 "-m elf32ppclinux %{!shared: %{!static: \ +#define LINK_OS_LINUX_SPEC32 LINK_OS_LINUX_EMUL32 " %{!shared: %{!static: \ %{rdynamic:-export-dynamic} \ -dynamic-linker " GNU_USER_DYNAMIC_LINKER32 "}}" -#define LINK_OS_LINUX_SPEC64 "-m elf64ppc %{!shared: %{!static: \ +#define LINK_OS_LINUX_SPEC64 LINK_OS_LINUX_EMUL64 " %{!shared: %{!static: \ %{rdynamic:-export-dynamic} \ -dynamic-linker " GNU_USER_DYNAMIC_LINKER64 "}}" diff --git a/gcc/config/rs6000/linuxaltivec.h b/gcc/config/rs6000/linuxaltivec.h index 632f58d5bafdd..f778dd8f73796 100644 --- a/gcc/config/rs6000/linuxaltivec.h +++ b/gcc/config/rs6000/linuxaltivec.h @@ -20,8 +20,13 @@ . */ /* Override rs6000.h and sysv4.h definition. */ +#if (TARGET_DEFAULT & MASK_LITTLE_ENDIAN) +#undef TARGET_DEFAULT +#define TARGET_DEFAULT (MASK_ALTIVEC | MASK_LITTLE_ENDIAN) +#else #undef TARGET_DEFAULT #define TARGET_DEFAULT MASK_ALTIVEC +#endif #undef SUBSUBTARGET_OVERRIDE_OPTIONS #define SUBSUBTARGET_OVERRIDE_OPTIONS rs6000_altivec_abi = 1 diff --git a/gcc/config/rs6000/linuxspe.h b/gcc/config/rs6000/linuxspe.h index 99b8c73716df3..54b0d11595037 100644 --- a/gcc/config/rs6000/linuxspe.h +++ b/gcc/config/rs6000/linuxspe.h @@ -20,8 +20,13 @@ . */ /* Override rs6000.h and sysv4.h definition. */ +#if (TARGET_DEFAULT & MASK_LITTLE_ENDIAN) +#undef TARGET_DEFAULT +#define TARGET_DEFAULT (MASK_STRICT_ALIGN | MASK_LITTLE_ENDIAN) +#else #undef TARGET_DEFAULT #define TARGET_DEFAULT MASK_STRICT_ALIGN +#endif #undef ASM_DEFAULT_SPEC #define ASM_DEFAULT_SPEC "-mppc -mspe -me500" diff --git a/gcc/config/rs6000/option-defaults.h b/gcc/config/rs6000/option-defaults.h index 2d7e36a6137d1..0d7ba1ea3ac41 100644 --- a/gcc/config/rs6000/option-defaults.h +++ b/gcc/config/rs6000/option-defaults.h @@ -54,6 +54,7 @@ --with-float is ignored if -mhard-float or -msoft-float are specified. */ #define OPTION_DEFAULT_SPECS \ + {"abi", "%{!mabi=elfv*:-mabi=%(VALUE)}" }, \ {"tune", "%{!mtune=*:%{!mcpu=*:-mtune=%(VALUE)}}" }, \ {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:-mtune=%(VALUE)}}}" }, \ {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:-mtune=%(VALUE)}}}" }, \ diff --git a/gcc/config/rs6000/power8.md b/gcc/config/rs6000/power8.md new file mode 100644 index 0000000000000..83bf71974830b --- /dev/null +++ b/gcc/config/rs6000/power8.md @@ -0,0 +1,373 @@ +;; Scheduling description for IBM POWER8 processor. +;; Copyright (C) 2013 Free Software Foundation, Inc. +;; +;; Contributed by Pat Haugen (pthaugen@us.ibm.com). + +;; This file is part of GCC. +;; +;; GCC is free software; you can redistribute it and/or modify it +;; under the terms of the GNU General Public License as published +;; by the Free Software Foundation; either version 3, or (at your +;; option) any later version. +;; +;; GCC is distributed in the hope that it will be useful, but WITHOUT +;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +;; License for more details. +;; +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; . + +(define_automaton "power8fxu,power8lsu,power8vsu,power8misc") + +(define_cpu_unit "fxu0_power8,fxu1_power8" "power8fxu") +(define_cpu_unit "lu0_power8,lu1_power8" "power8lsu") +(define_cpu_unit "lsu0_power8,lsu1_power8" "power8lsu") +(define_cpu_unit "vsu0_power8,vsu1_power8" "power8vsu") +(define_cpu_unit "bpu_power8,cru_power8" "power8misc") +(define_cpu_unit "du0_power8,du1_power8,du2_power8,du3_power8,du4_power8,\ + du5_power8,du6_power8" "power8misc") + + +; Dispatch group reservations +(define_reservation "DU_any_power8" + "du0_power8|du1_power8|du2_power8|du3_power8|du4_power8|\ + du5_power8") + +; 2-way Cracked instructions go in slots 0-1 +; (can also have a second in slots 3-4 if insns are adjacent) +(define_reservation "DU_cracked_power8" + "du0_power8+du1_power8") + +; Insns that are first in group +(define_reservation "DU_first_power8" + "du0_power8") + +; Insns that are first and last in group +(define_reservation "DU_both_power8" + "du0_power8+du1_power8+du2_power8+du3_power8+du4_power8+\ + du5_power8+du6_power8") + +; Dispatch slots are allocated in order conforming to program order. +(absence_set "du0_power8" "du1_power8,du2_power8,du3_power8,du4_power8,\ + du5_power8,du6_power8") +(absence_set "du1_power8" "du2_power8,du3_power8,du4_power8,du5_power8,\ + du6_power8") +(absence_set "du2_power8" "du3_power8,du4_power8,du5_power8,du6_power8") +(absence_set "du3_power8" "du4_power8,du5_power8,du6_power8") +(absence_set "du4_power8" "du5_power8,du6_power8") +(absence_set "du5_power8" "du6_power8") + + +; Execution unit reservations +(define_reservation "FXU_power8" + "fxu0_power8|fxu1_power8") + +(define_reservation "LU_power8" + "lu0_power8|lu1_power8") + +(define_reservation "LSU_power8" + "lsu0_power8|lsu1_power8") + +(define_reservation "LU_or_LSU_power8" + "lu0_power8|lu1_power8|lsu0_power8|lsu1_power8") + +(define_reservation "VSU_power8" + "vsu0_power8|vsu1_power8") + + +; LS Unit +(define_insn_reservation "power8-load" 3 + (and (eq_attr "type" "load") + (eq_attr "cpu" "power8")) + "DU_any_power8,LU_or_LSU_power8") + +(define_insn_reservation "power8-load-update" 3 + (and (eq_attr "type" "load_u,load_ux") + (eq_attr "cpu" "power8")) + "DU_cracked_power8,LU_or_LSU_power8+FXU_power8") + +(define_insn_reservation "power8-load-ext" 3 + (and (eq_attr "type" "load_ext") + (eq_attr "cpu" "power8")) + "DU_cracked_power8,LU_or_LSU_power8,FXU_power8") + +(define_insn_reservation "power8-load-ext-update" 3 + (and (eq_attr "type" "load_ext_u,load_ext_ux") + (eq_attr "cpu" "power8")) + "DU_both_power8,LU_or_LSU_power8+FXU_power8,FXU_power8") + +(define_insn_reservation "power8-fpload" 5 + (and (eq_attr "type" "fpload,vecload") + (eq_attr "cpu" "power8")) + "DU_any_power8,LU_power8") + +(define_insn_reservation "power8-fpload-update" 5 + (and (eq_attr "type" "fpload_u,fpload_ux") + (eq_attr "cpu" "power8")) + "DU_cracked_power8,LU_power8+FXU_power8") + +(define_insn_reservation "power8-store" 5 ; store-forwarding latency + (and (eq_attr "type" "store,store_u") + (eq_attr "cpu" "power8")) + "DU_any_power8,LSU_power8+LU_power8") + +(define_insn_reservation "power8-store-update-indexed" 5 + (and (eq_attr "type" "store_ux") + (eq_attr "cpu" "power8")) + "DU_cracked_power8,LSU_power8+LU_power8") + +(define_insn_reservation "power8-fpstore" 5 + (and (eq_attr "type" "fpstore") + (eq_attr "cpu" "power8")) + "DU_any_power8,LSU_power8+VSU_power8") + +(define_insn_reservation "power8-fpstore-update" 5 + (and (eq_attr "type" "fpstore_u,fpstore_ux") + (eq_attr "cpu" "power8")) + "DU_any_power8,LSU_power8+VSU_power8") + +(define_insn_reservation "power8-vecstore" 5 + (and (eq_attr "type" "vecstore") + (eq_attr "cpu" "power8")) + "DU_cracked_power8,LSU_power8+VSU_power8") + +(define_insn_reservation "power8-larx" 3 + (and (eq_attr "type" "load_l") + (eq_attr "cpu" "power8")) + "DU_both_power8,LU_or_LSU_power8") + +(define_insn_reservation "power8-stcx" 10 + (and (eq_attr "type" "store_c") + (eq_attr "cpu" "power8")) + "DU_both_power8,LSU_power8+LU_power8") + +(define_insn_reservation "power8-sync" 1 + (and (eq_attr "type" "sync,isync") + (eq_attr "cpu" "power8")) + "DU_both_power8,LSU_power8") + + +; FX Unit +(define_insn_reservation "power8-1cyc" 1 + (and (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\ + var_shift_rotate,exts,isel") + (eq_attr "cpu" "power8")) + "DU_any_power8,FXU_power8") + +; Extra cycle to LU/LSU +(define_bypass 2 "power8-1cyc" + "power8-load*,power8-fpload*,power8-store*,power8-fpstore*,\ + power8-vecstore,power8-larx,power8-stcx") +; "power8-load,power8-load-update,power8-load-ext,\ +; power8-load-ext-update,power8-fpload,power8-fpload-update,\ +; power8-store,power8-store-update,power8-store-update-indexed,\ +; power8-fpstore,power8-fpstore-update,power8-vecstore,\ +; power8-larx,power8-stcx") + +(define_insn_reservation "power8-2cyc" 2 + (and (eq_attr "type" "cntlz,popcnt") + (eq_attr "cpu" "power8")) + "DU_any_power8,FXU_power8") + +(define_insn_reservation "power8-two" 2 + (and (eq_attr "type" "two") + (eq_attr "cpu" "power8")) + "DU_any_power8+DU_any_power8,FXU_power8,FXU_power8") + +(define_insn_reservation "power8-three" 3 + (and (eq_attr "type" "three") + (eq_attr "cpu" "power8")) + "DU_any_power8+DU_any_power8+DU_any_power8,FXU_power8,FXU_power8,FXU_power8") + +; cmp - Normal compare insns +(define_insn_reservation "power8-cmp" 2 + (and (eq_attr "type" "cmp") + (eq_attr "cpu" "power8")) + "DU_any_power8,FXU_power8") + +; fast_compare : add./and./nor./etc +(define_insn_reservation "power8-fast-compare" 2 + (and (eq_attr "type" "fast_compare") + (eq_attr "cpu" "power8")) + "DU_any_power8,FXU_power8") + +; compare : rldicl./exts./etc +; delayed_compare : rlwinm./slwi./etc +; var_delayed_compare : rlwnm./slw./etc +(define_insn_reservation "power8-compare" 2 + (and (eq_attr "type" "compare,delayed_compare,var_delayed_compare") + (eq_attr "cpu" "power8")) + "DU_cracked_power8,FXU_power8,FXU_power8") + +; Extra cycle to LU/LSU +(define_bypass 3 "power8-fast-compare,power8-compare" + "power8-load*,power8-fpload*,power8-store*,power8-fpstore*,\ + power8-vecstore,power8-larx,power8-stcx") + +; 5 cycle CR latency +(define_bypass 5 "power8-fast-compare,power8-compare" + "power8-crlogical,power8-mfcr,power8-mfcrf,power8-branch") + +(define_insn_reservation "power8-mul" 4 + (and (eq_attr "type" "imul,imul2,imul3,lmul") + (eq_attr "cpu" "power8")) + "DU_any_power8,FXU_power8") + +(define_insn_reservation "power8-mul-compare" 4 + (and (eq_attr "type" "imul_compare,lmul_compare") + (eq_attr "cpu" "power8")) + "DU_cracked_power8,FXU_power8") + +; Extra cycle to LU/LSU +(define_bypass 5 "power8-mul,power8-mul-compare" + "power8-load*,power8-fpload*,power8-store*,power8-fpstore*,\ + power8-vecstore,power8-larx,power8-stcx") + +; 7 cycle CR latency +(define_bypass 7 "power8-mul,power8-mul-compare" + "power8-crlogical,power8-mfcr,power8-mfcrf,power8-branch") + +; FXU divides are not pipelined +(define_insn_reservation "power8-idiv" 37 + (and (eq_attr "type" "idiv") + (eq_attr "cpu" "power8")) + "DU_any_power8,fxu0_power8*37|fxu1_power8*37") + +(define_insn_reservation "power8-ldiv" 68 + (and (eq_attr "type" "ldiv") + (eq_attr "cpu" "power8")) + "DU_any_power8,fxu0_power8*68|fxu1_power8*68") + +(define_insn_reservation "power8-mtjmpr" 5 + (and (eq_attr "type" "mtjmpr") + (eq_attr "cpu" "power8")) + "DU_first_power8,FXU_power8") + +; Should differentiate between 1 cr field and > 1 since mtocrf is not microcode +(define_insn_reservation "power8-mtcr" 3 + (and (eq_attr "type" "mtcr") + (eq_attr "cpu" "power8")) + "DU_both_power8,FXU_power8") + + +; CR Unit +(define_insn_reservation "power8-mfjmpr" 5 + (and (eq_attr "type" "mfjmpr") + (eq_attr "cpu" "power8")) + "DU_first_power8,cru_power8+FXU_power8") + +(define_insn_reservation "power8-crlogical" 3 + (and (eq_attr "type" "cr_logical,delayed_cr") + (eq_attr "cpu" "power8")) + "DU_first_power8,cru_power8") + +(define_insn_reservation "power8-mfcr" 5 + (and (eq_attr "type" "mfcr") + (eq_attr "cpu" "power8")) + "DU_both_power8,cru_power8") + +(define_insn_reservation "power8-mfcrf" 3 + (and (eq_attr "type" "mfcrf") + (eq_attr "cpu" "power8")) + "DU_first_power8,cru_power8") + + +; BR Unit +; Branches take dispatch slot 7, but reserve any remaining prior slots to +; prevent other insns from grabbing them once this is assigned. +(define_insn_reservation "power8-branch" 3 + (and (eq_attr "type" "jmpreg,branch") + (eq_attr "cpu" "power8")) + "(du6_power8\ + |du5_power8+du6_power8\ + |du4_power8+du5_power8+du6_power8\ + |du3_power8+du4_power8+du5_power8+du6_power8\ + |du2_power8+du3_power8+du4_power8+du5_power8+du6_power8\ + |du1_power8+du2_power8+du3_power8+du4_power8+du5_power8+du6_power8\ + |du0_power8+du1_power8+du2_power8+du3_power8+du4_power8+du5_power8+\ + du6_power8),bpu_power8") + +; Branch updating LR/CTR feeding mf[lr|ctr] +(define_bypass 4 "power8-branch" "power8-mfjmpr") + + +; VS Unit (includes FP/VSX/VMX/DFP/Crypto) +(define_insn_reservation "power8-fp" 6 + (and (eq_attr "type" "fp,dmul") + (eq_attr "cpu" "power8")) + "DU_any_power8,VSU_power8") + +; Additional 3 cycles for any CR result +(define_bypass 9 "power8-fp" "power8-crlogical,power8-mfcr*,power8-branch") + +(define_insn_reservation "power8-fpcompare" 8 + (and (eq_attr "type" "fpcompare") + (eq_attr "cpu" "power8")) + "DU_any_power8,VSU_power8") + +(define_insn_reservation "power8-sdiv" 27 + (and (eq_attr "type" "sdiv") + (eq_attr "cpu" "power8")) + "DU_any_power8,VSU_power8") + +(define_insn_reservation "power8-ddiv" 33 + (and (eq_attr "type" "ddiv") + (eq_attr "cpu" "power8")) + "DU_any_power8,VSU_power8") + +(define_insn_reservation "power8-sqrt" 32 + (and (eq_attr "type" "ssqrt") + (eq_attr "cpu" "power8")) + "DU_any_power8,VSU_power8") + +(define_insn_reservation "power8-dsqrt" 44 + (and (eq_attr "type" "dsqrt") + (eq_attr "cpu" "power8")) + "DU_any_power8,VSU_power8") + +(define_insn_reservation "power8-vecsimple" 2 + (and (eq_attr "type" "vecperm,vecsimple,veccmp") + (eq_attr "cpu" "power8")) + "DU_any_power8,VSU_power8") + +(define_insn_reservation "power8-vecnormal" 6 + (and (eq_attr "type" "vecfloat,vecdouble") + (eq_attr "cpu" "power8")) + "DU_any_power8,VSU_power8") + +(define_bypass 7 "power8-vecnormal" + "power8-vecsimple,power8-veccomplex,power8-fpstore*,\ + power8-vecstore") + +(define_insn_reservation "power8-veccomplex" 7 + (and (eq_attr "type" "veccomplex") + (eq_attr "cpu" "power8")) + "DU_any_power8,VSU_power8") + +(define_insn_reservation "power8-vecfdiv" 25 + (and (eq_attr "type" "vecfdiv") + (eq_attr "cpu" "power8")) + "DU_any_power8,VSU_power8") + +(define_insn_reservation "power8-vecdiv" 31 + (and (eq_attr "type" "vecdiv") + (eq_attr "cpu" "power8")) + "DU_any_power8,VSU_power8") + +(define_insn_reservation "power8-mffgpr" 5 + (and (eq_attr "type" "mffgpr") + (eq_attr "cpu" "power8")) + "DU_any_power8,VSU_power8") + +(define_insn_reservation "power8-mftgpr" 6 + (and (eq_attr "type" "mftgpr") + (eq_attr "cpu" "power8")) + "DU_any_power8,VSU_power8") + +(define_insn_reservation "power8-crypto" 7 + (and (eq_attr "type" "crypto") + (eq_attr "cpu" "power8")) + "DU_any_power8,VSU_power8") + diff --git a/gcc/config/rs6000/ppc-asm.h b/gcc/config/rs6000/ppc-asm.h index db490b6c9b825..8108efd07f5b4 100644 --- a/gcc/config/rs6000/ppc-asm.h +++ b/gcc/config/rs6000/ppc-asm.h @@ -256,7 +256,30 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see * the real function with one or two leading periods respectively. */ -#if defined (__powerpc64__) +#if defined(__powerpc64__) && _CALL_ELF == 2 + +/* Defining "toc" above breaks @toc in assembler code. */ +#undef toc + +#define FUNC_NAME(name) GLUE(__USER_LABEL_PREFIX__,name) +#define JUMP_TARGET(name) FUNC_NAME(name) +#define FUNC_START(name) \ + .type FUNC_NAME(name),@function; \ + .globl FUNC_NAME(name); \ +FUNC_NAME(name): \ +0: addis 2,12,(.TOC.-0b)@ha; \ + addi 2,2,(.TOC.-0b)@l; \ + .localentry FUNC_NAME(name),.-FUNC_NAME(name) + +#define HIDDEN_FUNC(name) \ + FUNC_START(name) \ + .hidden FUNC_NAME(name); + +#define FUNC_END(name) \ + .size FUNC_NAME(name),.-FUNC_NAME(name) + +#elif defined (__powerpc64__) + #define FUNC_NAME(name) GLUE(.,name) #define JUMP_TARGET(name) FUNC_NAME(name) #define FUNC_START(name) \ diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md index 868ba567976a6..6ee392d837f79 100644 --- a/gcc/config/rs6000/predicates.md +++ b/gcc/config/rs6000/predicates.md @@ -124,6 +124,11 @@ (and (match_code "const_int") (match_test "INTVAL (op) >= -16 && INTVAL (op) <= 15"))) +;; Return 1 if op is a unsigned 3-bit constant integer. +(define_predicate "u3bit_cint_operand" + (and (match_code "const_int") + (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 7"))) + ;; Return 1 if op is a unsigned 5-bit constant integer. (define_predicate "u5bit_cint_operand" (and (match_code "const_int") @@ -135,6 +140,11 @@ (and (match_code "const_int") (match_test "INTVAL (op) >= -128 && INTVAL (op) <= 127"))) +;; Return 1 if op is a unsigned 10-bit constant integer. +(define_predicate "u10bit_cint_operand" + (and (match_code "const_int") + (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 1023"))) + ;; Return 1 if op is a constant integer that can fit in a D field. (define_predicate "short_cint_operand" (and (match_code "const_int") @@ -161,11 +171,21 @@ (and (match_code "const_int") (match_test "IN_RANGE (INTVAL (op), 0, 1)"))) +;; Match op = 0..3. +(define_predicate "const_0_to_3_operand" + (and (match_code "const_int") + (match_test "IN_RANGE (INTVAL (op), 0, 3)"))) + ;; Match op = 2 or op = 3. (define_predicate "const_2_to_3_operand" (and (match_code "const_int") (match_test "IN_RANGE (INTVAL (op), 2, 3)"))) +;; Match op = 0..15 +(define_predicate "const_0_to_15_operand" + (and (match_code "const_int") + (match_test "IN_RANGE (INTVAL (op), 0, 15)"))) + ;; Return 1 if op is a register that is not special. (define_predicate "gpc_reg_operand" (match_operand 0 "register_operand") @@ -182,9 +202,95 @@ if (REGNO (op) >= ARG_POINTER_REGNUM && !CA_REGNO_P (REGNO (op))) return 1; + if (TARGET_VSX && VSX_REGNO_P (REGNO (op))) + return 1; + return INT_REGNO_P (REGNO (op)) || FP_REGNO_P (REGNO (op)); }) +;; Return 1 if op is a general purpose register. Unlike gpc_reg_operand, don't +;; allow floating point or vector registers. +(define_predicate "int_reg_operand" + (match_operand 0 "register_operand") +{ + if ((TARGET_E500_DOUBLE || TARGET_SPE) && invalid_e500_subreg (op, mode)) + return 0; + + if (GET_CODE (op) == SUBREG) + op = SUBREG_REG (op); + + if (!REG_P (op)) + return 0; + + if (REGNO (op) >= FIRST_PSEUDO_REGISTER) + return 1; + + return INT_REGNO_P (REGNO (op)); +}) + +;; Like int_reg_operand, but only return true for base registers +(define_predicate "base_reg_operand" + (match_operand 0 "int_reg_operand") +{ + if (GET_CODE (op) == SUBREG) + op = SUBREG_REG (op); + + if (!REG_P (op)) + return 0; + + return (REGNO (op) != FIRST_GPR_REGNO); +}) + +;; Return 1 if op is a HTM specific SPR register. +(define_predicate "htm_spr_reg_operand" + (match_operand 0 "register_operand") +{ + if (!TARGET_HTM) + return 0; + + if (GET_CODE (op) == SUBREG) + op = SUBREG_REG (op); + + if (!REG_P (op)) + return 0; + + switch (REGNO (op)) + { + case TFHAR_REGNO: + case TFIAR_REGNO: + case TEXASR_REGNO: + return 1; + default: + break; + } + + /* Unknown SPR. */ + return 0; +}) + +;; Return 1 if op is a general purpose register that is an even register +;; which suitable for a load/store quad operation +(define_predicate "quad_int_reg_operand" + (match_operand 0 "register_operand") +{ + HOST_WIDE_INT r; + + if (!TARGET_QUAD_MEMORY && !TARGET_QUAD_MEMORY_ATOMIC) + return 0; + + if (GET_CODE (op) == SUBREG) + op = SUBREG_REG (op); + + if (!REG_P (op)) + return 0; + + r = REGNO (op); + if (r >= FIRST_PSEUDO_REGISTER) + return 1; + + return (INT_REGNO_P (r) && ((r & 1) == 0)); +}) + ;; Return 1 if op is a register that is a condition register field. (define_predicate "cc_reg_operand" (match_operand 0 "register_operand") @@ -275,14 +381,18 @@ (ior (match_code "const_int") (match_operand 0 "gpc_reg_operand"))) +;; Return 1 if op is a constant integer valid for addition with addis, addi. +(define_predicate "add_cint_operand" + (and (match_code "const_int") + (match_test "(unsigned HOST_WIDE_INT) + (INTVAL (op) + (mode == SImode ? 0x80000000 : 0x80008000)) + < (unsigned HOST_WIDE_INT) 0x100000000ll"))) + ;; Return 1 if op is a constant integer valid for addition ;; or non-special register. (define_predicate "reg_or_add_cint_operand" (if_then_else (match_code "const_int") - (match_test "(HOST_BITS_PER_WIDE_INT == 32 - && (mode == SImode || INTVAL (op) < 0x7fff8000)) - || ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80008000) - < (unsigned HOST_WIDE_INT) 0x100000000ll)") + (match_operand 0 "add_cint_operand") (match_operand 0 "gpc_reg_operand"))) ;; Return 1 if op is a constant integer valid for subtraction @@ -311,6 +421,11 @@ && CONST_DOUBLE_HIGH (op) == 0") (match_operand 0 "gpc_reg_operand")))) +;; Like reg_or_logical_cint_operand, but allow vsx registers +(define_predicate "vsx_reg_or_cint_operand" + (ior (match_operand 0 "vsx_register_operand") + (match_operand 0 "reg_or_logical_cint_operand"))) + ;; Return 1 if operand is a CONST_DOUBLE that can be set in a register ;; with no more than one instruction per word. (define_predicate "easy_fp_constant" @@ -329,6 +444,11 @@ && mode != DImode) return 1; + /* The constant 0.0 is easy under VSX. */ + if ((mode == SFmode || mode == DFmode || mode == SDmode || mode == DDmode) + && VECTOR_UNIT_VSX_P (DFmode) && op == CONST0_RTX (mode)) + return 1; + if (DECIMAL_FLOAT_MODE_P (mode)) return 0; @@ -464,9 +584,11 @@ (match_test "easy_altivec_constant (op, mode)"))) { HOST_WIDE_INT val; + int elt; if (mode == V2DImode || mode == V2DFmode) return 0; - val = const_vector_elt_as_int (op, GET_MODE_NUNITS (mode) - 1); + elt = BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) - 1 : 0; + val = const_vector_elt_as_int (op, elt); val = ((val & 0xff) ^ 0x80) - 0x80; return EASY_VECTOR_15_ADD_SELF (val); }) @@ -478,9 +600,11 @@ (match_test "easy_altivec_constant (op, mode)"))) { HOST_WIDE_INT val; + int elt; if (mode == V2DImode || mode == V2DFmode) return 0; - val = const_vector_elt_as_int (op, GET_MODE_NUNITS (mode) - 1); + elt = BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) - 1 : 0; + val = const_vector_elt_as_int (op, elt); return EASY_VECTOR_MSB (val, GET_MODE_INNER (mode)); }) @@ -513,6 +637,55 @@ (and (match_operand 0 "memory_operand") (match_test "offsettable_nonstrict_memref_p (op)"))) +;; Return 1 if the operand is suitable for load/store quad memory. +;; This predicate only checks for non-atomic loads/stores (not lqarx/stqcx). +(define_predicate "quad_memory_operand" + (match_code "mem") +{ + rtx addr, op0, op1; + int ret; + + if (!TARGET_QUAD_MEMORY && !TARGET_SYNC_TI) + ret = 0; + + else if (!memory_operand (op, mode)) + ret = 0; + + else if (GET_MODE_SIZE (GET_MODE (op)) != 16) + ret = 0; + + else if (MEM_ALIGN (op) < 128) + ret = 0; + + else + { + addr = XEXP (op, 0); + if (int_reg_operand (addr, Pmode)) + ret = 1; + + else if (GET_CODE (addr) != PLUS) + ret = 0; + + else + { + op0 = XEXP (addr, 0); + op1 = XEXP (addr, 1); + ret = (int_reg_operand (op0, Pmode) + && GET_CODE (op1) == CONST_INT + && IN_RANGE (INTVAL (op1), -32768, 32767) + && (INTVAL (op1) & 15) == 0); + } + } + + if (TARGET_DEBUG_ADDR) + { + fprintf (stderr, "\nquad_memory_operand, ret = %s\n", ret ? "true" : "false"); + debug_rtx (op); + } + + return ret; +}) + ;; Return 1 if the operand is an indexed or indirect memory operand. (define_predicate "indexed_or_indirect_operand" (match_code "mem") @@ -527,6 +700,19 @@ return indexed_or_indirect_address (op, mode); }) +;; Like indexed_or_indirect_operand, but also allow a GPR register if direct +;; moves are supported. +(define_predicate "reg_or_indexed_operand" + (match_code "mem,reg") +{ + if (MEM_P (op)) + return indexed_or_indirect_operand (op, mode); + else if (TARGET_DIRECT_MOVE) + return register_operand (op, mode); + return + 0; +}) + ;; Return 1 if the operand is an indexed or indirect memory operand with an ;; AND -16 in it, used to recognize when we need to switch to Altivec loads ;; to realign loops instead of VSX (altivec silently ignores the bottom bits, @@ -552,6 +738,28 @@ && REG_P (XEXP (op, 1)))") (match_operand 0 "address_operand"))) +;; Return 1 if the operand is an index-form address. +(define_special_predicate "indexed_address" + (match_test "(GET_CODE (op) == PLUS + && REG_P (XEXP (op, 0)) + && REG_P (XEXP (op, 1)))")) + +;; Return 1 if the operand is a MEM with an update-form address. This may +;; also include update-indexed form. +(define_special_predicate "update_address_mem" + (match_test "(MEM_P (op) + && (GET_CODE (XEXP (op, 0)) == PRE_INC + || GET_CODE (XEXP (op, 0)) == PRE_DEC + || GET_CODE (XEXP (op, 0)) == PRE_MODIFY))")) + +;; Return 1 if the operand is a MEM with an update-indexed-form address. Note +;; that PRE_INC/PRE_DEC will always be non-indexed (i.e. non X-form) since the +;; increment is based on the mode size and will therefor always be a const. +(define_special_predicate "update_indexed_address_mem" + (match_test "(MEM_P (op) + && GET_CODE (XEXP (op, 0)) == PRE_MODIFY + && indexed_address (XEXP (XEXP (op, 0), 1), mode))")) + ;; Used for the destination of the fix_truncdfsi2 expander. ;; If stfiwx will be used, the result goes to memory; otherwise, ;; we're going to emit a store and a load of a subreg, so the dest is a @@ -875,7 +1083,8 @@ (and (match_code "symbol_ref") (match_test "(DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op)) && ((SYMBOL_REF_LOCAL_P (op) - && (DEFAULT_ABI != ABI_AIX + && ((DEFAULT_ABI != ABI_AIX + && DEFAULT_ABI != ABI_ELFv2) || !SYMBOL_REF_EXTERNAL_P (op))) || (op == XEXP (DECL_RTL (current_function_decl), 0)))"))) @@ -1356,6 +1565,26 @@ return 1; }) +;; Return 1 if OP is valid for crsave insn, known to be a PARALLEL. +(define_predicate "crsave_operation" + (match_code "parallel") +{ + int count = XVECLEN (op, 0); + int i; + + for (i = 1; i < count; i++) + { + rtx exp = XVECEXP (op, 0, i); + + if (GET_CODE (exp) != USE + || GET_CODE (XEXP (exp, 0)) != REG + || GET_MODE (XEXP (exp, 0)) != CCmode + || ! CR_REGNO_P (REGNO (XEXP (exp, 0)))) + return 0; + } + return 1; +}) + ;; Return 1 if OP is valid for lmw insn, known to be a PARALLEL. (define_predicate "lmw_operation" (match_code "parallel") @@ -1521,8 +1750,159 @@ (define_predicate "small_toc_ref" (match_code "unspec,plus") { - if (GET_CODE (op) == PLUS && CONST_INT_P (XEXP (op, 1))) + if (GET_CODE (op) == PLUS && add_cint_operand (XEXP (op, 1), mode)) op = XEXP (op, 0); return GET_CODE (op) == UNSPEC && XINT (op, 1) == UNSPEC_TOCREL; }) + +;; Match the first insn (addis) in fusing the combination of addis and loads to +;; GPR registers on power8. +(define_predicate "fusion_gpr_addis" + (match_code "const_int,high,plus") +{ + HOST_WIDE_INT value; + rtx int_const; + + if (GET_CODE (op) == HIGH) + return 1; + + if (CONST_INT_P (op)) + int_const = op; + + else if (GET_CODE (op) == PLUS + && base_reg_operand (XEXP (op, 0), Pmode) + && CONST_INT_P (XEXP (op, 1))) + int_const = XEXP (op, 1); + + else + return 0; + + /* Power8 currently will only do the fusion if the top 11 bits of the addis + value are all 1's or 0's. */ + value = INTVAL (int_const); + if ((value & (HOST_WIDE_INT)0xffff) != 0) + return 0; + + if ((value & (HOST_WIDE_INT)0xffff0000) == 0) + return 0; + + return (IN_RANGE (value >> 16, -32, 31)); +}) + +;; Match the second insn (lbz, lhz, lwz, ld) in fusing the combination of addis +;; and loads to GPR registers on power8. +(define_predicate "fusion_gpr_mem_load" + (match_code "mem,sign_extend,zero_extend") +{ + rtx addr, base, offset; + + /* Handle sign/zero extend. */ + if (GET_CODE (op) == ZERO_EXTEND + || (TARGET_P8_FUSION_SIGN && GET_CODE (op) == SIGN_EXTEND)) + { + op = XEXP (op, 0); + mode = GET_MODE (op); + } + + if (!MEM_P (op)) + return 0; + + switch (mode) + { + case QImode: + case HImode: + case SImode: + break; + + case DImode: + if (!TARGET_POWERPC64) + return 0; + break; + + default: + return 0; + } + + addr = XEXP (op, 0); + if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM) + return 0; + + base = XEXP (addr, 0); + if (!base_reg_operand (base, GET_MODE (base))) + return 0; + + offset = XEXP (addr, 1); + + if (GET_CODE (addr) == PLUS) + return satisfies_constraint_I (offset); + + else if (GET_CODE (addr) == LO_SUM) + { + if (TARGET_XCOFF || (TARGET_ELF && TARGET_POWERPC64)) + return small_toc_ref (offset, GET_MODE (offset)); + + else if (TARGET_ELF && !TARGET_POWERPC64) + return CONSTANT_P (offset); + } + + return 0; +}) + +;; Match a GPR load (lbz, lhz, lwz, ld) that uses a combined address in the +;; memory field with both the addis and the memory offset. Sign extension +;; is not handled here, since lha and lwa are not fused. +(define_predicate "fusion_gpr_mem_combo" + (match_code "mem,zero_extend") +{ + rtx addr, base, offset; + + /* Handle zero extend. */ + if (GET_CODE (op) == ZERO_EXTEND) + { + op = XEXP (op, 0); + mode = GET_MODE (op); + } + + if (!MEM_P (op)) + return 0; + + switch (mode) + { + case QImode: + case HImode: + case SImode: + break; + + case DImode: + if (!TARGET_POWERPC64) + return 0; + break; + + default: + return 0; + } + + addr = XEXP (op, 0); + if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM) + return 0; + + base = XEXP (addr, 0); + if (!fusion_gpr_addis (base, GET_MODE (base))) + return 0; + + offset = XEXP (addr, 1); + if (GET_CODE (addr) == PLUS) + return satisfies_constraint_I (offset); + + else if (GET_CODE (addr) == LO_SUM) + { + if (TARGET_XCOFF || (TARGET_ELF && TARGET_POWERPC64)) + return small_toc_ref (offset, GET_MODE (offset)); + + else if (TARGET_ELF && !TARGET_POWERPC64) + return CONSTANT_P (offset); + } + + return 0; +}) diff --git a/gcc/config/rs6000/rs6000-builtin.def b/gcc/config/rs6000/rs6000-builtin.def index a545fe3e448e2..7497df3da7560 100644 --- a/gcc/config/rs6000/rs6000-builtin.def +++ b/gcc/config/rs6000/rs6000-builtin.def @@ -30,7 +30,8 @@ RS6000_BUILTIN_A -- ABS builtins RS6000_BUILTIN_D -- DST builtins RS6000_BUILTIN_E -- SPE EVSEL builtins. - RS6000_BUILTIN_P -- Altivec and VSX predicate builtins + RS6000_BUILTIN_H -- HTM builtins + RS6000_BUILTIN_P -- Altivec, VSX, ISA 2.07 vector predicate builtins RS6000_BUILTIN_Q -- Paired floating point VSX predicate builtins RS6000_BUILTIN_S -- SPE predicate builtins RS6000_BUILTIN_X -- special builtins @@ -66,6 +67,10 @@ #error "RS6000_BUILTIN_E is not defined." #endif +#ifndef RS6000_BUILTIN_H + #error "RS6000_BUILTIN_H is not defined." +#endif + #ifndef RS6000_BUILTIN_P #error "RS6000_BUILTIN_P is not defined." #endif @@ -301,6 +306,189 @@ | RS6000_BTC_SPECIAL), \ CODE_FOR_nothing) /* ICODE */ +/* ISA 2.07 (power8) vector convenience macros. */ +/* For the instructions that are encoded as altivec instructions use + __builtin_altivec_ as the builtin name. */ +#define BU_P8V_AV_1(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_1 (P8V_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_altivec_" NAME, /* NAME */ \ + RS6000_BTM_P8_VECTOR, /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_UNARY), \ + CODE_FOR_ ## ICODE) /* ICODE */ + +#define BU_P8V_AV_2(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_2 (P8V_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_altivec_" NAME, /* NAME */ \ + RS6000_BTM_P8_VECTOR, /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_BINARY), \ + CODE_FOR_ ## ICODE) /* ICODE */ + +#define BU_P8V_AV_3(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_3 (P8V_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_altivec_" NAME, /* NAME */ \ + RS6000_BTM_P8_VECTOR, /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_TERNARY), \ + CODE_FOR_ ## ICODE) /* ICODE */ + +#define BU_P8V_AV_P(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_P (P8V_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_altivec_" NAME, /* NAME */ \ + RS6000_BTM_P8_VECTOR, /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_PREDICATE), \ + CODE_FOR_ ## ICODE) /* ICODE */ + +/* For the instructions encoded as VSX instructions use __builtin_vsx as the + builtin name. */ +#define BU_P8V_VSX_1(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_1 (P8V_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_vsx_" NAME, /* NAME */ \ + RS6000_BTM_P8_VECTOR, /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_UNARY), \ + CODE_FOR_ ## ICODE) /* ICODE */ + +#define BU_P8V_OVERLOAD_1(ENUM, NAME) \ + RS6000_BUILTIN_1 (P8V_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ + "__builtin_vec_" NAME, /* NAME */ \ + RS6000_BTM_P8_VECTOR, /* MASK */ \ + (RS6000_BTC_OVERLOADED /* ATTR */ \ + | RS6000_BTC_UNARY), \ + CODE_FOR_nothing) /* ICODE */ + +#define BU_P8V_OVERLOAD_2(ENUM, NAME) \ + RS6000_BUILTIN_2 (P8V_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ + "__builtin_vec_" NAME, /* NAME */ \ + RS6000_BTM_P8_VECTOR, /* MASK */ \ + (RS6000_BTC_OVERLOADED /* ATTR */ \ + | RS6000_BTC_BINARY), \ + CODE_FOR_nothing) /* ICODE */ + +#define BU_P8V_OVERLOAD_3(ENUM, NAME) \ + RS6000_BUILTIN_3 (P8V_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ + "__builtin_vec_" NAME, /* NAME */ \ + RS6000_BTM_P8_VECTOR, /* MASK */ \ + (RS6000_BTC_OVERLOADED /* ATTR */ \ + | RS6000_BTC_TERNARY), \ + CODE_FOR_nothing) /* ICODE */ + +/* Crypto convenience macros. */ +#define BU_CRYPTO_1(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_1 (CRYPTO_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_crypto_" NAME, /* NAME */ \ + RS6000_BTM_CRYPTO, /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_UNARY), \ + CODE_FOR_ ## ICODE) /* ICODE */ + +#define BU_CRYPTO_2(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_2 (CRYPTO_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_crypto_" NAME, /* NAME */ \ + RS6000_BTM_CRYPTO, /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_BINARY), \ + CODE_FOR_ ## ICODE) /* ICODE */ + +#define BU_CRYPTO_2A(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_2 (CRYPTO_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_crypto_" NAME, /* NAME */ \ + RS6000_BTM_P8_VECTOR, /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_BINARY), \ + CODE_FOR_ ## ICODE) /* ICODE */ + +#define BU_CRYPTO_3(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_3 (CRYPTO_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_crypto_" NAME, /* NAME */ \ + RS6000_BTM_CRYPTO, /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_TERNARY), \ + CODE_FOR_ ## ICODE) /* ICODE */ + +#define BU_CRYPTO_3A(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_3 (CRYPTO_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_crypto_" NAME, /* NAME */ \ + RS6000_BTM_P8_VECTOR, /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_TERNARY), \ + CODE_FOR_ ## ICODE) /* ICODE */ + +#define BU_CRYPTO_OVERLOAD_1(ENUM, NAME) \ + RS6000_BUILTIN_1 (CRYPTO_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_crypto_" NAME, /* NAME */ \ + RS6000_BTM_CRYPTO, /* MASK */ \ + (RS6000_BTC_OVERLOADED /* ATTR */ \ + | RS6000_BTC_UNARY), \ + CODE_FOR_nothing) /* ICODE */ + +#define BU_CRYPTO_OVERLOAD_2A(ENUM, NAME) \ + RS6000_BUILTIN_2 (CRYPTO_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_crypto_" NAME, /* NAME */ \ + RS6000_BTM_P8_VECTOR, /* MASK */ \ + (RS6000_BTC_OVERLOADED /* ATTR */ \ + | RS6000_BTC_BINARY), \ + CODE_FOR_nothing) /* ICODE */ + +#define BU_CRYPTO_OVERLOAD_3(ENUM, NAME) \ + RS6000_BUILTIN_3 (CRYPTO_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_crypto_" NAME, /* NAME */ \ + RS6000_BTM_CRYPTO, /* MASK */ \ + (RS6000_BTC_OVERLOADED /* ATTR */ \ + | RS6000_BTC_TERNARY), \ + CODE_FOR_nothing) /* ICODE */ + +#define BU_CRYPTO_OVERLOAD_3A(ENUM, NAME) \ + RS6000_BUILTIN_3 (CRYPTO_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_crypto_" NAME, /* NAME */ \ + RS6000_BTM_P8_VECTOR, /* MASK */ \ + (RS6000_BTC_OVERLOADED /* ATTR */ \ + | RS6000_BTC_TERNARY), \ + CODE_FOR_nothing) /* ICODE */ + +/* HTM convenience macros. */ +#define BU_HTM_0(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_H (HTM_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_" NAME, /* NAME */ \ + RS6000_BTM_HTM, /* MASK */ \ + RS6000_BTC_ ## ATTR, /* ATTR */ \ + CODE_FOR_ ## ICODE) /* ICODE */ + +#define BU_HTM_1(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_H (HTM_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_" NAME, /* NAME */ \ + RS6000_BTM_HTM, /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_UNARY), \ + CODE_FOR_ ## ICODE) /* ICODE */ + +#define BU_HTM_2(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_H (HTM_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_" NAME, /* NAME */ \ + RS6000_BTM_HTM, /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_BINARY), \ + CODE_FOR_ ## ICODE) /* ICODE */ + +#define BU_HTM_3(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_H (HTM_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_" NAME, /* NAME */ \ + RS6000_BTM_HTM, /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_TERNARY), \ + CODE_FOR_ ## ICODE) /* ICODE */ + +#define BU_HTM_V1(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_H (HTM_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_" NAME, /* NAME */ \ + RS6000_BTM_HTM, /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_UNARY \ + | RS6000_BTC_VOID), \ + CODE_FOR_ ## ICODE) /* ICODE */ + /* SPE convenience macros. */ #define BU_SPE_1(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_1 (SPE_BUILTIN_ ## ENUM, /* ENUM */ \ @@ -397,6 +585,68 @@ MASK, /* MASK */ \ (ATTR | RS6000_BTC_SPECIAL), /* ATTR */ \ CODE_FOR_nothing) /* ICODE */ + + +/* Decimal floating point builtins for instructions. */ +#define BU_DFP_MISC_1(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_1 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_" NAME, /* NAME */ \ + RS6000_BTM_DFP, /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_UNARY), \ + CODE_FOR_ ## ICODE) /* ICODE */ + +#define BU_DFP_MISC_2(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_2 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_" NAME, /* NAME */ \ + RS6000_BTM_DFP, /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_BINARY), \ + CODE_FOR_ ## ICODE) /* ICODE */ + + +/* Miscellaneous builtins for instructions added in ISA 2.06. These + instructions don't require either the DFP or VSX options, just the basic ISA + 2.06 (popcntd) enablement since they operate on general purpose + registers. */ +#define BU_P7_MISC_1(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_1 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_" NAME, /* NAME */ \ + RS6000_BTM_POPCNTD, /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_UNARY), \ + CODE_FOR_ ## ICODE) /* ICODE */ + +#define BU_P7_MISC_2(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_2 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_" NAME, /* NAME */ \ + RS6000_BTM_POPCNTD, /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_BINARY), \ + CODE_FOR_ ## ICODE) /* ICODE */ + + +/* Miscellaneous builtins for instructions added in ISA 2.07. These + instructions do require the ISA 2.07 vector support, but they aren't vector + instructions. */ +#define BU_P8V_MISC_3(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_3 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_" NAME, /* NAME */ \ + RS6000_BTM_P8_VECTOR, /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_TERNARY), \ + CODE_FOR_ ## ICODE) /* ICODE */ + +/* 128-bit long double floating point builtins. */ +#define BU_LDBL128_2(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_2 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_" NAME, /* NAME */ \ + (RS6000_BTM_HARD_FLOAT /* MASK */ \ + | RS6000_BTM_LDBL128), \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_BINARY), \ + CODE_FOR_ ## ICODE) /* ICODE */ + #endif /* Insure 0 is not a legitimate index. */ @@ -414,12 +664,14 @@ BU_ALTIVEC_3 (VMSUMSHM, "vmsumshm", CONST, altivec_vmsumshm) BU_ALTIVEC_3 (VMSUMUHS, "vmsumuhs", SAT, altivec_vmsumuhs) BU_ALTIVEC_3 (VMSUMSHS, "vmsumshs", SAT, altivec_vmsumshs) BU_ALTIVEC_3 (VNMSUBFP, "vnmsubfp", FP, nfmsv4sf4) +BU_ALTIVEC_3 (VPERM_1TI, "vperm_1ti", CONST, altivec_vperm_v1ti) BU_ALTIVEC_3 (VPERM_2DF, "vperm_2df", CONST, altivec_vperm_v2df) BU_ALTIVEC_3 (VPERM_2DI, "vperm_2di", CONST, altivec_vperm_v2di) BU_ALTIVEC_3 (VPERM_4SF, "vperm_4sf", CONST, altivec_vperm_v4sf) BU_ALTIVEC_3 (VPERM_4SI, "vperm_4si", CONST, altivec_vperm_v4si) BU_ALTIVEC_3 (VPERM_8HI, "vperm_8hi", CONST, altivec_vperm_v8hi) BU_ALTIVEC_3 (VPERM_16QI, "vperm_16qi", CONST, altivec_vperm_v16qi_uns) +BU_ALTIVEC_3 (VPERM_1TI_UNS, "vperm_1ti_uns", CONST, altivec_vperm_v1ti_uns) BU_ALTIVEC_3 (VPERM_2DI_UNS, "vperm_2di_uns", CONST, altivec_vperm_v2di_uns) BU_ALTIVEC_3 (VPERM_4SI_UNS, "vperm_4si_uns", CONST, altivec_vperm_v4si_uns) BU_ALTIVEC_3 (VPERM_8HI_UNS, "vperm_8hi_uns", CONST, altivec_vperm_v8hi_uns) @@ -430,10 +682,12 @@ BU_ALTIVEC_3 (VSEL_8HI, "vsel_8hi", CONST, vector_select_v8hi) BU_ALTIVEC_3 (VSEL_16QI, "vsel_16qi", CONST, vector_select_v16qi) BU_ALTIVEC_3 (VSEL_2DF, "vsel_2df", CONST, vector_select_v2df) BU_ALTIVEC_3 (VSEL_2DI, "vsel_2di", CONST, vector_select_v2di) +BU_ALTIVEC_3 (VSEL_1TI, "vsel_1ti", CONST, vector_select_v1ti) BU_ALTIVEC_3 (VSEL_4SI_UNS, "vsel_4si_uns", CONST, vector_select_v4si_uns) BU_ALTIVEC_3 (VSEL_8HI_UNS, "vsel_8hi_uns", CONST, vector_select_v8hi_uns) BU_ALTIVEC_3 (VSEL_16QI_UNS, "vsel_16qi_uns", CONST, vector_select_v16qi_uns) BU_ALTIVEC_3 (VSEL_2DI_UNS, "vsel_2di_uns", CONST, vector_select_v2di_uns) +BU_ALTIVEC_3 (VSEL_1TI_UNS, "vsel_1ti_uns", CONST, vector_select_v1ti_uns) BU_ALTIVEC_3 (VSLDOI_16QI, "vsldoi_16qi", CONST, altivec_vsldoi_v16qi) BU_ALTIVEC_3 (VSLDOI_8HI, "vsldoi_8hi", CONST, altivec_vsldoi_v8hi) BU_ALTIVEC_3 (VSLDOI_4SI, "vsldoi_4si", CONST, altivec_vsldoi_v4si) @@ -626,6 +880,8 @@ BU_ALTIVEC_X (ST_INTERNAL_2df, "st_internal_4sf", MEM) BU_ALTIVEC_X (LD_INTERNAL_2df, "ld_internal_2df", MEM) BU_ALTIVEC_X (ST_INTERNAL_2di, "st_internal_2di", MEM) BU_ALTIVEC_X (LD_INTERNAL_2di, "ld_internal_2di", MEM) +BU_ALTIVEC_X (ST_INTERNAL_1ti, "st_internal_1ti", MEM) +BU_ALTIVEC_X (LD_INTERNAL_1ti, "ld_internal_1ti", MEM) BU_ALTIVEC_X (MTVSCR, "mtvscr", MISC) BU_ALTIVEC_X (MFVSCR, "mfvscr", MISC) BU_ALTIVEC_X (DSSALL, "dssall", MISC) @@ -636,8 +892,26 @@ BU_ALTIVEC_X (LVEBX, "lvebx", MEM) BU_ALTIVEC_X (LVEHX, "lvehx", MEM) BU_ALTIVEC_X (LVEWX, "lvewx", MEM) BU_ALTIVEC_X (LVXL, "lvxl", MEM) +BU_ALTIVEC_X (LVXL_V2DF, "lvxl_v2df", MEM) +BU_ALTIVEC_X (LVXL_V2DI, "lvxl_v2di", MEM) +BU_ALTIVEC_X (LVXL_V4SF, "lvxl_v4sf", MEM) +BU_ALTIVEC_X (LVXL_V4SI, "lvxl_v4si", MEM) +BU_ALTIVEC_X (LVXL_V8HI, "lvxl_v8hi", MEM) +BU_ALTIVEC_X (LVXL_V16QI, "lvxl_v16qi", MEM) BU_ALTIVEC_X (LVX, "lvx", MEM) +BU_ALTIVEC_X (LVX_V2DF, "lvx_v2df", MEM) +BU_ALTIVEC_X (LVX_V2DI, "lvx_v2di", MEM) +BU_ALTIVEC_X (LVX_V4SF, "lvx_v4sf", MEM) +BU_ALTIVEC_X (LVX_V4SI, "lvx_v4si", MEM) +BU_ALTIVEC_X (LVX_V8HI, "lvx_v8hi", MEM) +BU_ALTIVEC_X (LVX_V16QI, "lvx_v16qi", MEM) BU_ALTIVEC_X (STVX, "stvx", MEM) +BU_ALTIVEC_X (STVX_V2DF, "stvx_v2df", MEM) +BU_ALTIVEC_X (STVX_V2DI, "stvx_v2di", MEM) +BU_ALTIVEC_X (STVX_V4SF, "stvx_v4sf", MEM) +BU_ALTIVEC_X (STVX_V4SI, "stvx_v4si", MEM) +BU_ALTIVEC_X (STVX_V8HI, "stvx_v8hi", MEM) +BU_ALTIVEC_X (STVX_V16QI, "stvx_v16qi", MEM) BU_ALTIVEC_C (LVLX, "lvlx", MEM) BU_ALTIVEC_C (LVLXL, "lvlxl", MEM) BU_ALTIVEC_C (LVRX, "lvrx", MEM) @@ -646,6 +920,12 @@ BU_ALTIVEC_X (STVEBX, "stvebx", MEM) BU_ALTIVEC_X (STVEHX, "stvehx", MEM) BU_ALTIVEC_X (STVEWX, "stvewx", MEM) BU_ALTIVEC_X (STVXL, "stvxl", MEM) +BU_ALTIVEC_X (STVXL_V2DF, "stvxl_v2df", MEM) +BU_ALTIVEC_X (STVXL_V2DI, "stvxl_v2di", MEM) +BU_ALTIVEC_X (STVXL_V4SF, "stvxl_v4sf", MEM) +BU_ALTIVEC_X (STVXL_V4SI, "stvxl_v4si", MEM) +BU_ALTIVEC_X (STVXL_V8HI, "stvxl_v8hi", MEM) +BU_ALTIVEC_X (STVXL_V16QI, "stvxl_v16qi", MEM) BU_ALTIVEC_C (STVLX, "stvlx", MEM) BU_ALTIVEC_C (STVLXL, "stvlxl", MEM) BU_ALTIVEC_C (STVRX, "stvrx", MEM) @@ -904,34 +1184,40 @@ BU_VSX_3 (XVMSUBDP, "xvmsubdp", CONST, fmsv2df4) BU_VSX_3 (XVNMADDDP, "xvnmadddp", CONST, nfmav2df4) BU_VSX_3 (XVNMSUBDP, "xvnmsubdp", CONST, nfmsv2df4) +BU_VSX_3 (XXSEL_1TI, "xxsel_1ti", CONST, vector_select_v1ti) BU_VSX_3 (XXSEL_2DI, "xxsel_2di", CONST, vector_select_v2di) BU_VSX_3 (XXSEL_2DF, "xxsel_2df", CONST, vector_select_v2df) BU_VSX_3 (XXSEL_4SF, "xxsel_4sf", CONST, vector_select_v4sf) BU_VSX_3 (XXSEL_4SI, "xxsel_4si", CONST, vector_select_v4si) BU_VSX_3 (XXSEL_8HI, "xxsel_8hi", CONST, vector_select_v8hi) BU_VSX_3 (XXSEL_16QI, "xxsel_16qi", CONST, vector_select_v16qi) +BU_VSX_3 (XXSEL_1TI_UNS, "xxsel_1ti_uns", CONST, vector_select_v1ti_uns) BU_VSX_3 (XXSEL_2DI_UNS, "xxsel_2di_uns", CONST, vector_select_v2di_uns) BU_VSX_3 (XXSEL_4SI_UNS, "xxsel_4si_uns", CONST, vector_select_v4si_uns) BU_VSX_3 (XXSEL_8HI_UNS, "xxsel_8hi_uns", CONST, vector_select_v8hi_uns) BU_VSX_3 (XXSEL_16QI_UNS, "xxsel_16qi_uns", CONST, vector_select_v16qi_uns) +BU_VSX_3 (VPERM_1TI, "vperm_1ti", CONST, altivec_vperm_v1ti) BU_VSX_3 (VPERM_2DI, "vperm_2di", CONST, altivec_vperm_v2di) BU_VSX_3 (VPERM_2DF, "vperm_2df", CONST, altivec_vperm_v2df) BU_VSX_3 (VPERM_4SF, "vperm_4sf", CONST, altivec_vperm_v4sf) BU_VSX_3 (VPERM_4SI, "vperm_4si", CONST, altivec_vperm_v4si) BU_VSX_3 (VPERM_8HI, "vperm_8hi", CONST, altivec_vperm_v8hi) BU_VSX_3 (VPERM_16QI, "vperm_16qi", CONST, altivec_vperm_v16qi) +BU_VSX_3 (VPERM_1TI_UNS, "vperm_1ti_uns", CONST, altivec_vperm_v1ti_uns) BU_VSX_3 (VPERM_2DI_UNS, "vperm_2di_uns", CONST, altivec_vperm_v2di_uns) BU_VSX_3 (VPERM_4SI_UNS, "vperm_4si_uns", CONST, altivec_vperm_v4si_uns) BU_VSX_3 (VPERM_8HI_UNS, "vperm_8hi_uns", CONST, altivec_vperm_v8hi_uns) BU_VSX_3 (VPERM_16QI_UNS, "vperm_16qi_uns", CONST, altivec_vperm_v16qi_uns) +BU_VSX_3 (XXPERMDI_1TI, "xxpermdi_1ti", CONST, vsx_xxpermdi_v1ti) BU_VSX_3 (XXPERMDI_2DF, "xxpermdi_2df", CONST, vsx_xxpermdi_v2df) BU_VSX_3 (XXPERMDI_2DI, "xxpermdi_2di", CONST, vsx_xxpermdi_v2di) BU_VSX_3 (XXPERMDI_4SF, "xxpermdi_4sf", CONST, vsx_xxpermdi_v4sf) BU_VSX_3 (XXPERMDI_4SI, "xxpermdi_4si", CONST, vsx_xxpermdi_v4si) BU_VSX_3 (XXPERMDI_8HI, "xxpermdi_8hi", CONST, vsx_xxpermdi_v8hi) BU_VSX_3 (XXPERMDI_16QI, "xxpermdi_16qi", CONST, vsx_xxpermdi_v16qi) +BU_VSX_3 (SET_1TI, "set_1ti", CONST, vsx_set_v1ti) BU_VSX_3 (SET_2DF, "set_2df", CONST, vsx_set_v2df) BU_VSX_3 (SET_2DI, "set_2di", CONST, vsx_set_v2di) BU_VSX_3 (XXSLDWI_2DI, "xxsldwi_2di", CONST, vsx_xxsldwi_v2di) @@ -987,6 +1273,16 @@ BU_VSX_2 (VEC_MERGEL_V2DF, "mergel_2df", CONST, vsx_mergel_v2df) BU_VSX_2 (VEC_MERGEL_V2DI, "mergel_2di", CONST, vsx_mergel_v2di) BU_VSX_2 (VEC_MERGEH_V2DF, "mergeh_2df", CONST, vsx_mergeh_v2df) BU_VSX_2 (VEC_MERGEH_V2DI, "mergeh_2di", CONST, vsx_mergeh_v2di) +BU_VSX_2 (XXSPLTD_V2DF, "xxspltd_2df", CONST, vsx_xxspltd_v2df) +BU_VSX_2 (XXSPLTD_V2DI, "xxspltd_2di", CONST, vsx_xxspltd_v2di) +BU_VSX_2 (DIV_V2DI, "div_2di", CONST, vsx_div_v2di) +BU_VSX_2 (UDIV_V2DI, "udiv_2di", CONST, vsx_udiv_v2di) +BU_VSX_2 (MUL_V2DI, "mul_2di", CONST, vsx_mul_v2di) + +BU_VSX_2 (XVCVSXDDP_SCALE, "xvcvsxddp_scale", CONST, vsx_xvcvsxddp_scale) +BU_VSX_2 (XVCVUXDDP_SCALE, "xvcvuxddp_scale", CONST, vsx_xvcvuxddp_scale) +BU_VSX_2 (XVCVDPSXDS_SCALE, "xvcvdpsxds_scale", CONST, vsx_xvcvdpsxds_scale) +BU_VSX_2 (XVCVDPUXDS_SCALE, "xvcvdpuxds_scale", CONST, vsx_xvcvdpuxds_scale) /* VSX abs builtin functions. */ BU_VSX_A (XVABSDP, "xvabsdp", CONST, absv2df2) @@ -1012,7 +1308,7 @@ BU_VSX_1 (XVTSQRTSP_FG, "xvtsqrtsp_fg", CONST, vsx_tsqrtv4sf2_fg) BU_VSX_1 (XVRESP, "xvresp", CONST, vsx_frev4sf2) BU_VSX_1 (XSCVDPSP, "xscvdpsp", CONST, vsx_xscvdpsp) -BU_VSX_1 (XSCVSPDP, "xscvspdp", CONST, vsx_xscvdpsp) +BU_VSX_1 (XSCVSPDP, "xscvspdp", CONST, vsx_xscvspdp) BU_VSX_1 (XVCVDPSP, "xvcvdpsp", CONST, vsx_xvcvdpsp) BU_VSX_1 (XVCVSPDP, "xvcvspdp", CONST, vsx_xvcvspdp) BU_VSX_1 (XSTSQRTDP_FE, "xstsqrtdp_fe", CONST, vsx_tsqrtdf2_fe) @@ -1052,9 +1348,9 @@ BU_VSX_1 (XVRSPIZ, "xvrspiz", CONST, vsx_btruncv4sf2) BU_VSX_1 (XSRDPI, "xsrdpi", CONST, vsx_xsrdpi) BU_VSX_1 (XSRDPIC, "xsrdpic", CONST, vsx_xsrdpic) -BU_VSX_1 (XSRDPIM, "xsrdpim", CONST, vsx_floordf2) -BU_VSX_1 (XSRDPIP, "xsrdpip", CONST, vsx_ceildf2) -BU_VSX_1 (XSRDPIZ, "xsrdpiz", CONST, vsx_btruncdf2) +BU_VSX_1 (XSRDPIM, "xsrdpim", CONST, floordf2) +BU_VSX_1 (XSRDPIP, "xsrdpip", CONST, ceildf2) +BU_VSX_1 (XSRDPIZ, "xsrdpiz", CONST, btruncdf2) /* VSX predicate functions. */ BU_VSX_P (XVCMPEQSP_P, "xvcmpeqsp_p", CONST, vector_eq_v4sf_p) @@ -1066,6 +1362,7 @@ BU_VSX_P (XVCMPGTDP_P, "xvcmpgtdp_p", CONST, vector_gt_v2df_p) /* VSX builtins that are handled as special cases. */ BU_VSX_X (LXSDX, "lxsdx", MEM) +BU_VSX_X (LXVD2X_V1TI, "lxvd2x_v1ti", MEM) BU_VSX_X (LXVD2X_V2DF, "lxvd2x_v2df", MEM) BU_VSX_X (LXVD2X_V2DI, "lxvd2x_v2di", MEM) BU_VSX_X (LXVDSX, "lxvdsx", MEM) @@ -1074,6 +1371,7 @@ BU_VSX_X (LXVW4X_V4SI, "lxvw4x_v4si", MEM) BU_VSX_X (LXVW4X_V8HI, "lxvw4x_v8hi", MEM) BU_VSX_X (LXVW4X_V16QI, "lxvw4x_v16qi", MEM) BU_VSX_X (STXSDX, "stxsdx", MEM) +BU_VSX_X (STXVD2X_V1TI, "stxsdx_v1ti", MEM) BU_VSX_X (STXVD2X_V2DF, "stxsdx_v2df", MEM) BU_VSX_X (STXVD2X_V2DI, "stxsdx_v2di", MEM) BU_VSX_X (STXVW4X_V4SF, "stxsdx_v4sf", MEM) @@ -1104,10 +1402,13 @@ BU_VSX_X (XSNMADDMDP, "xsnmaddmdp", FP) BU_VSX_X (XSNMSUBADP, "xsnmsubadp", FP) BU_VSX_X (XSNMSUBMDP, "xsnmsubmdp", FP) BU_VSX_X (XSSUBDP, "xssubdp", FP) +BU_VSX_X (VEC_INIT_V1TI, "vec_init_v1ti", CONST) BU_VSX_X (VEC_INIT_V2DF, "vec_init_v2df", CONST) BU_VSX_X (VEC_INIT_V2DI, "vec_init_v2di", CONST) +BU_VSX_X (VEC_SET_V1TI, "vec_set_v1ti", CONST) BU_VSX_X (VEC_SET_V2DF, "vec_set_v2df", CONST) BU_VSX_X (VEC_SET_V2DI, "vec_set_v2di", CONST) +BU_VSX_X (VEC_EXT_V1TI, "vec_ext_v1ti", CONST) BU_VSX_X (VEC_EXT_V2DF, "vec_ext_v2df", CONST) BU_VSX_X (VEC_EXT_V2DI, "vec_ext_v2di", CONST) @@ -1131,6 +1432,247 @@ BU_VSX_OVERLOAD_2 (XXSPLTW, "xxspltw") /* VSX builtins that are handled as special cases. */ BU_VSX_OVERLOAD_X (LD, "ld") BU_VSX_OVERLOAD_X (ST, "st") + +/* 1 argument VSX instructions added in ISA 2.07. */ +BU_P8V_VSX_1 (XSCVSPDPN, "xscvspdpn", CONST, vsx_xscvspdpn) +BU_P8V_VSX_1 (XSCVDPSPN, "xscvdpspn", CONST, vsx_xscvdpspn) + +/* 1 argument altivec instructions added in ISA 2.07. */ +BU_P8V_AV_1 (ABS_V2DI, "abs_v2di", CONST, absv2di2) +BU_P8V_AV_1 (VUPKHSW, "vupkhsw", CONST, altivec_vupkhsw) +BU_P8V_AV_1 (VUPKLSW, "vupklsw", CONST, altivec_vupklsw) +BU_P8V_AV_1 (VCLZB, "vclzb", CONST, clzv16qi2) +BU_P8V_AV_1 (VCLZH, "vclzh", CONST, clzv8hi2) +BU_P8V_AV_1 (VCLZW, "vclzw", CONST, clzv4si2) +BU_P8V_AV_1 (VCLZD, "vclzd", CONST, clzv2di2) +BU_P8V_AV_1 (VPOPCNTB, "vpopcntb", CONST, popcountv16qi2) +BU_P8V_AV_1 (VPOPCNTH, "vpopcnth", CONST, popcountv8hi2) +BU_P8V_AV_1 (VPOPCNTW, "vpopcntw", CONST, popcountv4si2) +BU_P8V_AV_1 (VPOPCNTD, "vpopcntd", CONST, popcountv2di2) +BU_P8V_AV_1 (VGBBD, "vgbbd", CONST, p8v_vgbbd) + +/* 2 argument altivec instructions added in ISA 2.07. */ +BU_P8V_AV_2 (VADDCUQ, "vaddcuq", CONST, altivec_vaddcuq) +BU_P8V_AV_2 (VADDUDM, "vaddudm", CONST, addv2di3) +BU_P8V_AV_2 (VADDUQM, "vadduqm", CONST, altivec_vadduqm) +BU_P8V_AV_2 (VMINSD, "vminsd", CONST, sminv2di3) +BU_P8V_AV_2 (VMAXSD, "vmaxsd", CONST, smaxv2di3) +BU_P8V_AV_2 (VMINUD, "vminud", CONST, uminv2di3) +BU_P8V_AV_2 (VMAXUD, "vmaxud", CONST, umaxv2di3) +BU_P8V_AV_2 (VMRGEW, "vmrgew", CONST, p8_vmrgew) +BU_P8V_AV_2 (VMRGOW, "vmrgow", CONST, p8_vmrgow) +BU_P8V_AV_2 (VBPERMQ, "vbpermq", CONST, altivec_vbpermq) +BU_P8V_AV_2 (VPKUDUM, "vpkudum", CONST, altivec_vpkudum) +BU_P8V_AV_2 (VPKSDSS, "vpksdss", CONST, altivec_vpksdss) +BU_P8V_AV_2 (VPKUDUS, "vpkudus", CONST, altivec_vpkudus) +BU_P8V_AV_2 (VPKSDUS, "vpksdus", CONST, altivec_vpksdus) +BU_P8V_AV_2 (VRLD, "vrld", CONST, vrotlv2di3) +BU_P8V_AV_2 (VSLD, "vsld", CONST, vashlv2di3) +BU_P8V_AV_2 (VSRD, "vsrd", CONST, vlshrv2di3) +BU_P8V_AV_2 (VSRAD, "vsrad", CONST, vashrv2di3) +BU_P8V_AV_2 (VSUBCUQ, "vsubcuq", CONST, altivec_vsubcuq) +BU_P8V_AV_2 (VSUBUDM, "vsubudm", CONST, subv2di3) +BU_P8V_AV_2 (VSUBUQM, "vsubuqm", CONST, altivec_vsubuqm) + +BU_P8V_AV_2 (EQV_V16QI, "eqv_v16qi", CONST, eqvv16qi3) +BU_P8V_AV_2 (EQV_V8HI, "eqv_v8hi", CONST, eqvv8hi3) +BU_P8V_AV_2 (EQV_V4SI, "eqv_v4si", CONST, eqvv4si3) +BU_P8V_AV_2 (EQV_V2DI, "eqv_v2di", CONST, eqvv2di3) +BU_P8V_AV_2 (EQV_V1TI, "eqv_v1ti", CONST, eqvv1ti3) +BU_P8V_AV_2 (EQV_V4SF, "eqv_v4sf", CONST, eqvv4sf3) +BU_P8V_AV_2 (EQV_V2DF, "eqv_v2df", CONST, eqvv2df3) + +BU_P8V_AV_2 (NAND_V16QI, "nand_v16qi", CONST, nandv16qi3) +BU_P8V_AV_2 (NAND_V8HI, "nand_v8hi", CONST, nandv8hi3) +BU_P8V_AV_2 (NAND_V4SI, "nand_v4si", CONST, nandv4si3) +BU_P8V_AV_2 (NAND_V2DI, "nand_v2di", CONST, nandv2di3) +BU_P8V_AV_2 (NAND_V1TI, "nand_v1ti", CONST, nandv1ti3) +BU_P8V_AV_2 (NAND_V4SF, "nand_v4sf", CONST, nandv4sf3) +BU_P8V_AV_2 (NAND_V2DF, "nand_v2df", CONST, nandv2df3) + +BU_P8V_AV_2 (ORC_V16QI, "orc_v16qi", CONST, orcv16qi3) +BU_P8V_AV_2 (ORC_V8HI, "orc_v8hi", CONST, orcv8hi3) +BU_P8V_AV_2 (ORC_V4SI, "orc_v4si", CONST, orcv4si3) +BU_P8V_AV_2 (ORC_V2DI, "orc_v2di", CONST, orcv2di3) +BU_P8V_AV_2 (ORC_V1TI, "orc_v1ti", CONST, orcv1ti3) +BU_P8V_AV_2 (ORC_V4SF, "orc_v4sf", CONST, orcv4sf3) +BU_P8V_AV_2 (ORC_V2DF, "orc_v2df", CONST, orcv2df3) + +/* 3 argument altivec instructions added in ISA 2.07. */ +BU_P8V_AV_3 (VADDEUQM, "vaddeuqm", CONST, altivec_vaddeuqm) +BU_P8V_AV_3 (VADDECUQ, "vaddecuq", CONST, altivec_vaddecuq) +BU_P8V_AV_3 (VSUBEUQM, "vsubeuqm", CONST, altivec_vsubeuqm) +BU_P8V_AV_3 (VSUBECUQ, "vsubecuq", CONST, altivec_vsubecuq) + +/* Vector comparison instructions added in ISA 2.07. */ +BU_P8V_AV_2 (VCMPEQUD, "vcmpequd", CONST, vector_eqv2di) +BU_P8V_AV_2 (VCMPGTSD, "vcmpgtsd", CONST, vector_gtv2di) +BU_P8V_AV_2 (VCMPGTUD, "vcmpgtud", CONST, vector_gtuv2di) + +/* Vector comparison predicate instructions added in ISA 2.07. */ +BU_P8V_AV_P (VCMPEQUD_P, "vcmpequd_p", CONST, vector_eq_v2di_p) +BU_P8V_AV_P (VCMPGTSD_P, "vcmpgtsd_p", CONST, vector_gt_v2di_p) +BU_P8V_AV_P (VCMPGTUD_P, "vcmpgtud_p", CONST, vector_gtu_v2di_p) + +/* ISA 2.07 vector overloaded 1 argument functions. */ +BU_P8V_OVERLOAD_1 (VUPKHSW, "vupkhsw") +BU_P8V_OVERLOAD_1 (VUPKLSW, "vupklsw") +BU_P8V_OVERLOAD_1 (VCLZ, "vclz") +BU_P8V_OVERLOAD_1 (VCLZB, "vclzb") +BU_P8V_OVERLOAD_1 (VCLZH, "vclzh") +BU_P8V_OVERLOAD_1 (VCLZW, "vclzw") +BU_P8V_OVERLOAD_1 (VCLZD, "vclzd") +BU_P8V_OVERLOAD_1 (VPOPCNT, "vpopcnt") +BU_P8V_OVERLOAD_1 (VPOPCNTB, "vpopcntb") +BU_P8V_OVERLOAD_1 (VPOPCNTH, "vpopcnth") +BU_P8V_OVERLOAD_1 (VPOPCNTW, "vpopcntw") +BU_P8V_OVERLOAD_1 (VPOPCNTD, "vpopcntd") +BU_P8V_OVERLOAD_1 (VGBBD, "vgbbd") + +/* ISA 2.07 vector overloaded 2 argument functions. */ +BU_P8V_OVERLOAD_2 (EQV, "eqv") +BU_P8V_OVERLOAD_2 (NAND, "nand") +BU_P8V_OVERLOAD_2 (ORC, "orc") +BU_P8V_OVERLOAD_2 (VADDCUQ, "vaddcuq") +BU_P8V_OVERLOAD_2 (VADDUDM, "vaddudm") +BU_P8V_OVERLOAD_2 (VADDUQM, "vadduqm") +BU_P8V_OVERLOAD_2 (VBPERMQ, "vbpermq") +BU_P8V_OVERLOAD_2 (VMAXSD, "vmaxsd") +BU_P8V_OVERLOAD_2 (VMAXUD, "vmaxud") +BU_P8V_OVERLOAD_2 (VMINSD, "vminsd") +BU_P8V_OVERLOAD_2 (VMINUD, "vminud") +BU_P8V_OVERLOAD_2 (VMRGEW, "vmrgew") +BU_P8V_OVERLOAD_2 (VMRGOW, "vmrgow") +BU_P8V_OVERLOAD_2 (VPKSDSS, "vpksdss") +BU_P8V_OVERLOAD_2 (VPKSDUS, "vpksdus") +BU_P8V_OVERLOAD_2 (VPKUDUM, "vpkudum") +BU_P8V_OVERLOAD_2 (VPKUDUS, "vpkudus") +BU_P8V_OVERLOAD_2 (VRLD, "vrld") +BU_P8V_OVERLOAD_2 (VSLD, "vsld") +BU_P8V_OVERLOAD_2 (VSRAD, "vsrad") +BU_P8V_OVERLOAD_2 (VSRD, "vsrd") +BU_P8V_OVERLOAD_2 (VSUBCUQ, "vsubcuq") +BU_P8V_OVERLOAD_2 (VSUBUDM, "vsubudm") +BU_P8V_OVERLOAD_2 (VSUBUQM, "vsubuqm") + +/* ISA 2.07 vector overloaded 3 argument functions. */ +BU_P8V_OVERLOAD_3 (VADDECUQ, "vaddecuq") +BU_P8V_OVERLOAD_3 (VADDEUQM, "vaddeuqm") +BU_P8V_OVERLOAD_3 (VSUBECUQ, "vsubecuq") +BU_P8V_OVERLOAD_3 (VSUBEUQM, "vsubeuqm") + + +/* 2 argument extended divide functions added in ISA 2.06. */ +BU_P7_MISC_2 (DIVWE, "divwe", CONST, dive_si) +BU_P7_MISC_2 (DIVWEO, "divweo", CONST, diveo_si) +BU_P7_MISC_2 (DIVWEU, "divweu", CONST, diveu_si) +BU_P7_MISC_2 (DIVWEUO, "divweuo", CONST, diveuo_si) +BU_P7_MISC_2 (DIVDE, "divde", CONST, dive_di) +BU_P7_MISC_2 (DIVDEO, "divdeo", CONST, diveo_di) +BU_P7_MISC_2 (DIVDEU, "divdeu", CONST, diveu_di) +BU_P7_MISC_2 (DIVDEUO, "divdeuo", CONST, diveuo_di) + +/* 1 argument DFP (decimal floating point) functions added in ISA 2.05. */ +BU_DFP_MISC_1 (DXEX, "dxex", CONST, dfp_dxex_dd) +BU_DFP_MISC_1 (DXEXQ, "dxexq", CONST, dfp_dxex_td) + +/* 2 argument DFP (decimal floating point) functions added in ISA 2.05. */ +BU_DFP_MISC_2 (DDEDPD, "ddedpd", CONST, dfp_ddedpd_dd) +BU_DFP_MISC_2 (DDEDPDQ, "ddedpdq", CONST, dfp_ddedpd_td) +BU_DFP_MISC_2 (DENBCD, "denbcd", CONST, dfp_denbcd_dd) +BU_DFP_MISC_2 (DENBCDQ, "denbcdq", CONST, dfp_denbcd_td) +BU_DFP_MISC_2 (DIEX, "diex", CONST, dfp_diex_dd) +BU_DFP_MISC_2 (DIEXQ, "diexq", CONST, dfp_diex_td) +BU_DFP_MISC_2 (DSCLI, "dscli", CONST, dfp_dscli_dd) +BU_DFP_MISC_2 (DSCLIQ, "dscliq", CONST, dfp_dscli_td) +BU_DFP_MISC_2 (DSCRI, "dscri", CONST, dfp_dscri_dd) +BU_DFP_MISC_2 (DSCRIQ, "dscriq", CONST, dfp_dscri_td) + +/* 1 argument BCD functions added in ISA 2.06. */ +BU_P7_MISC_1 (CDTBCD, "cdtbcd", CONST, cdtbcd) +BU_P7_MISC_1 (CBCDTD, "cbcdtd", CONST, cbcdtd) + +/* 2 argument BCD functions added in ISA 2.06. */ +BU_P7_MISC_2 (ADDG6S, "addg6s", CONST, addg6s) + +/* 3 argument BCD functions added in ISA 2.07. */ +BU_P8V_MISC_3 (BCDADD, "bcdadd", CONST, bcdadd) +BU_P8V_MISC_3 (BCDADD_LT, "bcdadd_lt", CONST, bcdadd_lt) +BU_P8V_MISC_3 (BCDADD_EQ, "bcdadd_eq", CONST, bcdadd_eq) +BU_P8V_MISC_3 (BCDADD_GT, "bcdadd_gt", CONST, bcdadd_gt) +BU_P8V_MISC_3 (BCDADD_OV, "bcdadd_ov", CONST, bcdadd_unordered) +BU_P8V_MISC_3 (BCDSUB, "bcdsub", CONST, bcdsub) +BU_P8V_MISC_3 (BCDSUB_LT, "bcdsub_lt", CONST, bcdsub_lt) +BU_P8V_MISC_3 (BCDSUB_EQ, "bcdsub_eq", CONST, bcdsub_eq) +BU_P8V_MISC_3 (BCDSUB_GT, "bcdsub_gt", CONST, bcdsub_gt) +BU_P8V_MISC_3 (BCDSUB_OV, "bcdsub_ov", CONST, bcdsub_unordered) + +/* 2 argument pack/unpack 128-bit floating point types. */ +BU_DFP_MISC_2 (PACK_TD, "pack_dec128", CONST, packtd) +BU_DFP_MISC_2 (UNPACK_TD, "unpack_dec128", CONST, unpacktd) + +BU_LDBL128_2 (PACK_TF, "pack_longdouble", CONST, packtf) +BU_LDBL128_2 (UNPACK_TF, "unpack_longdouble", CONST, unpacktf) + +BU_P7_MISC_2 (PACK_V1TI, "pack_vector_int128", CONST, packv1ti) +BU_P7_MISC_2 (UNPACK_V1TI, "unpack_vector_int128", CONST, unpackv1ti) + + +/* 1 argument crypto functions. */ +BU_CRYPTO_1 (VSBOX, "vsbox", CONST, crypto_vsbox) + +/* 2 argument crypto functions. */ +BU_CRYPTO_2 (VCIPHER, "vcipher", CONST, crypto_vcipher) +BU_CRYPTO_2 (VCIPHERLAST, "vcipherlast", CONST, crypto_vcipherlast) +BU_CRYPTO_2 (VNCIPHER, "vncipher", CONST, crypto_vncipher) +BU_CRYPTO_2 (VNCIPHERLAST, "vncipherlast", CONST, crypto_vncipherlast) +BU_CRYPTO_2A (VPMSUMB, "vpmsumb", CONST, crypto_vpmsumb) +BU_CRYPTO_2A (VPMSUMH, "vpmsumh", CONST, crypto_vpmsumh) +BU_CRYPTO_2A (VPMSUMW, "vpmsumw", CONST, crypto_vpmsumw) +BU_CRYPTO_2A (VPMSUMD, "vpmsumd", CONST, crypto_vpmsumd) + +/* 3 argument crypto functions. */ +BU_CRYPTO_3A (VPERMXOR_V2DI, "vpermxor_v2di", CONST, crypto_vpermxor_v2di) +BU_CRYPTO_3A (VPERMXOR_V4SI, "vpermxor_v4si", CONST, crypto_vpermxor_v4si) +BU_CRYPTO_3A (VPERMXOR_V8HI, "vpermxor_v8hi", CONST, crypto_vpermxor_v8hi) +BU_CRYPTO_3A (VPERMXOR_V16QI, "vpermxor_v16qi", CONST, crypto_vpermxor_v16qi) +BU_CRYPTO_3 (VSHASIGMAW, "vshasigmaw", CONST, crypto_vshasigmaw) +BU_CRYPTO_3 (VSHASIGMAD, "vshasigmad", CONST, crypto_vshasigmad) + +/* 2 argument crypto overloaded functions. */ +BU_CRYPTO_OVERLOAD_2A (VPMSUM, "vpmsum") + +/* 3 argument crypto overloaded functions. */ +BU_CRYPTO_OVERLOAD_3A (VPERMXOR, "vpermxor") +BU_CRYPTO_OVERLOAD_3 (VSHASIGMA, "vshasigma") + + +/* HTM functions. */ +BU_HTM_1 (TABORT, "tabort", CR, tabort) +BU_HTM_3 (TABORTDC, "tabortdc", CR, tabortdc) +BU_HTM_3 (TABORTDCI, "tabortdci", CR, tabortdci) +BU_HTM_3 (TABORTWC, "tabortwc", CR, tabortwc) +BU_HTM_3 (TABORTWCI, "tabortwci", CR, tabortwci) +BU_HTM_1 (TBEGIN, "tbegin", CR, tbegin) +BU_HTM_0 (TCHECK, "tcheck", CR, tcheck) +BU_HTM_1 (TEND, "tend", CR, tend) +BU_HTM_0 (TENDALL, "tendall", CR, tend) +BU_HTM_0 (TRECHKPT, "trechkpt", CR, trechkpt) +BU_HTM_1 (TRECLAIM, "treclaim", CR, treclaim) +BU_HTM_0 (TRESUME, "tresume", CR, tsr) +BU_HTM_0 (TSUSPEND, "tsuspend", CR, tsr) +BU_HTM_1 (TSR, "tsr", CR, tsr) +BU_HTM_0 (TTEST, "ttest", CR, ttest) + +BU_HTM_0 (GET_TFHAR, "get_tfhar", SPR, nothing) +BU_HTM_V1 (SET_TFHAR, "set_tfhar", SPR, nothing) +BU_HTM_0 (GET_TFIAR, "get_tfiar", SPR, nothing) +BU_HTM_V1 (SET_TFIAR, "set_tfiar", SPR, nothing) +BU_HTM_0 (GET_TEXASR, "get_texasr", SPR, nothing) +BU_HTM_V1 (SET_TEXASR, "set_texasr", SPR, nothing) +BU_HTM_0 (GET_TEXASRU, "get_texasru", SPR, nothing) +BU_HTM_V1 (SET_TEXASRU, "set_texasru", SPR, nothing) + /* 3 argument paired floating point builtins. */ BU_PAIRED_3 (MSUB, "msub", FP, fmsv2sf4) @@ -1430,10 +1972,10 @@ BU_SPECIAL_X (RS6000_BUILTIN_RSQRTF, "__builtin_rsqrtf", RS6000_BTM_FRSQRTES, RS6000_BTC_FP) BU_SPECIAL_X (RS6000_BUILTIN_GET_TB, "__builtin_ppc_get_timebase", - RS6000_BTM_ALWAYS, RS6000_BTC_MISC) + RS6000_BTM_ALWAYS, RS6000_BTC_MISC) BU_SPECIAL_X (RS6000_BUILTIN_MFTB, "__builtin_ppc_mftb", - RS6000_BTM_ALWAYS, RS6000_BTC_MISC) + RS6000_BTM_ALWAYS, RS6000_BTC_MISC) /* Darwin CfString builtin. */ BU_SPECIAL_X (RS6000_BUILTIN_CFSTRING, "__builtin_cfstring", RS6000_BTM_ALWAYS, diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c index a4f66ba8f1bdf..94f799cb3b80a 100644 --- a/gcc/config/rs6000/rs6000-c.c +++ b/gcc/config/rs6000/rs6000-c.c @@ -90,6 +90,8 @@ static GTY(()) tree pixel_keyword; static GTY(()) tree __bool_keyword; static GTY(()) tree bool_keyword; static GTY(()) tree _Bool_keyword; +static GTY(()) tree __int128_type; +static GTY(()) tree __uint128_type; /* Preserved across calls. */ static tree expand_bool_pixel; @@ -122,9 +124,10 @@ altivec_categorize_keyword (const cpp_token *tok) static void init_vector_keywords (void) { - /* Keywords without two leading underscores are context-sensitive, - and hence implemented as conditional macros, controlled by the - rs6000_macro_to_expand() function below. */ + /* Keywords without two leading underscores are context-sensitive, and hence + implemented as conditional macros, controlled by the + rs6000_macro_to_expand() function below. If we have ISA 2.07 64-bit + support, record the __int128_t and __uint128_t types. */ __vector_keyword = get_identifier ("__vector"); C_CPP_HASHNODE (__vector_keyword)->flags |= NODE_CONDITIONAL; @@ -146,6 +149,12 @@ init_vector_keywords (void) _Bool_keyword = get_identifier ("_Bool"); C_CPP_HASHNODE (_Bool_keyword)->flags |= NODE_CONDITIONAL; + + if (TARGET_VADDUQM) + { + __int128_type = get_identifier ("__int128_t"); + __uint128_type = get_identifier ("__uint128_t"); + } } /* Called to decide whether a conditional macro should be expanded. @@ -221,7 +230,8 @@ rs6000_macro_to_expand (cpp_reader *pfile, const cpp_token *tok) || rid_code == RID_SHORT || rid_code == RID_SIGNED || rid_code == RID_INT || rid_code == RID_CHAR || rid_code == RID_FLOAT - || (rid_code == RID_DOUBLE && TARGET_VSX)) + || (rid_code == RID_DOUBLE && TARGET_VSX) + || (rid_code == RID_INT128 && TARGET_VADDUQM)) { expand_this = C_CPP_HASHNODE (__vector_keyword); /* If the next keyword is bool or pixel, it @@ -248,6 +258,13 @@ rs6000_macro_to_expand (cpp_reader *pfile, const cpp_token *tok) expand_bool_pixel = __bool_keyword; } } + + /* Support vector __int128_t, but we don't need to worry about bool + or pixel on this type. */ + else if (TARGET_VADDUQM + && (ident == C_CPP_HASHNODE (__int128_type) + || ident == C_CPP_HASHNODE (__uint128_type))) + expand_this = C_CPP_HASHNODE (__vector_keyword); } } else if (expand_bool_pixel && ident == C_CPP_HASHNODE (__pixel_keyword)) @@ -315,6 +332,8 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags, rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6X"); if ((flags & OPTION_MASK_POPCNTD) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7"); + if ((flags & OPTION_MASK_DIRECT_MOVE) != 0) + rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR8"); if ((flags & OPTION_MASK_SOFT_FLOAT) != 0) rs6000_define_or_undefine_macro (define_p, "_SOFT_FLOAT"); if ((flags & OPTION_MASK_RECIP_PRECISION) != 0) @@ -331,6 +350,16 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags, } if ((flags & OPTION_MASK_VSX) != 0) rs6000_define_or_undefine_macro (define_p, "__VSX__"); + if ((flags & OPTION_MASK_HTM) != 0) + rs6000_define_or_undefine_macro (define_p, "__HTM__"); + if ((flags & OPTION_MASK_P8_VECTOR) != 0) + rs6000_define_or_undefine_macro (define_p, "__POWER8_VECTOR__"); + if ((flags & OPTION_MASK_QUAD_MEMORY) != 0) + rs6000_define_or_undefine_macro (define_p, "__QUAD_MEMORY__"); + if ((flags & OPTION_MASK_QUAD_MEMORY_ATOMIC) != 0) + rs6000_define_or_undefine_macro (define_p, "__QUAD_MEMORY_ATOMIC__"); + if ((flags & OPTION_MASK_CRYPTO) != 0) + rs6000_define_or_undefine_macro (define_p, "__CRYPTO__"); /* options from the builtin masks. */ if ((bu_mask & RS6000_BTM_SPE) != 0) @@ -453,6 +482,10 @@ rs6000_cpu_cpp_builtins (cpp_reader *pfile) case ABI_AIX: builtin_define ("_CALL_AIXDESC"); builtin_define ("_CALL_AIX"); + builtin_define ("_CALL_ELF=1"); + break; + case ABI_ELFv2: + builtin_define ("_CALL_ELF=2"); break; case ABI_DARWIN: builtin_define ("_CALL_DARWIN"); @@ -465,6 +498,13 @@ rs6000_cpu_cpp_builtins (cpp_reader *pfile) if (TARGET_SOFT_FLOAT || !TARGET_FPRS) builtin_define ("__NO_FPRS__"); + /* Whether aggregates passed by value are aligned to a 16 byte boundary + if their alignment is 16 bytes or larger. */ + if ((TARGET_MACHO && rs6000_darwin64_abi) + || DEFAULT_ABI == ABI_ELFv2 + || (DEFAULT_ABI == ABI_AIX && !rs6000_compat_align_parm)) + builtin_define ("__STRUCT_PARM_ALIGN__=16"); + /* Generate defines for Xilinx FPU. */ if (rs6000_xilinx_fpu) { @@ -505,6 +545,8 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 }, { ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, + { ALTIVEC_BUILTIN_VEC_ABS, P8V_BUILTIN_ABS_V2DI, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 }, { ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, { ALTIVEC_BUILTIN_VEC_ABS, VSX_BUILTIN_XVABSDP, @@ -553,6 +595,8 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, { ALTIVEC_BUILTIN_VEC_ROUND, ALTIVEC_BUILTIN_VRFIN, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, + { ALTIVEC_BUILTIN_VEC_ROUND, VSX_BUILTIN_XVRDPI, + RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, { ALTIVEC_BUILTIN_VEC_RECIP, ALTIVEC_BUILTIN_VRECIPFP, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, { ALTIVEC_BUILTIN_VEC_RECIP, VSX_BUILTIN_RECIP_V2DF, @@ -577,12 +621,20 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 }, { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSH, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 }, + { ALTIVEC_BUILTIN_VEC_UNPACKH, P8V_BUILTIN_VUPKHSW, + RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 }, + { ALTIVEC_BUILTIN_VEC_UNPACKH, P8V_BUILTIN_VUPKHSW, + RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 }, { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHPX, RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 }, { ALTIVEC_BUILTIN_VEC_VUPKHSH, ALTIVEC_BUILTIN_VUPKHSH, RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 }, { ALTIVEC_BUILTIN_VEC_VUPKHSH, ALTIVEC_BUILTIN_VUPKHSH, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 }, + { ALTIVEC_BUILTIN_VEC_VUPKHSH, P8V_BUILTIN_VUPKHSW, + RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 }, + { ALTIVEC_BUILTIN_VEC_VUPKHSH, P8V_BUILTIN_VUPKHSW, + RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 }, { ALTIVEC_BUILTIN_VEC_VUPKHPX, ALTIVEC_BUILTIN_VUPKHPX, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0, 0 }, { ALTIVEC_BUILTIN_VEC_VUPKHPX, ALTIVEC_BUILTIN_VUPKHPX, @@ -601,6 +653,10 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 }, { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSH, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 }, + { ALTIVEC_BUILTIN_VEC_UNPACKL, P8V_BUILTIN_VUPKLSW, + RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 }, + { ALTIVEC_BUILTIN_VEC_UNPACKL, P8V_BUILTIN_VUPKLSW, + RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 }, { ALTIVEC_BUILTIN_VEC_VUPKLPX, ALTIVEC_BUILTIN_VUPKLPX, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0, 0 }, { ALTIVEC_BUILTIN_VEC_VUPKLPX, ALTIVEC_BUILTIN_VUPKLPX, @@ -651,10 +707,27 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, + { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM, + RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDFP, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, { ALTIVEC_BUILTIN_VEC_ADD, VSX_BUILTIN_XVADDDP, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, + { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUQM, + RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 }, + { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUQM, + RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, + RS6000_BTI_unsigned_V1TI, 0 }, { ALTIVEC_BUILTIN_VEC_VADDFP, ALTIVEC_BUILTIN_VADDFP, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM, @@ -803,6 +876,18 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 }, + { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, + RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, @@ -857,6 +942,18 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 }, + { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, + RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, @@ -937,6 +1034,10 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUW, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, + { ALTIVEC_BUILTIN_VEC_CMPEQ, P8V_BUILTIN_VCMPEQUD, + RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_CMPEQ, P8V_BUILTIN_VCMPEQUD, + RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQFP, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, { ALTIVEC_BUILTIN_VEC_CMPEQ, VSX_BUILTIN_XVCMPEQDP, @@ -975,6 +1076,10 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTSW, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, + { ALTIVEC_BUILTIN_VEC_CMPGT, P8V_BUILTIN_VCMPGTUD, + RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_CMPGT, P8V_BUILTIN_VCMPGTSD, + RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTFP, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, { ALTIVEC_BUILTIN_VEC_CMPGT, VSX_BUILTIN_XVCMPGTDP, @@ -1021,6 +1126,10 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTSW, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, + { ALTIVEC_BUILTIN_VEC_CMPLT, P8V_BUILTIN_VCMPGTUD, + RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_CMPLT, P8V_BUILTIN_VCMPGTSD, + RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTFP, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, { ALTIVEC_BUILTIN_VEC_CMPLT, VSX_BUILTIN_XVCMPGTDP, @@ -1033,66 +1142,78 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 }, { ALTIVEC_BUILTIN_VEC_CTF, ALTIVEC_BUILTIN_VCFSX, RS6000_BTI_V4SF, RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0 }, + { ALTIVEC_BUILTIN_VEC_CTF, VSX_BUILTIN_XVCVSXDDP_SCALE, + RS6000_BTI_V2DF, RS6000_BTI_V2DI, RS6000_BTI_INTSI, 0}, + { ALTIVEC_BUILTIN_VEC_CTF, VSX_BUILTIN_XVCVUXDDP_SCALE, + RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 0}, { ALTIVEC_BUILTIN_VEC_VCFSX, ALTIVEC_BUILTIN_VCFSX, RS6000_BTI_V4SF, RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0 }, { ALTIVEC_BUILTIN_VEC_VCFUX, ALTIVEC_BUILTIN_VCFUX, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 }, { ALTIVEC_BUILTIN_VEC_CTS, ALTIVEC_BUILTIN_VCTSXS, RS6000_BTI_V4SI, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 }, + { ALTIVEC_BUILTIN_VEC_CTS, VSX_BUILTIN_XVCVDPSXDS_SCALE, + RS6000_BTI_V2DI, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 }, { ALTIVEC_BUILTIN_VEC_CTU, ALTIVEC_BUILTIN_VCTUXS, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 }, + { ALTIVEC_BUILTIN_VEC_CTU, VSX_BUILTIN_XVCVDPUXDS_SCALE, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 }, { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_XVDIVSP, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_XVDIVDP, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, - { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX, + { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_DIV_V2DI, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, + { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_UDIV_V2DI, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DF, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 }, - { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX, + { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX, + { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX, + { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX, + { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 }, - { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX, + { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, - { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX, + { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX, + { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX, + { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, - { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX, + { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 }, - { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX, + { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX, + { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, - { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX, + { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 }, - { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX, + { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX, + { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX, + { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX, + { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, - { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX, + { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX, + { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, - { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX, + { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX, + { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX, + { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, - { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX, + { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX, + { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEBX, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, @@ -1130,55 +1251,55 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, { ALTIVEC_BUILTIN_VEC_LVEBX, ALTIVEC_BUILTIN_LVEBX, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, - { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL, + { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 }, - { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL, + { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, - { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL, + { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL, + { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL, + { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, - { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL, + { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 }, - { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL, + { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL, + { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, - { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL, + { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 }, - { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL, + { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL, + { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL, + { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL, + { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, - { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL, + { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL, + { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, - { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL, + { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL, + { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL, + { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, - { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL, + { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL, + { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, - { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL, + { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DF, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 }, - { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL, + { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL, + { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL, + { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, @@ -1418,6 +1539,18 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSW, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, + { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXUD, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXUD, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXUD, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXSD, + RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXSD, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXSD, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXFP, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, { ALTIVEC_BUILTIN_VEC_MAX, VSX_BUILTIN_XVMAXDP, @@ -1498,6 +1631,16 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI, + RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW, @@ -1546,6 +1689,16 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI, + RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW, @@ -1604,6 +1757,18 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSW, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, + { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINUD, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINUD, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINUD, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINSD, + RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINSD, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINSD, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINFP, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, { ALTIVEC_BUILTIN_VEC_MIN, VSX_BUILTIN_XVMINDP, @@ -1662,6 +1827,10 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, { VSX_BUILTIN_VEC_MUL, VSX_BUILTIN_XVMULDP, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, + { VSX_BUILTIN_VEC_MUL, VSX_BUILTIN_MUL_V2DI, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, + { VSX_BUILTIN_VEC_MUL, VSX_BUILTIN_MUL_V2DI, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULEUB, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULESB, @@ -1702,6 +1871,18 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, + { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, + RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, @@ -1732,6 +1913,18 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 }, + { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, + RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, @@ -1786,6 +1979,12 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUWUM, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, + { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM, + RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM, + RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_VPKUWUM, ALTIVEC_BUILTIN_VPKUWUM, RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_VPKUWUM, ALTIVEC_BUILTIN_VPKUWUM, @@ -1812,6 +2011,10 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_VPKUWUS, ALTIVEC_BUILTIN_VPKUWUS, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, + { ALTIVEC_BUILTIN_VEC_PACKS, P8V_BUILTIN_VPKUDUS, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_PACKS, P8V_BUILTIN_VPKSDSS, + RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_VPKSHSS, ALTIVEC_BUILTIN_VPKSHSS, RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, { ALTIVEC_BUILTIN_VEC_VPKUHUS, ALTIVEC_BUILTIN_VPKUHUS, @@ -1824,6 +2027,10 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_PACKSU, ALTIVEC_BUILTIN_VPKSWUS, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, + { ALTIVEC_BUILTIN_VEC_PACKSU, P8V_BUILTIN_VPKSDUS, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_PACKSU, P8V_BUILTIN_VPKSDUS, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_VPKSWUS, ALTIVEC_BUILTIN_VPKSWUS, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_VPKSHUS, ALTIVEC_BUILTIN_VPKSHUS, @@ -1844,6 +2051,10 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLW, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, + { ALTIVEC_BUILTIN_VEC_RL, P8V_BUILTIN_VRLD, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_RL, P8V_BUILTIN_VRLD, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_VRLW, ALTIVEC_BUILTIN_VRLW, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_VRLW, ALTIVEC_BUILTIN_VRLW, @@ -1868,6 +2079,10 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLW, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, + { ALTIVEC_BUILTIN_VEC_SL, P8V_BUILTIN_VSLD, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_SL, P8V_BUILTIN_VSLD, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_SQRT, VSX_BUILTIN_XVSQRTDP, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, { ALTIVEC_BUILTIN_VEC_SQRT, VSX_BUILTIN_XVSQRTSP, @@ -1998,6 +2213,14 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 }, { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTW, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, 0 }, + { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DF, + RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 }, + { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DI, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTSI, 0 }, + { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DI, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 0 }, + { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DI, + RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, 0 }, { ALTIVEC_BUILTIN_VEC_VSPLTW, ALTIVEC_BUILTIN_VSPLTW, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 }, { ALTIVEC_BUILTIN_VEC_VSPLTW, ALTIVEC_BUILTIN_VSPLTW, @@ -2032,6 +2255,10 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRW, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, + { ALTIVEC_BUILTIN_VEC_SR, P8V_BUILTIN_VSRD, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_SR, P8V_BUILTIN_VSRD, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_VSRW, ALTIVEC_BUILTIN_VSRW, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_VSRW, ALTIVEC_BUILTIN_VSRW, @@ -2056,6 +2283,10 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAW, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, + { ALTIVEC_BUILTIN_VEC_SRA, P8V_BUILTIN_VSRAD, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_SRA, P8V_BUILTIN_VSRD, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_VSRAW, ALTIVEC_BUILTIN_VSRAW, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_VSRAW, ALTIVEC_BUILTIN_VSRAW, @@ -2196,10 +2427,27 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, + { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM, + RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBFP, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, { ALTIVEC_BUILTIN_VEC_SUB, VSX_BUILTIN_XVSUBDP, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, + { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUQM, + RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 }, + { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUQM, + RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, + RS6000_BTI_unsigned_V1TI, 0 }, { ALTIVEC_BUILTIN_VEC_VSUBFP, ALTIVEC_BUILTIN_VSUBFP, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM, @@ -2364,6 +2612,18 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 }, + { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, + RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, @@ -2624,6 +2884,8 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_unsigned_V16QI }, { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI }, + { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_2DI, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI }, { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V16QI }, { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_4SI, @@ -2664,6 +2926,12 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI }, { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI }, + { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI }, + { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI }, + { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DI }, { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI }, { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SF, @@ -2730,63 +2998,63 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_NOT_OPAQUE }, { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_NOT_OPAQUE }, - { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX, + { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DF, RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF }, - { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX, + { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI, RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI }, - { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX, + { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI, RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V2DI }, - { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX, + { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI, RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI }, - { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX, + { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SF, RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF }, - { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX, + { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SF, RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float }, - { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX, + { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI, RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI }, - { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX, + { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI, RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX, + { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI, RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI }, - { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX, + { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI, RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, - { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX, + { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI, RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI }, - { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX, + { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI, RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, - { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX, + { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI, RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX, + { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI, RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI }, - { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX, + { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI, RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, - { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX, + { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI, RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI }, - { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX, + { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI, RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, - { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX, + { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI, RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI }, - { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX, + { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI, RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, - { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX, + { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI, RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, - { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX, + { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI, RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI }, - { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX, + { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI, RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, - { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX, + { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI, RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI }, - { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX, + { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI, RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, - { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX, + { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI, RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI }, - { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX, + { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI, RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, - { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX, + { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI, RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, - { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX, + { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI, RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI }, { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEBX, RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, @@ -2858,64 +3126,64 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_void }, { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX, RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_void }, - { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL, + { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SF, RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF }, - { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL, + { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SF, RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float }, - { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL, + { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI, RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI }, - { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL, + { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI, RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL, + { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI, RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI }, - { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL, + { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI, RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, - { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL, + { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI, RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI }, - { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL, + { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI, RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, - { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL, + { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI, RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL, + { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI, RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI }, - { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL, + { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI, RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, - { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL, + { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI, RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI }, - { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL, + { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI, RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, - { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL, + { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI, RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI }, - { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL, + { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI, RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, - { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL, + { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI, RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, - { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL, + { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI, RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI }, - { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL, + { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI, RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, - { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL, + { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI, RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI }, - { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL, + { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI, RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, - { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL, + { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI, RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI }, - { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL, + { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI, RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, - { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL, + { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI, RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, - { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL, + { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI, RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI }, - { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL, + { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DF, RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF }, - { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL, + { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DF, RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double }, - { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL, + { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DI, RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI }, - { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL, + { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DI, RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V2DI }, - { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL, + { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DI, RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI }, { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, @@ -3113,6 +3381,8 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DF, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 }, + { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DF, + RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 }, { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 }, { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI, @@ -3167,6 +3437,8 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DF, RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF }, + { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DF, + RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double }, { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI, RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI }, { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI, @@ -3277,6 +3549,18 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI }, { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSW_P, RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI }, + { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTUD_P, + RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI }, + { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTUD_P, + RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI }, + { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTUD_P, + RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI }, + { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTSD_P, + RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI }, + { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTSD_P, + RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI }, + { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTSD_P, + RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI }, { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTFP_P, RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF }, { ALTIVEC_BUILTIN_VEC_VCMPGT_P, VSX_BUILTIN_XVCMPGTDP_P, @@ -3327,6 +3611,20 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI }, { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P, RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI }, + { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P, + RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI }, + { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P, + RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI }, + { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P, + RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI }, + { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P, + RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI }, + { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P, + RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI }, + { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P, + RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI }, + { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P, + RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI }, { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQFP_P, RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF }, { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, VSX_BUILTIN_XVCMPEQDP_P, @@ -3372,11 +3670,513 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI }, { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSW_P, RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI }, + { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTUD_P, + RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI }, + { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTUD_P, + RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI }, + { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTUD_P, + RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI }, + { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTSD_P, + RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI }, + { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTSD_P, + RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI }, + { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTSD_P, + RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI }, { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGEFP_P, RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF }, { ALTIVEC_BUILTIN_VEC_VCMPGE_P, VSX_BUILTIN_XVCMPGEDP_P, RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF }, + /* Power8 vector overloaded functions. */ + { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI, + RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, + { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI, + RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, + { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI, + RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, + { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI, + RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, + RS6000_BTI_unsigned_V16QI, 0 }, + { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI, + RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, + RS6000_BTI_bool_V16QI, 0 }, + { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI, + RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, + RS6000_BTI_unsigned_V16QI, 0 }, + { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI, + RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, + { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI, + RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, + { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI, + RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, + { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI, + RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, + RS6000_BTI_unsigned_V8HI, 0 }, + { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI, + RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, + RS6000_BTI_bool_V8HI, 0 }, + { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI, + RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, + RS6000_BTI_unsigned_V8HI, 0 }, + { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI, + RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, + { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI, + RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, + { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI, + RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, + { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, + RS6000_BTI_unsigned_V4SI, 0 }, + { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, + RS6000_BTI_bool_V4SI, 0 }, + { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, + RS6000_BTI_unsigned_V4SI, 0 }, + { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI, + RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, + { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, + { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, + RS6000_BTI_unsigned_V2DI, 0 }, + { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, + RS6000_BTI_bool_V2DI, 0 }, + { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, + RS6000_BTI_unsigned_V2DI, 0 }, + { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SF, + RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, + { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DF, + RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, + + { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI, + RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, + { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI, + RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, + { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI, + RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, + { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI, + RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, + RS6000_BTI_unsigned_V16QI, 0 }, + { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI, + RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, + RS6000_BTI_bool_V16QI, 0 }, + { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI, + RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, + RS6000_BTI_unsigned_V16QI, 0 }, + { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI, + RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, + { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI, + RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, + { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI, + RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, + { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI, + RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, + RS6000_BTI_unsigned_V8HI, 0 }, + { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI, + RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, + RS6000_BTI_bool_V8HI, 0 }, + { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI, + RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, + RS6000_BTI_unsigned_V8HI, 0 }, + { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI, + RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, + { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI, + RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, + { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI, + RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, + { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, + RS6000_BTI_unsigned_V4SI, 0 }, + { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, + RS6000_BTI_bool_V4SI, 0 }, + { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, + RS6000_BTI_unsigned_V4SI, 0 }, + { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI, + RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, + { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, + { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, + RS6000_BTI_unsigned_V2DI, 0 }, + { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, + RS6000_BTI_bool_V2DI, 0 }, + { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, + RS6000_BTI_unsigned_V2DI, 0 }, + { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SF, + RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, + { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DF, + RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, + + { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI, + RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, + { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI, + RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, + { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI, + RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, + { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI, + RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, + RS6000_BTI_unsigned_V16QI, 0 }, + { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI, + RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, + RS6000_BTI_bool_V16QI, 0 }, + { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI, + RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, + RS6000_BTI_unsigned_V16QI, 0 }, + { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI, + RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, + { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI, + RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, + { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI, + RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, + { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI, + RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, + RS6000_BTI_unsigned_V8HI, 0 }, + { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI, + RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, + RS6000_BTI_bool_V8HI, 0 }, + { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI, + RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, + RS6000_BTI_unsigned_V8HI, 0 }, + { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI, + RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, + { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI, + RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, + { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI, + RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, + { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, + RS6000_BTI_unsigned_V4SI, 0 }, + { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, + RS6000_BTI_bool_V4SI, 0 }, + { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, + RS6000_BTI_unsigned_V4SI, 0 }, + { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI, + RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, + { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, + { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, + RS6000_BTI_unsigned_V2DI, 0 }, + { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, + RS6000_BTI_bool_V2DI, 0 }, + { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, + RS6000_BTI_unsigned_V2DI, 0 }, + { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SF, + RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, + { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DF, + RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, + + { P8V_BUILTIN_VEC_VADDCUQ, P8V_BUILTIN_VADDCUQ, + RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 }, + { P8V_BUILTIN_VEC_VADDCUQ, P8V_BUILTIN_VADDCUQ, + RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, + RS6000_BTI_unsigned_V1TI, 0 }, + + { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM, + RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, + { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, + { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + + { P8V_BUILTIN_VEC_VADDUQM, P8V_BUILTIN_VADDUQM, + RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 }, + { P8V_BUILTIN_VEC_VADDUQM, P8V_BUILTIN_VADDUQM, + RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, + RS6000_BTI_unsigned_V1TI, 0 }, + + { P8V_BUILTIN_VEC_VBPERMQ, P8V_BUILTIN_VBPERMQ, + RS6000_BTI_V2DI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, + { P8V_BUILTIN_VEC_VBPERMQ, P8V_BUILTIN_VBPERMQ, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, + RS6000_BTI_unsigned_V16QI, 0 }, + + { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZB, + RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, + { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZB, + RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 }, + { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZH, + RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 }, + { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZH, + RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 }, + { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZW, + RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, + { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZW, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 }, + { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZD, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 }, + { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZD, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 }, + + { P8V_BUILTIN_VEC_VCLZB, P8V_BUILTIN_VCLZB, + RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, + { P8V_BUILTIN_VEC_VCLZB, P8V_BUILTIN_VCLZB, + RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 }, + + { P8V_BUILTIN_VEC_VCLZH, P8V_BUILTIN_VCLZH, + RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 }, + { P8V_BUILTIN_VEC_VCLZH, P8V_BUILTIN_VCLZH, + RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 }, + + { P8V_BUILTIN_VEC_VCLZW, P8V_BUILTIN_VCLZW, + RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, + { P8V_BUILTIN_VEC_VCLZW, P8V_BUILTIN_VCLZW, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 }, + + { P8V_BUILTIN_VEC_VCLZD, P8V_BUILTIN_VCLZD, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 }, + { P8V_BUILTIN_VEC_VCLZD, P8V_BUILTIN_VCLZD, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 }, + + { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD, + RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, + { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD, + RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 }, + + { P8V_BUILTIN_VEC_VADDECUQ, P8V_BUILTIN_VADDECUQ, + RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI }, + { P8V_BUILTIN_VEC_VADDECUQ, P8V_BUILTIN_VADDECUQ, + RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, + RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI }, + + { P8V_BUILTIN_VEC_VADDEUQM, P8V_BUILTIN_VADDEUQM, + RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI }, + { P8V_BUILTIN_VEC_VADDEUQM, P8V_BUILTIN_VADDEUQM, + RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, + RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI }, + + { P8V_BUILTIN_VEC_VSUBECUQ, P8V_BUILTIN_VSUBECUQ, + RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI }, + { P8V_BUILTIN_VEC_VSUBECUQ, P8V_BUILTIN_VSUBECUQ, + RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, + RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI }, + + { P8V_BUILTIN_VEC_VSUBEUQM, P8V_BUILTIN_VSUBEUQM, + RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI }, + { P8V_BUILTIN_VEC_VSUBEUQM, P8V_BUILTIN_VSUBEUQM, + RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, + RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI }, + + { P8V_BUILTIN_VEC_VMINSD, P8V_BUILTIN_VMINSD, + RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, + { P8V_BUILTIN_VEC_VMINSD, P8V_BUILTIN_VMINSD, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { P8V_BUILTIN_VEC_VMINSD, P8V_BUILTIN_VMINSD, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, + + { P8V_BUILTIN_VEC_VMAXSD, P8V_BUILTIN_VMAXSD, + RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, + { P8V_BUILTIN_VEC_VMAXSD, P8V_BUILTIN_VMAXSD, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { P8V_BUILTIN_VEC_VMAXSD, P8V_BUILTIN_VMAXSD, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, + + { P8V_BUILTIN_VEC_VMINUD, P8V_BUILTIN_VMINUD, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, + RS6000_BTI_unsigned_V2DI, 0 }, + { P8V_BUILTIN_VEC_VMINUD, P8V_BUILTIN_VMINUD, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, + RS6000_BTI_bool_V2DI, 0 }, + { P8V_BUILTIN_VEC_VMINUD, P8V_BUILTIN_VMINUD, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, + RS6000_BTI_unsigned_V2DI, 0 }, + + { P8V_BUILTIN_VEC_VMAXUD, P8V_BUILTIN_VMAXUD, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, + RS6000_BTI_unsigned_V2DI, 0 }, + { P8V_BUILTIN_VEC_VMAXUD, P8V_BUILTIN_VMAXUD, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, + RS6000_BTI_bool_V2DI, 0 }, + { P8V_BUILTIN_VEC_VMAXUD, P8V_BUILTIN_VMAXUD, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, + RS6000_BTI_unsigned_V2DI, 0 }, + + { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW, + RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, + { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, + RS6000_BTI_unsigned_V4SI, 0 }, + { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW, + RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, + + { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW, + RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, + { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, + RS6000_BTI_unsigned_V4SI, 0 }, + { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW, + RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, + + { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTB, + RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, + { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTB, + RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 }, + { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTH, + RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 }, + { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTH, + RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 }, + { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTW, + RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, + { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTW, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 }, + { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTD, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 }, + { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTD, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 }, + + { P8V_BUILTIN_VEC_VPOPCNTB, P8V_BUILTIN_VPOPCNTB, + RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, + { P8V_BUILTIN_VEC_VPOPCNTB, P8V_BUILTIN_VPOPCNTB, + RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 }, + + { P8V_BUILTIN_VEC_VPOPCNTH, P8V_BUILTIN_VPOPCNTH, + RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 }, + { P8V_BUILTIN_VEC_VPOPCNTH, P8V_BUILTIN_VPOPCNTH, + RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 }, + + { P8V_BUILTIN_VEC_VPOPCNTW, P8V_BUILTIN_VPOPCNTW, + RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, + { P8V_BUILTIN_VEC_VPOPCNTW, P8V_BUILTIN_VPOPCNTW, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 }, + + { P8V_BUILTIN_VEC_VPOPCNTD, P8V_BUILTIN_VPOPCNTD, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 }, + { P8V_BUILTIN_VEC_VPOPCNTD, P8V_BUILTIN_VPOPCNTD, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 }, + + { P8V_BUILTIN_VEC_VPKUDUM, P8V_BUILTIN_VPKUDUM, + RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, + { P8V_BUILTIN_VEC_VPKUDUM, P8V_BUILTIN_VPKUDUM, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { P8V_BUILTIN_VEC_VPKUDUM, P8V_BUILTIN_VPKUDUM, + RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, + + { P8V_BUILTIN_VEC_VPKSDSS, P8V_BUILTIN_VPKSDSS, + RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, + + { P8V_BUILTIN_VEC_VPKUDUS, P8V_BUILTIN_VPKUDUS, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + + { P8V_BUILTIN_VEC_VPKSDUS, P8V_BUILTIN_VPKSDUS, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, + + { P8V_BUILTIN_VEC_VRLD, P8V_BUILTIN_VRLD, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { P8V_BUILTIN_VEC_VRLD, P8V_BUILTIN_VRLD, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + + { P8V_BUILTIN_VEC_VSLD, P8V_BUILTIN_VSLD, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { P8V_BUILTIN_VEC_VSLD, P8V_BUILTIN_VSLD, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + + { P8V_BUILTIN_VEC_VSRD, P8V_BUILTIN_VSRD, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { P8V_BUILTIN_VEC_VSRD, P8V_BUILTIN_VSRD, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + + { P8V_BUILTIN_VEC_VSRAD, P8V_BUILTIN_VSRAD, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { P8V_BUILTIN_VEC_VSRAD, P8V_BUILTIN_VSRD, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + + { P8V_BUILTIN_VEC_VSUBCUQ, P8V_BUILTIN_VSUBCUQ, + RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 }, + { P8V_BUILTIN_VEC_VSUBCUQ, P8V_BUILTIN_VSUBCUQ, + RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, + RS6000_BTI_unsigned_V1TI, 0 }, + + { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM, + RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, + { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, + { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + + { P8V_BUILTIN_VEC_VSUBUQM, P8V_BUILTIN_VSUBUQM, + RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 }, + { P8V_BUILTIN_VEC_VSUBUQM, P8V_BUILTIN_VSUBUQM, + RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, + RS6000_BTI_unsigned_V1TI, 0 }, + + { P8V_BUILTIN_VEC_VUPKHSW, P8V_BUILTIN_VUPKHSW, + RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 }, + { P8V_BUILTIN_VEC_VUPKHSW, P8V_BUILTIN_VUPKHSW, + RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 }, + + { P8V_BUILTIN_VEC_VUPKLSW, P8V_BUILTIN_VUPKLSW, + RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 }, + { P8V_BUILTIN_VEC_VUPKLSW, P8V_BUILTIN_VUPKLSW, + RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 }, + + { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD, + RS6000_BTI_V16QI, 0, 0, 0 }, + { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD, + RS6000_BTI_unsigned_V16QI, 0, 0, 0 }, + + /* Crypto builtins. */ + { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V16QI, + RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, + RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI }, + { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V8HI, + RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, + RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI }, + { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V4SI, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI }, + { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V2DI, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI }, + + { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMB, + RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, + RS6000_BTI_unsigned_V16QI, 0 }, + { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMH, + RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, + RS6000_BTI_unsigned_V8HI, 0 }, + { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMW, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, + RS6000_BTI_unsigned_V4SI, 0 }, + { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMD, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, + RS6000_BTI_unsigned_V2DI, 0 }, + + { CRYPTO_BUILTIN_VSHASIGMA, CRYPTO_BUILTIN_VSHASIGMAW, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, + RS6000_BTI_INTSI, RS6000_BTI_INTSI }, + { CRYPTO_BUILTIN_VSHASIGMA, CRYPTO_BUILTIN_VSHASIGMAD, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, + RS6000_BTI_INTSI, RS6000_BTI_INTSI }, + { (enum rs6000_builtins) 0, (enum rs6000_builtins) 0, 0, 0, 0, 0 } }; @@ -3462,7 +4262,8 @@ altivec_build_resolved_builtin (tree *args, int n, argument) is reversed. Patch the arguments here before building the resolved CALL_EXPR. */ if (desc->code == ALTIVEC_BUILTIN_VEC_VCMPGE_P - && desc->overloaded_code != ALTIVEC_BUILTIN_VCMPGEFP_P) + && desc->overloaded_code != ALTIVEC_BUILTIN_VCMPGEFP_P + && desc->overloaded_code != VSX_BUILTIN_XVCMPGEDP_P) { tree t; t = args[2], args[2] = args[1], args[1] = t; @@ -3520,6 +4321,14 @@ altivec_resolve_overloaded_builtin (location_t loc, tree fndecl, if (TARGET_DEBUG_BUILTIN) fprintf (stderr, "altivec_resolve_overloaded_builtin, code = %4d, %s\n", (int)fcode, IDENTIFIER_POINTER (DECL_NAME (fndecl))); + + /* vec_lvsl and vec_lvsr are deprecated for use with LE element order. */ + if (fcode == ALTIVEC_BUILTIN_VEC_LVSL && !VECTOR_ELT_ORDER_BIG) + warning (OPT_Wdeprecated, "vec_lvsl is deprecated for little endian; use \ +assignment for unaligned loads and stores"); + else if (fcode == ALTIVEC_BUILTIN_VEC_LVSR && !VECTOR_ELT_ORDER_BIG) + warning (OPT_Wdeprecated, "vec_lvsr is deprecated for little endian; use \ +assignment for unaligned loads and stores"); /* For now treat vec_splats and vec_promote as the same. */ if (fcode == ALTIVEC_BUILTIN_VEC_SPLATS @@ -3560,6 +4369,10 @@ altivec_resolve_overloaded_builtin (location_t loc, tree fndecl, unsigned_p = TYPE_UNSIGNED (type); switch (TYPE_MODE (type)) { + case TImode: + type = (unsigned_p ? unsigned_V1TI_type_node : V1TI_type_node); + size = 1; + break; case DImode: type = (unsigned_p ? unsigned_V2DI_type_node : V2DI_type_node); size = 2; @@ -3591,7 +4404,7 @@ altivec_resolve_overloaded_builtin (location_t loc, tree fndecl, return build_constructor (type, vec); } - /* For now use pointer tricks to do the extaction, unless we are on VSX + /* For now use pointer tricks to do the extraction, unless we are on VSX extracting a double from a constant offset. */ if (fcode == ALTIVEC_BUILTIN_VEC_EXTRACT) { @@ -3619,6 +4432,17 @@ altivec_resolve_overloaded_builtin (location_t loc, tree fndecl, if (!INTEGRAL_TYPE_P (TREE_TYPE (arg2))) goto bad; + /* If we are targeting little-endian, but -maltivec=be has been + specified to override the element order, adjust the element + number accordingly. */ + if (!BYTES_BIG_ENDIAN && rs6000_altivec_element_order == 2) + { + unsigned int last_elem = TYPE_VECTOR_SUBPARTS (arg1_type) - 1; + arg2 = fold_build2_loc (loc, MINUS_EXPR, TREE_TYPE (arg2), + build_int_cstu (TREE_TYPE (arg2), last_elem), + arg2); + } + /* If we can use the VSX xxpermdi instruction, use that for extract. */ mode = TYPE_MODE (arg1_type); if ((mode == V2DFmode || mode == V2DImode) && VECTOR_MEM_VSX_P (mode) @@ -3636,6 +4460,14 @@ altivec_resolve_overloaded_builtin (location_t loc, tree fndecl, if (call) return build_call_expr (call, 2, arg1, arg2); } + else if (mode == V1TImode && VECTOR_MEM_VSX_P (mode) + && TREE_CODE (arg2) == INTEGER_CST + && TREE_INT_CST_HIGH (arg2) == 0 + && TREE_INT_CST_LOW (arg2) == 0) + { + tree call = rs6000_builtin_decls[VSX_BUILTIN_VEC_EXT_V1TI]; + return build_call_expr (call, 2, arg1, arg2); + } /* Build *(((arg1_inner_type*)&(vector type){arg1})+arg2). */ arg1_inner_type = TREE_TYPE (arg1_type); @@ -3666,7 +4498,7 @@ altivec_resolve_overloaded_builtin (location_t loc, tree fndecl, return stmt; } - /* For now use pointer tricks to do the insertation, unless we are on VSX + /* For now use pointer tricks to do the insertion, unless we are on VSX inserting a double to a constant offset.. */ if (fcode == ALTIVEC_BUILTIN_VEC_INSERT) { @@ -3696,6 +4528,17 @@ altivec_resolve_overloaded_builtin (location_t loc, tree fndecl, if (!INTEGRAL_TYPE_P (TREE_TYPE (arg2))) goto bad; + /* If we are targeting little-endian, but -maltivec=be has been + specified to override the element order, adjust the element + number accordingly. */ + if (!BYTES_BIG_ENDIAN && rs6000_altivec_element_order == 2) + { + unsigned int last_elem = TYPE_VECTOR_SUBPARTS (arg1_type) - 1; + arg2 = fold_build2_loc (loc, MINUS_EXPR, TREE_TYPE (arg2), + build_int_cstu (TREE_TYPE (arg2), last_elem), + arg2); + } + /* If we can use the VSX xxpermdi instruction, use that for insert. */ mode = TYPE_MODE (arg1_type); if ((mode == V2DFmode || mode == V2DImode) && VECTOR_UNIT_VSX_P (mode) @@ -3715,6 +4558,17 @@ altivec_resolve_overloaded_builtin (location_t loc, tree fndecl, if (call) return build_call_expr (call, 3, arg1, arg0, arg2); } + else if (mode == V1TImode && VECTOR_UNIT_VSX_P (mode) + && TREE_CODE (arg2) == INTEGER_CST + && TREE_INT_CST_HIGH (arg2) == 0 + && TREE_INT_CST_LOW (arg2) == 0) + { + tree call = rs6000_builtin_decls[VSX_BUILTIN_VEC_SET_V1TI]; + + /* Note, __builtin_vec_insert_ has vector and scalar types + reversed. */ + return build_call_expr (call, 3, arg1, arg0, arg2); + } /* Build *(((arg1_inner_type*)&(vector type){arg1})+arg2) = arg0. */ arg1_inner_type = TREE_TYPE (arg1_type); @@ -3824,7 +4678,8 @@ altivec_resolve_overloaded_builtin (location_t loc, tree fndecl, && (desc->op2 == RS6000_BTI_NOT_OPAQUE || rs6000_builtin_type_compatible (types[1], desc->op2)) && (desc->op3 == RS6000_BTI_NOT_OPAQUE - || rs6000_builtin_type_compatible (types[2], desc->op3))) + || rs6000_builtin_type_compatible (types[2], desc->op3)) + && rs6000_builtin_decls[desc->overloaded_code] != NULL_TREE) return altivec_build_resolved_builtin (args, n, desc); bad: diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def index 3f17c6f2395f3..abe0ce6b7ac2f 100644 --- a/gcc/config/rs6000/rs6000-cpus.def +++ b/gcc/config/rs6000/rs6000-cpus.def @@ -1,5 +1,5 @@ /* IBM RS/6000 CPU names.. - Copyright (C) 1991-2013 Free Software Foundation, Inc. + Copyright (C) 1991-2015 Free Software Foundation, Inc. Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) This file is part of GCC. @@ -28,7 +28,7 @@ ALTIVEC, since in general it isn't a win on power6. In ISA 2.04, fsel, fre, fsqrt, etc. were no longer documented as optional. Group masks by server and embedded. */ -#define ISA_2_5_MASKS_EMBEDDED (ISA_2_2_MASKS \ +#define ISA_2_5_MASKS_EMBEDDED (ISA_2_4_MASKS \ | OPTION_MASK_CMPB \ | OPTION_MASK_RECIP_PRECISION \ | OPTION_MASK_PPC_GFXOPT \ @@ -38,12 +38,24 @@ /* For ISA 2.06, don't add ISEL, since in general it isn't a win, but altivec is a win so enable it. */ + /* OPTION_MASK_VSX_TIMODE should be set, but disable it for now until + PR 58587 is fixed. */ #define ISA_2_6_MASKS_EMBEDDED (ISA_2_5_MASKS_EMBEDDED | OPTION_MASK_POPCNTD) #define ISA_2_6_MASKS_SERVER (ISA_2_5_MASKS_SERVER \ | OPTION_MASK_POPCNTD \ | OPTION_MASK_ALTIVEC \ | OPTION_MASK_VSX) +/* For now, don't provide an embedded version of ISA 2.07. */ +#define ISA_2_7_MASKS_SERVER (ISA_2_6_MASKS_SERVER \ + | OPTION_MASK_P8_FUSION \ + | OPTION_MASK_P8_VECTOR \ + | OPTION_MASK_CRYPTO \ + | OPTION_MASK_DIRECT_MOVE \ + | OPTION_MASK_HTM \ + | OPTION_MASK_QUAD_MEMORY \ + | OPTION_MASK_QUAD_MEMORY_ATOMIC) + #define POWERPC_7400_MASK (OPTION_MASK_PPC_GFXOPT | OPTION_MASK_ALTIVEC) /* Deal with ports that do not have -mstrict-align. */ @@ -60,23 +72,31 @@ /* Mask of all options to set the default isa flags based on -mcpu=. */ #define POWERPC_MASKS (OPTION_MASK_ALTIVEC \ | OPTION_MASK_CMPB \ + | OPTION_MASK_CRYPTO \ | OPTION_MASK_DFP \ + | OPTION_MASK_DIRECT_MOVE \ | OPTION_MASK_DLMZB \ | OPTION_MASK_FPRND \ + | OPTION_MASK_HTM \ | OPTION_MASK_ISEL \ | OPTION_MASK_MFCRF \ | OPTION_MASK_MFPGPR \ | OPTION_MASK_MULHW \ | OPTION_MASK_NO_UPDATE \ + | OPTION_MASK_P8_FUSION \ + | OPTION_MASK_P8_VECTOR \ | OPTION_MASK_POPCNTB \ | OPTION_MASK_POPCNTD \ | OPTION_MASK_POWERPC64 \ | OPTION_MASK_PPC_GFXOPT \ | OPTION_MASK_PPC_GPOPT \ + | OPTION_MASK_QUAD_MEMORY \ + | OPTION_MASK_QUAD_MEMORY_ATOMIC \ | OPTION_MASK_RECIP_PRECISION \ | OPTION_MASK_SOFT_FLOAT \ | OPTION_MASK_STRICT_ALIGN_OPTIONAL \ - | OPTION_MASK_VSX) + | OPTION_MASK_VSX \ + | OPTION_MASK_VSX_TIMODE) #endif @@ -166,10 +186,8 @@ RS6000_CPU ("power7", PROCESSOR_POWER7, /* Don't add MASK_ISEL by default */ POWERPC_7400_MASK | MASK_POWERPC64 | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND | MASK_CMPB | MASK_DFP | MASK_POPCNTD | MASK_VSX | MASK_RECIP_PRECISION) -RS6000_CPU ("power8", PROCESSOR_POWER7, /* Don't add MASK_ISEL by default */ - POWERPC_7400_MASK | MASK_POWERPC64 | MASK_PPC_GPOPT | MASK_MFCRF - | MASK_POPCNTB | MASK_FPRND | MASK_CMPB | MASK_DFP | MASK_POPCNTD - | MASK_VSX | MASK_RECIP_PRECISION) +RS6000_CPU ("power8", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER) RS6000_CPU ("powerpc", PROCESSOR_POWERPC, 0) RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, MASK_PPC_GFXOPT | MASK_POWERPC64) +RS6000_CPU ("powerpc64le", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER) RS6000_CPU ("rs64", PROCESSOR_RS64A, MASK_PPC_GFXOPT | MASK_POWERPC64) diff --git a/gcc/config/rs6000/rs6000-modes.def b/gcc/config/rs6000/rs6000-modes.def index bc18f8a168c24..7062a22f281a2 100644 --- a/gcc/config/rs6000/rs6000-modes.def +++ b/gcc/config/rs6000/rs6000-modes.def @@ -38,6 +38,12 @@ VECTOR_MODES (INT, 8); /* V8QI V4HI V2SI */ VECTOR_MODES (INT, 16); /* V16QI V8HI V4SI V2DI */ VECTOR_MODES (INT, 32); /* V32QI V16HI V8SI V4DI */ VECTOR_MODE (INT, DI, 1); +VECTOR_MODE (INT, TI, 1); VECTOR_MODES (FLOAT, 8); /* V4HF V2SF */ VECTOR_MODES (FLOAT, 16); /* V8HF V4SF V2DF */ VECTOR_MODES (FLOAT, 32); /* V16HF V8SF V4DF */ + +/* Replacement for TImode that only is allowed in GPRs. We also use PTImode + for quad memory atomic operations to force getting an even/odd register + combination. */ +PARTIAL_INT_MODE (TI); diff --git a/gcc/config/rs6000/rs6000-opts.h b/gcc/config/rs6000/rs6000-opts.h index fc843fd19cab3..52fb5896516c1 100644 --- a/gcc/config/rs6000/rs6000-opts.h +++ b/gcc/config/rs6000/rs6000-opts.h @@ -59,7 +59,8 @@ enum processor_type PROCESSOR_POWER7, PROCESSOR_CELL, PROCESSOR_PPCA2, - PROCESSOR_TITAN + PROCESSOR_TITAN, + PROCESSOR_POWER8 }; /* FP processor type. */ @@ -100,7 +101,8 @@ enum group_termination /* Enumeration to give which calling sequence to use. */ enum rs6000_abi { ABI_NONE, - ABI_AIX, /* IBM's AIX */ + ABI_AIX, /* IBM's AIX, or Linux ELFv1 */ + ABI_ELFv2, /* Linux ELFv2 ABI */ ABI_V4, /* System V.4/eabi */ ABI_DARWIN /* Apple's Darwin (OS X kernel) */ }; @@ -131,11 +133,14 @@ enum rs6000_cmodel { CMODEL_LARGE }; -/* Describe which vector unit to use for a given machine mode. */ +/* Describe which vector unit to use for a given machine mode. The + VECTOR_MEM_* and VECTOR_UNIT_* macros assume that Altivec, VSX, and + P8_VECTOR are contiguous. */ enum rs6000_vector { VECTOR_NONE, /* Type is not a vector or not supported */ VECTOR_ALTIVEC, /* Use altivec for vector processing */ VECTOR_VSX, /* Use VSX for vector processing */ + VECTOR_P8_VECTOR, /* Use ISA 2.07 VSX for vector processing */ VECTOR_PAIRED, /* Use paired floating point for vectors */ VECTOR_SPE, /* Use SPE for vector processing */ VECTOR_OTHER /* Some other vector unit */ diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h index d9bcf1a41ede5..d4b93d9970df5 100644 --- a/gcc/config/rs6000/rs6000-protos.h +++ b/gcc/config/rs6000/rs6000-protos.h @@ -50,14 +50,22 @@ extern rtx rs6000_got_register (rtx); extern rtx find_addr_reg (rtx); extern rtx gen_easy_altivec_constant (rtx); extern const char *output_vec_const_move (rtx *); +extern const char *rs6000_output_move_128bit (rtx *); +extern bool rs6000_move_128bit_ok_p (rtx []); +extern bool rs6000_split_128bit_ok_p (rtx []); extern void rs6000_expand_vector_init (rtx, rtx); extern void paired_expand_vector_init (rtx, rtx); extern void rs6000_expand_vector_set (rtx, rtx, int); extern void rs6000_expand_vector_extract (rtx, rtx, int); extern bool altivec_expand_vec_perm_const (rtx op[4]); +extern void altivec_expand_vec_perm_le (rtx op[4]); extern bool rs6000_expand_vec_perm_const (rtx op[4]); +extern void altivec_expand_lvx_be (rtx, rtx, enum machine_mode, unsigned); +extern void altivec_expand_stvx_be (rtx, rtx, enum machine_mode, unsigned); +extern void altivec_expand_stvex_be (rtx, rtx, enum machine_mode, unsigned); extern void rs6000_expand_extract_even (rtx, rtx, rtx); extern void rs6000_expand_interleave (rtx, rtx, rtx, bool); +extern void rs6000_scale_v2df (rtx, rtx, int); extern void build_mask64_2_operands (rtx, rtx *); extern int expand_block_clear (rtx[]); extern int expand_block_move (rtx[]); @@ -70,6 +78,11 @@ extern int insvdi_rshift_rlwimi_p (rtx, rtx, rtx); extern int registers_ok_for_quad_peep (rtx, rtx); extern int mems_ok_for_quad_peep (rtx, rtx); extern bool gpr_or_gpr_p (rtx, rtx); +extern bool direct_move_p (rtx, rtx); +extern bool quad_load_store_p (rtx, rtx); +extern bool fusion_gpr_load_p (rtx, rtx, rtx, rtx); +extern void expand_fusion_gpr_load (rtx *); +extern const char *emit_fusion_gpr_load (rtx, rtx); extern enum reg_class (*rs6000_preferred_reload_class_ptr) (rtx, enum reg_class); extern enum reg_class (*rs6000_secondary_reload_class_ptr) (enum reg_class, @@ -116,6 +129,7 @@ extern rtx rs6000_longcall_ref (rtx); extern void rs6000_fatal_bad_address (rtx); extern rtx create_TOC_reference (rtx, rtx); extern void rs6000_split_multireg_move (rtx, rtx); +extern void rs6000_emit_le_vsx_move (rtx, rtx, enum machine_mode); extern void rs6000_emit_move (rtx, rtx, enum machine_mode); extern rtx rs6000_secondary_memory_needed_rtx (enum machine_mode); extern rtx (*rs6000_legitimize_reload_address_ptr) (rtx, enum machine_mode, @@ -135,9 +149,12 @@ extern rtx rs6000_address_for_fpconvert (rtx); extern rtx rs6000_address_for_altivec (rtx); extern rtx rs6000_allocate_stack_temp (enum machine_mode, bool, bool); extern int rs6000_loop_align (rtx); +extern void rs6000_split_logical (rtx [], enum rtx_code, bool, bool, bool, rtx); #endif /* RTX_CODE */ #ifdef TREE_CODE +extern unsigned int rs6000_data_alignment (tree, unsigned int, enum data_align); +extern bool rs6000_special_adjust_field_align_p (tree, unsigned int); extern unsigned int rs6000_special_round_type_align (tree, unsigned int, unsigned int); extern unsigned int darwin_rs6000_special_round_type_align (tree, unsigned int, @@ -146,6 +163,7 @@ extern tree altivec_resolve_overloaded_builtin (location_t, tree, void *); extern rtx rs6000_libcall_value (enum machine_mode); extern rtx rs6000_va_arg (tree, tree); extern int function_ok_for_sibcall (tree); +extern int rs6000_reg_parm_stack_space (tree, bool); extern void rs6000_elf_declare_function_name (FILE *, const char *, tree); extern bool rs6000_elf_in_small_data_p (const_tree); #ifdef ARGS_SIZE_RTX @@ -170,7 +188,8 @@ extern unsigned int rs6000_dbx_register_number (unsigned int); extern void rs6000_emit_epilogue (int); extern void rs6000_emit_eh_reg_restore (rtx, rtx); extern const char * output_isel (rtx *); -extern void rs6000_call_indirect_aix (rtx, rtx, rtx); +extern void rs6000_call_aix (rtx, rtx, rtx, rtx); +extern void rs6000_sibcall_aix (rtx, rtx, rtx, rtx); extern void rs6000_aix_asm_output_dwarf_table_ref (char *); extern void get_ppc476_thunk_name (char name[32]); extern bool rs6000_overloaded_builtin_p (enum rs6000_builtins); diff --git a/gcc/config/rs6000/rs6000-tables.opt b/gcc/config/rs6000/rs6000-tables.opt index fa87c7fb41945..ab1b20fd94fa6 100644 --- a/gcc/config/rs6000/rs6000-tables.opt +++ b/gcc/config/rs6000/rs6000-tables.opt @@ -186,5 +186,8 @@ EnumValue Enum(rs6000_cpu_opt_value) String(powerpc64) Value(52) EnumValue -Enum(rs6000_cpu_opt_value) String(rs64) Value(53) +Enum(rs6000_cpu_opt_value) String(powerpc64le) Value(53) + +EnumValue +Enum(rs6000_cpu_opt_value) String(rs64) Value(54) diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index fbf57be44a347..d94ccfe8a7e8f 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -1,5 +1,5 @@ /* Subroutines used for code generation on IBM RS/6000. - Copyright (C) 1991-2013 Free Software Foundation, Inc. + Copyright (C) 1991-2015 Free Software Foundation, Inc. Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) This file is part of GCC. @@ -56,9 +56,12 @@ #include "intl.h" #include "params.h" #include "tm-constrs.h" +#include "ira.h" #include "opts.h" #include "tree-vectorizer.h" #include "dumpfile.h" +#include "real.h" +#include "tree-pass.h" #if TARGET_XCOFF #include "xcoffout.h" /* get declarations of xcoff_*_section_name */ #endif @@ -96,6 +99,7 @@ typedef struct rs6000_stack { int spe_gp_save_offset; /* offset to save spe 64-bit gprs */ int varargs_save_offset; /* offset to save the varargs registers */ int ehrd_offset; /* offset to EH return data */ + int ehcr_offset; /* offset to EH CR field data */ int reg_size; /* register size (4 or 8) */ HOST_WIDE_INT vars_size; /* variable save area size */ int parm_size; /* outgoing parameter size */ @@ -139,6 +143,8 @@ typedef struct GTY(()) machine_function 64-bits wide and is allocated early enough so that the offset does not overflow the 16-bit load/store offset field. */ rtx sdmode_stack_slot; + /* Flag if r2 setup is needed with ELFv2 ABI. */ + bool r2_setup_needed; } machine_function; /* Support targetm.vectorize.builtin_mask_for_load. */ @@ -189,9 +195,6 @@ unsigned char rs6000_hard_regno_nregs[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER]; /* Map register number to register class. */ enum reg_class rs6000_regno_regclass[FIRST_PSEUDO_REGISTER]; -/* Reload functions based on the type and the vector unit. */ -static enum insn_code rs6000_vector_reload[NUM_MACHINE_MODES][2]; - static int dbg_cost_ctrl; /* Built in types. */ @@ -284,14 +287,111 @@ static struct { "rsqrtd", (RECIP_DF_RSQRT | RECIP_V2DF_RSQRT) }, }; -/* 2 argument gen function typedef. */ -typedef rtx (*gen_2arg_fn_t) (rtx, rtx, rtx); - /* Pointer to function (in rs6000-c.c) that can define or undefine target macros that have changed. Languages that don't support the preprocessor don't link in rs6000-c.c, so we can't call it directly. */ void (*rs6000_target_modify_macros_ptr) (bool, HOST_WIDE_INT, HOST_WIDE_INT); +/* Simplfy register classes into simpler classifications. We assume + GPR_REG_TYPE - FPR_REG_TYPE are ordered so that we can use a simple range + check for standard register classes (gpr/floating/altivec/vsx) and + floating/vector classes (float/altivec/vsx). */ + +enum rs6000_reg_type { + NO_REG_TYPE, + PSEUDO_REG_TYPE, + GPR_REG_TYPE, + VSX_REG_TYPE, + ALTIVEC_REG_TYPE, + FPR_REG_TYPE, + SPR_REG_TYPE, + CR_REG_TYPE, + SPE_ACC_TYPE, + SPEFSCR_REG_TYPE +}; + +/* Map register class to register type. */ +static enum rs6000_reg_type reg_class_to_reg_type[N_REG_CLASSES]; + +/* First/last register type for the 'normal' register types (i.e. general + purpose, floating point, altivec, and VSX registers). */ +#define IS_STD_REG_TYPE(RTYPE) IN_RANGE(RTYPE, GPR_REG_TYPE, FPR_REG_TYPE) + +#define IS_FP_VECT_REG_TYPE(RTYPE) IN_RANGE(RTYPE, VSX_REG_TYPE, FPR_REG_TYPE) + + +/* Register classes we care about in secondary reload or go if legitimate + address. We only need to worry about GPR, FPR, and Altivec registers here, + along an ANY field that is the OR of the 3 register classes. */ + +enum rs6000_reload_reg_type { + RELOAD_REG_GPR, /* General purpose registers. */ + RELOAD_REG_FPR, /* Traditional floating point regs. */ + RELOAD_REG_VMX, /* Altivec (VMX) registers. */ + RELOAD_REG_ANY, /* OR of GPR, FPR, Altivec masks. */ + N_RELOAD_REG +}; + +/* For setting up register classes, loop through the 3 register classes mapping + into real registers, and skip the ANY class, which is just an OR of the + bits. */ +#define FIRST_RELOAD_REG_CLASS RELOAD_REG_GPR +#define LAST_RELOAD_REG_CLASS RELOAD_REG_VMX + +/* Map reload register type to a register in the register class. */ +struct reload_reg_map_type { + const char *name; /* Register class name. */ + int reg; /* Register in the register class. */ +}; + +static const struct reload_reg_map_type reload_reg_map[N_RELOAD_REG] = { + { "Gpr", FIRST_GPR_REGNO }, /* RELOAD_REG_GPR. */ + { "Fpr", FIRST_FPR_REGNO }, /* RELOAD_REG_FPR. */ + { "VMX", FIRST_ALTIVEC_REGNO }, /* RELOAD_REG_VMX. */ + { "Any", -1 }, /* RELOAD_REG_ANY. */ +}; + +/* Mask bits for each register class, indexed per mode. Historically the + compiler has been more restrictive which types can do PRE_MODIFY instead of + PRE_INC and PRE_DEC, so keep track of sepaate bits for these two. */ +typedef unsigned char addr_mask_type; + +#define RELOAD_REG_VALID 0x01 /* Mode valid in register.. */ +#define RELOAD_REG_MULTIPLE 0x02 /* Mode takes multiple registers. */ +#define RELOAD_REG_INDEXED 0x04 /* Reg+reg addressing. */ +#define RELOAD_REG_OFFSET 0x08 /* Reg+offset addressing. */ +#define RELOAD_REG_PRE_INCDEC 0x10 /* PRE_INC/PRE_DEC valid. */ +#define RELOAD_REG_PRE_MODIFY 0x20 /* PRE_MODIFY valid. */ + +/* Register type masks based on the type, of valid addressing modes. */ +struct rs6000_reg_addr { + enum insn_code reload_load; /* INSN to reload for loading. */ + enum insn_code reload_store; /* INSN to reload for storing. */ + enum insn_code reload_fpr_gpr; /* INSN to move from FPR to GPR. */ + enum insn_code reload_gpr_vsx; /* INSN to move from GPR to VSX. */ + enum insn_code reload_vsx_gpr; /* INSN to move from VSX to GPR. */ + addr_mask_type addr_mask[(int)N_RELOAD_REG]; /* Valid address masks. */ + bool scalar_in_vmx_p; /* Scalar value can go in VMX. */ +}; + +static struct rs6000_reg_addr reg_addr[NUM_MACHINE_MODES]; + +/* Helper function to say whether a mode supports PRE_INC or PRE_DEC. */ +static inline bool +mode_supports_pre_incdec_p (enum machine_mode mode) +{ + return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_INCDEC) + != 0); +} + +/* Helper function to say whether a mode supports PRE_MODIFY. */ +static inline bool +mode_supports_pre_modify_p (enum machine_mode mode) +{ + return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_MODIFY) + != 0); +} + /* Target cpu costs. */ @@ -831,6 +931,25 @@ struct processor_costs power7_cost = { 12, /* prefetch streams */ }; +/* Instruction costs on POWER8 processors. */ +static const +struct processor_costs power8_cost = { + COSTS_N_INSNS (3), /* mulsi */ + COSTS_N_INSNS (3), /* mulsi_const */ + COSTS_N_INSNS (3), /* mulsi_const9 */ + COSTS_N_INSNS (3), /* muldi */ + COSTS_N_INSNS (19), /* divsi */ + COSTS_N_INSNS (35), /* divdi */ + COSTS_N_INSNS (3), /* fp */ + COSTS_N_INSNS (3), /* dmul */ + COSTS_N_INSNS (14), /* sdiv */ + COSTS_N_INSNS (17), /* ddiv */ + 128, /* cache line size */ + 32, /* l1 cache */ + 256, /* l2 cache */ + 12, /* prefetch streams */ +}; + /* Instruction costs on POWER A2 processors. */ static const struct processor_costs ppca2_cost = { @@ -858,6 +977,7 @@ struct processor_costs ppca2_cost = { #undef RS6000_BUILTIN_A #undef RS6000_BUILTIN_D #undef RS6000_BUILTIN_E +#undef RS6000_BUILTIN_H #undef RS6000_BUILTIN_P #undef RS6000_BUILTIN_Q #undef RS6000_BUILTIN_S @@ -881,6 +1001,9 @@ struct processor_costs ppca2_cost = { #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) \ { NAME, ICODE, MASK, ATTR }, +#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \ + { NAME, ICODE, MASK, ATTR }, + #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \ { NAME, ICODE, MASK, ATTR }, @@ -911,6 +1034,7 @@ static const struct rs6000_builtin_info_type rs6000_builtin_info[] = #undef RS6000_BUILTIN_A #undef RS6000_BUILTIN_D #undef RS6000_BUILTIN_E +#undef RS6000_BUILTIN_H #undef RS6000_BUILTIN_P #undef RS6000_BUILTIN_Q #undef RS6000_BUILTIN_S @@ -951,6 +1075,7 @@ static void rs6000_common_init_builtins (void); static void paired_init_builtins (void); static rtx paired_expand_predicate_builtin (enum insn_code, tree, rtx); static void spe_init_builtins (void); +static void htm_init_builtins (void); static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx); static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx); static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx); @@ -1023,6 +1148,14 @@ static void rs6000_print_isa_options (FILE *, int, const char *, static void rs6000_print_builtin_options (FILE *, int, const char *, HOST_WIDE_INT); +static enum rs6000_reg_type register_to_reg_type (rtx, bool *); +static bool rs6000_secondary_reload_move (enum rs6000_reg_type, + enum rs6000_reg_type, + enum machine_mode, + secondary_reload_info *, + bool); +static unsigned int rs6000_analyze_swaps (function *); + /* Hash table stuff for keeping track of TOC entries. */ struct GTY(()) toc_hash_struct @@ -1071,7 +1204,9 @@ char rs6000_reg_names[][8] = /* SPE registers. */ "spe_acc", "spefscr", /* Soft frame pointer. */ - "sfp" + "sfp", + /* HTM SPR registers. */ + "tfhar", "tfiar", "texasr" }; #ifdef TARGET_REGNAMES @@ -1097,7 +1232,9 @@ static const char alt_reg_names[][8] = /* SPE registers. */ "spe_acc", "spefscr", /* Soft frame pointer. */ - "sfp" + "sfp", + /* HTM SPR registers. */ + "tfhar", "tfiar", "texasr" }; #endif @@ -1319,6 +1456,9 @@ static const struct attribute_spec rs6000_attribute_table[] = #undef TARGET_RETURN_IN_MEMORY #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory +#undef TARGET_RETURN_IN_MSB +#define TARGET_RETURN_IN_MSB rs6000_return_in_msb + #undef TARGET_SETUP_INCOMING_VARARGS #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs @@ -1428,6 +1568,9 @@ static const struct attribute_spec rs6000_attribute_table[] = #undef TARGET_MODE_DEPENDENT_ADDRESS_P #define TARGET_MODE_DEPENDENT_ADDRESS_P rs6000_mode_dependent_address_p +#undef TARGET_LRA_P +#define TARGET_LRA_P rs6000_lra_p + #undef TARGET_CAN_ELIMINATE #define TARGET_CAN_ELIMINATE rs6000_can_eliminate @@ -1516,8 +1659,9 @@ rs6000_hard_regno_nregs_internal (int regno, enum machine_mode mode) { unsigned HOST_WIDE_INT reg_size; + /* TF/TD modes are special in that they always take 2 registers. */ if (FP_REGNO_P (regno)) - reg_size = (VECTOR_MEM_VSX_P (mode) + reg_size = ((VECTOR_MEM_VSX_P (mode) && mode != TDmode && mode != TFmode) ? UNITS_PER_VSX_WORD : UNITS_PER_FP_WORD); @@ -1549,16 +1693,35 @@ rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode) { int last_regno = regno + rs6000_hard_regno_nregs[mode][regno] - 1; + /* PTImode can only go in GPRs. Quad word memory operations require even/odd + register combinations, and use PTImode where we need to deal with quad + word memory operations. Don't allow quad words in the argument or frame + pointer registers, just registers 0..31. */ + if (mode == PTImode) + return (IN_RANGE (regno, FIRST_GPR_REGNO, LAST_GPR_REGNO) + && IN_RANGE (last_regno, FIRST_GPR_REGNO, LAST_GPR_REGNO) + && ((regno & 1) == 0)); + /* VSX registers that overlap the FPR registers are larger than for non-VSX implementations. Don't allow an item to be split between a FP register - and an Altivec register. */ - if (VECTOR_MEM_VSX_P (mode)) + and an Altivec register. Allow TImode in all VSX registers if the user + asked for it. */ + if (TARGET_VSX && VSX_REGNO_P (regno) + && (VECTOR_MEM_VSX_P (mode) + || reg_addr[mode].scalar_in_vmx_p + || (TARGET_VSX_TIMODE && mode == TImode) + || (TARGET_VADDUQM && mode == V1TImode))) { if (FP_REGNO_P (regno)) return FP_REGNO_P (last_regno); if (ALTIVEC_REGNO_P (regno)) - return ALTIVEC_REGNO_P (last_regno); + { + if (GET_MODE_SIZE (mode) != 16 && !reg_addr[mode].scalar_in_vmx_p) + return 0; + + return ALTIVEC_REGNO_P (last_regno); + } } /* The GPRs can hold any mode, but values bigger than one register @@ -1567,8 +1730,7 @@ rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode) return INT_REGNO_P (last_regno); /* The float registers (except for VSX vector modes) can only hold floating - modes and DImode. This excludes the 32-bit decimal float mode for - now. */ + modes and DImode. */ if (FP_REGNO_P (regno)) { if (SCALAR_FLOAT_MODE_P (mode) @@ -1596,15 +1758,15 @@ rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode) /* AltiVec only in AldyVec registers. */ if (ALTIVEC_REGNO_P (regno)) - return VECTOR_MEM_ALTIVEC_OR_VSX_P (mode); + return (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode) + || mode == V1TImode); /* ...but GPRs can hold SIMD data on the SPE in one register. */ if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode)) return 1; - /* We cannot put TImode anywhere except general register and it must be able - to fit within the register set. In the future, allow TImode in the - Altivec or VSX registers. */ + /* We cannot put non-VSX TImode or PTImode anywhere except general register + and it must be able to fit within the register set. */ return GET_MODE_SIZE (mode) <= UNITS_PER_WORD; } @@ -1671,6 +1833,16 @@ rs6000_debug_reg_print (int first_regno, int last_regno, const char *reg_name) comma = ", "; } + if (len > 70) + { + fprintf (stderr, ",\n\t"); + comma = ""; + } + + len += fprintf (stderr, "%sreg-class = %s", comma, + reg_class_names[(int)rs6000_regno_regclass[r]]); + comma = ", "; + if (len > 70) { fprintf (stderr, ",\n\t"); @@ -1681,6 +1853,65 @@ rs6000_debug_reg_print (int first_regno, int last_regno, const char *reg_name) } } +static const char * +rs6000_debug_vector_unit (enum rs6000_vector v) +{ + const char *ret; + + switch (v) + { + case VECTOR_NONE: ret = "none"; break; + case VECTOR_ALTIVEC: ret = "altivec"; break; + case VECTOR_VSX: ret = "vsx"; break; + case VECTOR_P8_VECTOR: ret = "p8_vector"; break; + case VECTOR_PAIRED: ret = "paired"; break; + case VECTOR_SPE: ret = "spe"; break; + case VECTOR_OTHER: ret = "other"; break; + default: ret = "unknown"; break; + } + + return ret; +} + +/* Print the address masks in a human readble fashion. */ +DEBUG_FUNCTION void +rs6000_debug_print_mode (ssize_t m) +{ + ssize_t rc; + + fprintf (stderr, "Mode: %-5s", GET_MODE_NAME (m)); + for (rc = 0; rc < N_RELOAD_REG; rc++) + { + addr_mask_type mask = reg_addr[m].addr_mask[rc]; + fprintf (stderr, + " %s: %c%c%c%c%c%c", + reload_reg_map[rc].name, + (mask & RELOAD_REG_VALID) != 0 ? 'v' : ' ', + (mask & RELOAD_REG_MULTIPLE) != 0 ? 'm' : ' ', + (mask & RELOAD_REG_INDEXED) != 0 ? 'i' : ' ', + (mask & RELOAD_REG_OFFSET) != 0 ? 'o' : ' ', + (mask & RELOAD_REG_PRE_INCDEC) != 0 ? '+' : ' ', + (mask & RELOAD_REG_PRE_MODIFY) != 0 ? '+' : ' '); + } + + if (rs6000_vector_unit[m] != VECTOR_NONE + || rs6000_vector_mem[m] != VECTOR_NONE + || (reg_addr[m].reload_store != CODE_FOR_nothing) + || (reg_addr[m].reload_load != CODE_FOR_nothing) + || reg_addr[m].scalar_in_vmx_p) + { + fprintf (stderr, + " Vector-arith=%-10s Vector-mem=%-10s Reload=%c%c Upper=%c", + rs6000_debug_vector_unit (rs6000_vector_unit[m]), + rs6000_debug_vector_unit (rs6000_vector_mem[m]), + (reg_addr[m].reload_store != CODE_FOR_nothing) ? 's' : '*', + (reg_addr[m].reload_load != CODE_FOR_nothing) ? 'l' : '*', + (reg_addr[m].scalar_in_vmx_p) ? 'y' : 'n'); + } + + fputs ("\n", stderr); +} + #define DEBUG_FMT_ID "%-32s= " #define DEBUG_FMT_D DEBUG_FMT_ID "%d\n" #define DEBUG_FMT_WX DEBUG_FMT_ID "%#.12" HOST_WIDE_INT_PRINT "x: " @@ -1693,6 +1924,7 @@ rs6000_debug_reg_global (void) static const char *const tf[2] = { "false", "true" }; const char *nl = (const char *)0; int m; + size_t m1, m2, v; char costly_num[20]; char nop_num[20]; char flags_buffer[40]; @@ -1703,20 +1935,69 @@ rs6000_debug_reg_global (void) const char *cmodel_str; struct cl_target_option cl_opts; - /* Map enum rs6000_vector to string. */ - static const char *rs6000_debug_vector_unit[] = { - "none", - "altivec", - "vsx", - "paired", - "spe", - "other" + /* Modes we want tieable information on. */ + static const enum machine_mode print_tieable_modes[] = { + QImode, + HImode, + SImode, + DImode, + TImode, + PTImode, + SFmode, + DFmode, + TFmode, + SDmode, + DDmode, + TDmode, + V8QImode, + V4HImode, + V2SImode, + V16QImode, + V8HImode, + V4SImode, + V2DImode, + V1TImode, + V32QImode, + V16HImode, + V8SImode, + V4DImode, + V2TImode, + V2SFmode, + V4SFmode, + V2DFmode, + V8SFmode, + V4DFmode, + CCmode, + CCUNSmode, + CCEQmode, + }; + + /* Virtual regs we are interested in. */ + const static struct { + int regno; /* register number. */ + const char *name; /* register name. */ + } virtual_regs[] = { + { STACK_POINTER_REGNUM, "stack pointer:" }, + { TOC_REGNUM, "toc: " }, + { STATIC_CHAIN_REGNUM, "static chain: " }, + { RS6000_PIC_OFFSET_TABLE_REGNUM, "pic offset: " }, + { HARD_FRAME_POINTER_REGNUM, "hard frame: " }, + { ARG_POINTER_REGNUM, "arg pointer: " }, + { FRAME_POINTER_REGNUM, "frame pointer:" }, + { FIRST_PSEUDO_REGISTER, "first pseudo: " }, + { FIRST_VIRTUAL_REGISTER, "first virtual:" }, + { VIRTUAL_INCOMING_ARGS_REGNUM, "incoming_args:" }, + { VIRTUAL_STACK_VARS_REGNUM, "stack_vars: " }, + { VIRTUAL_STACK_DYNAMIC_REGNUM, "stack_dynamic:" }, + { VIRTUAL_OUTGOING_ARGS_REGNUM, "outgoing_args:" }, + { VIRTUAL_CFA_REGNUM, "cfa (frame): " }, + { VIRTUAL_PREFERRED_STACK_BOUNDARY_REGNUM, "stack boundry:" }, + { LAST_VIRTUAL_REGISTER, "last virtual: " }, }; - fprintf (stderr, "Register information: (last virtual reg = %d)\n", - LAST_VIRTUAL_REGISTER); - rs6000_debug_reg_print (0, 31, "gr"); - rs6000_debug_reg_print (32, 63, "fp"); + fputs ("\nHard register information:\n", stderr); + rs6000_debug_reg_print (FIRST_GPR_REGNO, LAST_GPR_REGNO, "gr"); + rs6000_debug_reg_print (FIRST_FPR_REGNO, LAST_FPR_REGNO, "fp"); rs6000_debug_reg_print (FIRST_ALTIVEC_REGNO, LAST_ALTIVEC_REGNO, "vs"); @@ -1729,6 +2010,10 @@ rs6000_debug_reg_global (void) rs6000_debug_reg_print (SPE_ACC_REGNO, SPE_ACC_REGNO, "spe_a"); rs6000_debug_reg_print (SPEFSCR_REGNO, SPEFSCR_REGNO, "spe_f"); + fputs ("\nVirtual/stack/frame registers:\n", stderr); + for (v = 0; v < ARRAY_SIZE (virtual_regs); v++) + fprintf (stderr, "%s regno = %3d\n", virtual_regs[v].name, virtual_regs[v].regno); + fprintf (stderr, "\n" "d reg_class = %s\n" @@ -1737,24 +2022,77 @@ rs6000_debug_reg_global (void) "wa reg_class = %s\n" "wd reg_class = %s\n" "wf reg_class = %s\n" - "ws reg_class = %s\n\n", + "wg reg_class = %s\n" + "wh reg_class = %s\n" + "wi reg_class = %s\n" + "wj reg_class = %s\n" + "wk reg_class = %s\n" + "wl reg_class = %s\n" + "wm reg_class = %s\n" + "wr reg_class = %s\n" + "ws reg_class = %s\n" + "wt reg_class = %s\n" + "wu reg_class = %s\n" + "wv reg_class = %s\n" + "ww reg_class = %s\n" + "wx reg_class = %s\n" + "wy reg_class = %s\n" + "wz reg_class = %s\n" + "\n", reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_d]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_f]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_v]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wa]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wd]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wf]], - reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_ws]]); - + reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wg]], + reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wh]], + reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wi]], + reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wj]], + reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wk]], + reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wl]], + reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wm]], + reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wr]], + reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_ws]], + reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wt]], + reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wu]], + reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wv]], + reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_ww]], + reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wx]], + reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wy]], + reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wz]]); + + nl = "\n"; for (m = 0; m < NUM_MACHINE_MODES; ++m) - if (rs6000_vector_unit[m] || rs6000_vector_mem[m]) - { - nl = "\n"; - fprintf (stderr, "Vector mode: %-5s arithmetic: %-8s move: %-8s\n", - GET_MODE_NAME (m), - rs6000_debug_vector_unit[ rs6000_vector_unit[m] ], - rs6000_debug_vector_unit[ rs6000_vector_mem[m] ]); - } + rs6000_debug_print_mode (m); + + fputs ("\n", stderr); + + for (m1 = 0; m1 < ARRAY_SIZE (print_tieable_modes); m1++) + { + enum machine_mode mode1 = print_tieable_modes[m1]; + bool first_time = true; + + nl = (const char *)0; + for (m2 = 0; m2 < ARRAY_SIZE (print_tieable_modes); m2++) + { + enum machine_mode mode2 = print_tieable_modes[m2]; + if (mode1 != mode2 && MODES_TIEABLE_P (mode1, mode2)) + { + if (first_time) + { + fprintf (stderr, "Tieable modes %s:", GET_MODE_NAME (mode1)); + nl = "\n"; + first_time = false; + } + + fprintf (stderr, " %s", GET_MODE_NAME (mode2)); + } + } + + if (!first_time) + fputs ("\n", stderr); + } if (nl) fputs (nl, stderr); @@ -1916,6 +2254,7 @@ rs6000_debug_reg_global (void) { case ABI_NONE: abi_str = "none"; break; case ABI_AIX: abi_str = "aix"; break; + case ABI_ELFv2: abi_str = "ELFv2"; break; case ABI_V4: abi_str = "V4"; break; case ABI_DARWIN: abi_str = "darwin"; break; default: abi_str = "unknown"; break; @@ -1935,9 +2274,34 @@ rs6000_debug_reg_global (void) if (rs6000_float_gprs) fprintf (stderr, DEBUG_FMT_S, "float_gprs", "true"); + fprintf (stderr, DEBUG_FMT_S, "fprs", + (TARGET_FPRS ? "true" : "false")); + + fprintf (stderr, DEBUG_FMT_S, "single_float", + (TARGET_SINGLE_FLOAT ? "true" : "false")); + + fprintf (stderr, DEBUG_FMT_S, "double_float", + (TARGET_DOUBLE_FLOAT ? "true" : "false")); + + fprintf (stderr, DEBUG_FMT_S, "soft_float", + (TARGET_SOFT_FLOAT ? "true" : "false")); + + fprintf (stderr, DEBUG_FMT_S, "e500_single", + (TARGET_E500_SINGLE ? "true" : "false")); + + fprintf (stderr, DEBUG_FMT_S, "e500_double", + (TARGET_E500_DOUBLE ? "true" : "false")); + if (TARGET_LINK_STACK) fprintf (stderr, DEBUG_FMT_S, "link_stack", "true"); + if (targetm.lra_p ()) + fprintf (stderr, DEBUG_FMT_S, "lra", "true"); + + if (TARGET_P8_FUSION) + fprintf (stderr, DEBUG_FMT_S, "p8 fusion", + (TARGET_P8_FUSION_SIGN) ? "zero+sign" : "zero"); + fprintf (stderr, DEBUG_FMT_S, "plt-format", TARGET_SECURE_PLT ? "secure" : "bss"); fprintf (stderr, DEBUG_FMT_S, "struct-return", @@ -1957,11 +2321,107 @@ rs6000_debug_reg_global (void) (int)RS6000_BUILTIN_COUNT); } + +/* Update the addr mask bits in reg_addr to help secondary reload and go if + legitimate address support to figure out the appropriate addressing to + use. */ + +static void +rs6000_setup_reg_addr_masks (void) +{ + ssize_t rc, reg, m, nregs; + addr_mask_type any_addr_mask, addr_mask; + + for (m = 0; m < NUM_MACHINE_MODES; ++m) + { + enum machine_mode m2 = (enum machine_mode)m; + + /* SDmode is special in that we want to access it only via REG+REG + addressing on power7 and above, since we want to use the LFIWZX and + STFIWZX instructions to load it. */ + bool indexed_only_p = (m == SDmode && TARGET_NO_SDMODE_STACK); + + any_addr_mask = 0; + for (rc = FIRST_RELOAD_REG_CLASS; rc <= LAST_RELOAD_REG_CLASS; rc++) + { + addr_mask = 0; + reg = reload_reg_map[rc].reg; + + /* Can mode values go in the GPR/FPR/Altivec registers? */ + if (reg >= 0 && rs6000_hard_regno_mode_ok_p[m][reg]) + { + nregs = rs6000_hard_regno_nregs[m][reg]; + addr_mask |= RELOAD_REG_VALID; + + /* Indicate if the mode takes more than 1 physical register. If + it takes a single register, indicate it can do REG+REG + addressing. */ + if (nregs > 1 || m == BLKmode) + addr_mask |= RELOAD_REG_MULTIPLE; + else + addr_mask |= RELOAD_REG_INDEXED; + + /* Figure out if we can do PRE_INC, PRE_DEC, or PRE_MODIFY + addressing. Restrict addressing on SPE for 64-bit types + because of the SUBREG hackery used to address 64-bit floats in + '32-bit' GPRs. To simplify secondary reload, don't allow + update forms on scalar floating point types that can go in the + upper registers. */ + + if (TARGET_UPDATE + && (rc == RELOAD_REG_GPR || rc == RELOAD_REG_FPR) + && GET_MODE_SIZE (m2) <= 8 + && !VECTOR_MODE_P (m2) + && !COMPLEX_MODE_P (m2) + && !indexed_only_p + && !(TARGET_E500_DOUBLE && GET_MODE_SIZE (m2) == 8) + && !reg_addr[m2].scalar_in_vmx_p) + { + addr_mask |= RELOAD_REG_PRE_INCDEC; + + /* PRE_MODIFY is more restricted than PRE_INC/PRE_DEC in that + we don't allow PRE_MODIFY for some multi-register + operations. */ + switch (m) + { + default: + addr_mask |= RELOAD_REG_PRE_MODIFY; + break; + + case DImode: + if (TARGET_POWERPC64) + addr_mask |= RELOAD_REG_PRE_MODIFY; + break; + + case DFmode: + case DDmode: + if (TARGET_DF_INSN) + addr_mask |= RELOAD_REG_PRE_MODIFY; + break; + } + } + } + + /* GPR and FPR registers can do REG+OFFSET addressing, except + possibly for SDmode. */ + if ((addr_mask != 0) && !indexed_only_p + && (rc == RELOAD_REG_GPR || rc == RELOAD_REG_FPR)) + addr_mask |= RELOAD_REG_OFFSET; + + reg_addr[m].addr_mask[rc] = addr_mask; + any_addr_mask |= addr_mask; + } + + reg_addr[m].addr_mask[RELOAD_REG_ANY] = any_addr_mask; + } +} + + /* Initialize the various global tables that are based on register size. */ static void rs6000_init_hard_regno_mode_ok (bool global_init_p) { - int r, m, c; + ssize_t r, m, c; int align64; int align32; @@ -1990,20 +2450,54 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) rs6000_regno_regclass[VSCR_REGNO] = VRSAVE_REGS; rs6000_regno_regclass[SPE_ACC_REGNO] = SPE_ACC_REGS; rs6000_regno_regclass[SPEFSCR_REGNO] = SPEFSCR_REGS; + rs6000_regno_regclass[TFHAR_REGNO] = SPR_REGS; + rs6000_regno_regclass[TFIAR_REGNO] = SPR_REGS; + rs6000_regno_regclass[TEXASR_REGNO] = SPR_REGS; rs6000_regno_regclass[ARG_POINTER_REGNUM] = BASE_REGS; rs6000_regno_regclass[FRAME_POINTER_REGNUM] = BASE_REGS; - /* Precalculate vector information, this must be set up before the - rs6000_hard_regno_nregs_internal below. */ - for (m = 0; m < NUM_MACHINE_MODES; ++m) + /* Precalculate register class to simpler reload register class. We don't + need all of the register classes that are combinations of different + classes, just the simple ones that have constraint letters. */ + for (c = 0; c < N_REG_CLASSES; c++) + reg_class_to_reg_type[c] = NO_REG_TYPE; + + reg_class_to_reg_type[(int)GENERAL_REGS] = GPR_REG_TYPE; + reg_class_to_reg_type[(int)BASE_REGS] = GPR_REG_TYPE; + reg_class_to_reg_type[(int)VSX_REGS] = VSX_REG_TYPE; + reg_class_to_reg_type[(int)VRSAVE_REGS] = SPR_REG_TYPE; + reg_class_to_reg_type[(int)VSCR_REGS] = SPR_REG_TYPE; + reg_class_to_reg_type[(int)LINK_REGS] = SPR_REG_TYPE; + reg_class_to_reg_type[(int)CTR_REGS] = SPR_REG_TYPE; + reg_class_to_reg_type[(int)LINK_OR_CTR_REGS] = SPR_REG_TYPE; + reg_class_to_reg_type[(int)CR_REGS] = CR_REG_TYPE; + reg_class_to_reg_type[(int)CR0_REGS] = CR_REG_TYPE; + reg_class_to_reg_type[(int)SPE_ACC_REGS] = SPE_ACC_TYPE; + reg_class_to_reg_type[(int)SPEFSCR_REGS] = SPEFSCR_REG_TYPE; + + if (TARGET_VSX) + { + reg_class_to_reg_type[(int)FLOAT_REGS] = VSX_REG_TYPE; + reg_class_to_reg_type[(int)ALTIVEC_REGS] = VSX_REG_TYPE; + } + else { - rs6000_vector_unit[m] = rs6000_vector_mem[m] = VECTOR_NONE; - rs6000_vector_reload[m][0] = CODE_FOR_nothing; - rs6000_vector_reload[m][1] = CODE_FOR_nothing; + reg_class_to_reg_type[(int)FLOAT_REGS] = FPR_REG_TYPE; + reg_class_to_reg_type[(int)ALTIVEC_REGS] = ALTIVEC_REG_TYPE; } - for (c = 0; c < (int)(int)RS6000_CONSTRAINT_MAX; c++) - rs6000_constraints[c] = NO_REGS; + /* Precalculate the valid memory formats as well as the vector information, + this must be set up before the rs6000_hard_regno_nregs_internal calls + below. */ + gcc_assert ((int)VECTOR_NONE == 0); + memset ((void *) &rs6000_vector_unit[0], '\0', sizeof (rs6000_vector_unit)); + memset ((void *) &rs6000_vector_mem[0], '\0', sizeof (rs6000_vector_unit)); + + gcc_assert ((int)CODE_FOR_nothing == 0); + memset ((void *) ®_addr[0], '\0', sizeof (reg_addr)); + + gcc_assert ((int)NO_REGS == 0); + memset ((void *) &rs6000_constraints[0], '\0', sizeof (rs6000_constraints)); /* The VSX hardware allows native alignment for vectors, but control whether the compiler believes it can use native alignment or still uses 128-bit alignment. */ @@ -2065,13 +2559,19 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) } } - /* V2DImode, only allow under VSX, which can do V2DI insert/splat/extract. - Altivec doesn't have 64-bit support. */ + /* V2DImode, full mode depends on ISA 2.07 vector mode. Allow under VSX to + do insert/splat/extract. Altivec doesn't have 64-bit integer support. */ if (TARGET_VSX) { rs6000_vector_mem[V2DImode] = VECTOR_VSX; - rs6000_vector_unit[V2DImode] = VECTOR_NONE; + rs6000_vector_unit[V2DImode] + = (TARGET_P8_VECTOR) ? VECTOR_P8_VECTOR : VECTOR_NONE; rs6000_vector_align[V2DImode] = align64; + + rs6000_vector_mem[V1TImode] = VECTOR_VSX; + rs6000_vector_unit[V1TImode] + = (TARGET_P8_VECTOR) ? VECTOR_P8_VECTOR : VECTOR_NONE; + rs6000_vector_align[V1TImode] = 128; } /* DFmode, see if we want to use the VSX unit. */ @@ -2079,79 +2579,233 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) { rs6000_vector_unit[DFmode] = VECTOR_VSX; rs6000_vector_mem[DFmode] - = (TARGET_VSX_SCALAR_MEMORY ? VECTOR_VSX : VECTOR_NONE); + = (TARGET_UPPER_REGS_DF ? VECTOR_VSX : VECTOR_NONE); rs6000_vector_align[DFmode] = align64; } + /* Allow TImode in VSX register and set the VSX memory macros. */ + if (TARGET_VSX && TARGET_VSX_TIMODE) + { + rs6000_vector_mem[TImode] = VECTOR_VSX; + rs6000_vector_align[TImode] = align64; + } + /* TODO add SPE and paired floating point vector support. */ /* Register class constraints for the constraints that depend on compile - switches. */ + switches. When the VSX code was added, different constraints were added + based on the type (DFmode, V2DFmode, V4SFmode). For the vector types, all + of the VSX registers are used. The register classes for scalar floating + point types is set, based on whether we allow that type into the upper + (Altivec) registers. GCC has register classes to target the Altivec + registers for load/store operations, to select using a VSX memory + operation instead of the traditional floating point operation. The + constraints are: + + d - Register class to use with traditional DFmode instructions. + f - Register class to use with traditional SFmode instructions. + v - Altivec register. + wa - Any VSX register. + wc - Reserved to represent individual CR bits (used in LLVM). + wd - Preferred register class for V2DFmode. + wf - Preferred register class for V4SFmode. + wg - Float register for power6x move insns. + wh - FP register for direct move instructions. + wi - FP or VSX register to hold 64-bit integers for VSX insns. + wj - FP or VSX register to hold 64-bit integers for direct moves. + wk - FP or VSX register to hold 64-bit doubles for direct moves. + wl - Float register if we can do 32-bit signed int loads. + wm - VSX register for ISA 2.07 direct move operations. + wn - always NO_REGS. + wr - GPR if 64-bit mode is permitted. + ws - Register class to do ISA 2.06 DF operations. + wt - VSX register for TImode in VSX registers. + wu - Altivec register for ISA 2.07 VSX SF/SI load/stores. + wv - Altivec register for ISA 2.06 VSX DF/DI load/stores. + ww - Register class to do SF conversions in with VSX operations. + wx - Float register if we can do 32-bit int stores. + wy - Register class to do ISA 2.07 SF operations. + wz - Float register if we can do 32-bit unsigned int loads. */ + if (TARGET_HARD_FLOAT && TARGET_FPRS) - rs6000_constraints[RS6000_CONSTRAINT_f] = FLOAT_REGS; + rs6000_constraints[RS6000_CONSTRAINT_f] = FLOAT_REGS; /* SFmode */ if (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT) - rs6000_constraints[RS6000_CONSTRAINT_d] = FLOAT_REGS; + rs6000_constraints[RS6000_CONSTRAINT_d] = FLOAT_REGS; /* DFmode */ if (TARGET_VSX) { - /* At present, we just use VSX_REGS, but we have different constraints - based on the use, in case we want to fine tune the default register - class used. wa = any VSX register, wf = register class to use for - V4SF, wd = register class to use for V2DF, and ws = register classs to - use for DF scalars. */ rs6000_constraints[RS6000_CONSTRAINT_wa] = VSX_REGS; - rs6000_constraints[RS6000_CONSTRAINT_wf] = VSX_REGS; - rs6000_constraints[RS6000_CONSTRAINT_wd] = VSX_REGS; - rs6000_constraints[RS6000_CONSTRAINT_ws] = (TARGET_VSX_SCALAR_MEMORY - ? VSX_REGS - : FLOAT_REGS); + rs6000_constraints[RS6000_CONSTRAINT_wd] = VSX_REGS; /* V2DFmode */ + rs6000_constraints[RS6000_CONSTRAINT_wf] = VSX_REGS; /* V4SFmode */ + rs6000_constraints[RS6000_CONSTRAINT_wi] = FLOAT_REGS; /* DImode */ + + if (TARGET_VSX_TIMODE) + rs6000_constraints[RS6000_CONSTRAINT_wt] = VSX_REGS; /* TImode */ + + if (TARGET_UPPER_REGS_DF) /* DFmode */ + { + rs6000_constraints[RS6000_CONSTRAINT_ws] = VSX_REGS; + rs6000_constraints[RS6000_CONSTRAINT_wv] = ALTIVEC_REGS; + } + else + rs6000_constraints[RS6000_CONSTRAINT_ws] = FLOAT_REGS; } + /* Add conditional constraints based on various options, to allow us to + collapse multiple insn patterns. */ if (TARGET_ALTIVEC) rs6000_constraints[RS6000_CONSTRAINT_v] = ALTIVEC_REGS; - /* Set up the reload helper functions. */ + if (TARGET_MFPGPR) /* DFmode */ + rs6000_constraints[RS6000_CONSTRAINT_wg] = FLOAT_REGS; + + if (TARGET_LFIWAX) + rs6000_constraints[RS6000_CONSTRAINT_wl] = FLOAT_REGS; /* DImode */ + + if (TARGET_DIRECT_MOVE) + { + rs6000_constraints[RS6000_CONSTRAINT_wh] = FLOAT_REGS; + rs6000_constraints[RS6000_CONSTRAINT_wj] /* DImode */ + = rs6000_constraints[RS6000_CONSTRAINT_wi]; + rs6000_constraints[RS6000_CONSTRAINT_wk] /* DFmode */ + = rs6000_constraints[RS6000_CONSTRAINT_ws]; + rs6000_constraints[RS6000_CONSTRAINT_wm] = VSX_REGS; + } + + if (TARGET_POWERPC64) + rs6000_constraints[RS6000_CONSTRAINT_wr] = GENERAL_REGS; + + if (TARGET_P8_VECTOR && TARGET_UPPER_REGS_SF) /* SFmode */ + { + rs6000_constraints[RS6000_CONSTRAINT_wu] = ALTIVEC_REGS; + rs6000_constraints[RS6000_CONSTRAINT_wy] = VSX_REGS; + rs6000_constraints[RS6000_CONSTRAINT_ww] = VSX_REGS; + } + else if (TARGET_P8_VECTOR) + { + rs6000_constraints[RS6000_CONSTRAINT_wy] = FLOAT_REGS; + rs6000_constraints[RS6000_CONSTRAINT_ww] = FLOAT_REGS; + } + else if (TARGET_VSX) + rs6000_constraints[RS6000_CONSTRAINT_ww] = FLOAT_REGS; + + if (TARGET_STFIWX) + rs6000_constraints[RS6000_CONSTRAINT_wx] = FLOAT_REGS; /* DImode */ + + if (TARGET_LFIWZX) + rs6000_constraints[RS6000_CONSTRAINT_wz] = FLOAT_REGS; /* DImode */ + + /* Set up the reload helper and direct move functions. */ if (TARGET_VSX || TARGET_ALTIVEC) { if (TARGET_64BIT) { - rs6000_vector_reload[V16QImode][0] = CODE_FOR_reload_v16qi_di_store; - rs6000_vector_reload[V16QImode][1] = CODE_FOR_reload_v16qi_di_load; - rs6000_vector_reload[V8HImode][0] = CODE_FOR_reload_v8hi_di_store; - rs6000_vector_reload[V8HImode][1] = CODE_FOR_reload_v8hi_di_load; - rs6000_vector_reload[V4SImode][0] = CODE_FOR_reload_v4si_di_store; - rs6000_vector_reload[V4SImode][1] = CODE_FOR_reload_v4si_di_load; - rs6000_vector_reload[V2DImode][0] = CODE_FOR_reload_v2di_di_store; - rs6000_vector_reload[V2DImode][1] = CODE_FOR_reload_v2di_di_load; - rs6000_vector_reload[V4SFmode][0] = CODE_FOR_reload_v4sf_di_store; - rs6000_vector_reload[V4SFmode][1] = CODE_FOR_reload_v4sf_di_load; - rs6000_vector_reload[V2DFmode][0] = CODE_FOR_reload_v2df_di_store; - rs6000_vector_reload[V2DFmode][1] = CODE_FOR_reload_v2df_di_load; - if (TARGET_VSX && TARGET_VSX_SCALAR_MEMORY) + reg_addr[V16QImode].reload_store = CODE_FOR_reload_v16qi_di_store; + reg_addr[V16QImode].reload_load = CODE_FOR_reload_v16qi_di_load; + reg_addr[V8HImode].reload_store = CODE_FOR_reload_v8hi_di_store; + reg_addr[V8HImode].reload_load = CODE_FOR_reload_v8hi_di_load; + reg_addr[V4SImode].reload_store = CODE_FOR_reload_v4si_di_store; + reg_addr[V4SImode].reload_load = CODE_FOR_reload_v4si_di_load; + reg_addr[V2DImode].reload_store = CODE_FOR_reload_v2di_di_store; + reg_addr[V2DImode].reload_load = CODE_FOR_reload_v2di_di_load; + reg_addr[V1TImode].reload_store = CODE_FOR_reload_v1ti_di_store; + reg_addr[V1TImode].reload_load = CODE_FOR_reload_v1ti_di_load; + reg_addr[V4SFmode].reload_store = CODE_FOR_reload_v4sf_di_store; + reg_addr[V4SFmode].reload_load = CODE_FOR_reload_v4sf_di_load; + reg_addr[V2DFmode].reload_store = CODE_FOR_reload_v2df_di_store; + reg_addr[V2DFmode].reload_load = CODE_FOR_reload_v2df_di_load; + if (TARGET_VSX && TARGET_UPPER_REGS_DF) + { + reg_addr[DFmode].reload_store = CODE_FOR_reload_df_di_store; + reg_addr[DFmode].reload_load = CODE_FOR_reload_df_di_load; + reg_addr[DFmode].scalar_in_vmx_p = true; + reg_addr[DDmode].reload_store = CODE_FOR_reload_dd_di_store; + reg_addr[DDmode].reload_load = CODE_FOR_reload_dd_di_load; + } + if (TARGET_P8_VECTOR) + { + reg_addr[SFmode].reload_store = CODE_FOR_reload_sf_di_store; + reg_addr[SFmode].reload_load = CODE_FOR_reload_sf_di_load; + reg_addr[SDmode].reload_store = CODE_FOR_reload_sd_di_store; + reg_addr[SDmode].reload_load = CODE_FOR_reload_sd_di_load; + if (TARGET_UPPER_REGS_SF) + reg_addr[SFmode].scalar_in_vmx_p = true; + } + if (TARGET_VSX_TIMODE) + { + reg_addr[TImode].reload_store = CODE_FOR_reload_ti_di_store; + reg_addr[TImode].reload_load = CODE_FOR_reload_ti_di_load; + } + if (TARGET_DIRECT_MOVE) { - rs6000_vector_reload[DFmode][0] = CODE_FOR_reload_df_di_store; - rs6000_vector_reload[DFmode][1] = CODE_FOR_reload_df_di_load; + if (TARGET_POWERPC64) + { + reg_addr[TImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxti; + reg_addr[V1TImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv1ti; + reg_addr[V2DFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv2df; + reg_addr[V2DImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv2di; + reg_addr[V4SFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv4sf; + reg_addr[V4SImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv4si; + reg_addr[V8HImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv8hi; + reg_addr[V16QImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv16qi; + reg_addr[SFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxsf; + + reg_addr[TImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprti; + reg_addr[V1TImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv1ti; + reg_addr[V2DFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv2df; + reg_addr[V2DImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv2di; + reg_addr[V4SFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv4sf; + reg_addr[V4SImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv4si; + reg_addr[V8HImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv8hi; + reg_addr[V16QImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv16qi; + reg_addr[SFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprsf; + } + else + { + reg_addr[DImode].reload_fpr_gpr = CODE_FOR_reload_fpr_from_gprdi; + reg_addr[DDmode].reload_fpr_gpr = CODE_FOR_reload_fpr_from_gprdd; + reg_addr[DFmode].reload_fpr_gpr = CODE_FOR_reload_fpr_from_gprdf; + } } } else { - rs6000_vector_reload[V16QImode][0] = CODE_FOR_reload_v16qi_si_store; - rs6000_vector_reload[V16QImode][1] = CODE_FOR_reload_v16qi_si_load; - rs6000_vector_reload[V8HImode][0] = CODE_FOR_reload_v8hi_si_store; - rs6000_vector_reload[V8HImode][1] = CODE_FOR_reload_v8hi_si_load; - rs6000_vector_reload[V4SImode][0] = CODE_FOR_reload_v4si_si_store; - rs6000_vector_reload[V4SImode][1] = CODE_FOR_reload_v4si_si_load; - rs6000_vector_reload[V2DImode][0] = CODE_FOR_reload_v2di_si_store; - rs6000_vector_reload[V2DImode][1] = CODE_FOR_reload_v2di_si_load; - rs6000_vector_reload[V4SFmode][0] = CODE_FOR_reload_v4sf_si_store; - rs6000_vector_reload[V4SFmode][1] = CODE_FOR_reload_v4sf_si_load; - rs6000_vector_reload[V2DFmode][0] = CODE_FOR_reload_v2df_si_store; - rs6000_vector_reload[V2DFmode][1] = CODE_FOR_reload_v2df_si_load; - if (TARGET_VSX && TARGET_VSX_SCALAR_MEMORY) + reg_addr[V16QImode].reload_store = CODE_FOR_reload_v16qi_si_store; + reg_addr[V16QImode].reload_load = CODE_FOR_reload_v16qi_si_load; + reg_addr[V8HImode].reload_store = CODE_FOR_reload_v8hi_si_store; + reg_addr[V8HImode].reload_load = CODE_FOR_reload_v8hi_si_load; + reg_addr[V4SImode].reload_store = CODE_FOR_reload_v4si_si_store; + reg_addr[V4SImode].reload_load = CODE_FOR_reload_v4si_si_load; + reg_addr[V2DImode].reload_store = CODE_FOR_reload_v2di_si_store; + reg_addr[V2DImode].reload_load = CODE_FOR_reload_v2di_si_load; + reg_addr[V1TImode].reload_store = CODE_FOR_reload_v1ti_si_store; + reg_addr[V1TImode].reload_load = CODE_FOR_reload_v1ti_si_load; + reg_addr[V4SFmode].reload_store = CODE_FOR_reload_v4sf_si_store; + reg_addr[V4SFmode].reload_load = CODE_FOR_reload_v4sf_si_load; + reg_addr[V2DFmode].reload_store = CODE_FOR_reload_v2df_si_store; + reg_addr[V2DFmode].reload_load = CODE_FOR_reload_v2df_si_load; + if (TARGET_VSX && TARGET_UPPER_REGS_DF) + { + reg_addr[DFmode].reload_store = CODE_FOR_reload_df_si_store; + reg_addr[DFmode].reload_load = CODE_FOR_reload_df_si_load; + reg_addr[DFmode].scalar_in_vmx_p = true; + reg_addr[DDmode].reload_store = CODE_FOR_reload_dd_si_store; + reg_addr[DDmode].reload_load = CODE_FOR_reload_dd_si_load; + } + if (TARGET_P8_VECTOR) { - rs6000_vector_reload[DFmode][0] = CODE_FOR_reload_df_si_store; - rs6000_vector_reload[DFmode][1] = CODE_FOR_reload_df_si_load; + reg_addr[SFmode].reload_store = CODE_FOR_reload_sf_si_store; + reg_addr[SFmode].reload_load = CODE_FOR_reload_sf_si_load; + reg_addr[SDmode].reload_store = CODE_FOR_reload_sd_si_store; + reg_addr[SDmode].reload_load = CODE_FOR_reload_sd_si_load; + if (TARGET_UPPER_REGS_SF) + reg_addr[SFmode].scalar_in_vmx_p = true; + } + if (TARGET_VSX_TIMODE) + { + reg_addr[TImode].reload_store = CODE_FOR_reload_ti_si_store; + reg_addr[TImode].reload_load = CODE_FOR_reload_ti_si_load; } } } @@ -2186,8 +2840,18 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) reg_size = UNITS_PER_WORD; for (m = 0; m < NUM_MACHINE_MODES; ++m) - rs6000_class_max_nregs[m][c] - = (GET_MODE_SIZE (m) + reg_size - 1) / reg_size; + { + enum machine_mode m2 = (enum machine_mode)m; + int reg_size2 = reg_size; + + /* TFmode/TDmode always takes 2 registers, even in VSX. */ + if (TARGET_VSX && VSX_REG_CLASS_P (c) + && (m == TDmode || m == TFmode)) + reg_size2 = UNITS_PER_FP_WORD; + + rs6000_class_max_nregs[m][c] + = (GET_MODE_SIZE (m2) + reg_size2 - 1) / reg_size2; + } } if (TARGET_E500_DOUBLE) @@ -2261,6 +2925,11 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) } } + /* Update the addr mask bits in reg_addr to help secondary reload and go if + legitimate address support to figure out the appropriate addressing to + use. */ + rs6000_setup_reg_addr_masks (); + if (global_init_p || TARGET_DEBUG_TARGET) { if (TARGET_DEBUG_REG) @@ -2363,16 +3032,22 @@ darwin_rs6000_override_options (void) HOST_WIDE_INT rs6000_builtin_mask_calculate (void) { - return (((TARGET_ALTIVEC) ? RS6000_BTM_ALTIVEC : 0) - | ((TARGET_VSX) ? RS6000_BTM_VSX : 0) - | ((TARGET_SPE) ? RS6000_BTM_SPE : 0) - | ((TARGET_PAIRED_FLOAT) ? RS6000_BTM_PAIRED : 0) - | ((TARGET_FRE) ? RS6000_BTM_FRE : 0) - | ((TARGET_FRES) ? RS6000_BTM_FRES : 0) - | ((TARGET_FRSQRTE) ? RS6000_BTM_FRSQRTE : 0) - | ((TARGET_FRSQRTES) ? RS6000_BTM_FRSQRTES : 0) - | ((TARGET_POPCNTD) ? RS6000_BTM_POPCNTD : 0) - | ((rs6000_cpu == PROCESSOR_CELL) ? RS6000_BTM_CELL : 0)); + return (((TARGET_ALTIVEC) ? RS6000_BTM_ALTIVEC : 0) + | ((TARGET_VSX) ? RS6000_BTM_VSX : 0) + | ((TARGET_SPE) ? RS6000_BTM_SPE : 0) + | ((TARGET_PAIRED_FLOAT) ? RS6000_BTM_PAIRED : 0) + | ((TARGET_FRE) ? RS6000_BTM_FRE : 0) + | ((TARGET_FRES) ? RS6000_BTM_FRES : 0) + | ((TARGET_FRSQRTE) ? RS6000_BTM_FRSQRTE : 0) + | ((TARGET_FRSQRTES) ? RS6000_BTM_FRSQRTES : 0) + | ((TARGET_POPCNTD) ? RS6000_BTM_POPCNTD : 0) + | ((rs6000_cpu == PROCESSOR_CELL) ? RS6000_BTM_CELL : 0) + | ((TARGET_P8_VECTOR) ? RS6000_BTM_P8_VECTOR : 0) + | ((TARGET_CRYPTO) ? RS6000_BTM_CRYPTO : 0) + | ((TARGET_HTM) ? RS6000_BTM_HTM : 0) + | ((TARGET_DFP) ? RS6000_BTM_DFP : 0) + | ((TARGET_HARD_FLOAT) ? RS6000_BTM_HARD_FLOAT : 0) + | ((TARGET_LONG_DOUBLE_128) ? RS6000_BTM_LDBL128 : 0)); } /* Override command line options. Mostly we process the processor type and @@ -2409,7 +3084,8 @@ rs6000_option_override_internal (bool global_init_p) calculation works better for RTL loop invariant motion on targets with enough (>= 32) registers. It is an expensive optimization. So it is on only for peak performance. */ - if (optimize >= 3 && global_init_p) + if (optimize >= 3 && global_init_p + && !global_options_set.x_flag_ira_loop_pressure) flag_ira_loop_pressure = 1; /* Set the pointer size. */ @@ -2465,7 +3141,13 @@ rs6000_option_override_internal (bool global_init_p) } else { - const char *default_cpu = (TARGET_POWERPC64 ? "powerpc64" : "powerpc"); + /* PowerPC 64-bit LE requires at least ISA 2.07. */ + const char *default_cpu = ((!TARGET_POWERPC64) + ? "powerpc" + : ((BYTES_BIG_ENDIAN) + ? "powerpc64" + : "powerpc64le")); + rs6000_cpu_index = cpu_index = rs6000_cpu_name_lookup (default_cpu); have_cpu = false; } @@ -2484,15 +3166,18 @@ rs6000_option_override_internal (bool global_init_p) & set_masks); } else - rs6000_isa_flags |= (processor_target_table[cpu_index].target_enable - & ~rs6000_isa_flags_explicit); + { + /* If no -mcpu=, inherit any default options that were cleared via + POWERPC_MASKS. Originally, TARGET_DEFAULT was used to initialize + target_flags via the TARGET_DEFAULT_TARGET_FLAGS hook. When we switched + to using rs6000_isa_flags, we need to do the initialization here. - /* If no -mcpu=, inherit any default options that were cleared via - POWERPC_MASKS. Originally, TARGET_DEFAULT was used to initialize - target_flags via the TARGET_DEFAULT_TARGET_FLAGS hook. When we switched - to using rs6000_isa_flags, we need to do the initialization here. */ - if (!have_cpu) - rs6000_isa_flags |= (TARGET_DEFAULT & ~rs6000_isa_flags_explicit); + If there is a TARGET_DEFAULT, use that. Otherwise fall back to using + -mcpu=powerpc, -mcpu=powerpc64, or -mcpu=powerpc64le defaults. */ + HOST_WIDE_INT flags = ((TARGET_DEFAULT) ? TARGET_DEFAULT + : processor_target_table[cpu_index].target_enable); + rs6000_isa_flags |= (flags & ~rs6000_isa_flags_explicit); + } if (rs6000_tune_index >= 0) tune_index = rs6000_tune_index; @@ -2603,6 +3288,24 @@ rs6000_option_override_internal (bool global_init_p) } } + /* If little-endian, default to -mstrict-align on older processors. + Testing for htm matches power8 and later. */ + if (!BYTES_BIG_ENDIAN + && !(processor_target_table[tune_index].target_enable & OPTION_MASK_HTM)) + rs6000_isa_flags |= ~rs6000_isa_flags_explicit & OPTION_MASK_STRICT_ALIGN; + + /* -maltivec={le,be} implies -maltivec. */ + if (rs6000_altivec_element_order != 0) + rs6000_isa_flags |= OPTION_MASK_ALTIVEC; + + /* Disallow -maltivec=le in big endian mode for now. This is not + known to be useful for anyone. */ + if (BYTES_BIG_ENDIAN && rs6000_altivec_element_order == 1) + { + warning (0, N_("-maltivec=le not allowed for big-endian targets")); + rs6000_altivec_element_order = 0; + } + /* Add some warnings for VSX. */ if (TARGET_VSX) { @@ -2613,15 +3316,13 @@ rs6000_option_override_internal (bool global_init_p) if (rs6000_isa_flags_explicit & OPTION_MASK_VSX) msg = N_("-mvsx requires hardware floating point"); else - rs6000_isa_flags &= ~ OPTION_MASK_VSX; + { + rs6000_isa_flags &= ~ OPTION_MASK_VSX; + rs6000_isa_flags_explicit |= OPTION_MASK_VSX; + } } else if (TARGET_PAIRED_FLOAT) msg = N_("-mvsx and -mpaired are incompatible"); - /* The hardware will allow VSX and little endian, but until we make sure - things like vector select, etc. work don't allow VSX on little endian - systems at this point. */ - else if (!BYTES_BIG_ENDIAN) - msg = N_("-mvsx used with little endian code"); else if (TARGET_AVOID_XFORM > 0) msg = N_("-mvsx needs indexed addressing"); else if (!TARGET_ALTIVEC && (rs6000_isa_flags_explicit @@ -2641,9 +3342,24 @@ rs6000_option_override_internal (bool global_init_p) } } + /* If hard-float/altivec/vsx were explicitly turned off then don't allow + the -mcpu setting to enable options that conflict. */ + if ((!TARGET_HARD_FLOAT || !TARGET_ALTIVEC || !TARGET_VSX) + && (rs6000_isa_flags_explicit & (OPTION_MASK_SOFT_FLOAT + | OPTION_MASK_ALTIVEC + | OPTION_MASK_VSX)) != 0) + rs6000_isa_flags &= ~((OPTION_MASK_P8_VECTOR | OPTION_MASK_CRYPTO + | OPTION_MASK_DIRECT_MOVE) + & ~rs6000_isa_flags_explicit); + + if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET) + rs6000_print_isa_options (stderr, 0, "before defaults", rs6000_isa_flags); + /* For the newer switches (vsx, dfp, etc.) set some of the older options, unless the user explicitly used the -mno-