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Releases: espressif/qemu

esp-develop-20220203

03 Feb 12:27
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  • Rebased on top of QEMU 6.2.0. Fixed breakage/deprecations.
  • Fixed division by zero in UART emulation. (#24)
  • Fixed build errors under MSYS. (#31, thanks @smuehlst!)
  • ESP32 APP CPU now sees the correct ROM code. Previously PRO and APP CPUs in QEMU shared the same ROM code, which isn't the case on the real ESP32. This fixes, among other things, the location of APP CPU stack at boot time.

esp-develop-20210826

26 Aug 19:05
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  • Rebased on top of QEMU 6.1.0. Upgraded build dependencies, fixed breakage/deprecations.
  • Added SDMMC (SD Host) peripheral emulation (#5).
  • Added basic PSRAM emulation (#4). Either 2 MB or 4 MB of PSRAM can be added to the machine using -M command line option. "Himem" feature in ESP-IDF doesn't work yet, as only a simple linear cache mapping is supported.
  • Two environment variables have been introduced for compatibility with existing versions of GDB. The upcoming toolchain release, esp-2021r2, will ship a version of GDB that fixes a number of issues observed on Xtensa architecture. This release of QEMU can work with the older toolchain releases, if the following environment variables are set. It can also benefit from the fixes in the new release of GDB, in this case these variables shouldn't be set.
    • If QEMU_XTENSA_CORE_REGS_ONLY=1 is set, QEMU will only send non-privileged registers to GDB. Setting this to 1 matches the behavior in previous versions of QEMU. Otherwise, all registers (including the privileged ones) will be sent.
    • If QEMU_XTENSA_COUNT_WINDOW_REGS=1 is set, a0-a15 registers (i.e. the current register window) will be sent to GDB. Setting this to 1 matches the behavior in the previous versions of QEMU. Otherwise, window registers will not be sent, and GDB will treat them as pseudo registers.
  • Fixed DIO flash mode support (#16). Switching to DOUT mode is no longer necessary.
  • Fixed handling of DP83848C PHYSTS register (#14).
  • Fixed detection of ESP32 ECO3 version via APB_CTRL_DATE_REG.
  • Fixed LACT timer interrupt emulation.
  • Fixed switch fallthrough bugs in I2C emulation.
  • Fixed race conditions in eFuse emulation.

esp-develop-20210220

20 Feb 00:14
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  • Rebased on top of QEMU 5.2.0, fixed breakage/deprecations, adapted ESP32 patches to meson build system.
  • Added RSA peripheral based on libgcrypt.
  • Added flash encryption and decryption.
  • Added I2C peripheral (based on #11).
  • Enabled FPU coprocessor instructions for ESP32 core.
  • eFuse: fixed write operation wiping previously written bits.
  • SHA: fixed internal state not being reset when START register is written.
  • UART: simplified autobaud implementation, added RXFIFO_TOUT interrupt, added MEM_RX_STATUS register, exposed UART1 and UART2 devices.
  • esp32: fixed IRAM memory range, resolving the issue with loading esptool flasher stub.
  • esp32: updated ROM to ECO3 version.
  • timers: fixed compilation warnings.

esp-develop-20200528

28 May 16:37
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  • Rebase to QEMU v5.0.0 release
  • Fix LACT timer register access (fixes #7, thanks @peragwin)
  • Add partial FPU support (FPU2000 instructions only)

esp-develop-20191228

30 Dec 16:50
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  • Rebased to QEMU v4.2.0 release
  • Implemented cache illegal access interrupt
  • Implemented TIMG watchdogs
  • Fixed interrupt matrix not being reset properly
  • Fixed APP CPU not resumed when the stall flag is cleared
  • Fixed APP CPU stall state IRQ not cleared when DPORT is reset