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Verilog: lowering for concatenation of aval/bval encoded vectors #564

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Merged
merged 1 commit into from
Jul 15, 2024

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This adds lowering for the concatenation of aval/bval encoded bit-vectors.

@kroening kroening marked this pull request as ready for review June 20, 2024 16:16
if(is_aval_bval(src.type()))
{
auto width = aval_bval_width(src.type());
return extractbits_exprt{src, 0, bv_typet{width}};
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Shouldn't this be width instead of 0? (Can we have a test that catches this?)

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Fixed, test added!

{
// zeros, signaling 0/1
auto width = to_bitvector_type(src.type()).get_width();
return from_integer(0, bv_typet{width});
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Maybe throw in a cbmc upgrade and use the new bv_typet methods?

@kroening kroening force-pushed the aval-bval-concatenation branch 3 times, most recently from 2ab45ea to 8fc936e Compare July 13, 2024 00:28
This adds lowering for the concatenation of aval/bval encoded bit-vectors.
@kroening kroening force-pushed the aval-bval-concatenation branch from 8fc936e to b80d107 Compare July 13, 2024 00:30
@tautschnig tautschnig merged commit b991263 into main Jul 15, 2024
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@tautschnig tautschnig deleted the aval-bval-concatenation branch July 15, 2024 10:10
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2 participants