Verilog: aval/bval lowering of 4-valued logic #561
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tautschnig
approved these changes
Jun 19, 2024
| @@ -1,20 +1,20 @@ | |||
| module main(input clk, x, y); | |||
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| reg [1:0] cnt1; | |||
| reg z; | |||
| reg result; | |||
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I am assuming this was just drive-by cleanup?
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Yes, z could be read as high-impedance state.
src/verilog/aval_bval_encoding.h
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| #include <util/expr.h> | ||
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| class bv_typet; | ||
| class constant_exprt; |
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Nit-picking: I'd expect util/bitvector_types.h and util/std_expr.h to be included here for bv_typet and constant_exprt are returned by value. Or pick the other extreme and also forward-declare class exprt; and class typet;.
tautschnig
reviewed
Jun 19, 2024
| return result; | ||
| } | ||
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| bv_typet lower_to_aval_bval(const typet &src) |
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Shouldn't this be a bitvector_typet instead of just typet? This will then also avoid the to_bitvector_type a few lines further down.
tautschnig
reviewed
Jun 19, 2024
src/verilog/aval_bval_encoding.cpp
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| src, from_integer(width, integer_typet()), bv_typet{width}}; | ||
| } | ||
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| exprt adjust_size(const exprt &src, std::size_t dest_width) |
tautschnig
reviewed
Jun 19, 2024
src/verilog/aval_bval_encoding.cpp
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| return src; | ||
| } | ||
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| exprt combine_aval_bval(const exprt &aval, const exprt &bval, const typet &dest) |
This introduces the standard aval/bval lowering of Verilog's 4-valued logic into bit vectors.
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This introduces the standard aval/bval lowering of Verilog's 4-valued logic into bit vectors.